]>
Commit | Line | Data |
---|---|---|
dc1e35c6 SS |
1 | /* |
2 | * xsave/xrstor support. | |
3 | * | |
4 | * Author: Suresh Siddha <suresh.b.siddha@intel.com> | |
5 | */ | |
dc1e35c6 | 6 | #include <linux/compat.h> |
7e7ce87f | 7 | #include <linux/cpu.h> |
59a36d16 | 8 | |
df6b35f4 | 9 | #include <asm/fpu/api.h> |
78f7f1e5 | 10 | #include <asm/fpu/internal.h> |
fcbc99c4 | 11 | #include <asm/fpu/signal.h> |
59a36d16 | 12 | #include <asm/fpu/regset.h> |
b992c660 | 13 | |
375074cc | 14 | #include <asm/tlbflush.h> |
dc1e35c6 | 15 | |
5b073430 IM |
16 | static const char *xfeature_names[] = |
17 | { | |
18 | "x87 floating point registers" , | |
19 | "SSE registers" , | |
20 | "AVX registers" , | |
21 | "MPX bounds registers" , | |
22 | "MPX CSR" , | |
23 | "AVX-512 opmask" , | |
24 | "AVX-512 Hi256" , | |
25 | "AVX-512 ZMM_Hi256" , | |
26 | "unknown xstate feature" , | |
27 | }; | |
28 | ||
dc1e35c6 | 29 | /* |
614df7fb | 30 | * Mask of xstate features supported by the CPU and the kernel: |
dc1e35c6 | 31 | */ |
5b073430 | 32 | u64 xfeatures_mask __read_mostly; |
dc1e35c6 | 33 | |
a8424003 DH |
34 | static unsigned int xstate_offsets[XFEATURES_NR_MAX] = { [ 0 ... XFEATURES_NR_MAX - 1] = -1}; |
35 | static unsigned int xstate_sizes[XFEATURES_NR_MAX] = { [ 0 ... XFEATURES_NR_MAX - 1] = -1}; | |
614df7fb | 36 | static unsigned int xstate_comp_offsets[sizeof(xfeatures_mask)*8]; |
84246fe4 IM |
37 | |
38 | /* The number of supported xfeatures in xfeatures_mask: */ | |
39 | static unsigned int xfeatures_nr; | |
a1488f8b | 40 | |
0a265375 DH |
41 | /* |
42 | * Clear all of the X86_FEATURE_* bits that are unavailable | |
43 | * when the CPU has no XSAVE support. | |
44 | */ | |
45 | void fpu__xstate_clear_all_cpu_caps(void) | |
46 | { | |
47 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
48 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
49 | setup_clear_cpu_cap(X86_FEATURE_XSAVEC); | |
50 | setup_clear_cpu_cap(X86_FEATURE_XSAVES); | |
51 | setup_clear_cpu_cap(X86_FEATURE_AVX); | |
52 | setup_clear_cpu_cap(X86_FEATURE_AVX2); | |
53 | setup_clear_cpu_cap(X86_FEATURE_AVX512F); | |
54 | setup_clear_cpu_cap(X86_FEATURE_AVX512PF); | |
55 | setup_clear_cpu_cap(X86_FEATURE_AVX512ER); | |
56 | setup_clear_cpu_cap(X86_FEATURE_AVX512CD); | |
57 | setup_clear_cpu_cap(X86_FEATURE_MPX); | |
58 | } | |
59 | ||
5b073430 IM |
60 | /* |
61 | * Return whether the system supports a given xfeature. | |
62 | * | |
63 | * Also return the name of the (most advanced) feature that the caller requested: | |
64 | */ | |
65 | int cpu_has_xfeatures(u64 xfeatures_needed, const char **feature_name) | |
66 | { | |
67 | u64 xfeatures_missing = xfeatures_needed & ~xfeatures_mask; | |
68 | ||
69 | if (unlikely(feature_name)) { | |
70 | long xfeature_idx, max_idx; | |
71 | u64 xfeatures_print; | |
72 | /* | |
73 | * So we use FLS here to be able to print the most advanced | |
74 | * feature that was requested but is missing. So if a driver | |
d91cab78 | 75 | * asks about "XFEATURE_MASK_SSE | XFEATURE_MASK_YMM" we'll print the |
5b073430 IM |
76 | * missing AVX feature - this is the most informative message |
77 | * to users: | |
78 | */ | |
79 | if (xfeatures_missing) | |
80 | xfeatures_print = xfeatures_missing; | |
81 | else | |
82 | xfeatures_print = xfeatures_needed; | |
83 | ||
84 | xfeature_idx = fls64(xfeatures_print)-1; | |
85 | max_idx = ARRAY_SIZE(xfeature_names)-1; | |
86 | xfeature_idx = min(xfeature_idx, max_idx); | |
87 | ||
88 | *feature_name = xfeature_names[xfeature_idx]; | |
89 | } | |
90 | ||
91 | if (xfeatures_missing) | |
92 | return 0; | |
93 | ||
94 | return 1; | |
95 | } | |
96 | EXPORT_SYMBOL_GPL(cpu_has_xfeatures); | |
97 | ||
29104e10 | 98 | /* |
aeb997b9 IM |
99 | * When executing XSAVEOPT (or other optimized XSAVE instructions), if |
100 | * a processor implementation detects that an FPU state component is still | |
101 | * (or is again) in its initialized state, it may clear the corresponding | |
102 | * bit in the header.xfeatures field, and can skip the writeout of registers | |
103 | * to the corresponding memory layout. | |
73a3aeb3 IM |
104 | * |
105 | * This means that when the bit is zero, the state component might still contain | |
106 | * some previous - non-initialized register state. | |
107 | * | |
108 | * Before writing xstate information to user-space we sanitize those components, | |
109 | * to always ensure that the memory layout of a feature will be in the init state | |
110 | * if the corresponding header bit is zero. This is to ensure that user-space doesn't | |
111 | * see some stale state in the memory layout during signal handling, debugging etc. | |
29104e10 | 112 | */ |
36e49e7f | 113 | void fpstate_sanitize_xstate(struct fpu *fpu) |
29104e10 | 114 | { |
c47ada30 | 115 | struct fxregs_state *fx = &fpu->state.fxsave; |
73a3aeb3 | 116 | int feature_bit; |
400e4b20 | 117 | u64 xfeatures; |
29104e10 | 118 | |
1ac91a76 | 119 | if (!use_xsaveopt()) |
29104e10 SS |
120 | return; |
121 | ||
36e49e7f | 122 | xfeatures = fpu->state.xsave.header.xfeatures; |
29104e10 SS |
123 | |
124 | /* | |
125 | * None of the feature bits are in init state. So nothing else | |
0d2eb44f | 126 | * to do for us, as the memory layout is up to date. |
29104e10 | 127 | */ |
400e4b20 | 128 | if ((xfeatures & xfeatures_mask) == xfeatures_mask) |
29104e10 SS |
129 | return; |
130 | ||
131 | /* | |
132 | * FP is in init state | |
133 | */ | |
d91cab78 | 134 | if (!(xfeatures & XFEATURE_MASK_FP)) { |
29104e10 SS |
135 | fx->cwd = 0x37f; |
136 | fx->swd = 0; | |
137 | fx->twd = 0; | |
138 | fx->fop = 0; | |
139 | fx->rip = 0; | |
140 | fx->rdp = 0; | |
141 | memset(&fx->st_space[0], 0, 128); | |
142 | } | |
143 | ||
144 | /* | |
145 | * SSE is in init state | |
146 | */ | |
d91cab78 | 147 | if (!(xfeatures & XFEATURE_MASK_SSE)) |
29104e10 SS |
148 | memset(&fx->xmm_space[0], 0, 256); |
149 | ||
73a3aeb3 IM |
150 | /* |
151 | * First two features are FPU and SSE, which above we handled | |
152 | * in a special way already: | |
153 | */ | |
154 | feature_bit = 0x2; | |
400e4b20 | 155 | xfeatures = (xfeatures_mask & ~xfeatures) >> 2; |
29104e10 SS |
156 | |
157 | /* | |
73a3aeb3 IM |
158 | * Update all the remaining memory layouts according to their |
159 | * standard xstate layout, if their header bit is in the init | |
160 | * state: | |
29104e10 | 161 | */ |
400e4b20 IM |
162 | while (xfeatures) { |
163 | if (xfeatures & 0x1) { | |
29104e10 SS |
164 | int offset = xstate_offsets[feature_bit]; |
165 | int size = xstate_sizes[feature_bit]; | |
166 | ||
73a3aeb3 | 167 | memcpy((void *)fx + offset, |
6f575023 | 168 | (void *)&init_fpstate.xsave + offset, |
29104e10 SS |
169 | size); |
170 | } | |
171 | ||
400e4b20 | 172 | xfeatures >>= 1; |
29104e10 SS |
173 | feature_bit++; |
174 | } | |
175 | } | |
176 | ||
dc1e35c6 | 177 | /* |
55cc4678 IM |
178 | * Enable the extended processor state save/restore feature. |
179 | * Called once per CPU onlining. | |
dc1e35c6 | 180 | */ |
55cc4678 | 181 | void fpu__init_cpu_xstate(void) |
dc1e35c6 | 182 | { |
e84611fc | 183 | if (!cpu_has_xsave || !xfeatures_mask) |
55cc4678 IM |
184 | return; |
185 | ||
375074cc | 186 | cr4_set_bits(X86_CR4_OSXSAVE); |
614df7fb | 187 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); |
dc1e35c6 SS |
188 | } |
189 | ||
a1488f8b | 190 | /* |
39f1acd2 IM |
191 | * Record the offsets and sizes of various xstates contained |
192 | * in the XSAVE state memory layout. | |
193 | * | |
194 | * ( Note that certain features might be non-present, for them | |
195 | * we'll have 0 offset and 0 size. ) | |
a1488f8b | 196 | */ |
4995b9db | 197 | static void __init setup_xstate_features(void) |
a1488f8b | 198 | { |
39f1acd2 | 199 | u32 eax, ebx, ecx, edx, leaf; |
a1488f8b | 200 | |
84246fe4 | 201 | xfeatures_nr = fls64(xfeatures_mask); |
a1488f8b | 202 | |
39f1acd2 | 203 | for (leaf = 2; leaf < xfeatures_nr; leaf++) { |
ee813d53 | 204 | cpuid_count(XSTATE_CPUID, leaf, &eax, &ebx, &ecx, &edx); |
a1488f8b | 205 | |
a1488f8b SS |
206 | xstate_offsets[leaf] = ebx; |
207 | xstate_sizes[leaf] = eax; | |
208 | ||
b0815359 | 209 | printk(KERN_INFO "x86/fpu: xstate_offset[%d]: %4d, xstate_sizes[%d]: %4d\n", leaf, ebx, leaf, eax); |
39f1acd2 | 210 | } |
a1488f8b SS |
211 | } |
212 | ||
32231879 | 213 | static void __init print_xstate_feature(u64 xstate_mask) |
69496e10 | 214 | { |
33588b52 | 215 | const char *feature_name; |
69496e10 | 216 | |
33588b52 IM |
217 | if (cpu_has_xfeatures(xstate_mask, &feature_name)) |
218 | pr_info("x86/fpu: Supporting XSAVE feature 0x%02Lx: '%s'\n", xstate_mask, feature_name); | |
69496e10 IM |
219 | } |
220 | ||
221 | /* | |
222 | * Print out all the supported xstate features: | |
223 | */ | |
32231879 | 224 | static void __init print_xstate_features(void) |
69496e10 | 225 | { |
d91cab78 DH |
226 | print_xstate_feature(XFEATURE_MASK_FP); |
227 | print_xstate_feature(XFEATURE_MASK_SSE); | |
228 | print_xstate_feature(XFEATURE_MASK_YMM); | |
229 | print_xstate_feature(XFEATURE_MASK_BNDREGS); | |
230 | print_xstate_feature(XFEATURE_MASK_BNDCSR); | |
231 | print_xstate_feature(XFEATURE_MASK_OPMASK); | |
232 | print_xstate_feature(XFEATURE_MASK_ZMM_Hi256); | |
233 | print_xstate_feature(XFEATURE_MASK_Hi16_ZMM); | |
69496e10 IM |
234 | } |
235 | ||
7496d645 FY |
236 | /* |
237 | * This function sets up offsets and sizes of all extended states in | |
238 | * xsave area. This supports both standard format and compacted format | |
239 | * of the xsave aread. | |
7496d645 | 240 | */ |
32231879 | 241 | static void __init setup_xstate_comp(void) |
7496d645 | 242 | { |
614df7fb | 243 | unsigned int xstate_comp_sizes[sizeof(xfeatures_mask)*8]; |
7496d645 FY |
244 | int i; |
245 | ||
8ff925e1 FY |
246 | /* |
247 | * The FP xstates and SSE xstates are legacy states. They are always | |
248 | * in the fixed offsets in the xsave area in either compacted form | |
249 | * or standard form. | |
250 | */ | |
251 | xstate_comp_offsets[0] = 0; | |
c47ada30 | 252 | xstate_comp_offsets[1] = offsetof(struct fxregs_state, xmm_space); |
7496d645 FY |
253 | |
254 | if (!cpu_has_xsaves) { | |
84246fe4 | 255 | for (i = 2; i < xfeatures_nr; i++) { |
614df7fb | 256 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) { |
7496d645 FY |
257 | xstate_comp_offsets[i] = xstate_offsets[i]; |
258 | xstate_comp_sizes[i] = xstate_sizes[i]; | |
259 | } | |
260 | } | |
261 | return; | |
262 | } | |
263 | ||
264 | xstate_comp_offsets[2] = FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
265 | ||
84246fe4 | 266 | for (i = 2; i < xfeatures_nr; i++) { |
614df7fb | 267 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) |
7496d645 FY |
268 | xstate_comp_sizes[i] = xstate_sizes[i]; |
269 | else | |
270 | xstate_comp_sizes[i] = 0; | |
271 | ||
272 | if (i > 2) | |
273 | xstate_comp_offsets[i] = xstate_comp_offsets[i-1] | |
274 | + xstate_comp_sizes[i-1]; | |
275 | ||
276 | } | |
277 | } | |
278 | ||
dc1e35c6 SS |
279 | /* |
280 | * setup the xstate image representing the init state | |
281 | */ | |
32231879 | 282 | static void __init setup_init_fpu_buf(void) |
dc1e35c6 | 283 | { |
e97131a8 IM |
284 | static int on_boot_cpu = 1; |
285 | ||
286 | WARN_ON_FPU(!on_boot_cpu); | |
287 | on_boot_cpu = 0; | |
288 | ||
5d2bd700 SS |
289 | if (!cpu_has_xsave) |
290 | return; | |
291 | ||
292 | setup_xstate_features(); | |
69496e10 | 293 | print_xstate_features(); |
a1488f8b | 294 | |
47c2f292 | 295 | if (cpu_has_xsaves) { |
6f575023 IM |
296 | init_fpstate.xsave.header.xcomp_bv = (u64)1 << 63 | xfeatures_mask; |
297 | init_fpstate.xsave.header.xfeatures = xfeatures_mask; | |
47c2f292 FY |
298 | } |
299 | ||
29104e10 SS |
300 | /* |
301 | * Init all the features state with header_bv being 0x0 | |
302 | */ | |
d65fcd60 | 303 | copy_kernel_to_xregs_booting(&init_fpstate.xsave); |
3e261c14 | 304 | |
29104e10 SS |
305 | /* |
306 | * Dump the init state again. This is to identify the init state | |
307 | * of any feature which is not represented by all zero's. | |
308 | */ | |
c6813144 | 309 | copy_xregs_to_kernel_booting(&init_fpstate.xsave); |
dc1e35c6 SS |
310 | } |
311 | ||
7e7ce87f | 312 | /* |
614df7fb | 313 | * Calculate total size of enabled xstates in XCR0/xfeatures_mask. |
7e7ce87f | 314 | */ |
4109ca06 | 315 | static unsigned int __init calculate_xstate_size(void) |
7e7ce87f FY |
316 | { |
317 | unsigned int eax, ebx, ecx, edx; | |
4109ca06 | 318 | unsigned int calculated_xstate_size; |
7e7ce87f FY |
319 | int i; |
320 | ||
321 | if (!cpu_has_xsaves) { | |
322 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
4109ca06 DH |
323 | calculated_xstate_size = ebx; |
324 | return calculated_xstate_size; | |
7e7ce87f FY |
325 | } |
326 | ||
4109ca06 | 327 | calculated_xstate_size = FXSAVE_SIZE + XSAVE_HDR_SIZE; |
7e7ce87f | 328 | for (i = 2; i < 64; i++) { |
614df7fb | 329 | if (test_bit(i, (unsigned long *)&xfeatures_mask)) { |
7e7ce87f | 330 | cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx); |
4109ca06 | 331 | calculated_xstate_size += eax; |
7e7ce87f FY |
332 | } |
333 | } | |
4109ca06 DH |
334 | return calculated_xstate_size; |
335 | } | |
336 | ||
337 | /* | |
338 | * Will the runtime-enumerated 'xstate_size' fit in the init | |
339 | * task's statically-allocated buffer? | |
340 | */ | |
341 | static bool is_supported_xstate_size(unsigned int test_xstate_size) | |
342 | { | |
343 | if (test_xstate_size <= sizeof(union fpregs_state)) | |
344 | return true; | |
345 | ||
346 | pr_warn("x86/fpu: xstate buffer too small (%zu < %d), disabling xsave\n", | |
347 | sizeof(union fpregs_state), test_xstate_size); | |
348 | return false; | |
349 | } | |
350 | ||
351 | static int init_xstate_size(void) | |
352 | { | |
353 | /* Recompute the context size for enabled features: */ | |
354 | unsigned int possible_xstate_size = calculate_xstate_size(); | |
355 | ||
356 | /* Ensure we have the space to store all enabled: */ | |
357 | if (!is_supported_xstate_size(possible_xstate_size)) | |
358 | return -EINVAL; | |
359 | ||
360 | /* | |
361 | * The size is OK, we are definitely going to use xsave, | |
362 | * make it known to the world that we need more space. | |
363 | */ | |
364 | xstate_size = possible_xstate_size; | |
365 | return 0; | |
366 | } | |
367 | ||
d91cab78 DH |
368 | /* |
369 | * We enabled the XSAVE hardware, but something went wrong and | |
370 | * we can not use it. Disable it. | |
371 | */ | |
372 | static void fpu__init_disable_system_xstate(void) | |
4109ca06 DH |
373 | { |
374 | xfeatures_mask = 0; | |
375 | cr4_clear_bits(X86_CR4_OSXSAVE); | |
376 | fpu__xstate_clear_all_cpu_caps(); | |
7e7ce87f FY |
377 | } |
378 | ||
dc1e35c6 SS |
379 | /* |
380 | * Enable and initialize the xsave feature. | |
55cc4678 | 381 | * Called once per system bootup. |
dc1e35c6 | 382 | */ |
32231879 | 383 | void __init fpu__init_system_xstate(void) |
dc1e35c6 SS |
384 | { |
385 | unsigned int eax, ebx, ecx, edx; | |
e97131a8 | 386 | static int on_boot_cpu = 1; |
4109ca06 | 387 | int err; |
e97131a8 IM |
388 | |
389 | WARN_ON_FPU(!on_boot_cpu); | |
390 | on_boot_cpu = 0; | |
dc1e35c6 | 391 | |
e9dbfd67 IM |
392 | if (!cpu_has_xsave) { |
393 | pr_info("x86/fpu: Legacy x87 FPU detected.\n"); | |
394 | return; | |
395 | } | |
396 | ||
ee813d53 | 397 | if (boot_cpu_data.cpuid_level < XSTATE_CPUID) { |
e97131a8 | 398 | WARN_ON_FPU(1); |
ee813d53 RR |
399 | return; |
400 | } | |
401 | ||
402 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
614df7fb | 403 | xfeatures_mask = eax + ((u64)edx << 32); |
dc1e35c6 | 404 | |
d91cab78 | 405 | if ((xfeatures_mask & XFEATURE_MASK_FPSSE) != XFEATURE_MASK_FPSSE) { |
614df7fb | 406 | pr_err("x86/fpu: FP/SSE not present amongst the CPU's xstate features: 0x%llx.\n", xfeatures_mask); |
dc1e35c6 SS |
407 | BUG(); |
408 | } | |
409 | ||
6e553594 | 410 | /* Support only the state known to the OS: */ |
614df7fb | 411 | xfeatures_mask = xfeatures_mask & XCNTXT_MASK; |
97e80a70 | 412 | |
55cc4678 IM |
413 | /* Enable xstate instructions to be able to continue with initialization: */ |
414 | fpu__init_cpu_xstate(); | |
4109ca06 DH |
415 | err = init_xstate_size(); |
416 | if (err) { | |
417 | /* something went wrong, boot without any XSAVE support */ | |
418 | fpu__init_disable_system_xstate(); | |
419 | return; | |
420 | } | |
dc1e35c6 | 421 | |
614df7fb | 422 | update_regset_xstate_info(xstate_size, xfeatures_mask); |
b992c660 | 423 | fpu__init_prepare_fx_sw_frame(); |
5d2bd700 | 424 | setup_init_fpu_buf(); |
5fd402df | 425 | setup_xstate_comp(); |
dc1e35c6 | 426 | |
b0815359 | 427 | pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is %d bytes, using '%s' format.\n", |
614df7fb | 428 | xfeatures_mask, |
32d4d9cc IM |
429 | xstate_size, |
430 | cpu_has_xsaves ? "compacted" : "standard"); | |
dc1e35c6 | 431 | } |
82d4150c | 432 | |
9254aaa0 IM |
433 | /* |
434 | * Restore minimal FPU state after suspend: | |
435 | */ | |
436 | void fpu__resume_cpu(void) | |
437 | { | |
438 | /* | |
439 | * Restore XCR0 on xsave capable CPUs: | |
440 | */ | |
441 | if (cpu_has_xsave) | |
442 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); | |
443 | } | |
444 | ||
7496d645 FY |
445 | /* |
446 | * Given the xsave area and a state inside, this function returns the | |
447 | * address of the state. | |
448 | * | |
449 | * This is the API that is called to get xstate address in either | |
450 | * standard format or compacted format of xsave area. | |
451 | * | |
0c4109be DH |
452 | * Note that if there is no data for the field in the xsave buffer |
453 | * this will return NULL. | |
454 | * | |
7496d645 | 455 | * Inputs: |
0c4109be DH |
456 | * xstate: the thread's storage area for all FPU data |
457 | * xstate_feature: state which is defined in xsave.h (e.g. | |
d91cab78 | 458 | * XFEATURE_MASK_FP, XFEATURE_MASK_SSE, etc...) |
7496d645 | 459 | * Output: |
0c4109be DH |
460 | * address of the state in the xsave area, or NULL if the |
461 | * field is not present in the xsave buffer. | |
7496d645 | 462 | */ |
0c4109be | 463 | void *get_xsave_addr(struct xregs_state *xsave, int xstate_feature) |
7496d645 | 464 | { |
0c4109be DH |
465 | int feature_nr = fls64(xstate_feature) - 1; |
466 | /* | |
467 | * Do we even *have* xsave state? | |
468 | */ | |
469 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) | |
470 | return NULL; | |
471 | ||
472 | xsave = ¤t->thread.fpu.state.xsave; | |
473 | /* | |
474 | * We should not ever be requesting features that we | |
475 | * have not enabled. Remember that pcntxt_mask is | |
476 | * what we write to the XCR0 register. | |
477 | */ | |
478 | WARN_ONCE(!(xfeatures_mask & xstate_feature), | |
479 | "get of unsupported state"); | |
480 | /* | |
481 | * This assumes the last 'xsave*' instruction to | |
482 | * have requested that 'xstate_feature' be saved. | |
483 | * If it did not, we might be seeing and old value | |
484 | * of the field in the buffer. | |
485 | * | |
486 | * This can happen because the last 'xsave' did not | |
487 | * request that this feature be saved (unlikely) | |
488 | * or because the "init optimization" caused it | |
489 | * to not be saved. | |
490 | */ | |
491 | if (!(xsave->header.xfeatures & xstate_feature)) | |
7496d645 FY |
492 | return NULL; |
493 | ||
0c4109be | 494 | return (void *)xsave + xstate_comp_offsets[feature_nr]; |
7496d645 | 495 | } |
ba7b3920 | 496 | EXPORT_SYMBOL_GPL(get_xsave_addr); |
04cd027b DH |
497 | |
498 | /* | |
499 | * This wraps up the common operations that need to occur when retrieving | |
500 | * data from xsave state. It first ensures that the current task was | |
501 | * using the FPU and retrieves the data in to a buffer. It then calculates | |
502 | * the offset of the requested field in the buffer. | |
503 | * | |
504 | * This function is safe to call whether the FPU is in use or not. | |
505 | * | |
506 | * Note that this only works on the current task. | |
507 | * | |
508 | * Inputs: | |
d91cab78 DH |
509 | * @xsave_state: state which is defined in xsave.h (e.g. XFEATURE_MASK_FP, |
510 | * XFEATURE_MASK_SSE, etc...) | |
04cd027b DH |
511 | * Output: |
512 | * address of the state in the xsave area or NULL if the state | |
513 | * is not present or is in its 'init state'. | |
514 | */ | |
515 | const void *get_xsave_field_ptr(int xsave_state) | |
516 | { | |
517 | struct fpu *fpu = ¤t->thread.fpu; | |
518 | ||
519 | if (!fpu->fpstate_active) | |
520 | return NULL; | |
521 | /* | |
522 | * fpu__save() takes the CPU's xstate registers | |
523 | * and saves them off to the 'fpu memory buffer. | |
524 | */ | |
525 | fpu__save(fpu); | |
526 | ||
527 | return get_xsave_addr(&fpu->state.xsave, xsave_state); | |
528 | } |