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Commit | Line | Data |
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dc1e35c6 SS |
1 | /* |
2 | * xsave/xrstor support. | |
3 | * | |
4 | * Author: Suresh Siddha <suresh.b.siddha@intel.com> | |
5 | */ | |
dc1e35c6 | 6 | #include <linux/compat.h> |
7e7ce87f | 7 | #include <linux/cpu.h> |
59a36d16 | 8 | |
df6b35f4 | 9 | #include <asm/fpu/api.h> |
78f7f1e5 | 10 | #include <asm/fpu/internal.h> |
fcbc99c4 | 11 | #include <asm/fpu/signal.h> |
59a36d16 | 12 | #include <asm/fpu/regset.h> |
b992c660 | 13 | |
375074cc | 14 | #include <asm/tlbflush.h> |
dc1e35c6 | 15 | |
1f96b1ef DH |
16 | /* |
17 | * Although we spell it out in here, the Processor Trace | |
18 | * xfeature is completely unused. We use other mechanisms | |
19 | * to save/restore PT state in Linux. | |
20 | */ | |
5b073430 IM |
21 | static const char *xfeature_names[] = |
22 | { | |
23 | "x87 floating point registers" , | |
24 | "SSE registers" , | |
25 | "AVX registers" , | |
26 | "MPX bounds registers" , | |
27 | "MPX CSR" , | |
28 | "AVX-512 opmask" , | |
29 | "AVX-512 Hi256" , | |
30 | "AVX-512 ZMM_Hi256" , | |
1f96b1ef | 31 | "Processor Trace (unused)" , |
5b073430 IM |
32 | }; |
33 | ||
dc1e35c6 | 34 | /* |
614df7fb | 35 | * Mask of xstate features supported by the CPU and the kernel: |
dc1e35c6 | 36 | */ |
5b073430 | 37 | u64 xfeatures_mask __read_mostly; |
dc1e35c6 | 38 | |
dad8c4fe DH |
39 | static unsigned int xstate_offsets[XFEATURE_MAX] = { [ 0 ... XFEATURE_MAX - 1] = -1}; |
40 | static unsigned int xstate_sizes[XFEATURE_MAX] = { [ 0 ... XFEATURE_MAX - 1] = -1}; | |
614df7fb | 41 | static unsigned int xstate_comp_offsets[sizeof(xfeatures_mask)*8]; |
84246fe4 | 42 | |
0a265375 DH |
43 | /* |
44 | * Clear all of the X86_FEATURE_* bits that are unavailable | |
45 | * when the CPU has no XSAVE support. | |
46 | */ | |
47 | void fpu__xstate_clear_all_cpu_caps(void) | |
48 | { | |
49 | setup_clear_cpu_cap(X86_FEATURE_XSAVE); | |
50 | setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT); | |
51 | setup_clear_cpu_cap(X86_FEATURE_XSAVEC); | |
52 | setup_clear_cpu_cap(X86_FEATURE_XSAVES); | |
53 | setup_clear_cpu_cap(X86_FEATURE_AVX); | |
54 | setup_clear_cpu_cap(X86_FEATURE_AVX2); | |
55 | setup_clear_cpu_cap(X86_FEATURE_AVX512F); | |
56 | setup_clear_cpu_cap(X86_FEATURE_AVX512PF); | |
57 | setup_clear_cpu_cap(X86_FEATURE_AVX512ER); | |
58 | setup_clear_cpu_cap(X86_FEATURE_AVX512CD); | |
59 | setup_clear_cpu_cap(X86_FEATURE_MPX); | |
eb7c5f87 | 60 | setup_clear_cpu_cap(X86_FEATURE_XGETBV1); |
0a265375 DH |
61 | } |
62 | ||
5b073430 IM |
63 | /* |
64 | * Return whether the system supports a given xfeature. | |
65 | * | |
66 | * Also return the name of the (most advanced) feature that the caller requested: | |
67 | */ | |
68 | int cpu_has_xfeatures(u64 xfeatures_needed, const char **feature_name) | |
69 | { | |
70 | u64 xfeatures_missing = xfeatures_needed & ~xfeatures_mask; | |
71 | ||
72 | if (unlikely(feature_name)) { | |
73 | long xfeature_idx, max_idx; | |
74 | u64 xfeatures_print; | |
75 | /* | |
76 | * So we use FLS here to be able to print the most advanced | |
77 | * feature that was requested but is missing. So if a driver | |
d91cab78 | 78 | * asks about "XFEATURE_MASK_SSE | XFEATURE_MASK_YMM" we'll print the |
5b073430 IM |
79 | * missing AVX feature - this is the most informative message |
80 | * to users: | |
81 | */ | |
82 | if (xfeatures_missing) | |
83 | xfeatures_print = xfeatures_missing; | |
84 | else | |
85 | xfeatures_print = xfeatures_needed; | |
86 | ||
87 | xfeature_idx = fls64(xfeatures_print)-1; | |
88 | max_idx = ARRAY_SIZE(xfeature_names)-1; | |
89 | xfeature_idx = min(xfeature_idx, max_idx); | |
90 | ||
91 | *feature_name = xfeature_names[xfeature_idx]; | |
92 | } | |
93 | ||
94 | if (xfeatures_missing) | |
95 | return 0; | |
96 | ||
97 | return 1; | |
98 | } | |
99 | EXPORT_SYMBOL_GPL(cpu_has_xfeatures); | |
100 | ||
29104e10 | 101 | /* |
aeb997b9 IM |
102 | * When executing XSAVEOPT (or other optimized XSAVE instructions), if |
103 | * a processor implementation detects that an FPU state component is still | |
104 | * (or is again) in its initialized state, it may clear the corresponding | |
105 | * bit in the header.xfeatures field, and can skip the writeout of registers | |
106 | * to the corresponding memory layout. | |
73a3aeb3 IM |
107 | * |
108 | * This means that when the bit is zero, the state component might still contain | |
109 | * some previous - non-initialized register state. | |
110 | * | |
111 | * Before writing xstate information to user-space we sanitize those components, | |
112 | * to always ensure that the memory layout of a feature will be in the init state | |
113 | * if the corresponding header bit is zero. This is to ensure that user-space doesn't | |
114 | * see some stale state in the memory layout during signal handling, debugging etc. | |
29104e10 | 115 | */ |
36e49e7f | 116 | void fpstate_sanitize_xstate(struct fpu *fpu) |
29104e10 | 117 | { |
c47ada30 | 118 | struct fxregs_state *fx = &fpu->state.fxsave; |
73a3aeb3 | 119 | int feature_bit; |
400e4b20 | 120 | u64 xfeatures; |
29104e10 | 121 | |
1ac91a76 | 122 | if (!use_xsaveopt()) |
29104e10 SS |
123 | return; |
124 | ||
36e49e7f | 125 | xfeatures = fpu->state.xsave.header.xfeatures; |
29104e10 SS |
126 | |
127 | /* | |
128 | * None of the feature bits are in init state. So nothing else | |
0d2eb44f | 129 | * to do for us, as the memory layout is up to date. |
29104e10 | 130 | */ |
400e4b20 | 131 | if ((xfeatures & xfeatures_mask) == xfeatures_mask) |
29104e10 SS |
132 | return; |
133 | ||
134 | /* | |
135 | * FP is in init state | |
136 | */ | |
d91cab78 | 137 | if (!(xfeatures & XFEATURE_MASK_FP)) { |
29104e10 SS |
138 | fx->cwd = 0x37f; |
139 | fx->swd = 0; | |
140 | fx->twd = 0; | |
141 | fx->fop = 0; | |
142 | fx->rip = 0; | |
143 | fx->rdp = 0; | |
144 | memset(&fx->st_space[0], 0, 128); | |
145 | } | |
146 | ||
147 | /* | |
148 | * SSE is in init state | |
149 | */ | |
d91cab78 | 150 | if (!(xfeatures & XFEATURE_MASK_SSE)) |
29104e10 SS |
151 | memset(&fx->xmm_space[0], 0, 256); |
152 | ||
73a3aeb3 IM |
153 | /* |
154 | * First two features are FPU and SSE, which above we handled | |
155 | * in a special way already: | |
156 | */ | |
157 | feature_bit = 0x2; | |
400e4b20 | 158 | xfeatures = (xfeatures_mask & ~xfeatures) >> 2; |
29104e10 SS |
159 | |
160 | /* | |
73a3aeb3 IM |
161 | * Update all the remaining memory layouts according to their |
162 | * standard xstate layout, if their header bit is in the init | |
163 | * state: | |
29104e10 | 164 | */ |
400e4b20 IM |
165 | while (xfeatures) { |
166 | if (xfeatures & 0x1) { | |
29104e10 SS |
167 | int offset = xstate_offsets[feature_bit]; |
168 | int size = xstate_sizes[feature_bit]; | |
169 | ||
73a3aeb3 | 170 | memcpy((void *)fx + offset, |
6f575023 | 171 | (void *)&init_fpstate.xsave + offset, |
29104e10 SS |
172 | size); |
173 | } | |
174 | ||
400e4b20 | 175 | xfeatures >>= 1; |
29104e10 SS |
176 | feature_bit++; |
177 | } | |
178 | } | |
179 | ||
dc1e35c6 | 180 | /* |
55cc4678 IM |
181 | * Enable the extended processor state save/restore feature. |
182 | * Called once per CPU onlining. | |
dc1e35c6 | 183 | */ |
55cc4678 | 184 | void fpu__init_cpu_xstate(void) |
dc1e35c6 | 185 | { |
e84611fc | 186 | if (!cpu_has_xsave || !xfeatures_mask) |
55cc4678 IM |
187 | return; |
188 | ||
375074cc | 189 | cr4_set_bits(X86_CR4_OSXSAVE); |
614df7fb | 190 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); |
dc1e35c6 SS |
191 | } |
192 | ||
e6e888f9 DH |
193 | /* |
194 | * Note that in the future we will likely need a pair of | |
195 | * functions here: one for user xstates and the other for | |
196 | * system xstates. For now, they are the same. | |
197 | */ | |
198 | static int xfeature_enabled(enum xfeature xfeature) | |
199 | { | |
200 | return !!(xfeatures_mask & (1UL << xfeature)); | |
201 | } | |
202 | ||
a1488f8b | 203 | /* |
39f1acd2 IM |
204 | * Record the offsets and sizes of various xstates contained |
205 | * in the XSAVE state memory layout. | |
a1488f8b | 206 | */ |
4995b9db | 207 | static void __init setup_xstate_features(void) |
a1488f8b | 208 | { |
ee9ae257 | 209 | u32 eax, ebx, ecx, edx, i; |
e6e888f9 DH |
210 | /* start at the beginnning of the "extended state" */ |
211 | unsigned int last_good_offset = offsetof(struct xregs_state, | |
212 | extended_state_area); | |
a1488f8b | 213 | |
ee9ae257 | 214 | for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) { |
e6e888f9 DH |
215 | if (!xfeature_enabled(i)) |
216 | continue; | |
a1488f8b | 217 | |
e6e888f9 | 218 | cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx); |
ee9ae257 DH |
219 | xstate_offsets[i] = ebx; |
220 | xstate_sizes[i] = eax; | |
e6e888f9 DH |
221 | /* |
222 | * In our xstate size checks, we assume that the | |
223 | * highest-numbered xstate feature has the | |
224 | * highest offset in the buffer. Ensure it does. | |
225 | */ | |
226 | WARN_ONCE(last_good_offset > xstate_offsets[i], | |
227 | "x86/fpu: misordered xstate at %d\n", last_good_offset); | |
228 | last_good_offset = xstate_offsets[i]; | |
a1488f8b | 229 | |
ee9ae257 | 230 | printk(KERN_INFO "x86/fpu: xstate_offset[%d]: %4d, xstate_sizes[%d]: %4d\n", i, ebx, i, eax); |
39f1acd2 | 231 | } |
a1488f8b SS |
232 | } |
233 | ||
32231879 | 234 | static void __init print_xstate_feature(u64 xstate_mask) |
69496e10 | 235 | { |
33588b52 | 236 | const char *feature_name; |
69496e10 | 237 | |
33588b52 IM |
238 | if (cpu_has_xfeatures(xstate_mask, &feature_name)) |
239 | pr_info("x86/fpu: Supporting XSAVE feature 0x%02Lx: '%s'\n", xstate_mask, feature_name); | |
69496e10 IM |
240 | } |
241 | ||
242 | /* | |
243 | * Print out all the supported xstate features: | |
244 | */ | |
32231879 | 245 | static void __init print_xstate_features(void) |
69496e10 | 246 | { |
d91cab78 DH |
247 | print_xstate_feature(XFEATURE_MASK_FP); |
248 | print_xstate_feature(XFEATURE_MASK_SSE); | |
249 | print_xstate_feature(XFEATURE_MASK_YMM); | |
250 | print_xstate_feature(XFEATURE_MASK_BNDREGS); | |
251 | print_xstate_feature(XFEATURE_MASK_BNDCSR); | |
252 | print_xstate_feature(XFEATURE_MASK_OPMASK); | |
253 | print_xstate_feature(XFEATURE_MASK_ZMM_Hi256); | |
254 | print_xstate_feature(XFEATURE_MASK_Hi16_ZMM); | |
69496e10 IM |
255 | } |
256 | ||
7496d645 FY |
257 | /* |
258 | * This function sets up offsets and sizes of all extended states in | |
259 | * xsave area. This supports both standard format and compacted format | |
260 | * of the xsave aread. | |
7496d645 | 261 | */ |
32231879 | 262 | static void __init setup_xstate_comp(void) |
7496d645 | 263 | { |
614df7fb | 264 | unsigned int xstate_comp_sizes[sizeof(xfeatures_mask)*8]; |
7496d645 FY |
265 | int i; |
266 | ||
8ff925e1 FY |
267 | /* |
268 | * The FP xstates and SSE xstates are legacy states. They are always | |
269 | * in the fixed offsets in the xsave area in either compacted form | |
270 | * or standard form. | |
271 | */ | |
272 | xstate_comp_offsets[0] = 0; | |
c47ada30 | 273 | xstate_comp_offsets[1] = offsetof(struct fxregs_state, xmm_space); |
7496d645 FY |
274 | |
275 | if (!cpu_has_xsaves) { | |
ee9ae257 | 276 | for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) { |
633d54c4 | 277 | if (xfeature_enabled(i)) { |
7496d645 FY |
278 | xstate_comp_offsets[i] = xstate_offsets[i]; |
279 | xstate_comp_sizes[i] = xstate_sizes[i]; | |
280 | } | |
281 | } | |
282 | return; | |
283 | } | |
284 | ||
8a93c9e0 DH |
285 | xstate_comp_offsets[FIRST_EXTENDED_XFEATURE] = |
286 | FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
7496d645 | 287 | |
ee9ae257 | 288 | for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) { |
633d54c4 | 289 | if (xfeature_enabled(i)) |
7496d645 FY |
290 | xstate_comp_sizes[i] = xstate_sizes[i]; |
291 | else | |
292 | xstate_comp_sizes[i] = 0; | |
293 | ||
8a93c9e0 | 294 | if (i > FIRST_EXTENDED_XFEATURE) |
7496d645 FY |
295 | xstate_comp_offsets[i] = xstate_comp_offsets[i-1] |
296 | + xstate_comp_sizes[i-1]; | |
297 | ||
298 | } | |
299 | } | |
300 | ||
dc1e35c6 SS |
301 | /* |
302 | * setup the xstate image representing the init state | |
303 | */ | |
32231879 | 304 | static void __init setup_init_fpu_buf(void) |
dc1e35c6 | 305 | { |
e49a449b | 306 | static int on_boot_cpu __initdata = 1; |
e97131a8 IM |
307 | |
308 | WARN_ON_FPU(!on_boot_cpu); | |
309 | on_boot_cpu = 0; | |
310 | ||
5d2bd700 SS |
311 | if (!cpu_has_xsave) |
312 | return; | |
313 | ||
314 | setup_xstate_features(); | |
69496e10 | 315 | print_xstate_features(); |
a1488f8b | 316 | |
47c2f292 | 317 | if (cpu_has_xsaves) { |
6f575023 IM |
318 | init_fpstate.xsave.header.xcomp_bv = (u64)1 << 63 | xfeatures_mask; |
319 | init_fpstate.xsave.header.xfeatures = xfeatures_mask; | |
47c2f292 FY |
320 | } |
321 | ||
29104e10 SS |
322 | /* |
323 | * Init all the features state with header_bv being 0x0 | |
324 | */ | |
d65fcd60 | 325 | copy_kernel_to_xregs_booting(&init_fpstate.xsave); |
3e261c14 | 326 | |
29104e10 SS |
327 | /* |
328 | * Dump the init state again. This is to identify the init state | |
329 | * of any feature which is not represented by all zero's. | |
330 | */ | |
c6813144 | 331 | copy_xregs_to_kernel_booting(&init_fpstate.xsave); |
dc1e35c6 SS |
332 | } |
333 | ||
65ac2e9b DH |
334 | static int xfeature_is_supervisor(int xfeature_nr) |
335 | { | |
336 | /* | |
337 | * We currently do not support supervisor states, but if | |
338 | * we did, we could find out like this. | |
339 | * | |
340 | * SDM says: If state component i is a user state component, | |
341 | * ECX[0] return 0; if state component i is a supervisor | |
342 | * state component, ECX[0] returns 1. | |
343 | u32 eax, ebx, ecx, edx; | |
344 | cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx; | |
345 | return !!(ecx & 1); | |
346 | */ | |
347 | return 0; | |
348 | } | |
349 | /* | |
350 | static int xfeature_is_user(int xfeature_nr) | |
351 | { | |
352 | return !xfeature_is_supervisor(xfeature_nr); | |
353 | } | |
354 | */ | |
355 | ||
356 | /* | |
357 | * This check is important because it is easy to get XSTATE_* | |
358 | * confused with XSTATE_BIT_*. | |
359 | */ | |
360 | #define CHECK_XFEATURE(nr) do { \ | |
361 | WARN_ON(nr < FIRST_EXTENDED_XFEATURE); \ | |
362 | WARN_ON(nr >= XFEATURE_MAX); \ | |
363 | } while (0) | |
364 | ||
365 | /* | |
366 | * We could cache this like xstate_size[], but we only use | |
367 | * it here, so it would be a waste of space. | |
368 | */ | |
369 | static int xfeature_is_aligned(int xfeature_nr) | |
370 | { | |
371 | u32 eax, ebx, ecx, edx; | |
372 | ||
373 | CHECK_XFEATURE(xfeature_nr); | |
374 | cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx); | |
375 | /* | |
376 | * The value returned by ECX[1] indicates the alignment | |
377 | * of state component i when the compacted format | |
378 | * of the extended region of an XSAVE area is used | |
379 | */ | |
380 | return !!(ecx & 2); | |
381 | } | |
382 | ||
383 | static int xfeature_uncompacted_offset(int xfeature_nr) | |
384 | { | |
385 | u32 eax, ebx, ecx, edx; | |
386 | ||
387 | CHECK_XFEATURE(xfeature_nr); | |
388 | cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx); | |
389 | return ebx; | |
390 | } | |
391 | ||
392 | static int xfeature_size(int xfeature_nr) | |
393 | { | |
394 | u32 eax, ebx, ecx, edx; | |
395 | ||
396 | CHECK_XFEATURE(xfeature_nr); | |
397 | cpuid_count(XSTATE_CPUID, xfeature_nr, &eax, &ebx, &ecx, &edx); | |
398 | return eax; | |
399 | } | |
400 | ||
401 | /* | |
402 | * 'XSAVES' implies two different things: | |
403 | * 1. saving of supervisor/system state | |
404 | * 2. using the compacted format | |
405 | * | |
406 | * Use this function when dealing with the compacted format so | |
407 | * that it is obvious which aspect of 'XSAVES' is being handled | |
408 | * by the calling code. | |
409 | */ | |
410 | static int using_compacted_format(void) | |
411 | { | |
412 | return cpu_has_xsaves; | |
413 | } | |
414 | ||
415 | static void __xstate_dump_leaves(void) | |
416 | { | |
417 | int i; | |
418 | u32 eax, ebx, ecx, edx; | |
419 | static int should_dump = 1; | |
420 | ||
421 | if (!should_dump) | |
422 | return; | |
423 | should_dump = 0; | |
424 | /* | |
425 | * Dump out a few leaves past the ones that we support | |
426 | * just in case there are some goodies up there | |
427 | */ | |
428 | for (i = 0; i < XFEATURE_MAX + 10; i++) { | |
429 | cpuid_count(XSTATE_CPUID, i, &eax, &ebx, &ecx, &edx); | |
430 | pr_warn("CPUID[%02x, %02x]: eax=%08x ebx=%08x ecx=%08x edx=%08x\n", | |
431 | XSTATE_CPUID, i, eax, ebx, ecx, edx); | |
432 | } | |
433 | } | |
434 | ||
435 | #define XSTATE_WARN_ON(x) do { \ | |
436 | if (WARN_ONCE(x, "XSAVE consistency problem, dumping leaves")) { \ | |
437 | __xstate_dump_leaves(); \ | |
438 | } \ | |
439 | } while (0) | |
440 | ||
ef78f2a4 DH |
441 | #define XCHECK_SZ(sz, nr, nr_macro, __struct) do { \ |
442 | if ((nr == nr_macro) && \ | |
443 | WARN_ONCE(sz != sizeof(__struct), \ | |
444 | "%s: struct is %zu bytes, cpu state %d bytes\n", \ | |
445 | __stringify(nr_macro), sizeof(__struct), sz)) { \ | |
446 | __xstate_dump_leaves(); \ | |
447 | } \ | |
448 | } while (0) | |
449 | ||
450 | /* | |
451 | * We have a C struct for each 'xstate'. We need to ensure | |
452 | * that our software representation matches what the CPU | |
453 | * tells us about the state's size. | |
454 | */ | |
455 | static void check_xstate_against_struct(int nr) | |
456 | { | |
457 | /* | |
458 | * Ask the CPU for the size of the state. | |
459 | */ | |
460 | int sz = xfeature_size(nr); | |
461 | /* | |
462 | * Match each CPU state with the corresponding software | |
463 | * structure. | |
464 | */ | |
465 | XCHECK_SZ(sz, nr, XFEATURE_YMM, struct ymmh_struct); | |
466 | XCHECK_SZ(sz, nr, XFEATURE_BNDREGS, struct mpx_bndreg_state); | |
467 | XCHECK_SZ(sz, nr, XFEATURE_BNDCSR, struct mpx_bndcsr_state); | |
468 | XCHECK_SZ(sz, nr, XFEATURE_OPMASK, struct avx_512_opmask_state); | |
469 | XCHECK_SZ(sz, nr, XFEATURE_ZMM_Hi256, struct avx_512_zmm_uppers_state); | |
470 | XCHECK_SZ(sz, nr, XFEATURE_Hi16_ZMM, struct avx_512_hi16_state); | |
471 | ||
472 | /* | |
473 | * Make *SURE* to add any feature numbers in below if | |
474 | * there are "holes" in the xsave state component | |
475 | * numbers. | |
476 | */ | |
477 | if ((nr < XFEATURE_YMM) || | |
1f96b1ef DH |
478 | (nr >= XFEATURE_MAX) || |
479 | (nr == XFEATURE_PT_UNIMPLEMENTED_SO_FAR)) { | |
ef78f2a4 DH |
480 | WARN_ONCE(1, "no structure for xstate: %d\n", nr); |
481 | XSTATE_WARN_ON(1); | |
482 | } | |
483 | } | |
484 | ||
65ac2e9b DH |
485 | /* |
486 | * This essentially double-checks what the cpu told us about | |
487 | * how large the XSAVE buffer needs to be. We are recalculating | |
488 | * it to be safe. | |
489 | */ | |
490 | static void do_extra_xstate_size_checks(void) | |
491 | { | |
492 | int paranoid_xstate_size = FXSAVE_SIZE + XSAVE_HDR_SIZE; | |
493 | int i; | |
494 | ||
495 | for (i = FIRST_EXTENDED_XFEATURE; i < XFEATURE_MAX; i++) { | |
496 | if (!xfeature_enabled(i)) | |
497 | continue; | |
ef78f2a4 DH |
498 | |
499 | check_xstate_against_struct(i); | |
65ac2e9b DH |
500 | /* |
501 | * Supervisor state components can be managed only by | |
502 | * XSAVES, which is compacted-format only. | |
503 | */ | |
504 | if (!using_compacted_format()) | |
505 | XSTATE_WARN_ON(xfeature_is_supervisor(i)); | |
506 | ||
507 | /* Align from the end of the previous feature */ | |
508 | if (xfeature_is_aligned(i)) | |
509 | paranoid_xstate_size = ALIGN(paranoid_xstate_size, 64); | |
510 | /* | |
511 | * The offset of a given state in the non-compacted | |
512 | * format is given to us in a CPUID leaf. We check | |
513 | * them for being ordered (increasing offsets) in | |
514 | * setup_xstate_features(). | |
515 | */ | |
516 | if (!using_compacted_format()) | |
517 | paranoid_xstate_size = xfeature_uncompacted_offset(i); | |
518 | /* | |
519 | * The compacted-format offset always depends on where | |
520 | * the previous state ended. | |
521 | */ | |
522 | paranoid_xstate_size += xfeature_size(i); | |
523 | } | |
524 | XSTATE_WARN_ON(paranoid_xstate_size != xstate_size); | |
525 | } | |
526 | ||
7e7ce87f | 527 | /* |
614df7fb | 528 | * Calculate total size of enabled xstates in XCR0/xfeatures_mask. |
65ac2e9b DH |
529 | * |
530 | * Note the SDM's wording here. "sub-function 0" only enumerates | |
531 | * the size of the *user* states. If we use it to size a buffer | |
532 | * that we use 'XSAVES' on, we could potentially overflow the | |
533 | * buffer because 'XSAVES' saves system states too. | |
534 | * | |
535 | * Note that we do not currently set any bits on IA32_XSS so | |
536 | * 'XCR0 | IA32_XSS == XCR0' for now. | |
7e7ce87f | 537 | */ |
4109ca06 | 538 | static unsigned int __init calculate_xstate_size(void) |
7e7ce87f FY |
539 | { |
540 | unsigned int eax, ebx, ecx, edx; | |
4109ca06 | 541 | unsigned int calculated_xstate_size; |
7e7ce87f FY |
542 | |
543 | if (!cpu_has_xsaves) { | |
65ac2e9b DH |
544 | /* |
545 | * - CPUID function 0DH, sub-function 0: | |
546 | * EBX enumerates the size (in bytes) required by | |
547 | * the XSAVE instruction for an XSAVE area | |
548 | * containing all the *user* state components | |
549 | * corresponding to bits currently set in XCR0. | |
550 | */ | |
7e7ce87f | 551 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); |
4109ca06 | 552 | calculated_xstate_size = ebx; |
65ac2e9b DH |
553 | } else { |
554 | /* | |
555 | * - CPUID function 0DH, sub-function 1: | |
556 | * EBX enumerates the size (in bytes) required by | |
557 | * the XSAVES instruction for an XSAVE area | |
558 | * containing all the state components | |
559 | * corresponding to bits currently set in | |
560 | * XCR0 | IA32_XSS. | |
561 | */ | |
562 | cpuid_count(XSTATE_CPUID, 1, &eax, &ebx, &ecx, &edx); | |
563 | calculated_xstate_size = ebx; | |
7e7ce87f | 564 | } |
4109ca06 DH |
565 | return calculated_xstate_size; |
566 | } | |
567 | ||
568 | /* | |
569 | * Will the runtime-enumerated 'xstate_size' fit in the init | |
570 | * task's statically-allocated buffer? | |
571 | */ | |
572 | static bool is_supported_xstate_size(unsigned int test_xstate_size) | |
573 | { | |
574 | if (test_xstate_size <= sizeof(union fpregs_state)) | |
575 | return true; | |
576 | ||
577 | pr_warn("x86/fpu: xstate buffer too small (%zu < %d), disabling xsave\n", | |
578 | sizeof(union fpregs_state), test_xstate_size); | |
579 | return false; | |
580 | } | |
581 | ||
582 | static int init_xstate_size(void) | |
583 | { | |
584 | /* Recompute the context size for enabled features: */ | |
585 | unsigned int possible_xstate_size = calculate_xstate_size(); | |
586 | ||
587 | /* Ensure we have the space to store all enabled: */ | |
588 | if (!is_supported_xstate_size(possible_xstate_size)) | |
589 | return -EINVAL; | |
590 | ||
591 | /* | |
592 | * The size is OK, we are definitely going to use xsave, | |
593 | * make it known to the world that we need more space. | |
594 | */ | |
595 | xstate_size = possible_xstate_size; | |
65ac2e9b | 596 | do_extra_xstate_size_checks(); |
4109ca06 DH |
597 | return 0; |
598 | } | |
599 | ||
d91cab78 DH |
600 | /* |
601 | * We enabled the XSAVE hardware, but something went wrong and | |
602 | * we can not use it. Disable it. | |
603 | */ | |
604 | static void fpu__init_disable_system_xstate(void) | |
4109ca06 DH |
605 | { |
606 | xfeatures_mask = 0; | |
607 | cr4_clear_bits(X86_CR4_OSXSAVE); | |
608 | fpu__xstate_clear_all_cpu_caps(); | |
7e7ce87f FY |
609 | } |
610 | ||
dc1e35c6 SS |
611 | /* |
612 | * Enable and initialize the xsave feature. | |
55cc4678 | 613 | * Called once per system bootup. |
dc1e35c6 | 614 | */ |
32231879 | 615 | void __init fpu__init_system_xstate(void) |
dc1e35c6 SS |
616 | { |
617 | unsigned int eax, ebx, ecx, edx; | |
e49a449b | 618 | static int on_boot_cpu __initdata = 1; |
4109ca06 | 619 | int err; |
e97131a8 IM |
620 | |
621 | WARN_ON_FPU(!on_boot_cpu); | |
622 | on_boot_cpu = 0; | |
dc1e35c6 | 623 | |
e9dbfd67 IM |
624 | if (!cpu_has_xsave) { |
625 | pr_info("x86/fpu: Legacy x87 FPU detected.\n"); | |
626 | return; | |
627 | } | |
628 | ||
ee813d53 | 629 | if (boot_cpu_data.cpuid_level < XSTATE_CPUID) { |
e97131a8 | 630 | WARN_ON_FPU(1); |
ee813d53 RR |
631 | return; |
632 | } | |
633 | ||
634 | cpuid_count(XSTATE_CPUID, 0, &eax, &ebx, &ecx, &edx); | |
614df7fb | 635 | xfeatures_mask = eax + ((u64)edx << 32); |
dc1e35c6 | 636 | |
d91cab78 | 637 | if ((xfeatures_mask & XFEATURE_MASK_FPSSE) != XFEATURE_MASK_FPSSE) { |
614df7fb | 638 | pr_err("x86/fpu: FP/SSE not present amongst the CPU's xstate features: 0x%llx.\n", xfeatures_mask); |
dc1e35c6 SS |
639 | BUG(); |
640 | } | |
641 | ||
a5fe93a5 | 642 | xfeatures_mask &= fpu__get_supported_xfeatures_mask(); |
97e80a70 | 643 | |
55cc4678 IM |
644 | /* Enable xstate instructions to be able to continue with initialization: */ |
645 | fpu__init_cpu_xstate(); | |
4109ca06 DH |
646 | err = init_xstate_size(); |
647 | if (err) { | |
648 | /* something went wrong, boot without any XSAVE support */ | |
649 | fpu__init_disable_system_xstate(); | |
650 | return; | |
651 | } | |
dc1e35c6 | 652 | |
614df7fb | 653 | update_regset_xstate_info(xstate_size, xfeatures_mask); |
b992c660 | 654 | fpu__init_prepare_fx_sw_frame(); |
5d2bd700 | 655 | setup_init_fpu_buf(); |
5fd402df | 656 | setup_xstate_comp(); |
dc1e35c6 | 657 | |
b0815359 | 658 | pr_info("x86/fpu: Enabled xstate features 0x%llx, context size is %d bytes, using '%s' format.\n", |
614df7fb | 659 | xfeatures_mask, |
32d4d9cc IM |
660 | xstate_size, |
661 | cpu_has_xsaves ? "compacted" : "standard"); | |
dc1e35c6 | 662 | } |
82d4150c | 663 | |
9254aaa0 IM |
664 | /* |
665 | * Restore minimal FPU state after suspend: | |
666 | */ | |
667 | void fpu__resume_cpu(void) | |
668 | { | |
669 | /* | |
670 | * Restore XCR0 on xsave capable CPUs: | |
671 | */ | |
672 | if (cpu_has_xsave) | |
673 | xsetbv(XCR_XFEATURE_ENABLED_MASK, xfeatures_mask); | |
674 | } | |
675 | ||
7496d645 FY |
676 | /* |
677 | * Given the xsave area and a state inside, this function returns the | |
678 | * address of the state. | |
679 | * | |
680 | * This is the API that is called to get xstate address in either | |
681 | * standard format or compacted format of xsave area. | |
682 | * | |
0c4109be DH |
683 | * Note that if there is no data for the field in the xsave buffer |
684 | * this will return NULL. | |
685 | * | |
7496d645 | 686 | * Inputs: |
0c4109be DH |
687 | * xstate: the thread's storage area for all FPU data |
688 | * xstate_feature: state which is defined in xsave.h (e.g. | |
d91cab78 | 689 | * XFEATURE_MASK_FP, XFEATURE_MASK_SSE, etc...) |
7496d645 | 690 | * Output: |
0c4109be DH |
691 | * address of the state in the xsave area, or NULL if the |
692 | * field is not present in the xsave buffer. | |
7496d645 | 693 | */ |
0c4109be | 694 | void *get_xsave_addr(struct xregs_state *xsave, int xstate_feature) |
7496d645 | 695 | { |
0c4109be DH |
696 | int feature_nr = fls64(xstate_feature) - 1; |
697 | /* | |
698 | * Do we even *have* xsave state? | |
699 | */ | |
700 | if (!boot_cpu_has(X86_FEATURE_XSAVE)) | |
701 | return NULL; | |
702 | ||
0c4109be DH |
703 | /* |
704 | * We should not ever be requesting features that we | |
705 | * have not enabled. Remember that pcntxt_mask is | |
706 | * what we write to the XCR0 register. | |
707 | */ | |
708 | WARN_ONCE(!(xfeatures_mask & xstate_feature), | |
709 | "get of unsupported state"); | |
710 | /* | |
711 | * This assumes the last 'xsave*' instruction to | |
712 | * have requested that 'xstate_feature' be saved. | |
713 | * If it did not, we might be seeing and old value | |
714 | * of the field in the buffer. | |
715 | * | |
716 | * This can happen because the last 'xsave' did not | |
717 | * request that this feature be saved (unlikely) | |
718 | * or because the "init optimization" caused it | |
719 | * to not be saved. | |
720 | */ | |
721 | if (!(xsave->header.xfeatures & xstate_feature)) | |
7496d645 FY |
722 | return NULL; |
723 | ||
0c4109be | 724 | return (void *)xsave + xstate_comp_offsets[feature_nr]; |
7496d645 | 725 | } |
ba7b3920 | 726 | EXPORT_SYMBOL_GPL(get_xsave_addr); |
04cd027b DH |
727 | |
728 | /* | |
729 | * This wraps up the common operations that need to occur when retrieving | |
730 | * data from xsave state. It first ensures that the current task was | |
731 | * using the FPU and retrieves the data in to a buffer. It then calculates | |
732 | * the offset of the requested field in the buffer. | |
733 | * | |
734 | * This function is safe to call whether the FPU is in use or not. | |
735 | * | |
736 | * Note that this only works on the current task. | |
737 | * | |
738 | * Inputs: | |
d91cab78 DH |
739 | * @xsave_state: state which is defined in xsave.h (e.g. XFEATURE_MASK_FP, |
740 | * XFEATURE_MASK_SSE, etc...) | |
04cd027b DH |
741 | * Output: |
742 | * address of the state in the xsave area or NULL if the state | |
743 | * is not present or is in its 'init state'. | |
744 | */ | |
745 | const void *get_xsave_field_ptr(int xsave_state) | |
746 | { | |
747 | struct fpu *fpu = ¤t->thread.fpu; | |
748 | ||
749 | if (!fpu->fpstate_active) | |
750 | return NULL; | |
751 | /* | |
752 | * fpu__save() takes the CPU's xstate registers | |
753 | * and saves them off to the 'fpu memory buffer. | |
754 | */ | |
755 | fpu__save(fpu); | |
756 | ||
757 | return get_xsave_addr(&fpu->state.xsave, xsave_state); | |
758 | } |