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Commit | Line | Data |
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1da177e4 | 1 | /* |
1da177e4 LT |
2 | * |
3 | * Copyright (C) 1991, 1992 Linus Torvalds | |
4 | * | |
5 | * Enhanced CPU detection and feature setting code by Mike Jagdis | |
6 | * and Martin Mares, November 1997. | |
7 | */ | |
8 | ||
9 | .text | |
1da177e4 | 10 | #include <linux/threads.h> |
8b2f7fff | 11 | #include <linux/init.h> |
1da177e4 LT |
12 | #include <linux/linkage.h> |
13 | #include <asm/segment.h> | |
0341c14d JF |
14 | #include <asm/page_types.h> |
15 | #include <asm/pgtable_types.h> | |
1da177e4 LT |
16 | #include <asm/cache.h> |
17 | #include <asm/thread_info.h> | |
86feeaa8 | 18 | #include <asm/asm-offsets.h> |
1da177e4 | 19 | #include <asm/setup.h> |
551889a6 | 20 | #include <asm/processor-flags.h> |
8a50e513 PA |
21 | #include <asm/msr-index.h> |
22 | #include <asm/cpufeature.h> | |
60a5317f | 23 | #include <asm/percpu.h> |
551889a6 IC |
24 | |
25 | /* Physical address */ | |
26 | #define pa(X) ((X) - __PAGE_OFFSET) | |
1da177e4 LT |
27 | |
28 | /* | |
29 | * References to members of the new_cpu_data structure. | |
30 | */ | |
31 | ||
32 | #define X86 new_cpu_data+CPUINFO_x86 | |
33 | #define X86_VENDOR new_cpu_data+CPUINFO_x86_vendor | |
34 | #define X86_MODEL new_cpu_data+CPUINFO_x86_model | |
35 | #define X86_MASK new_cpu_data+CPUINFO_x86_mask | |
36 | #define X86_HARD_MATH new_cpu_data+CPUINFO_hard_math | |
37 | #define X86_CPUID new_cpu_data+CPUINFO_cpuid_level | |
38 | #define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability | |
39 | #define X86_VENDOR_ID new_cpu_data+CPUINFO_x86_vendor_id | |
40 | ||
41 | /* | |
c090f532 JF |
42 | * This is how much memory in addition to the memory covered up to |
43 | * and including _end we need mapped initially. | |
9ce8c2ed | 44 | * We need: |
2bd2753f YL |
45 | * (KERNEL_IMAGE_SIZE/4096) / 1024 pages (worst case, non PAE) |
46 | * (KERNEL_IMAGE_SIZE/4096) / 512 + 4 pages (worst case for PAE) | |
1da177e4 LT |
47 | * |
48 | * Modulo rounding, each megabyte assigned here requires a kilobyte of | |
49 | * memory, which is currently unreclaimed. | |
50 | * | |
51 | * This should be a multiple of a page. | |
2bd2753f YL |
52 | * |
53 | * KERNEL_IMAGE_SIZE should be greater than pa(_end) | |
54 | * and small than max_low_pfn, otherwise will waste some page table entries | |
1da177e4 | 55 | */ |
1da177e4 | 56 | |
9ce8c2ed | 57 | #if PTRS_PER_PMD > 1 |
c090f532 | 58 | #define PAGE_TABLE_SIZE(pages) (((pages) / PTRS_PER_PMD) + PTRS_PER_PGD) |
9ce8c2ed | 59 | #else |
c090f532 | 60 | #define PAGE_TABLE_SIZE(pages) ((pages) / PTRS_PER_PGD) |
9ce8c2ed | 61 | #endif |
9ce8c2ed | 62 | |
c090f532 | 63 | /* Enough space to fit pagetables for the low memory linear map */ |
60ac9821 PA |
64 | MAPPING_BEYOND_END = \ |
65 | PAGE_TABLE_SIZE(((1<<32) - __PAGE_OFFSET) >> PAGE_SHIFT) << PAGE_SHIFT | |
c090f532 JF |
66 | |
67 | /* | |
68 | * Worst-case size of the kernel mapping we need to make: | |
69 | * the worst-case size of the kernel itself, plus the extra we need | |
70 | * to map for the linear map. | |
71 | */ | |
72 | KERNEL_PAGES = (KERNEL_IMAGE_SIZE + MAPPING_BEYOND_END)>>PAGE_SHIFT | |
73 | ||
b8a22a62 | 74 | INIT_MAP_SIZE = PAGE_TABLE_SIZE(KERNEL_PAGES) * PAGE_SIZE_asm |
2bd2753f | 75 | RESERVE_BRK(pagetables, INIT_MAP_SIZE) |
796216a5 | 76 | |
1da177e4 LT |
77 | /* |
78 | * 32-bit kernel entrypoint; only used by the boot CPU. On entry, | |
79 | * %esi points to the real-mode code as a 32-bit pointer. | |
80 | * CS and DS must be 4 GB flat segments, but we don't depend on | |
81 | * any particular GDT layout, because we load our own as soon as we | |
82 | * can. | |
83 | */ | |
4ae59b91 | 84 | __HEAD |
1da177e4 | 85 | ENTRY(startup_32) |
a24e7851 RR |
86 | /* test KEEP_SEGMENTS flag to see if the bootloader is asking |
87 | us to not reload segments */ | |
88 | testb $(1<<6), BP_loadflags(%esi) | |
89 | jnz 2f | |
1da177e4 LT |
90 | |
91 | /* | |
92 | * Set segments to known values. | |
93 | */ | |
551889a6 | 94 | lgdt pa(boot_gdt_descr) |
1da177e4 LT |
95 | movl $(__BOOT_DS),%eax |
96 | movl %eax,%ds | |
97 | movl %eax,%es | |
98 | movl %eax,%fs | |
99 | movl %eax,%gs | |
a24e7851 | 100 | 2: |
1da177e4 LT |
101 | |
102 | /* | |
103 | * Clear BSS first so that there are no surprises... | |
1da177e4 | 104 | */ |
a24e7851 | 105 | cld |
1da177e4 | 106 | xorl %eax,%eax |
551889a6 IC |
107 | movl $pa(__bss_start),%edi |
108 | movl $pa(__bss_stop),%ecx | |
1da177e4 LT |
109 | subl %edi,%ecx |
110 | shrl $2,%ecx | |
111 | rep ; stosl | |
484b90c4 VG |
112 | /* |
113 | * Copy bootup parameters out of the way. | |
114 | * Note: %esi still has the pointer to the real-mode data. | |
115 | * With the kexec as boot loader, parameter segment might be loaded beyond | |
116 | * kernel image and might not even be addressable by early boot page tables. | |
117 | * (kexec on panic case). Hence copy out the parameters before initializing | |
118 | * page tables. | |
119 | */ | |
551889a6 | 120 | movl $pa(boot_params),%edi |
484b90c4 VG |
121 | movl $(PARAM_SIZE/4),%ecx |
122 | cld | |
123 | rep | |
124 | movsl | |
551889a6 | 125 | movl pa(boot_params) + NEW_CL_POINTER,%esi |
484b90c4 | 126 | andl %esi,%esi |
fa76dab9 | 127 | jz 1f # No comand line |
551889a6 | 128 | movl $pa(boot_command_line),%edi |
484b90c4 VG |
129 | movl $(COMMAND_LINE_SIZE/4),%ecx |
130 | rep | |
131 | movsl | |
132 | 1: | |
1da177e4 | 133 | |
fd699c76 AS |
134 | #ifdef CONFIG_OLPC_OPENFIRMWARE |
135 | /* save OFW's pgdir table for later use when calling into OFW */ | |
136 | movl %cr3, %eax | |
137 | movl %eax, pa(olpc_ofw_pgd) | |
138 | #endif | |
139 | ||
a24e7851 | 140 | #ifdef CONFIG_PARAVIRT |
551889a6 IC |
141 | /* This is can only trip for a broken bootloader... */ |
142 | cmpw $0x207, pa(boot_params + BP_version) | |
a24e7851 RR |
143 | jb default_entry |
144 | ||
145 | /* Paravirt-compatible boot parameters. Look to see what architecture | |
146 | we're booting under. */ | |
551889a6 | 147 | movl pa(boot_params + BP_hardware_subarch), %eax |
a24e7851 RR |
148 | cmpl $num_subarch_entries, %eax |
149 | jae bad_subarch | |
150 | ||
551889a6 | 151 | movl pa(subarch_entries)(,%eax,4), %eax |
a24e7851 RR |
152 | subl $__PAGE_OFFSET, %eax |
153 | jmp *%eax | |
154 | ||
155 | bad_subarch: | |
156 | WEAK(lguest_entry) | |
157 | WEAK(xen_entry) | |
158 | /* Unknown implementation; there's really | |
159 | nothing we can do at this point. */ | |
160 | ud2a | |
8b2f7fff SR |
161 | |
162 | __INITDATA | |
163 | ||
a24e7851 RR |
164 | subarch_entries: |
165 | .long default_entry /* normal x86/PC */ | |
166 | .long lguest_entry /* lguest hypervisor */ | |
167 | .long xen_entry /* Xen hypervisor */ | |
162bc7ab | 168 | .long default_entry /* Moorestown MID */ |
a24e7851 RR |
169 | num_subarch_entries = (. - subarch_entries) / 4 |
170 | .previous | |
171 | #endif /* CONFIG_PARAVIRT */ | |
172 | ||
1da177e4 LT |
173 | /* |
174 | * Initialize page tables. This creates a PDE and a set of page | |
2bd2753f | 175 | * tables, which are located immediately beyond __brk_base. The variable |
ccf3fe02 | 176 | * _brk_end is set up to point to the first "safe" location. |
1da177e4 | 177 | * Mappings are created both at virtual address 0 (identity mapping) |
2bd2753f | 178 | * and PAGE_OFFSET for up to _end. |
1da177e4 | 179 | * |
551889a6 | 180 | * Note that the stack is not yet set up! |
1da177e4 | 181 | */ |
a24e7851 | 182 | default_entry: |
551889a6 IC |
183 | #ifdef CONFIG_X86_PAE |
184 | ||
185 | /* | |
b40827fa BP |
186 | * In PAE mode initial_page_table is statically defined to contain |
187 | * enough entries to cover the VMSPLIT option (that is the top 1, 2 or 3 | |
188 | * entries). The identity mapping is handled by pointing two PGD entries | |
189 | * to the first kernel PMD. | |
551889a6 | 190 | * |
b40827fa | 191 | * Note the upper half of each PMD or PTE are always zero at this stage. |
551889a6 IC |
192 | */ |
193 | ||
86b2b70e | 194 | #define KPMDS (((-__PAGE_OFFSET) >> 30) & 3) /* Number of kernel PMDs */ |
551889a6 IC |
195 | |
196 | xorl %ebx,%ebx /* %ebx is kept at zero */ | |
197 | ||
ccf3fe02 | 198 | movl $pa(__brk_base), %edi |
b40827fa | 199 | movl $pa(initial_pg_pmd), %edx |
b2bc2731 | 200 | movl $PTE_IDENT_ATTR, %eax |
551889a6 | 201 | 10: |
b2bc2731 | 202 | leal PDE_IDENT_ATTR(%edi),%ecx /* Create PMD entry */ |
551889a6 IC |
203 | movl %ecx,(%edx) /* Store PMD entry */ |
204 | /* Upper half already zero */ | |
205 | addl $8,%edx | |
206 | movl $512,%ecx | |
207 | 11: | |
208 | stosl | |
209 | xchgl %eax,%ebx | |
210 | stosl | |
211 | xchgl %eax,%ebx | |
212 | addl $0x1000,%eax | |
213 | loop 11b | |
214 | ||
215 | /* | |
c090f532 | 216 | * End condition: we must map up to the end + MAPPING_BEYOND_END. |
551889a6 | 217 | */ |
c090f532 | 218 | movl $pa(_end) + MAPPING_BEYOND_END + PTE_IDENT_ATTR, %ebp |
551889a6 IC |
219 | cmpl %ebp,%eax |
220 | jb 10b | |
221 | 1: | |
ccf3fe02 JF |
222 | addl $__PAGE_OFFSET, %edi |
223 | movl %edi, pa(_brk_end) | |
6af61a76 YL |
224 | shrl $12, %eax |
225 | movl %eax, pa(max_pfn_mapped) | |
551889a6 IC |
226 | |
227 | /* Do early initialization of the fixmap area */ | |
b40827fa BP |
228 | movl $pa(initial_pg_fixmap)+PDE_IDENT_ATTR,%eax |
229 | movl %eax,pa(initial_pg_pmd+0x1000*KPMDS-8) | |
551889a6 IC |
230 | #else /* Not PAE */ |
231 | ||
232 | page_pde_offset = (__PAGE_OFFSET >> 20); | |
233 | ||
ccf3fe02 | 234 | movl $pa(__brk_base), %edi |
b40827fa | 235 | movl $pa(initial_page_table), %edx |
b2bc2731 | 236 | movl $PTE_IDENT_ATTR, %eax |
1da177e4 | 237 | 10: |
b2bc2731 | 238 | leal PDE_IDENT_ATTR(%edi),%ecx /* Create PDE entry */ |
1da177e4 LT |
239 | movl %ecx,(%edx) /* Store identity PDE entry */ |
240 | movl %ecx,page_pde_offset(%edx) /* Store kernel PDE entry */ | |
241 | addl $4,%edx | |
242 | movl $1024, %ecx | |
243 | 11: | |
244 | stosl | |
245 | addl $0x1000,%eax | |
246 | loop 11b | |
551889a6 | 247 | /* |
c090f532 | 248 | * End condition: we must map up to the end + MAPPING_BEYOND_END. |
551889a6 | 249 | */ |
c090f532 | 250 | movl $pa(_end) + MAPPING_BEYOND_END + PTE_IDENT_ATTR, %ebp |
1da177e4 LT |
251 | cmpl %ebp,%eax |
252 | jb 10b | |
ccf3fe02 JF |
253 | addl $__PAGE_OFFSET, %edi |
254 | movl %edi, pa(_brk_end) | |
6af61a76 YL |
255 | shrl $12, %eax |
256 | movl %eax, pa(max_pfn_mapped) | |
17d57a92 | 257 | |
551889a6 | 258 | /* Do early initialization of the fixmap area */ |
b40827fa BP |
259 | movl $pa(initial_pg_fixmap)+PDE_IDENT_ATTR,%eax |
260 | movl %eax,pa(initial_page_table+0xffc) | |
551889a6 | 261 | #endif |
1da177e4 | 262 | jmp 3f |
1da177e4 LT |
263 | /* |
264 | * Non-boot CPU entry point; entered from trampoline.S | |
265 | * We can't lgdt here, because lgdt itself uses a data segment, but | |
52de74dd | 266 | * we know the trampoline has already loaded the boot_gdt for us. |
f8657e1b VG |
267 | * |
268 | * If cpu hotplug is not supported then this code can go in init section | |
269 | * which will be freed later | |
1da177e4 | 270 | */ |
f8657e1b | 271 | |
78b89ecd | 272 | __CPUINIT |
f8657e1b VG |
273 | |
274 | #ifdef CONFIG_SMP | |
1da177e4 LT |
275 | ENTRY(startup_32_smp) |
276 | cld | |
277 | movl $(__BOOT_DS),%eax | |
278 | movl %eax,%ds | |
279 | movl %eax,%es | |
280 | movl %eax,%fs | |
281 | movl %eax,%gs | |
5756dd59 IC |
282 | #endif /* CONFIG_SMP */ |
283 | 3: | |
1da177e4 LT |
284 | |
285 | /* | |
286 | * New page tables may be in 4Mbyte page mode and may | |
287 | * be using the global pages. | |
288 | * | |
289 | * NOTE! If we are on a 486 we may have no cr4 at all! | |
290 | * So we do not try to touch it unless we really have | |
291 | * some bits in it to set. This won't work if the BSP | |
292 | * implements cr4 but this AP does not -- very unlikely | |
293 | * but be warned! The same applies to the pse feature | |
294 | * if not equally supported. --macro | |
295 | * | |
296 | * NOTE! We have to correct for the fact that we're | |
297 | * not yet offset PAGE_OFFSET.. | |
298 | */ | |
551889a6 | 299 | #define cr4_bits pa(mmu_cr4_features) |
1da177e4 LT |
300 | movl cr4_bits,%edx |
301 | andl %edx,%edx | |
302 | jz 6f | |
303 | movl %cr4,%eax # Turn on paging options (PSE,PAE,..) | |
304 | orl %edx,%eax | |
305 | movl %eax,%cr4 | |
306 | ||
8a50e513 PA |
307 | testb $X86_CR4_PAE, %al # check if PAE is enabled |
308 | jz 6f | |
1da177e4 LT |
309 | |
310 | /* Check if extended functions are implemented */ | |
311 | movl $0x80000000, %eax | |
312 | cpuid | |
8a50e513 PA |
313 | /* Value must be in the range 0x80000001 to 0x8000ffff */ |
314 | subl $0x80000001, %eax | |
315 | cmpl $(0x8000ffff-0x80000001), %eax | |
316 | ja 6f | |
1da177e4 LT |
317 | mov $0x80000001, %eax |
318 | cpuid | |
319 | /* Execute Disable bit supported? */ | |
8a50e513 | 320 | btl $(X86_FEATURE_NX & 31), %edx |
1da177e4 LT |
321 | jnc 6f |
322 | ||
323 | /* Setup EFER (Extended Feature Enable Register) */ | |
8a50e513 | 324 | movl $MSR_EFER, %ecx |
1da177e4 LT |
325 | rdmsr |
326 | ||
8a50e513 | 327 | btsl $_EFER_NX, %eax |
1da177e4 LT |
328 | /* Make changes effective */ |
329 | wrmsr | |
330 | ||
331 | 6: | |
1da177e4 LT |
332 | |
333 | /* | |
334 | * Enable paging | |
335 | */ | |
b40827fa | 336 | movl $pa(initial_page_table), %eax |
1da177e4 LT |
337 | movl %eax,%cr3 /* set the page table pointer.. */ |
338 | movl %cr0,%eax | |
551889a6 | 339 | orl $X86_CR0_PG,%eax |
1da177e4 LT |
340 | movl %eax,%cr0 /* ..and set paging (PG) bit */ |
341 | ljmp $__BOOT_CS,$1f /* Clear prefetch and normalize %eip */ | |
342 | 1: | |
343 | /* Set up the stack pointer */ | |
344 | lss stack_start,%esp | |
345 | ||
346 | /* | |
347 | * Initialize eflags. Some BIOS's leave bits like NT set. This would | |
348 | * confuse the debugger if this code is traced. | |
349 | * XXX - best to initialize before switching to protected mode. | |
350 | */ | |
351 | pushl $0 | |
352 | popfl | |
353 | ||
354 | #ifdef CONFIG_SMP | |
50359501 | 355 | cmpb $0, ready |
1da177e4 LT |
356 | jz 1f /* Initial CPU cleans BSS */ |
357 | jmp checkCPUtype | |
358 | 1: | |
359 | #endif /* CONFIG_SMP */ | |
360 | ||
361 | /* | |
362 | * start system 32-bit setup. We need to re-do some of the things done | |
363 | * in 16-bit mode for the "real" operations. | |
364 | */ | |
365 | call setup_idt | |
366 | ||
1da177e4 LT |
367 | checkCPUtype: |
368 | ||
369 | movl $-1,X86_CPUID # -1 for no CPUID initially | |
370 | ||
371 | /* check if it is 486 or 386. */ | |
372 | /* | |
373 | * XXX - this does a lot of unnecessary setup. Alignment checks don't | |
374 | * apply at our cpl of 0 and the stack ought to be aligned already, and | |
375 | * we don't need to preserve eflags. | |
376 | */ | |
377 | ||
378 | movb $3,X86 # at least 386 | |
379 | pushfl # push EFLAGS | |
380 | popl %eax # get EFLAGS | |
381 | movl %eax,%ecx # save original EFLAGS | |
382 | xorl $0x240000,%eax # flip AC and ID bits in EFLAGS | |
383 | pushl %eax # copy to EFLAGS | |
384 | popfl # set EFLAGS | |
385 | pushfl # get new EFLAGS | |
386 | popl %eax # put it in eax | |
387 | xorl %ecx,%eax # change in flags | |
388 | pushl %ecx # restore original EFLAGS | |
389 | popfl | |
390 | testl $0x40000,%eax # check if AC bit changed | |
391 | je is386 | |
392 | ||
393 | movb $4,X86 # at least 486 | |
394 | testl $0x200000,%eax # check if ID bit changed | |
395 | je is486 | |
396 | ||
397 | /* get vendor info */ | |
398 | xorl %eax,%eax # call CPUID with 0 -> return vendor ID | |
399 | cpuid | |
400 | movl %eax,X86_CPUID # save CPUID level | |
401 | movl %ebx,X86_VENDOR_ID # lo 4 chars | |
402 | movl %edx,X86_VENDOR_ID+4 # next 4 chars | |
403 | movl %ecx,X86_VENDOR_ID+8 # last 4 chars | |
404 | ||
405 | orl %eax,%eax # do we have processor info as well? | |
406 | je is486 | |
407 | ||
408 | movl $1,%eax # Use the CPUID instruction to get CPU type | |
409 | cpuid | |
410 | movb %al,%cl # save reg for future use | |
411 | andb $0x0f,%ah # mask processor family | |
412 | movb %ah,X86 | |
413 | andb $0xf0,%al # mask model | |
414 | shrb $4,%al | |
415 | movb %al,X86_MODEL | |
416 | andb $0x0f,%cl # mask mask revision | |
417 | movb %cl,X86_MASK | |
418 | movl %edx,X86_CAPABILITY | |
419 | ||
420 | is486: movl $0x50022,%ecx # set AM, WP, NE and MP | |
421 | jmp 2f | |
422 | ||
423 | is386: movl $2,%ecx # set MP | |
424 | 2: movl %cr0,%eax | |
425 | andl $0x80000011,%eax # Save PG,PE,ET | |
426 | orl %ecx,%eax | |
427 | movl %eax,%cr0 | |
428 | ||
429 | call check_x87 | |
2a57ff1a | 430 | lgdt early_gdt_descr |
1da177e4 LT |
431 | lidt idt_descr |
432 | ljmp $(__KERNEL_CS),$1f | |
433 | 1: movl $(__KERNEL_DS),%eax # reload all the segment registers | |
434 | movl %eax,%ss # after changing gdt. | |
435 | ||
436 | movl $(__USER_DS),%eax # DS/ES contains default USER segment | |
437 | movl %eax,%ds | |
438 | movl %eax,%es | |
439 | ||
0dd76d73 BG |
440 | movl $(__KERNEL_PERCPU), %eax |
441 | movl %eax,%fs # set this cpu's percpu | |
442 | ||
60a5317f TH |
443 | #ifdef CONFIG_CC_STACKPROTECTOR |
444 | /* | |
445 | * The linker can't handle this by relocation. Manually set | |
446 | * base address in stack canary segment descriptor. | |
447 | */ | |
448 | cmpb $0,ready | |
449 | jne 1f | |
dd17c8f7 RR |
450 | movl $gdt_page,%eax |
451 | movl $stack_canary,%ecx | |
60a5317f TH |
452 | movw %cx, 8 * GDT_ENTRY_STACK_CANARY + 2(%eax) |
453 | shrl $16, %ecx | |
454 | movb %cl, 8 * GDT_ENTRY_STACK_CANARY + 4(%eax) | |
455 | movb %ch, 8 * GDT_ENTRY_STACK_CANARY + 7(%eax) | |
456 | 1: | |
457 | #endif | |
458 | movl $(__KERNEL_STACK_CANARY),%eax | |
464d1a78 | 459 | movl %eax,%gs |
60a5317f TH |
460 | |
461 | xorl %eax,%eax # Clear LDT | |
1da177e4 | 462 | lldt %ax |
f95d47ca | 463 | |
1da177e4 | 464 | cld # gcc2 wants the direction flag cleared at all times |
26fd5e08 | 465 | pushl $0 # fake return address for unwinder |
1da177e4 | 466 | #ifdef CONFIG_SMP |
d92de65c SL |
467 | movb ready, %cl |
468 | movb $1, ready | |
29fe5f3b | 469 | cmpb $0,%cl # the first CPU calls start_kernel |
7c3576d2 | 470 | je 1f |
3e970473 | 471 | movl (stack_start), %esp |
7c3576d2 | 472 | 1: |
1da177e4 | 473 | #endif /* CONFIG_SMP */ |
e3f77edf | 474 | jmp *(initial_code) |
1da177e4 LT |
475 | |
476 | /* | |
477 | * We depend on ET to be correct. This checks for 287/387. | |
478 | */ | |
479 | check_x87: | |
480 | movb $0,X86_HARD_MATH | |
481 | clts | |
482 | fninit | |
483 | fstsw %ax | |
484 | cmpb $0,%al | |
485 | je 1f | |
486 | movl %cr0,%eax /* no coprocessor: have to set bits */ | |
487 | xorl $4,%eax /* set EM */ | |
488 | movl %eax,%cr0 | |
489 | ret | |
490 | ALIGN | |
491 | 1: movb $1,X86_HARD_MATH | |
492 | .byte 0xDB,0xE4 /* fsetpm for 287, ignored by 387 */ | |
493 | ret | |
494 | ||
495 | /* | |
496 | * setup_idt | |
497 | * | |
498 | * sets up a idt with 256 entries pointing to | |
499 | * ignore_int, interrupt gates. It doesn't actually load | |
500 | * idt - that can be done only after paging has been enabled | |
501 | * and the kernel moved to PAGE_OFFSET. Interrupts | |
502 | * are enabled elsewhere, when we can be relatively | |
503 | * sure everything is ok. | |
504 | * | |
505 | * Warning: %esi is live across this function. | |
506 | */ | |
507 | setup_idt: | |
508 | lea ignore_int,%edx | |
509 | movl $(__KERNEL_CS << 16),%eax | |
510 | movw %dx,%ax /* selector = 0x0010 = cs */ | |
511 | movw $0x8E00,%dx /* interrupt gate - dpl=0, present */ | |
512 | ||
513 | lea idt_table,%edi | |
514 | mov $256,%ecx | |
515 | rp_sidt: | |
516 | movl %eax,(%edi) | |
517 | movl %edx,4(%edi) | |
518 | addl $8,%edi | |
519 | dec %ecx | |
520 | jne rp_sidt | |
ec5c0926 CE |
521 | |
522 | .macro set_early_handler handler,trapno | |
523 | lea \handler,%edx | |
524 | movl $(__KERNEL_CS << 16),%eax | |
525 | movw %dx,%ax | |
526 | movw $0x8E00,%dx /* interrupt gate - dpl=0, present */ | |
527 | lea idt_table,%edi | |
528 | movl %eax,8*\trapno(%edi) | |
529 | movl %edx,8*\trapno+4(%edi) | |
530 | .endm | |
531 | ||
532 | set_early_handler handler=early_divide_err,trapno=0 | |
533 | set_early_handler handler=early_illegal_opcode,trapno=6 | |
534 | set_early_handler handler=early_protection_fault,trapno=13 | |
535 | set_early_handler handler=early_page_fault,trapno=14 | |
536 | ||
1da177e4 LT |
537 | ret |
538 | ||
ec5c0926 CE |
539 | early_divide_err: |
540 | xor %edx,%edx | |
541 | pushl $0 /* fake errcode */ | |
542 | jmp early_fault | |
543 | ||
544 | early_illegal_opcode: | |
545 | movl $6,%edx | |
546 | pushl $0 /* fake errcode */ | |
547 | jmp early_fault | |
548 | ||
549 | early_protection_fault: | |
550 | movl $13,%edx | |
551 | jmp early_fault | |
552 | ||
553 | early_page_fault: | |
554 | movl $14,%edx | |
555 | jmp early_fault | |
556 | ||
557 | early_fault: | |
558 | cld | |
559 | #ifdef CONFIG_PRINTK | |
382f64ab | 560 | pusha |
ec5c0926 CE |
561 | movl $(__KERNEL_DS),%eax |
562 | movl %eax,%ds | |
563 | movl %eax,%es | |
564 | cmpl $2,early_recursion_flag | |
565 | je hlt_loop | |
566 | incl early_recursion_flag | |
567 | movl %cr2,%eax | |
568 | pushl %eax | |
569 | pushl %edx /* trapno */ | |
570 | pushl $fault_msg | |
ec5c0926 | 571 | call printk |
ec5c0926 | 572 | #endif |
94878efd | 573 | call dump_stack |
ec5c0926 CE |
574 | hlt_loop: |
575 | hlt | |
576 | jmp hlt_loop | |
577 | ||
1da177e4 LT |
578 | /* This is the default interrupt "handler" :-) */ |
579 | ALIGN | |
580 | ignore_int: | |
581 | cld | |
d59745ce | 582 | #ifdef CONFIG_PRINTK |
1da177e4 LT |
583 | pushl %eax |
584 | pushl %ecx | |
585 | pushl %edx | |
586 | pushl %es | |
587 | pushl %ds | |
588 | movl $(__KERNEL_DS),%eax | |
589 | movl %eax,%ds | |
590 | movl %eax,%es | |
ec5c0926 CE |
591 | cmpl $2,early_recursion_flag |
592 | je hlt_loop | |
593 | incl early_recursion_flag | |
1da177e4 LT |
594 | pushl 16(%esp) |
595 | pushl 24(%esp) | |
596 | pushl 32(%esp) | |
597 | pushl 40(%esp) | |
598 | pushl $int_msg | |
599 | call printk | |
d5e397cb IM |
600 | |
601 | call dump_stack | |
602 | ||
1da177e4 LT |
603 | addl $(5*4),%esp |
604 | popl %ds | |
605 | popl %es | |
606 | popl %edx | |
607 | popl %ecx | |
608 | popl %eax | |
d59745ce | 609 | #endif |
1da177e4 LT |
610 | iret |
611 | ||
0e83815b | 612 | __REFDATA |
583323b9 TG |
613 | .align 4 |
614 | ENTRY(initial_code) | |
615 | .long i386_start_kernel | |
616 | ||
1da177e4 LT |
617 | /* |
618 | * BSS section | |
619 | */ | |
02b7da37 | 620 | __PAGE_ALIGNED_BSS |
5ead97c8 | 621 | .align PAGE_SIZE_asm |
551889a6 | 622 | #ifdef CONFIG_X86_PAE |
b40827fa | 623 | initial_pg_pmd: |
551889a6 IC |
624 | .fill 1024*KPMDS,4,0 |
625 | #else | |
b40827fa | 626 | ENTRY(initial_page_table) |
1da177e4 | 627 | .fill 1024,4,0 |
551889a6 | 628 | #endif |
b40827fa | 629 | initial_pg_fixmap: |
b1c931e3 | 630 | .fill 1024,4,0 |
1da177e4 LT |
631 | ENTRY(empty_zero_page) |
632 | .fill 4096,1,0 | |
b40827fa BP |
633 | ENTRY(swapper_pg_dir) |
634 | .fill 1024,4,0 | |
2bd2753f | 635 | |
1da177e4 LT |
636 | /* |
637 | * This starts the data section. | |
638 | */ | |
551889a6 | 639 | #ifdef CONFIG_X86_PAE |
abe1ee3a | 640 | __PAGE_ALIGNED_DATA |
551889a6 IC |
641 | /* Page-aligned for the benefit of paravirt? */ |
642 | .align PAGE_SIZE_asm | |
b40827fa BP |
643 | ENTRY(initial_page_table) |
644 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 /* low identity map */ | |
551889a6 | 645 | # if KPMDS == 3 |
b40827fa BP |
646 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 |
647 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR+0x1000),0 | |
648 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR+0x2000),0 | |
551889a6 IC |
649 | # elif KPMDS == 2 |
650 | .long 0,0 | |
b40827fa BP |
651 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 |
652 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR+0x1000),0 | |
551889a6 IC |
653 | # elif KPMDS == 1 |
654 | .long 0,0 | |
655 | .long 0,0 | |
b40827fa | 656 | .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 |
551889a6 IC |
657 | # else |
658 | # error "Kernel PMDs should be 1, 2 or 3" | |
659 | # endif | |
660 | .align PAGE_SIZE_asm /* needs to be page-sized too */ | |
661 | #endif | |
662 | ||
1da177e4 | 663 | .data |
1da177e4 LT |
664 | ENTRY(stack_start) |
665 | .long init_thread_union+THREAD_SIZE | |
666 | .long __BOOT_DS | |
667 | ||
668 | ready: .byte 0 | |
669 | ||
ec5c0926 CE |
670 | early_recursion_flag: |
671 | .long 0 | |
672 | ||
1da177e4 | 673 | int_msg: |
d5e397cb | 674 | .asciz "Unknown interrupt or fault at: %p %p %p\n" |
1da177e4 | 675 | |
ec5c0926 | 676 | fault_msg: |
575ca735 VN |
677 | /* fault info: */ |
678 | .ascii "BUG: Int %d: CR2 %p\n" | |
679 | /* pusha regs: */ | |
680 | .ascii " EDI %p ESI %p EBP %p ESP %p\n" | |
681 | .ascii " EBX %p EDX %p ECX %p EAX %p\n" | |
682 | /* fault frame: */ | |
683 | .ascii " err %p EIP %p CS %p flg %p\n" | |
684 | .ascii "Stack: %p %p %p %p %p %p %p %p\n" | |
685 | .ascii " %p %p %p %p %p %p %p %p\n" | |
686 | .asciz " %p %p %p %p %p %p %p %p\n" | |
ec5c0926 | 687 | |
9702785a | 688 | #include "../../x86/xen/xen-head.S" |
5ead97c8 | 689 | |
1da177e4 LT |
690 | /* |
691 | * The IDT and GDT 'descriptors' are a strange 48-bit object | |
692 | * only used by the lidt and lgdt instructions. They are not | |
693 | * like usual segment descriptors - they consist of a 16-bit | |
694 | * segment size, and 32-bit linear address value: | |
695 | */ | |
696 | ||
697 | .globl boot_gdt_descr | |
698 | .globl idt_descr | |
1da177e4 LT |
699 | |
700 | ALIGN | |
701 | # early boot GDT descriptor (must use 1:1 address mapping) | |
702 | .word 0 # 32 bit align gdt_desc.address | |
703 | boot_gdt_descr: | |
704 | .word __BOOT_DS+7 | |
52de74dd | 705 | .long boot_gdt - __PAGE_OFFSET |
1da177e4 LT |
706 | |
707 | .word 0 # 32-bit align idt_desc.address | |
708 | idt_descr: | |
709 | .word IDT_ENTRIES*8-1 # idt contains 256 entries | |
710 | .long idt_table | |
711 | ||
712 | # boot GDT descriptor (later on used by CPU#0): | |
713 | .word 0 # 32 bit align gdt_desc.address | |
2a57ff1a | 714 | ENTRY(early_gdt_descr) |
1da177e4 | 715 | .word GDT_ENTRIES*8-1 |
dd17c8f7 | 716 | .long gdt_page /* Overwritten for secondary CPUs */ |
1da177e4 | 717 | |
1da177e4 | 718 | /* |
52de74dd | 719 | * The boot_gdt must mirror the equivalent in setup.S and is |
1da177e4 LT |
720 | * used only for booting. |
721 | */ | |
722 | .align L1_CACHE_BYTES | |
52de74dd | 723 | ENTRY(boot_gdt) |
1da177e4 LT |
724 | .fill GDT_ENTRY_BOOT_CS,8,0 |
725 | .quad 0x00cf9a000000ffff /* kernel 4GB code at 0x00000000 */ | |
726 | .quad 0x00cf92000000ffff /* kernel 4GB data at 0x00000000 */ |