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x86, head_32: Remove second CPUID detection from default_entry
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CommitLineData
1da177e4 1/*
1da177e4
LT
2 *
3 * Copyright (C) 1991, 1992 Linus Torvalds
4 *
5 * Enhanced CPU detection and feature setting code by Mike Jagdis
6 * and Martin Mares, November 1997.
7 */
8
9.text
1da177e4 10#include <linux/threads.h>
8b2f7fff 11#include <linux/init.h>
1da177e4
LT
12#include <linux/linkage.h>
13#include <asm/segment.h>
0341c14d
JF
14#include <asm/page_types.h>
15#include <asm/pgtable_types.h>
1da177e4
LT
16#include <asm/cache.h>
17#include <asm/thread_info.h>
86feeaa8 18#include <asm/asm-offsets.h>
1da177e4 19#include <asm/setup.h>
551889a6 20#include <asm/processor-flags.h>
8a50e513
PA
21#include <asm/msr-index.h>
22#include <asm/cpufeature.h>
60a5317f 23#include <asm/percpu.h>
4c5023a3 24#include <asm/nops.h>
551889a6
IC
25
26/* Physical address */
27#define pa(X) ((X) - __PAGE_OFFSET)
1da177e4
LT
28
29/*
30 * References to members of the new_cpu_data structure.
31 */
32
33#define X86 new_cpu_data+CPUINFO_x86
34#define X86_VENDOR new_cpu_data+CPUINFO_x86_vendor
35#define X86_MODEL new_cpu_data+CPUINFO_x86_model
36#define X86_MASK new_cpu_data+CPUINFO_x86_mask
37#define X86_HARD_MATH new_cpu_data+CPUINFO_hard_math
38#define X86_CPUID new_cpu_data+CPUINFO_cpuid_level
39#define X86_CAPABILITY new_cpu_data+CPUINFO_x86_capability
40#define X86_VENDOR_ID new_cpu_data+CPUINFO_x86_vendor_id
41
42/*
c090f532
JF
43 * This is how much memory in addition to the memory covered up to
44 * and including _end we need mapped initially.
9ce8c2ed 45 * We need:
2bd2753f
YL
46 * (KERNEL_IMAGE_SIZE/4096) / 1024 pages (worst case, non PAE)
47 * (KERNEL_IMAGE_SIZE/4096) / 512 + 4 pages (worst case for PAE)
1da177e4
LT
48 *
49 * Modulo rounding, each megabyte assigned here requires a kilobyte of
50 * memory, which is currently unreclaimed.
51 *
52 * This should be a multiple of a page.
2bd2753f
YL
53 *
54 * KERNEL_IMAGE_SIZE should be greater than pa(_end)
55 * and small than max_low_pfn, otherwise will waste some page table entries
1da177e4 56 */
1da177e4 57
9ce8c2ed 58#if PTRS_PER_PMD > 1
c090f532 59#define PAGE_TABLE_SIZE(pages) (((pages) / PTRS_PER_PMD) + PTRS_PER_PGD)
9ce8c2ed 60#else
c090f532 61#define PAGE_TABLE_SIZE(pages) ((pages) / PTRS_PER_PGD)
9ce8c2ed 62#endif
9ce8c2ed 63
147dd561
PA
64/* Number of possible pages in the lowmem region */
65LOWMEM_PAGES = (((1<<32) - __PAGE_OFFSET) >> PAGE_SHIFT)
66
c090f532 67/* Enough space to fit pagetables for the low memory linear map */
147dd561 68MAPPING_BEYOND_END = PAGE_TABLE_SIZE(LOWMEM_PAGES) << PAGE_SHIFT
c090f532
JF
69
70/*
71 * Worst-case size of the kernel mapping we need to make:
147dd561
PA
72 * a relocatable kernel can live anywhere in lowmem, so we need to be able
73 * to map all of lowmem.
c090f532 74 */
147dd561 75KERNEL_PAGES = LOWMEM_PAGES
c090f532 76
7bf04be8 77INIT_MAP_SIZE = PAGE_TABLE_SIZE(KERNEL_PAGES) * PAGE_SIZE
2bd2753f 78RESERVE_BRK(pagetables, INIT_MAP_SIZE)
796216a5 79
1da177e4
LT
80/*
81 * 32-bit kernel entrypoint; only used by the boot CPU. On entry,
82 * %esi points to the real-mode code as a 32-bit pointer.
83 * CS and DS must be 4 GB flat segments, but we don't depend on
84 * any particular GDT layout, because we load our own as soon as we
85 * can.
86 */
4ae59b91 87__HEAD
1da177e4 88ENTRY(startup_32)
11d4c3f9
PA
89 movl pa(stack_start),%ecx
90
a24e7851
RR
91 /* test KEEP_SEGMENTS flag to see if the bootloader is asking
92 us to not reload segments */
93 testb $(1<<6), BP_loadflags(%esi)
94 jnz 2f
1da177e4
LT
95
96/*
97 * Set segments to known values.
98 */
551889a6 99 lgdt pa(boot_gdt_descr)
1da177e4
LT
100 movl $(__BOOT_DS),%eax
101 movl %eax,%ds
102 movl %eax,%es
103 movl %eax,%fs
104 movl %eax,%gs
11d4c3f9 105 movl %eax,%ss
a24e7851 1062:
11d4c3f9 107 leal -__PAGE_OFFSET(%ecx),%esp
1da177e4
LT
108
109/*
110 * Clear BSS first so that there are no surprises...
1da177e4 111 */
a24e7851 112 cld
1da177e4 113 xorl %eax,%eax
551889a6
IC
114 movl $pa(__bss_start),%edi
115 movl $pa(__bss_stop),%ecx
1da177e4
LT
116 subl %edi,%ecx
117 shrl $2,%ecx
118 rep ; stosl
484b90c4
VG
119/*
120 * Copy bootup parameters out of the way.
121 * Note: %esi still has the pointer to the real-mode data.
122 * With the kexec as boot loader, parameter segment might be loaded beyond
123 * kernel image and might not even be addressable by early boot page tables.
124 * (kexec on panic case). Hence copy out the parameters before initializing
125 * page tables.
126 */
551889a6 127 movl $pa(boot_params),%edi
484b90c4
VG
128 movl $(PARAM_SIZE/4),%ecx
129 cld
130 rep
131 movsl
551889a6 132 movl pa(boot_params) + NEW_CL_POINTER,%esi
484b90c4 133 andl %esi,%esi
b595076a 134 jz 1f # No command line
551889a6 135 movl $pa(boot_command_line),%edi
484b90c4
VG
136 movl $(COMMAND_LINE_SIZE/4),%ecx
137 rep
138 movsl
1391:
1da177e4 140
dc3119e7 141#ifdef CONFIG_OLPC
fd699c76
AS
142 /* save OFW's pgdir table for later use when calling into OFW */
143 movl %cr3, %eax
144 movl %eax, pa(olpc_ofw_pgd)
145#endif
146
1da177e4
LT
147/*
148 * Initialize page tables. This creates a PDE and a set of page
2bd2753f 149 * tables, which are located immediately beyond __brk_base. The variable
ccf3fe02 150 * _brk_end is set up to point to the first "safe" location.
1da177e4 151 * Mappings are created both at virtual address 0 (identity mapping)
2bd2753f 152 * and PAGE_OFFSET for up to _end.
1da177e4 153 */
551889a6
IC
154#ifdef CONFIG_X86_PAE
155
156 /*
b40827fa
BP
157 * In PAE mode initial_page_table is statically defined to contain
158 * enough entries to cover the VMSPLIT option (that is the top 1, 2 or 3
159 * entries). The identity mapping is handled by pointing two PGD entries
160 * to the first kernel PMD.
551889a6 161 *
b40827fa 162 * Note the upper half of each PMD or PTE are always zero at this stage.
551889a6
IC
163 */
164
86b2b70e 165#define KPMDS (((-__PAGE_OFFSET) >> 30) & 3) /* Number of kernel PMDs */
551889a6
IC
166
167 xorl %ebx,%ebx /* %ebx is kept at zero */
168
ccf3fe02 169 movl $pa(__brk_base), %edi
b40827fa 170 movl $pa(initial_pg_pmd), %edx
b2bc2731 171 movl $PTE_IDENT_ATTR, %eax
551889a6 17210:
b2bc2731 173 leal PDE_IDENT_ATTR(%edi),%ecx /* Create PMD entry */
551889a6
IC
174 movl %ecx,(%edx) /* Store PMD entry */
175 /* Upper half already zero */
176 addl $8,%edx
177 movl $512,%ecx
17811:
179 stosl
180 xchgl %eax,%ebx
181 stosl
182 xchgl %eax,%ebx
183 addl $0x1000,%eax
184 loop 11b
185
186 /*
c090f532 187 * End condition: we must map up to the end + MAPPING_BEYOND_END.
551889a6 188 */
c090f532 189 movl $pa(_end) + MAPPING_BEYOND_END + PTE_IDENT_ATTR, %ebp
551889a6
IC
190 cmpl %ebp,%eax
191 jb 10b
1921:
ccf3fe02
JF
193 addl $__PAGE_OFFSET, %edi
194 movl %edi, pa(_brk_end)
6af61a76
YL
195 shrl $12, %eax
196 movl %eax, pa(max_pfn_mapped)
551889a6
IC
197
198 /* Do early initialization of the fixmap area */
b40827fa
BP
199 movl $pa(initial_pg_fixmap)+PDE_IDENT_ATTR,%eax
200 movl %eax,pa(initial_pg_pmd+0x1000*KPMDS-8)
551889a6
IC
201#else /* Not PAE */
202
203page_pde_offset = (__PAGE_OFFSET >> 20);
204
ccf3fe02 205 movl $pa(__brk_base), %edi
b40827fa 206 movl $pa(initial_page_table), %edx
b2bc2731 207 movl $PTE_IDENT_ATTR, %eax
1da177e4 20810:
b2bc2731 209 leal PDE_IDENT_ATTR(%edi),%ecx /* Create PDE entry */
1da177e4
LT
210 movl %ecx,(%edx) /* Store identity PDE entry */
211 movl %ecx,page_pde_offset(%edx) /* Store kernel PDE entry */
212 addl $4,%edx
213 movl $1024, %ecx
21411:
215 stosl
216 addl $0x1000,%eax
217 loop 11b
551889a6 218 /*
c090f532 219 * End condition: we must map up to the end + MAPPING_BEYOND_END.
551889a6 220 */
c090f532 221 movl $pa(_end) + MAPPING_BEYOND_END + PTE_IDENT_ATTR, %ebp
1da177e4
LT
222 cmpl %ebp,%eax
223 jb 10b
ccf3fe02
JF
224 addl $__PAGE_OFFSET, %edi
225 movl %edi, pa(_brk_end)
6af61a76
YL
226 shrl $12, %eax
227 movl %eax, pa(max_pfn_mapped)
17d57a92 228
551889a6 229 /* Do early initialization of the fixmap area */
b40827fa
BP
230 movl $pa(initial_pg_fixmap)+PDE_IDENT_ATTR,%eax
231 movl %eax,pa(initial_page_table+0xffc)
551889a6 232#endif
d50d8fe1
RR
233
234#ifdef CONFIG_PARAVIRT
235 /* This is can only trip for a broken bootloader... */
236 cmpw $0x207, pa(boot_params + BP_version)
237 jb default_entry
238
239 /* Paravirt-compatible boot parameters. Look to see what architecture
240 we're booting under. */
241 movl pa(boot_params + BP_hardware_subarch), %eax
242 cmpl $num_subarch_entries, %eax
243 jae bad_subarch
244
245 movl pa(subarch_entries)(,%eax,4), %eax
246 subl $__PAGE_OFFSET, %eax
247 jmp *%eax
248
249bad_subarch:
250WEAK(lguest_entry)
251WEAK(xen_entry)
252 /* Unknown implementation; there's really
253 nothing we can do at this point. */
254 ud2a
255
256 __INITDATA
257
258subarch_entries:
259 .long default_entry /* normal x86/PC */
260 .long lguest_entry /* lguest hypervisor */
261 .long xen_entry /* Xen hypervisor */
262 .long default_entry /* Moorestown MID */
263num_subarch_entries = (. - subarch_entries) / 4
264.previous
265#else
266 jmp default_entry
267#endif /* CONFIG_PARAVIRT */
268
3e2a0cc3
FY
269#ifdef CONFIG_HOTPLUG_CPU
270/*
271 * Boot CPU0 entry point. It's called from play_dead(). Everything has been set
272 * up already except stack. We just set up stack here. Then call
273 * start_secondary().
274 */
275ENTRY(start_cpu0)
276 movl stack_start, %ecx
277 movl %ecx, %esp
278 jmp *(initial_code)
279ENDPROC(start_cpu0)
280#endif
281
1da177e4
LT
282/*
283 * Non-boot CPU entry point; entered from trampoline.S
284 * We can't lgdt here, because lgdt itself uses a data segment, but
52de74dd 285 * we know the trampoline has already loaded the boot_gdt for us.
f8657e1b
VG
286 *
287 * If cpu hotplug is not supported then this code can go in init section
288 * which will be freed later
1da177e4 289 */
78b89ecd 290__CPUINIT
1da177e4
LT
291ENTRY(startup_32_smp)
292 cld
293 movl $(__BOOT_DS),%eax
294 movl %eax,%ds
295 movl %eax,%es
296 movl %eax,%fs
297 movl %eax,%gs
11d4c3f9
PA
298 movl pa(stack_start),%ecx
299 movl %eax,%ss
300 leal -__PAGE_OFFSET(%ecx),%esp
48927bbb 301
d50d8fe1 302default_entry:
021ef050
PA
303#define CR0_STATE (X86_CR0_PE | X86_CR0_MP | X86_CR0_ET | \
304 X86_CR0_NE | X86_CR0_WP | X86_CR0_AM | \
305 X86_CR0_PG)
306 movl $(CR0_STATE & ~X86_CR0_PG),%eax
307 movl %eax,%cr0
308
1da177e4 309/*
9efb58de
BP
310 * We want to start out with EFLAGS unambiguously cleared. Some BIOSes leave
311 * bits like NT set. This would confuse the debugger if this code is traced. So
312 * initialize them properly now before switching to protected mode. That means
313 * DF in particular (even though we have cleared it earlier after copying the
314 * command line) because GCC expects it.
315 */
316 pushl $0
317 popfl
318
319/*
320 * New page tables may be in 4Mbyte page mode and may be using the global pages.
1da177e4 321 *
9efb58de
BP
322 * NOTE! If we are on a 486 we may have no cr4 at all! Specifically, cr4 exists
323 * if and only if CPUID exists and has flags other than the FPU flag set.
1da177e4 324 */
9efb58de 325 movl $-1,pa(X86_CPUID) # preset CPUID level
5a5a51db
PA
326 movl $X86_EFLAGS_ID,%ecx
327 pushl %ecx
9efb58de 328 popfl # set EFLAGS=ID
5a5a51db 329 pushfl
9efb58de
BP
330 popl %eax # get EFLAGS
331 testl $X86_EFLAGS_ID,%eax # did EFLAGS.ID remained set?
332 jz 6f # hw disallowed setting of ID bit
333 # which means no CPUID and no CR4
334
335 xorl %eax,%eax
336 cpuid
337 movl %eax,pa(X86_CPUID) # save largest std CPUID function
5a5a51db 338
6662c34f
PA
339 movl $1,%eax
340 cpuid
9efb58de
BP
341 andl $~1,%edx # Ignore CPUID.FPU
342 jz 6f # No flags or only CPUID.FPU = no CR4
6662c34f 343
5a5a51db 344 movl pa(mmu_cr4_features),%eax
1da177e4
LT
345 movl %eax,%cr4
346
8a50e513
PA
347 testb $X86_CR4_PAE, %al # check if PAE is enabled
348 jz 6f
1da177e4
LT
349
350 /* Check if extended functions are implemented */
351 movl $0x80000000, %eax
352 cpuid
8a50e513
PA
353 /* Value must be in the range 0x80000001 to 0x8000ffff */
354 subl $0x80000001, %eax
355 cmpl $(0x8000ffff-0x80000001), %eax
356 ja 6f
ebba638a
KC
357
358 /* Clear bogus XD_DISABLE bits */
359 call verify_cpu
360
1da177e4
LT
361 mov $0x80000001, %eax
362 cpuid
363 /* Execute Disable bit supported? */
8a50e513 364 btl $(X86_FEATURE_NX & 31), %edx
1da177e4
LT
365 jnc 6f
366
367 /* Setup EFER (Extended Feature Enable Register) */
8a50e513 368 movl $MSR_EFER, %ecx
1da177e4
LT
369 rdmsr
370
8a50e513 371 btsl $_EFER_NX, %eax
1da177e4
LT
372 /* Make changes effective */
373 wrmsr
374
3756:
1da177e4
LT
376
377/*
378 * Enable paging
379 */
b40827fa 380 movl $pa(initial_page_table), %eax
1da177e4 381 movl %eax,%cr3 /* set the page table pointer.. */
021ef050 382 movl $CR0_STATE,%eax
1da177e4
LT
383 movl %eax,%cr0 /* ..and set paging (PG) bit */
384 ljmp $__BOOT_CS,$1f /* Clear prefetch and normalize %eip */
3851:
11d4c3f9
PA
386 /* Shift the stack pointer to a virtual address */
387 addl $__PAGE_OFFSET, %esp
1da177e4 388
1da177e4
LT
389/*
390 * start system 32-bit setup. We need to re-do some of the things done
391 * in 16-bit mode for the "real" operations.
392 */
4c5023a3
PA
393 movl setup_once_ref,%eax
394 andl %eax,%eax
395 jz 1f # Did we do this already?
396 call *%eax
3971:
166df91d 398
1da177e4 399/*
166df91d 400 * Check if it is 486
1da177e4 401 */
c3a22a26 402 cmpl $-1,X86_CPUID
1da177e4
LT
403 je is486
404
405 /* get vendor info */
406 xorl %eax,%eax # call CPUID with 0 -> return vendor ID
407 cpuid
408 movl %eax,X86_CPUID # save CPUID level
409 movl %ebx,X86_VENDOR_ID # lo 4 chars
410 movl %edx,X86_VENDOR_ID+4 # next 4 chars
411 movl %ecx,X86_VENDOR_ID+8 # last 4 chars
412
413 orl %eax,%eax # do we have processor info as well?
414 je is486
415
416 movl $1,%eax # Use the CPUID instruction to get CPU type
417 cpuid
418 movb %al,%cl # save reg for future use
419 andb $0x0f,%ah # mask processor family
420 movb %ah,X86
421 andb $0xf0,%al # mask model
422 shrb $4,%al
423 movb %al,X86_MODEL
424 andb $0x0f,%cl # mask mask revision
425 movb %cl,X86_MASK
426 movl %edx,X86_CAPABILITY
427
c3a22a26
BP
428is486:
429 movb $4,X86
430 movl $0x50022,%ecx # set AM, WP, NE and MP
166df91d 431 movl %cr0,%eax
1da177e4
LT
432 andl $0x80000011,%eax # Save PG,PE,ET
433 orl %ecx,%eax
434 movl %eax,%cr0
435
436 call check_x87
2a57ff1a 437 lgdt early_gdt_descr
1da177e4
LT
438 lidt idt_descr
439 ljmp $(__KERNEL_CS),$1f
4401: movl $(__KERNEL_DS),%eax # reload all the segment registers
441 movl %eax,%ss # after changing gdt.
442
443 movl $(__USER_DS),%eax # DS/ES contains default USER segment
444 movl %eax,%ds
445 movl %eax,%es
446
0dd76d73
BG
447 movl $(__KERNEL_PERCPU), %eax
448 movl %eax,%fs # set this cpu's percpu
449
60a5317f 450 movl $(__KERNEL_STACK_CANARY),%eax
464d1a78 451 movl %eax,%gs
60a5317f
TH
452
453 xorl %eax,%eax # Clear LDT
1da177e4 454 lldt %ax
f95d47ca 455
26fd5e08 456 pushl $0 # fake return address for unwinder
e3f77edf 457 jmp *(initial_code)
1da177e4
LT
458
459/*
460 * We depend on ET to be correct. This checks for 287/387.
461 */
462check_x87:
463 movb $0,X86_HARD_MATH
464 clts
465 fninit
466 fstsw %ax
467 cmpb $0,%al
468 je 1f
469 movl %cr0,%eax /* no coprocessor: have to set bits */
470 xorl $4,%eax /* set EM */
471 movl %eax,%cr0
472 ret
473 ALIGN
4741: movb $1,X86_HARD_MATH
475 .byte 0xDB,0xE4 /* fsetpm for 287, ignored by 387 */
476 ret
477
4c5023a3
PA
478
479#include "verify_cpu.S"
480
1da177e4 481/*
4c5023a3 482 * setup_once
1da177e4 483 *
4c5023a3 484 * The setup work we only want to run on the BSP.
1da177e4
LT
485 *
486 * Warning: %esi is live across this function.
487 */
4c5023a3
PA
488__INIT
489setup_once:
490 /*
491 * Set up a idt with 256 entries pointing to ignore_int,
492 * interrupt gates. It doesn't actually load idt - that needs
493 * to be done on each CPU. Interrupts are enabled elsewhere,
494 * when we can be relatively sure everything is ok.
495 */
1da177e4 496
4c5023a3
PA
497 movl $idt_table,%edi
498 movl $early_idt_handlers,%eax
499 movl $NUM_EXCEPTION_VECTORS,%ecx
5001:
1da177e4 501 movl %eax,(%edi)
4c5023a3
PA
502 movl %eax,4(%edi)
503 /* interrupt gate, dpl=0, present */
504 movl $(0x8E000000 + __KERNEL_CS),2(%edi)
505 addl $9,%eax
1da177e4 506 addl $8,%edi
4c5023a3 507 loop 1b
ec5c0926 508
4c5023a3
PA
509 movl $256 - NUM_EXCEPTION_VECTORS,%ecx
510 movl $ignore_int,%edx
ec5c0926 511 movl $(__KERNEL_CS << 16),%eax
4c5023a3 512 movw %dx,%ax /* selector = 0x0010 = cs */
ec5c0926 513 movw $0x8E00,%dx /* interrupt gate - dpl=0, present */
4c5023a3
PA
5142:
515 movl %eax,(%edi)
516 movl %edx,4(%edi)
517 addl $8,%edi
518 loop 2b
ec5c0926 519
4c5023a3
PA
520#ifdef CONFIG_CC_STACKPROTECTOR
521 /*
522 * Configure the stack canary. The linker can't handle this by
523 * relocation. Manually set base address in stack canary
524 * segment descriptor.
525 */
526 movl $gdt_page,%eax
527 movl $stack_canary,%ecx
528 movw %cx, 8 * GDT_ENTRY_STACK_CANARY + 2(%eax)
529 shrl $16, %ecx
530 movb %cl, 8 * GDT_ENTRY_STACK_CANARY + 4(%eax)
531 movb %ch, 8 * GDT_ENTRY_STACK_CANARY + 7(%eax)
532#endif
ec5c0926 533
4c5023a3 534 andl $0,setup_once_ref /* Once is enough, thanks */
1da177e4
LT
535 ret
536
4c5023a3
PA
537ENTRY(early_idt_handlers)
538 # 36(%esp) %eflags
539 # 32(%esp) %cs
540 # 28(%esp) %eip
541 # 24(%rsp) error code
542 i = 0
543 .rept NUM_EXCEPTION_VECTORS
544 .if (EXCEPTION_ERRCODE_MASK >> i) & 1
545 ASM_NOP2
546 .else
547 pushl $0 # Dummy error code, to make stack frame uniform
548 .endif
549 pushl $i # 20(%esp) Vector number
550 jmp early_idt_handler
551 i = i + 1
552 .endr
553ENDPROC(early_idt_handlers)
554
555 /* This is global to keep gas from relaxing the jumps */
556ENTRY(early_idt_handler)
557 cld
558 cmpl $2,%ss:early_recursion_flag
559 je hlt_loop
560 incl %ss:early_recursion_flag
ec5c0926 561
4c5023a3
PA
562 push %eax # 16(%esp)
563 push %ecx # 12(%esp)
564 push %edx # 8(%esp)
565 push %ds # 4(%esp)
566 push %es # 0(%esp)
567 movl $(__KERNEL_DS),%eax
568 movl %eax,%ds
569 movl %eax,%es
ec5c0926 570
4c5023a3
PA
571 cmpl $(__KERNEL_CS),32(%esp)
572 jne 10f
ec5c0926 573
4c5023a3
PA
574 leal 28(%esp),%eax # Pointer to %eip
575 call early_fixup_exception
576 andl %eax,%eax
577 jnz ex_entry /* found an exception entry */
ec5c0926 578
4c5023a3 57910:
ec5c0926 580#ifdef CONFIG_PRINTK
4c5023a3
PA
581 xorl %eax,%eax
582 movw %ax,2(%esp) /* clean up the segment values on some cpus */
583 movw %ax,6(%esp)
584 movw %ax,34(%esp)
585 leal 40(%esp),%eax
586 pushl %eax /* %esp before the exception */
587 pushl %ebx
588 pushl %ebp
589 pushl %esi
590 pushl %edi
ec5c0926
CE
591 movl %cr2,%eax
592 pushl %eax
4c5023a3 593 pushl (20+6*4)(%esp) /* trapno */
ec5c0926 594 pushl $fault_msg
ec5c0926 595 call printk
ec5c0926 596#endif
94878efd 597 call dump_stack
ec5c0926
CE
598hlt_loop:
599 hlt
600 jmp hlt_loop
601
4c5023a3
PA
602ex_entry:
603 pop %es
604 pop %ds
605 pop %edx
606 pop %ecx
607 pop %eax
608 addl $8,%esp /* drop vector number and error code */
609 decl %ss:early_recursion_flag
610 iret
611ENDPROC(early_idt_handler)
612
1da177e4
LT
613/* This is the default interrupt "handler" :-) */
614 ALIGN
615ignore_int:
616 cld
d59745ce 617#ifdef CONFIG_PRINTK
1da177e4
LT
618 pushl %eax
619 pushl %ecx
620 pushl %edx
621 pushl %es
622 pushl %ds
623 movl $(__KERNEL_DS),%eax
624 movl %eax,%ds
625 movl %eax,%es
ec5c0926
CE
626 cmpl $2,early_recursion_flag
627 je hlt_loop
628 incl early_recursion_flag
1da177e4
LT
629 pushl 16(%esp)
630 pushl 24(%esp)
631 pushl 32(%esp)
632 pushl 40(%esp)
633 pushl $int_msg
634 call printk
d5e397cb
IM
635
636 call dump_stack
637
1da177e4
LT
638 addl $(5*4),%esp
639 popl %ds
640 popl %es
641 popl %edx
642 popl %ecx
643 popl %eax
d59745ce 644#endif
1da177e4 645 iret
4c5023a3
PA
646ENDPROC(ignore_int)
647__INITDATA
648 .align 4
649early_recursion_flag:
650 .long 0
1da177e4 651
4c5023a3
PA
652__REFDATA
653 .align 4
583323b9
TG
654ENTRY(initial_code)
655 .long i386_start_kernel
4c5023a3
PA
656ENTRY(setup_once_ref)
657 .long setup_once
583323b9 658
1da177e4
LT
659/*
660 * BSS section
661 */
02b7da37 662__PAGE_ALIGNED_BSS
7bf04be8 663 .align PAGE_SIZE
551889a6 664#ifdef CONFIG_X86_PAE
d50d8fe1 665initial_pg_pmd:
551889a6
IC
666 .fill 1024*KPMDS,4,0
667#else
b40827fa 668ENTRY(initial_page_table)
1da177e4 669 .fill 1024,4,0
551889a6 670#endif
d50d8fe1 671initial_pg_fixmap:
b1c931e3 672 .fill 1024,4,0
1da177e4
LT
673ENTRY(empty_zero_page)
674 .fill 4096,1,0
b40827fa
BP
675ENTRY(swapper_pg_dir)
676 .fill 1024,4,0
2bd2753f 677
1da177e4
LT
678/*
679 * This starts the data section.
680 */
551889a6 681#ifdef CONFIG_X86_PAE
abe1ee3a 682__PAGE_ALIGNED_DATA
551889a6 683 /* Page-aligned for the benefit of paravirt? */
7bf04be8 684 .align PAGE_SIZE
b40827fa
BP
685ENTRY(initial_page_table)
686 .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0 /* low identity map */
551889a6 687# if KPMDS == 3
b40827fa
BP
688 .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0
689 .long pa(initial_pg_pmd+PGD_IDENT_ATTR+0x1000),0
690 .long pa(initial_pg_pmd+PGD_IDENT_ATTR+0x2000),0
551889a6
IC
691# elif KPMDS == 2
692 .long 0,0
b40827fa
BP
693 .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0
694 .long pa(initial_pg_pmd+PGD_IDENT_ATTR+0x1000),0
551889a6
IC
695# elif KPMDS == 1
696 .long 0,0
697 .long 0,0
b40827fa 698 .long pa(initial_pg_pmd+PGD_IDENT_ATTR),0
551889a6
IC
699# else
700# error "Kernel PMDs should be 1, 2 or 3"
701# endif
7bf04be8 702 .align PAGE_SIZE /* needs to be page-sized too */
551889a6
IC
703#endif
704
1da177e4 705.data
11d4c3f9 706.balign 4
1da177e4
LT
707ENTRY(stack_start)
708 .long init_thread_union+THREAD_SIZE
1da177e4 709
4c5023a3 710__INITRODATA
1da177e4 711int_msg:
d5e397cb 712 .asciz "Unknown interrupt or fault at: %p %p %p\n"
1da177e4 713
ec5c0926 714fault_msg:
575ca735
VN
715/* fault info: */
716 .ascii "BUG: Int %d: CR2 %p\n"
4c5023a3
PA
717/* regs pushed in early_idt_handler: */
718 .ascii " EDI %p ESI %p EBP %p EBX %p\n"
719 .ascii " ESP %p ES %p DS %p\n"
720 .ascii " EDX %p ECX %p EAX %p\n"
575ca735 721/* fault frame: */
4c5023a3 722 .ascii " vec %p err %p EIP %p CS %p flg %p\n"
575ca735
VN
723 .ascii "Stack: %p %p %p %p %p %p %p %p\n"
724 .ascii " %p %p %p %p %p %p %p %p\n"
725 .asciz " %p %p %p %p %p %p %p %p\n"
ec5c0926 726
9702785a 727#include "../../x86/xen/xen-head.S"
5ead97c8 728
1da177e4
LT
729/*
730 * The IDT and GDT 'descriptors' are a strange 48-bit object
731 * only used by the lidt and lgdt instructions. They are not
732 * like usual segment descriptors - they consist of a 16-bit
733 * segment size, and 32-bit linear address value:
734 */
735
4c5023a3 736 .data
1da177e4
LT
737.globl boot_gdt_descr
738.globl idt_descr
1da177e4
LT
739
740 ALIGN
741# early boot GDT descriptor (must use 1:1 address mapping)
742 .word 0 # 32 bit align gdt_desc.address
743boot_gdt_descr:
744 .word __BOOT_DS+7
52de74dd 745 .long boot_gdt - __PAGE_OFFSET
1da177e4
LT
746
747 .word 0 # 32-bit align idt_desc.address
748idt_descr:
749 .word IDT_ENTRIES*8-1 # idt contains 256 entries
750 .long idt_table
751
752# boot GDT descriptor (later on used by CPU#0):
753 .word 0 # 32 bit align gdt_desc.address
2a57ff1a 754ENTRY(early_gdt_descr)
1da177e4 755 .word GDT_ENTRIES*8-1
dd17c8f7 756 .long gdt_page /* Overwritten for secondary CPUs */
1da177e4 757
1da177e4 758/*
52de74dd 759 * The boot_gdt must mirror the equivalent in setup.S and is
1da177e4
LT
760 * used only for booting.
761 */
762 .align L1_CACHE_BYTES
52de74dd 763ENTRY(boot_gdt)
1da177e4
LT
764 .fill GDT_ENTRY_BOOT_CS,8,0
765 .quad 0x00cf9a000000ffff /* kernel 4GB code at 0x00000000 */
766 .quad 0x00cf92000000ffff /* kernel 4GB data at 0x00000000 */