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x86/idt: Move IST stack based traps to table init
[people/arne_f/kernel.git] / arch / x86 / kernel / idt.c
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1/*
2 * Interrupt descriptor table related code
3 *
4 * This file is licensed under the GPL V2
5 */
6#include <linux/interrupt.h>
7
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8#include <asm/traps.h>
9#include <asm/proto.h>
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10#include <asm/desc.h>
11
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12struct idt_data {
13 unsigned int vector;
14 unsigned int segment;
15 struct idt_bits bits;
16 const void *addr;
17};
18
19#define DPL0 0x0
20#define DPL3 0x3
21
22#define DEFAULT_STACK 0
23
24#define G(_vector, _addr, _ist, _type, _dpl, _segment) \
25 { \
26 .vector = _vector, \
27 .bits.ist = _ist, \
28 .bits.type = _type, \
29 .bits.dpl = _dpl, \
30 .bits.p = 1, \
31 .addr = _addr, \
32 .segment = _segment, \
33 }
34
35/* Interrupt gate */
36#define INTG(_vector, _addr) \
37 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS)
38
39/* System interrupt gate */
40#define SYSG(_vector, _addr) \
41 G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS)
42
43/* Interrupt gate with interrupt stack */
44#define ISTG(_vector, _addr, _ist) \
45 G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS)
46
47/* Task gate */
48#define TSKG(_vector, _gdt) \
49 G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3)
50
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51/*
52 * Early traps running on the DEFAULT_STACK because the other interrupt
53 * stacks work only after cpu_init().
54 */
55static const __initdata struct idt_data early_idts[] = {
56 INTG(X86_TRAP_DB, debug),
57 SYSG(X86_TRAP_BP, int3),
58#ifdef CONFIG_X86_32
59 INTG(X86_TRAP_PF, page_fault),
60#endif
61};
62
63#ifdef CONFIG_X86_64
64/*
65 * Early traps running on the DEFAULT_STACK because the other interrupt
66 * stacks work only after cpu_init().
67 */
68static const __initdata struct idt_data early_pf_idts[] = {
69 INTG(X86_TRAP_PF, page_fault),
70};
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71
72/*
73 * Override for the debug_idt. Same as the default, but with interrupt
74 * stack set to DEFAULT_STACK (0). Required for NMI trap handling.
75 */
76static const __initdata struct idt_data dbg_idts[] = {
77 INTG(X86_TRAP_DB, debug),
78 INTG(X86_TRAP_BP, int3),
79};
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80#endif
81
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82/* Must be page-aligned because the real IDT is used in a fixmap. */
83gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss;
84
d8ed9d48 85struct desc_ptr idt_descr __ro_after_init = {
16bc18d8 86 .size = (IDT_ENTRIES * 2 * sizeof(unsigned long)) - 1,
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87 .address = (unsigned long) idt_table,
88};
89
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90#ifdef CONFIG_X86_64
91/* No need to be aligned, but done to keep all IDTs defined the same way. */
92gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss;
93
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94/*
95 * The exceptions which use Interrupt stacks. They are setup after
96 * cpu_init() when the TSS has been initialized.
97 */
98static const __initdata struct idt_data ist_idts[] = {
99 ISTG(X86_TRAP_DB, debug, DEBUG_STACK),
100 ISTG(X86_TRAP_NMI, nmi, NMI_STACK),
101 ISTG(X86_TRAP_BP, int3, DEBUG_STACK),
102 ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK),
103#ifdef CONFIG_X86_MCE
104 ISTG(X86_TRAP_MC, &machine_check, MCE_STACK),
105#endif
106};
107
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108/*
109 * Override for the debug_idt. Same as the default, but with interrupt
110 * stack set to DEFAULT_STACK (0). Required for NMI trap handling.
111 */
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112const struct desc_ptr debug_idt_descr = {
113 .size = IDT_ENTRIES * 16 - 1,
114 .address = (unsigned long) debug_idt_table,
115};
116#endif
e802a51e 117
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118static inline void idt_init_desc(gate_desc *gate, const struct idt_data *d)
119{
120 unsigned long addr = (unsigned long) d->addr;
121
122 gate->offset_low = (u16) addr;
123 gate->segment = (u16) d->segment;
124 gate->bits = d->bits;
125 gate->offset_middle = (u16) (addr >> 16);
126#ifdef CONFIG_X86_64
127 gate->offset_high = (u32) (addr >> 32);
128 gate->reserved = 0;
129#endif
130}
131
132static __init void
133idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size)
134{
135 gate_desc desc;
136
137 for (; size > 0; t++, size--) {
138 idt_init_desc(&desc, t);
139 set_bit(t->vector, used_vectors);
140 write_idt_entry(idt, t->vector, &desc);
141 }
142}
143
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144/**
145 * idt_setup_early_traps - Initialize the idt table with early traps
146 *
147 * On X8664 these traps do not use interrupt stacks as they can't work
148 * before cpu_init() is invoked and sets up TSS. The IST variants are
149 * installed after that.
150 */
151void __init idt_setup_early_traps(void)
152{
153 idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts));
154 load_idt(&idt_descr);
155}
156
157#ifdef CONFIG_X86_64
158/**
159 * idt_setup_early_pf - Initialize the idt table with early pagefault handler
160 *
161 * On X8664 this does not use interrupt stacks as they can't work before
162 * cpu_init() is invoked and sets up TSS. The IST variant is installed
163 * after that.
164 *
165 * FIXME: Why is 32bit and 64bit installing the PF handler at different
166 * places in the early setup code?
167 */
168void __init idt_setup_early_pf(void)
169{
170 idt_setup_from_table(idt_table, early_pf_idts,
171 ARRAY_SIZE(early_pf_idts));
172}
0a30908b 173
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174/**
175 * idt_setup_ist_traps - Initialize the idt table with traps using IST
176 */
177void __init idt_setup_ist_traps(void)
178{
179 idt_setup_from_table(idt_table, ist_idts, ARRAY_SIZE(ist_idts));
180}
181
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182/**
183 * idt_setup_debugidt_traps - Initialize the debug idt table with debug traps
184 */
185void __init idt_setup_debugidt_traps(void)
186{
187 memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16);
188
189 idt_setup_from_table(debug_idt_table, dbg_idts, ARRAY_SIZE(dbg_idts));
190}
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191#endif
192
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193/**
194 * idt_setup_early_handler - Initializes the idt table with early handlers
195 */
196void __init idt_setup_early_handler(void)
197{
198 int i;
199
200 for (i = 0; i < NUM_EXCEPTION_VECTORS; i++)
201 set_intr_gate(i, early_idt_handler_array[i]);
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202#ifdef CONFIG_X86_32
203 for ( ; i < NR_VECTORS; i++)
204 set_intr_gate(i, early_ignore_irq);
205#endif
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206 load_idt(&idt_descr);
207}
208
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209/**
210 * idt_invalidate - Invalidate interrupt descriptor table
211 * @addr: The virtual address of the 'invalid' IDT
212 */
213void idt_invalidate(void *addr)
214{
215 struct desc_ptr idt = { .address = (unsigned long) addr, .size = 0 };
216
217 load_idt(&idt);
218}