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d8ed9d48 TG |
1 | /* |
2 | * Interrupt descriptor table related code | |
3 | * | |
4 | * This file is licensed under the GPL V2 | |
5 | */ | |
6 | #include <linux/interrupt.h> | |
7 | ||
3318e974 TG |
8 | #include <asm/traps.h> |
9 | #include <asm/proto.h> | |
d8ed9d48 TG |
10 | #include <asm/desc.h> |
11 | ||
3318e974 TG |
12 | struct idt_data { |
13 | unsigned int vector; | |
14 | unsigned int segment; | |
15 | struct idt_bits bits; | |
16 | const void *addr; | |
17 | }; | |
18 | ||
19 | #define DPL0 0x0 | |
20 | #define DPL3 0x3 | |
21 | ||
22 | #define DEFAULT_STACK 0 | |
23 | ||
24 | #define G(_vector, _addr, _ist, _type, _dpl, _segment) \ | |
25 | { \ | |
26 | .vector = _vector, \ | |
27 | .bits.ist = _ist, \ | |
28 | .bits.type = _type, \ | |
29 | .bits.dpl = _dpl, \ | |
30 | .bits.p = 1, \ | |
31 | .addr = _addr, \ | |
32 | .segment = _segment, \ | |
33 | } | |
34 | ||
35 | /* Interrupt gate */ | |
36 | #define INTG(_vector, _addr) \ | |
37 | G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL0, __KERNEL_CS) | |
38 | ||
39 | /* System interrupt gate */ | |
40 | #define SYSG(_vector, _addr) \ | |
41 | G(_vector, _addr, DEFAULT_STACK, GATE_INTERRUPT, DPL3, __KERNEL_CS) | |
42 | ||
43 | /* Interrupt gate with interrupt stack */ | |
44 | #define ISTG(_vector, _addr, _ist) \ | |
45 | G(_vector, _addr, _ist, GATE_INTERRUPT, DPL0, __KERNEL_CS) | |
46 | ||
47 | /* Task gate */ | |
48 | #define TSKG(_vector, _gdt) \ | |
49 | G(_vector, NULL, DEFAULT_STACK, GATE_TASK, DPL0, _gdt << 3) | |
50 | ||
433f8924 TG |
51 | /* |
52 | * Early traps running on the DEFAULT_STACK because the other interrupt | |
53 | * stacks work only after cpu_init(). | |
54 | */ | |
55 | static const __initdata struct idt_data early_idts[] = { | |
56 | INTG(X86_TRAP_DB, debug), | |
57 | SYSG(X86_TRAP_BP, int3), | |
58 | #ifdef CONFIG_X86_32 | |
59 | INTG(X86_TRAP_PF, page_fault), | |
60 | #endif | |
61 | }; | |
62 | ||
b70543a0 TG |
63 | /* |
64 | * The default IDT entries which are set up in trap_init() before | |
65 | * cpu_init() is invoked. Interrupt stacks cannot be used at that point and | |
66 | * the traps which use them are reinitialized with IST after cpu_init() has | |
67 | * set up TSS. | |
68 | */ | |
69 | static const __initdata struct idt_data def_idts[] = { | |
70 | INTG(X86_TRAP_DE, divide_error), | |
71 | INTG(X86_TRAP_NMI, nmi), | |
72 | INTG(X86_TRAP_BR, bounds), | |
73 | INTG(X86_TRAP_UD, invalid_op), | |
74 | INTG(X86_TRAP_NM, device_not_available), | |
75 | INTG(X86_TRAP_OLD_MF, coprocessor_segment_overrun), | |
76 | INTG(X86_TRAP_TS, invalid_TSS), | |
77 | INTG(X86_TRAP_NP, segment_not_present), | |
78 | INTG(X86_TRAP_SS, stack_segment), | |
79 | INTG(X86_TRAP_GP, general_protection), | |
80 | INTG(X86_TRAP_SPURIOUS, spurious_interrupt_bug), | |
81 | INTG(X86_TRAP_MF, coprocessor_error), | |
82 | INTG(X86_TRAP_AC, alignment_check), | |
83 | INTG(X86_TRAP_XF, simd_coprocessor_error), | |
84 | ||
85 | #ifdef CONFIG_X86_32 | |
86 | TSKG(X86_TRAP_DF, GDT_ENTRY_DOUBLEFAULT_TSS), | |
87 | #else | |
88 | INTG(X86_TRAP_DF, double_fault), | |
89 | #endif | |
90 | INTG(X86_TRAP_DB, debug), | |
91 | INTG(X86_TRAP_NMI, nmi), | |
92 | INTG(X86_TRAP_BP, int3), | |
93 | ||
94 | #ifdef CONFIG_X86_MCE | |
95 | INTG(X86_TRAP_MC, &machine_check), | |
96 | #endif | |
97 | ||
98 | SYSG(X86_TRAP_OF, overflow), | |
99 | #if defined(CONFIG_IA32_EMULATION) | |
100 | SYSG(IA32_SYSCALL_VECTOR, entry_INT80_compat), | |
101 | #elif defined(CONFIG_X86_32) | |
102 | SYSG(IA32_SYSCALL_VECTOR, entry_INT80_32), | |
103 | #endif | |
104 | }; | |
105 | ||
433f8924 TG |
106 | #ifdef CONFIG_X86_64 |
107 | /* | |
108 | * Early traps running on the DEFAULT_STACK because the other interrupt | |
109 | * stacks work only after cpu_init(). | |
110 | */ | |
111 | static const __initdata struct idt_data early_pf_idts[] = { | |
112 | INTG(X86_TRAP_PF, page_fault), | |
113 | }; | |
0a30908b TG |
114 | |
115 | /* | |
116 | * Override for the debug_idt. Same as the default, but with interrupt | |
117 | * stack set to DEFAULT_STACK (0). Required for NMI trap handling. | |
118 | */ | |
119 | static const __initdata struct idt_data dbg_idts[] = { | |
120 | INTG(X86_TRAP_DB, debug), | |
121 | INTG(X86_TRAP_BP, int3), | |
122 | }; | |
433f8924 TG |
123 | #endif |
124 | ||
d8ed9d48 TG |
125 | /* Must be page-aligned because the real IDT is used in a fixmap. */ |
126 | gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss; | |
127 | ||
d8ed9d48 | 128 | struct desc_ptr idt_descr __ro_after_init = { |
16bc18d8 | 129 | .size = (IDT_ENTRIES * 2 * sizeof(unsigned long)) - 1, |
d8ed9d48 TG |
130 | .address = (unsigned long) idt_table, |
131 | }; | |
132 | ||
16bc18d8 TG |
133 | #ifdef CONFIG_X86_64 |
134 | /* No need to be aligned, but done to keep all IDTs defined the same way. */ | |
135 | gate_desc debug_idt_table[IDT_ENTRIES] __page_aligned_bss; | |
136 | ||
90f6225f TG |
137 | /* |
138 | * The exceptions which use Interrupt stacks. They are setup after | |
139 | * cpu_init() when the TSS has been initialized. | |
140 | */ | |
141 | static const __initdata struct idt_data ist_idts[] = { | |
142 | ISTG(X86_TRAP_DB, debug, DEBUG_STACK), | |
143 | ISTG(X86_TRAP_NMI, nmi, NMI_STACK), | |
144 | ISTG(X86_TRAP_BP, int3, DEBUG_STACK), | |
145 | ISTG(X86_TRAP_DF, double_fault, DOUBLEFAULT_STACK), | |
146 | #ifdef CONFIG_X86_MCE | |
147 | ISTG(X86_TRAP_MC, &machine_check, MCE_STACK), | |
148 | #endif | |
149 | }; | |
150 | ||
0a30908b TG |
151 | /* |
152 | * Override for the debug_idt. Same as the default, but with interrupt | |
153 | * stack set to DEFAULT_STACK (0). Required for NMI trap handling. | |
154 | */ | |
d8ed9d48 TG |
155 | const struct desc_ptr debug_idt_descr = { |
156 | .size = IDT_ENTRIES * 16 - 1, | |
157 | .address = (unsigned long) debug_idt_table, | |
158 | }; | |
159 | #endif | |
e802a51e | 160 | |
3318e974 TG |
161 | static inline void idt_init_desc(gate_desc *gate, const struct idt_data *d) |
162 | { | |
163 | unsigned long addr = (unsigned long) d->addr; | |
164 | ||
165 | gate->offset_low = (u16) addr; | |
166 | gate->segment = (u16) d->segment; | |
167 | gate->bits = d->bits; | |
168 | gate->offset_middle = (u16) (addr >> 16); | |
169 | #ifdef CONFIG_X86_64 | |
170 | gate->offset_high = (u32) (addr >> 32); | |
171 | gate->reserved = 0; | |
172 | #endif | |
173 | } | |
174 | ||
175 | static __init void | |
176 | idt_setup_from_table(gate_desc *idt, const struct idt_data *t, int size) | |
177 | { | |
178 | gate_desc desc; | |
179 | ||
180 | for (; size > 0; t++, size--) { | |
181 | idt_init_desc(&desc, t); | |
182 | set_bit(t->vector, used_vectors); | |
183 | write_idt_entry(idt, t->vector, &desc); | |
184 | } | |
185 | } | |
186 | ||
433f8924 TG |
187 | /** |
188 | * idt_setup_early_traps - Initialize the idt table with early traps | |
189 | * | |
190 | * On X8664 these traps do not use interrupt stacks as they can't work | |
191 | * before cpu_init() is invoked and sets up TSS. The IST variants are | |
192 | * installed after that. | |
193 | */ | |
194 | void __init idt_setup_early_traps(void) | |
195 | { | |
196 | idt_setup_from_table(idt_table, early_idts, ARRAY_SIZE(early_idts)); | |
197 | load_idt(&idt_descr); | |
198 | } | |
199 | ||
b70543a0 TG |
200 | /** |
201 | * idt_setup_traps - Initialize the idt table with default traps | |
202 | */ | |
203 | void __init idt_setup_traps(void) | |
204 | { | |
205 | idt_setup_from_table(idt_table, def_idts, ARRAY_SIZE(def_idts)); | |
206 | } | |
207 | ||
433f8924 TG |
208 | #ifdef CONFIG_X86_64 |
209 | /** | |
210 | * idt_setup_early_pf - Initialize the idt table with early pagefault handler | |
211 | * | |
212 | * On X8664 this does not use interrupt stacks as they can't work before | |
213 | * cpu_init() is invoked and sets up TSS. The IST variant is installed | |
214 | * after that. | |
215 | * | |
216 | * FIXME: Why is 32bit and 64bit installing the PF handler at different | |
217 | * places in the early setup code? | |
218 | */ | |
219 | void __init idt_setup_early_pf(void) | |
220 | { | |
221 | idt_setup_from_table(idt_table, early_pf_idts, | |
222 | ARRAY_SIZE(early_pf_idts)); | |
223 | } | |
0a30908b | 224 | |
90f6225f TG |
225 | /** |
226 | * idt_setup_ist_traps - Initialize the idt table with traps using IST | |
227 | */ | |
228 | void __init idt_setup_ist_traps(void) | |
229 | { | |
230 | idt_setup_from_table(idt_table, ist_idts, ARRAY_SIZE(ist_idts)); | |
231 | } | |
232 | ||
0a30908b TG |
233 | /** |
234 | * idt_setup_debugidt_traps - Initialize the debug idt table with debug traps | |
235 | */ | |
236 | void __init idt_setup_debugidt_traps(void) | |
237 | { | |
238 | memcpy(&debug_idt_table, &idt_table, IDT_ENTRIES * 16); | |
239 | ||
240 | idt_setup_from_table(debug_idt_table, dbg_idts, ARRAY_SIZE(dbg_idts)); | |
241 | } | |
433f8924 TG |
242 | #endif |
243 | ||
588787fd TG |
244 | /** |
245 | * idt_setup_early_handler - Initializes the idt table with early handlers | |
246 | */ | |
247 | void __init idt_setup_early_handler(void) | |
248 | { | |
249 | int i; | |
250 | ||
251 | for (i = 0; i < NUM_EXCEPTION_VECTORS; i++) | |
252 | set_intr_gate(i, early_idt_handler_array[i]); | |
87e81786 TG |
253 | #ifdef CONFIG_X86_32 |
254 | for ( ; i < NR_VECTORS; i++) | |
255 | set_intr_gate(i, early_ignore_irq); | |
256 | #endif | |
588787fd TG |
257 | load_idt(&idt_descr); |
258 | } | |
259 | ||
e802a51e TG |
260 | /** |
261 | * idt_invalidate - Invalidate interrupt descriptor table | |
262 | * @addr: The virtual address of the 'invalid' IDT | |
263 | */ | |
264 | void idt_invalidate(void *addr) | |
265 | { | |
266 | struct desc_ptr idt = { .address = (unsigned long) addr, .size = 0 }; | |
267 | ||
268 | load_idt(&idt); | |
269 | } |