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9ff554e9 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
c767a54b | 2 | /* |
4cedb334 GOC |
3 | * x86 SMP booting functions |
4 | * | |
87c6fe26 | 5 | * (c) 1995 Alan Cox, Building #3 <alan@lxorguk.ukuu.org.uk> |
8f47e163 | 6 | * (c) 1998, 1999, 2000, 2009 Ingo Molnar <mingo@redhat.com> |
4cedb334 GOC |
7 | * Copyright 2001 Andi Kleen, SuSE Labs. |
8 | * | |
9 | * Much of the core SMP work is based on previous work by Thomas Radke, to | |
10 | * whom a great many thanks are extended. | |
11 | * | |
12 | * Thanks to Intel for making available several different Pentium, | |
13 | * Pentium Pro and Pentium-II/Xeon MP machines. | |
14 | * Original development of Linux SMP code supported by Caldera. | |
15 | * | |
4cedb334 GOC |
16 | * Fixes |
17 | * Felix Koop : NR_CPUS used properly | |
18 | * Jose Renau : Handle single CPU case. | |
19 | * Alan Cox : By repeated request 8) - Total BogoMIPS report. | |
20 | * Greg Wright : Fix for kernel stacks panic. | |
21 | * Erich Boleyn : MP v1.4 and additional changes. | |
22 | * Matthias Sattler : Changes for 2.1 kernel map. | |
23 | * Michel Lespinasse : Changes for 2.1 kernel map. | |
24 | * Michael Chastain : Change trampoline.S to gnu as. | |
25 | * Alan Cox : Dumb bug: 'B' step PPro's are fine | |
26 | * Ingo Molnar : Added APIC timers, based on code | |
27 | * from Jose Renau | |
28 | * Ingo Molnar : various cleanups and rewrites | |
29 | * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug. | |
30 | * Maciej W. Rozycki : Bits for genuine 82489DX APICs | |
31 | * Andi Kleen : Changed for SMP boot into long mode. | |
32 | * Martin J. Bligh : Added support for multi-quad systems | |
33 | * Dave Jones : Report invalid combinations of Athlon CPUs. | |
34 | * Rusty Russell : Hacked into shape for new "hotplug" boot process. | |
35 | * Andi Kleen : Converted to new state machine. | |
36 | * Ashok Raj : CPU hotplug support | |
37 | * Glauber Costa : i386 and x86_64 integration | |
38 | */ | |
39 | ||
c767a54b JP |
40 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
41 | ||
68a1c3f8 GC |
42 | #include <linux/init.h> |
43 | #include <linux/smp.h> | |
186f4360 | 44 | #include <linux/export.h> |
70708a18 | 45 | #include <linux/sched.h> |
105ab3d8 | 46 | #include <linux/sched/topology.h> |
ef8bd77f | 47 | #include <linux/sched/hotplug.h> |
68db0cf1 | 48 | #include <linux/sched/task_stack.h> |
69c18c15 | 49 | #include <linux/percpu.h> |
57c8a661 | 50 | #include <linux/memblock.h> |
cb3c8b90 GOC |
51 | #include <linux/err.h> |
52 | #include <linux/nmi.h> | |
69575d38 | 53 | #include <linux/tboot.h> |
35f720c5 | 54 | #include <linux/stackprotector.h> |
5a0e3ad6 | 55 | #include <linux/gfp.h> |
1a022e3f | 56 | #include <linux/cpuidle.h> |
98fa15f3 | 57 | #include <linux/numa.h> |
69c18c15 | 58 | |
8aef135c | 59 | #include <asm/acpi.h> |
cb3c8b90 | 60 | #include <asm/desc.h> |
69c18c15 GC |
61 | #include <asm/nmi.h> |
62 | #include <asm/irq.h> | |
48927bbb | 63 | #include <asm/realmode.h> |
69c18c15 GC |
64 | #include <asm/cpu.h> |
65 | #include <asm/numa.h> | |
cb3c8b90 GOC |
66 | #include <asm/pgtable.h> |
67 | #include <asm/tlbflush.h> | |
68 | #include <asm/mtrr.h> | |
ea530692 | 69 | #include <asm/mwait.h> |
7b6aa335 | 70 | #include <asm/apic.h> |
7167d08e | 71 | #include <asm/io_apic.h> |
78f7f1e5 | 72 | #include <asm/fpu/internal.h> |
569712b2 | 73 | #include <asm/setup.h> |
bdbcdd48 | 74 | #include <asm/uv/uv.h> |
cb3c8b90 | 75 | #include <linux/mc146818rtc.h> |
b81bb373 | 76 | #include <asm/i8259.h> |
646e29a1 | 77 | #include <asm/misc.h> |
9043442b | 78 | #include <asm/qspinlock.h> |
1340ccfa AS |
79 | #include <asm/intel-family.h> |
80 | #include <asm/cpu_device_id.h> | |
1f50ddb4 | 81 | #include <asm/spec-ctrl.h> |
447ae316 | 82 | #include <asm/hw_irq.h> |
48927bbb | 83 | |
a355352b | 84 | /* representing HT siblings of each logical CPU */ |
0816b0f0 | 85 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_sibling_map); |
a355352b GC |
86 | EXPORT_PER_CPU_SYMBOL(cpu_sibling_map); |
87 | ||
88 | /* representing HT and core siblings of each logical CPU */ | |
0816b0f0 | 89 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_core_map); |
a355352b GC |
90 | EXPORT_PER_CPU_SYMBOL(cpu_core_map); |
91 | ||
2e4c54da LB |
92 | /* representing HT, core, and die siblings of each logical CPU */ |
93 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_die_map); | |
94 | EXPORT_PER_CPU_SYMBOL(cpu_die_map); | |
95 | ||
0816b0f0 | 96 | DEFINE_PER_CPU_READ_MOSTLY(cpumask_var_t, cpu_llc_shared_map); |
b3d7336d | 97 | |
a355352b | 98 | /* Per CPU bogomips and other parameters */ |
2c773dd3 | 99 | DEFINE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info); |
a355352b | 100 | EXPORT_PER_CPU_SYMBOL(cpu_info); |
768d9505 | 101 | |
1f12e32f | 102 | /* Logical package management. We might want to allocate that dynamically */ |
1f12e32f TG |
103 | unsigned int __max_logical_packages __read_mostly; |
104 | EXPORT_SYMBOL(__max_logical_packages); | |
7b0501b1 | 105 | static unsigned int logical_packages __read_mostly; |
212bf4fd | 106 | static unsigned int logical_die __read_mostly; |
1f12e32f | 107 | |
70b8301f | 108 | /* Maximum number of SMT threads on any online core */ |
947134d9 | 109 | int __read_mostly __max_smt_threads = 1; |
70b8301f | 110 | |
7d25127c TC |
111 | /* Flag to indicate if a complete sched domain rebuild is required */ |
112 | bool x86_topology_update; | |
113 | ||
114 | int arch_update_cpu_topology(void) | |
115 | { | |
116 | int retval = x86_topology_update; | |
117 | ||
118 | x86_topology_update = false; | |
119 | return retval; | |
120 | } | |
121 | ||
f77aa308 TG |
122 | static inline void smpboot_setup_warm_reset_vector(unsigned long start_eip) |
123 | { | |
124 | unsigned long flags; | |
125 | ||
126 | spin_lock_irqsave(&rtc_lock, flags); | |
127 | CMOS_WRITE(0xa, 0xf); | |
128 | spin_unlock_irqrestore(&rtc_lock, flags); | |
f77aa308 TG |
129 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_HIGH)) = |
130 | start_eip >> 4; | |
f77aa308 TG |
131 | *((volatile unsigned short *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = |
132 | start_eip & 0xf; | |
f77aa308 TG |
133 | } |
134 | ||
135 | static inline void smpboot_restore_warm_reset_vector(void) | |
136 | { | |
137 | unsigned long flags; | |
138 | ||
f77aa308 TG |
139 | /* |
140 | * Paranoid: Set warm reset code and vector here back | |
141 | * to default values. | |
142 | */ | |
143 | spin_lock_irqsave(&rtc_lock, flags); | |
144 | CMOS_WRITE(0, 0xf); | |
145 | spin_unlock_irqrestore(&rtc_lock, flags); | |
146 | ||
147 | *((volatile u32 *)phys_to_virt(TRAMPOLINE_PHYS_LOW)) = 0; | |
148 | } | |
149 | ||
b56e7d45 | 150 | static void init_freq_invariance(bool secondary); |
1567c3e3 | 151 | |
cb3c8b90 | 152 | /* |
30106c17 FY |
153 | * Report back to the Boot Processor during boot time or to the caller processor |
154 | * during CPU online. | |
cb3c8b90 | 155 | */ |
148f9bb8 | 156 | static void smp_callin(void) |
cb3c8b90 | 157 | { |
f91fecc0 | 158 | int cpuid; |
cb3c8b90 GOC |
159 | |
160 | /* | |
161 | * If waken up by an INIT in an 82489DX configuration | |
656bba30 LB |
162 | * cpu_callout_mask guarantees we don't get here before |
163 | * an INIT_deassert IPI reaches our local APIC, so it is | |
164 | * now safe to touch our local APIC. | |
cb3c8b90 | 165 | */ |
e1c467e6 | 166 | cpuid = smp_processor_id(); |
cb3c8b90 | 167 | |
cb3c8b90 GOC |
168 | /* |
169 | * the boot CPU has finished the init stage and is spinning | |
170 | * on callin_map until we finish. We are free to set up this | |
171 | * CPU, first the APIC. (this is probably redundant on most | |
172 | * boards) | |
173 | */ | |
05f7e46d | 174 | apic_ap_setup(); |
cb3c8b90 | 175 | |
b565201c JS |
176 | /* |
177 | * Save our processor parameters. Note: this information | |
178 | * is needed for clock calibration. | |
179 | */ | |
180 | smp_store_cpu_info(cpuid); | |
181 | ||
76ce7cfe PT |
182 | /* |
183 | * The topology information must be up to date before | |
184 | * calibrate_delay() and notify_cpu_starting(). | |
185 | */ | |
186 | set_cpu_sibling_map(raw_smp_processor_id()); | |
187 | ||
b56e7d45 | 188 | init_freq_invariance(true); |
1567c3e3 | 189 | |
cb3c8b90 GOC |
190 | /* |
191 | * Get our bogomips. | |
b565201c JS |
192 | * Update loops_per_jiffy in cpu_data. Previous call to |
193 | * smp_store_cpu_info() stored a value that is close but not as | |
194 | * accurate as the value just calculated. | |
cb3c8b90 | 195 | */ |
cb3c8b90 | 196 | calibrate_delay(); |
b565201c | 197 | cpu_data(cpuid).loops_per_jiffy = loops_per_jiffy; |
cfc1b9a6 | 198 | pr_debug("Stack at about %p\n", &cpuid); |
cb3c8b90 | 199 | |
5ef428c4 AK |
200 | wmb(); |
201 | ||
85257024 PZ |
202 | notify_cpu_starting(cpuid); |
203 | ||
cb3c8b90 GOC |
204 | /* |
205 | * Allow the master to continue. | |
206 | */ | |
c2d1cec1 | 207 | cpumask_set_cpu(cpuid, cpu_callin_mask); |
cb3c8b90 GOC |
208 | } |
209 | ||
e1c467e6 FY |
210 | static int cpu0_logical_apicid; |
211 | static int enable_start_cpu0; | |
bbc2ff6a GOC |
212 | /* |
213 | * Activate a secondary processor. | |
214 | */ | |
148f9bb8 | 215 | static void notrace start_secondary(void *unused) |
bbc2ff6a GOC |
216 | { |
217 | /* | |
c7ad5ad2 AL |
218 | * Don't put *anything* except direct CPU state initialization |
219 | * before cpu_init(), SMP booting is too fragile that we want to | |
220 | * limit the things done here to the most necessary things. | |
bbc2ff6a | 221 | */ |
7652ac92 | 222 | cr4_init(); |
e1c467e6 | 223 | |
fd89a137 | 224 | #ifdef CONFIG_X86_32 |
b40827fa | 225 | /* switch away from the initial page table */ |
fd89a137 JR |
226 | load_cr3(swapper_pg_dir); |
227 | __flush_tlb_all(); | |
228 | #endif | |
55d2d0ad | 229 | load_current_idt(); |
4ba55e65 AL |
230 | cpu_init(); |
231 | x86_cpuinit.early_percpu_clock_init(); | |
232 | preempt_disable(); | |
233 | smp_callin(); | |
234 | ||
235 | enable_start_cpu0 = 0; | |
236 | ||
bbc2ff6a GOC |
237 | /* otherwise gcc will move up smp_processor_id before the cpu_init */ |
238 | barrier(); | |
239 | /* | |
a1652bb8 | 240 | * Check TSC synchronization with the boot CPU: |
bbc2ff6a GOC |
241 | */ |
242 | check_tsc_sync_target(); | |
243 | ||
1f50ddb4 TG |
244 | speculative_store_bypass_ht_init(); |
245 | ||
bbc2ff6a | 246 | /* |
8ed4f3e6 TG |
247 | * Lock vector_lock, set CPU online and bring the vector |
248 | * allocator online. Online must be set with vector_lock held | |
249 | * to prevent a concurrent irq setup/teardown from seeing a | |
250 | * half valid vector space. | |
bbc2ff6a | 251 | */ |
d388e5fd | 252 | lock_vector_lock(); |
c2d1cec1 | 253 | set_cpu_online(smp_processor_id(), true); |
8ed4f3e6 | 254 | lapic_online(); |
d388e5fd | 255 | unlock_vector_lock(); |
2a442c9c | 256 | cpu_set_state_online(smp_processor_id()); |
78c06176 | 257 | x86_platform.nmi_init(); |
bbc2ff6a | 258 | |
0cefa5b9 MS |
259 | /* enable local interrupts */ |
260 | local_irq_enable(); | |
261 | ||
35f720c5 JP |
262 | /* to prevent fake stack check failure in clock setup */ |
263 | boot_init_stack_canary(); | |
0cefa5b9 | 264 | |
736decac | 265 | x86_cpuinit.setup_percpu_clockev(); |
bbc2ff6a GOC |
266 | |
267 | wmb(); | |
fc6d73d6 | 268 | cpu_startup_entry(CPUHP_AP_ONLINE_IDLE); |
a9a3ed1e BP |
269 | |
270 | /* | |
271 | * Prevent tail call to cpu_startup_entry() because the stack protector | |
272 | * guard has been changed a couple of function calls up, in | |
273 | * boot_init_stack_canary() and must not be checked before tail calling | |
274 | * another function. | |
275 | */ | |
276 | prevent_tail_call_optimization(); | |
bbc2ff6a GOC |
277 | } |
278 | ||
6a4d2657 TG |
279 | /** |
280 | * topology_is_primary_thread - Check whether CPU is the primary SMT thread | |
281 | * @cpu: CPU to check | |
282 | */ | |
283 | bool topology_is_primary_thread(unsigned int cpu) | |
284 | { | |
285 | return apic_id_is_primary_thread(per_cpu(x86_cpu_to_apicid, cpu)); | |
286 | } | |
287 | ||
f048c399 TG |
288 | /** |
289 | * topology_smt_supported - Check whether SMT is supported by the CPUs | |
290 | */ | |
291 | bool topology_smt_supported(void) | |
292 | { | |
293 | return smp_num_siblings > 1; | |
294 | } | |
295 | ||
30bb9811 AK |
296 | /** |
297 | * topology_phys_to_logical_pkg - Map a physical package id to a logical | |
298 | * | |
299 | * Returns logical package id or -1 if not found | |
300 | */ | |
301 | int topology_phys_to_logical_pkg(unsigned int phys_pkg) | |
302 | { | |
303 | int cpu; | |
304 | ||
305 | for_each_possible_cpu(cpu) { | |
306 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
307 | ||
308 | if (c->initialized && c->phys_proc_id == phys_pkg) | |
309 | return c->logical_proc_id; | |
310 | } | |
311 | return -1; | |
312 | } | |
313 | EXPORT_SYMBOL(topology_phys_to_logical_pkg); | |
212bf4fd LB |
314 | /** |
315 | * topology_phys_to_logical_die - Map a physical die id to logical | |
316 | * | |
317 | * Returns logical die id or -1 if not found | |
318 | */ | |
319 | int topology_phys_to_logical_die(unsigned int die_id, unsigned int cur_cpu) | |
320 | { | |
321 | int cpu; | |
322 | int proc_id = cpu_data(cur_cpu).phys_proc_id; | |
323 | ||
324 | for_each_possible_cpu(cpu) { | |
325 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
326 | ||
327 | if (c->initialized && c->cpu_die_id == die_id && | |
328 | c->phys_proc_id == proc_id) | |
329 | return c->logical_die_id; | |
330 | } | |
331 | return -1; | |
332 | } | |
333 | EXPORT_SYMBOL(topology_phys_to_logical_die); | |
30bb9811 | 334 | |
9d85eb91 TG |
335 | /** |
336 | * topology_update_package_map - Update the physical to logical package map | |
337 | * @pkg: The physical package id as retrieved via CPUID | |
338 | * @cpu: The cpu for which this is updated | |
339 | */ | |
340 | int topology_update_package_map(unsigned int pkg, unsigned int cpu) | |
1f12e32f | 341 | { |
30bb9811 | 342 | int new; |
1f12e32f | 343 | |
30bb9811 AK |
344 | /* Already available somewhere? */ |
345 | new = topology_phys_to_logical_pkg(pkg); | |
346 | if (new >= 0) | |
1f12e32f TG |
347 | goto found; |
348 | ||
7b0501b1 | 349 | new = logical_packages++; |
9d85eb91 TG |
350 | if (new != pkg) { |
351 | pr_info("CPU %u Converting physical %u to logical package %u\n", | |
352 | cpu, pkg, new); | |
353 | } | |
1f12e32f | 354 | found: |
30bb9811 | 355 | cpu_data(cpu).logical_proc_id = new; |
1f12e32f TG |
356 | return 0; |
357 | } | |
212bf4fd LB |
358 | /** |
359 | * topology_update_die_map - Update the physical to logical die map | |
360 | * @die: The die id as retrieved via CPUID | |
361 | * @cpu: The cpu for which this is updated | |
362 | */ | |
363 | int topology_update_die_map(unsigned int die, unsigned int cpu) | |
364 | { | |
365 | int new; | |
366 | ||
367 | /* Already available somewhere? */ | |
368 | new = topology_phys_to_logical_die(die, cpu); | |
369 | if (new >= 0) | |
370 | goto found; | |
371 | ||
372 | new = logical_die++; | |
373 | if (new != die) { | |
374 | pr_info("CPU %u Converting physical %u to logical die %u\n", | |
375 | cpu, die, new); | |
376 | } | |
377 | found: | |
378 | cpu_data(cpu).logical_die_id = new; | |
379 | return 0; | |
380 | } | |
1f12e32f | 381 | |
30106c17 FY |
382 | void __init smp_store_boot_cpu_info(void) |
383 | { | |
384 | int id = 0; /* CPU 0 */ | |
385 | struct cpuinfo_x86 *c = &cpu_data(id); | |
386 | ||
387 | *c = boot_cpu_data; | |
388 | c->cpu_index = id; | |
b4c0a732 | 389 | topology_update_package_map(c->phys_proc_id, id); |
212bf4fd | 390 | topology_update_die_map(c->cpu_die_id, id); |
30bb9811 | 391 | c->initialized = true; |
30106c17 FY |
392 | } |
393 | ||
1d89a7f0 GOC |
394 | /* |
395 | * The bootstrap kernel entry code has set these up. Save them for | |
396 | * a given CPU | |
397 | */ | |
148f9bb8 | 398 | void smp_store_cpu_info(int id) |
1d89a7f0 GOC |
399 | { |
400 | struct cpuinfo_x86 *c = &cpu_data(id); | |
401 | ||
30bb9811 AK |
402 | /* Copy boot_cpu_data only on the first bringup */ |
403 | if (!c->initialized) | |
404 | *c = boot_cpu_data; | |
1d89a7f0 | 405 | c->cpu_index = id; |
30106c17 FY |
406 | /* |
407 | * During boot time, CPU0 has this setup already. Save the info when | |
408 | * bringing up AP or offlined CPU0. | |
409 | */ | |
410 | identify_secondary_cpu(c); | |
30bb9811 | 411 | c->initialized = true; |
1d89a7f0 GOC |
412 | } |
413 | ||
cebf15eb DH |
414 | static bool |
415 | topology_same_node(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) | |
416 | { | |
417 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
418 | ||
419 | return (cpu_to_node(cpu1) == cpu_to_node(cpu2)); | |
420 | } | |
421 | ||
148f9bb8 | 422 | static bool |
316ad248 | 423 | topology_sane(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o, const char *name) |
d4fbe4f0 | 424 | { |
316ad248 PZ |
425 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
426 | ||
cebf15eb | 427 | return !WARN_ONCE(!topology_same_node(c, o), |
316ad248 PZ |
428 | "sched: CPU #%d's %s-sibling CPU #%d is not on the same node! " |
429 | "[node: %d != %d]. Ignoring dependency.\n", | |
430 | cpu1, name, cpu2, cpu_to_node(cpu1), cpu_to_node(cpu2)); | |
431 | } | |
432 | ||
7d79a7bd | 433 | #define link_mask(mfunc, c1, c2) \ |
316ad248 | 434 | do { \ |
7d79a7bd BG |
435 | cpumask_set_cpu((c1), mfunc(c2)); \ |
436 | cpumask_set_cpu((c2), mfunc(c1)); \ | |
316ad248 PZ |
437 | } while (0) |
438 | ||
148f9bb8 | 439 | static bool match_smt(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 440 | { |
362f924b | 441 | if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { |
316ad248 PZ |
442 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; |
443 | ||
444 | if (c->phys_proc_id == o->phys_proc_id && | |
7745f03e | 445 | c->cpu_die_id == o->cpu_die_id && |
79a8b9aa BP |
446 | per_cpu(cpu_llc_id, cpu1) == per_cpu(cpu_llc_id, cpu2)) { |
447 | if (c->cpu_core_id == o->cpu_core_id) | |
448 | return topology_sane(c, o, "smt"); | |
449 | ||
450 | if ((c->cu_id != 0xff) && | |
451 | (o->cu_id != 0xff) && | |
452 | (c->cu_id == o->cu_id)) | |
453 | return topology_sane(c, o, "smt"); | |
454 | } | |
316ad248 PZ |
455 | |
456 | } else if (c->phys_proc_id == o->phys_proc_id && | |
7745f03e | 457 | c->cpu_die_id == o->cpu_die_id && |
316ad248 PZ |
458 | c->cpu_core_id == o->cpu_core_id) { |
459 | return topology_sane(c, o, "smt"); | |
460 | } | |
461 | ||
462 | return false; | |
463 | } | |
464 | ||
1340ccfa AS |
465 | /* |
466 | * Define snc_cpu[] for SNC (Sub-NUMA Cluster) CPUs. | |
467 | * | |
468 | * These are Intel CPUs that enumerate an LLC that is shared by | |
469 | * multiple NUMA nodes. The LLC on these systems is shared for | |
470 | * off-package data access but private to the NUMA node (half | |
471 | * of the package) for on-package access. | |
472 | * | |
473 | * CPUID (the source of the information about the LLC) can only | |
474 | * enumerate the cache as being shared *or* unshared, but not | |
475 | * this particular configuration. The CPU in this case enumerates | |
476 | * the cache to be shared across the entire package (spanning both | |
477 | * NUMA nodes). | |
478 | */ | |
479 | ||
480 | static const struct x86_cpu_id snc_cpu[] = { | |
adefe55e | 481 | X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, NULL), |
1340ccfa AS |
482 | {} |
483 | }; | |
484 | ||
148f9bb8 | 485 | static bool match_llc(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 PZ |
486 | { |
487 | int cpu1 = c->cpu_index, cpu2 = o->cpu_index; | |
488 | ||
1340ccfa AS |
489 | /* Do not match if we do not have a valid APICID for cpu: */ |
490 | if (per_cpu(cpu_llc_id, cpu1) == BAD_APICID) | |
491 | return false; | |
316ad248 | 492 | |
1340ccfa AS |
493 | /* Do not match if LLC id does not match: */ |
494 | if (per_cpu(cpu_llc_id, cpu1) != per_cpu(cpu_llc_id, cpu2)) | |
495 | return false; | |
496 | ||
497 | /* | |
498 | * Allow the SNC topology without warning. Return of false | |
499 | * means 'c' does not share the LLC of 'o'. This will be | |
500 | * reflected to userspace. | |
501 | */ | |
502 | if (!topology_same_node(c, o) && x86_match_cpu(snc_cpu)) | |
503 | return false; | |
504 | ||
505 | return topology_sane(c, o, "llc"); | |
d4fbe4f0 AH |
506 | } |
507 | ||
cebf15eb DH |
508 | /* |
509 | * Unlike the other levels, we do not enforce keeping a | |
510 | * multicore group inside a NUMA node. If this happens, we will | |
511 | * discard the MC level of the topology later. | |
512 | */ | |
169d0869 | 513 | static bool match_pkg(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
316ad248 | 514 | { |
cebf15eb DH |
515 | if (c->phys_proc_id == o->phys_proc_id) |
516 | return true; | |
316ad248 PZ |
517 | return false; |
518 | } | |
1d89a7f0 | 519 | |
2e4c54da LB |
520 | static bool match_die(struct cpuinfo_x86 *c, struct cpuinfo_x86 *o) |
521 | { | |
522 | if ((c->phys_proc_id == o->phys_proc_id) && | |
523 | (c->cpu_die_id == o->cpu_die_id)) | |
524 | return true; | |
525 | return false; | |
526 | } | |
527 | ||
528 | ||
d3d37d85 TC |
529 | #if defined(CONFIG_SCHED_SMT) || defined(CONFIG_SCHED_MC) |
530 | static inline int x86_sched_itmt_flags(void) | |
531 | { | |
532 | return sysctl_sched_itmt_enabled ? SD_ASYM_PACKING : 0; | |
533 | } | |
534 | ||
535 | #ifdef CONFIG_SCHED_MC | |
536 | static int x86_core_flags(void) | |
537 | { | |
538 | return cpu_core_flags() | x86_sched_itmt_flags(); | |
539 | } | |
540 | #endif | |
541 | #ifdef CONFIG_SCHED_SMT | |
542 | static int x86_smt_flags(void) | |
543 | { | |
544 | return cpu_smt_flags() | x86_sched_itmt_flags(); | |
545 | } | |
546 | #endif | |
547 | #endif | |
548 | ||
8f37961c | 549 | static struct sched_domain_topology_level x86_numa_in_package_topology[] = { |
cebf15eb | 550 | #ifdef CONFIG_SCHED_SMT |
d3d37d85 | 551 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
cebf15eb DH |
552 | #endif |
553 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 554 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
cebf15eb DH |
555 | #endif |
556 | { NULL, }, | |
557 | }; | |
8f37961c TC |
558 | |
559 | static struct sched_domain_topology_level x86_topology[] = { | |
560 | #ifdef CONFIG_SCHED_SMT | |
d3d37d85 | 561 | { cpu_smt_mask, x86_smt_flags, SD_INIT_NAME(SMT) }, |
8f37961c TC |
562 | #endif |
563 | #ifdef CONFIG_SCHED_MC | |
d3d37d85 | 564 | { cpu_coregroup_mask, x86_core_flags, SD_INIT_NAME(MC) }, |
8f37961c TC |
565 | #endif |
566 | { cpu_cpu_mask, SD_INIT_NAME(DIE) }, | |
567 | { NULL, }, | |
568 | }; | |
569 | ||
cebf15eb | 570 | /* |
8f37961c | 571 | * Set if a package/die has multiple NUMA nodes inside. |
1340ccfa AS |
572 | * AMD Magny-Cours, Intel Cluster-on-Die, and Intel |
573 | * Sub-NUMA Clustering have this. | |
cebf15eb | 574 | */ |
8f37961c | 575 | static bool x86_has_numa_in_package; |
cebf15eb | 576 | |
148f9bb8 | 577 | void set_cpu_sibling_map(int cpu) |
768d9505 | 578 | { |
316ad248 | 579 | bool has_smt = smp_num_siblings > 1; |
b0bc225d | 580 | bool has_mp = has_smt || boot_cpu_data.x86_max_cores > 1; |
768d9505 | 581 | struct cpuinfo_x86 *c = &cpu_data(cpu); |
316ad248 | 582 | struct cpuinfo_x86 *o; |
70b8301f | 583 | int i, threads; |
768d9505 | 584 | |
c2d1cec1 | 585 | cpumask_set_cpu(cpu, cpu_sibling_setup_mask); |
768d9505 | 586 | |
b0bc225d | 587 | if (!has_mp) { |
7d79a7bd | 588 | cpumask_set_cpu(cpu, topology_sibling_cpumask(cpu)); |
316ad248 | 589 | cpumask_set_cpu(cpu, cpu_llc_shared_mask(cpu)); |
7d79a7bd | 590 | cpumask_set_cpu(cpu, topology_core_cpumask(cpu)); |
2e4c54da | 591 | cpumask_set_cpu(cpu, topology_die_cpumask(cpu)); |
768d9505 GC |
592 | c->booted_cores = 1; |
593 | return; | |
594 | } | |
595 | ||
c2d1cec1 | 596 | for_each_cpu(i, cpu_sibling_setup_mask) { |
316ad248 PZ |
597 | o = &cpu_data(i); |
598 | ||
599 | if ((i == cpu) || (has_smt && match_smt(c, o))) | |
7d79a7bd | 600 | link_mask(topology_sibling_cpumask, cpu, i); |
316ad248 | 601 | |
b0bc225d | 602 | if ((i == cpu) || (has_mp && match_llc(c, o))) |
7d79a7bd | 603 | link_mask(cpu_llc_shared_mask, cpu, i); |
316ad248 | 604 | |
ceb1cbac KB |
605 | } |
606 | ||
607 | /* | |
608 | * This needs a separate iteration over the cpus because we rely on all | |
7d79a7bd | 609 | * topology_sibling_cpumask links to be set-up. |
ceb1cbac KB |
610 | */ |
611 | for_each_cpu(i, cpu_sibling_setup_mask) { | |
612 | o = &cpu_data(i); | |
613 | ||
169d0869 | 614 | if ((i == cpu) || (has_mp && match_pkg(c, o))) { |
7d79a7bd | 615 | link_mask(topology_core_cpumask, cpu, i); |
316ad248 | 616 | |
768d9505 GC |
617 | /* |
618 | * Does this new cpu bringup a new core? | |
619 | */ | |
7d79a7bd BG |
620 | if (cpumask_weight( |
621 | topology_sibling_cpumask(cpu)) == 1) { | |
768d9505 GC |
622 | /* |
623 | * for each core in package, increment | |
624 | * the booted_cores for this new cpu | |
625 | */ | |
7d79a7bd BG |
626 | if (cpumask_first( |
627 | topology_sibling_cpumask(i)) == i) | |
768d9505 GC |
628 | c->booted_cores++; |
629 | /* | |
630 | * increment the core count for all | |
631 | * the other cpus in this package | |
632 | */ | |
633 | if (i != cpu) | |
634 | cpu_data(i).booted_cores++; | |
635 | } else if (i != cpu && !c->booted_cores) | |
636 | c->booted_cores = cpu_data(i).booted_cores; | |
637 | } | |
169d0869 | 638 | if (match_pkg(c, o) && !topology_same_node(c, o)) |
8f37961c | 639 | x86_has_numa_in_package = true; |
2e4c54da LB |
640 | |
641 | if ((i == cpu) || (has_mp && match_die(c, o))) | |
642 | link_mask(topology_die_cpumask, cpu, i); | |
768d9505 | 643 | } |
70b8301f AK |
644 | |
645 | threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
646 | if (threads > __max_smt_threads) | |
647 | __max_smt_threads = threads; | |
768d9505 GC |
648 | } |
649 | ||
70708a18 | 650 | /* maps the cpu to the sched domain representing multi-core */ |
030bb203 | 651 | const struct cpumask *cpu_coregroup_mask(int cpu) |
70708a18 | 652 | { |
9f646389 | 653 | return cpu_llc_shared_mask(cpu); |
030bb203 RR |
654 | } |
655 | ||
a4928cff | 656 | static void impress_friends(void) |
904541e2 GOC |
657 | { |
658 | int cpu; | |
659 | unsigned long bogosum = 0; | |
660 | /* | |
661 | * Allow the user to impress friends. | |
662 | */ | |
c767a54b | 663 | pr_debug("Before bogomips\n"); |
904541e2 | 664 | for_each_possible_cpu(cpu) |
c2d1cec1 | 665 | if (cpumask_test_cpu(cpu, cpu_callout_mask)) |
904541e2 | 666 | bogosum += cpu_data(cpu).loops_per_jiffy; |
c767a54b | 667 | pr_info("Total of %d processors activated (%lu.%02lu BogoMIPS)\n", |
f68e00a3 | 668 | num_online_cpus(), |
904541e2 GOC |
669 | bogosum/(500000/HZ), |
670 | (bogosum/(5000/HZ))%100); | |
671 | ||
c767a54b | 672 | pr_debug("Before bogocount - setting activated=1\n"); |
904541e2 GOC |
673 | } |
674 | ||
569712b2 | 675 | void __inquire_remote_apic(int apicid) |
cb3c8b90 GOC |
676 | { |
677 | unsigned i, regs[] = { APIC_ID >> 4, APIC_LVR >> 4, APIC_SPIV >> 4 }; | |
a6c23905 | 678 | const char * const names[] = { "ID", "VERSION", "SPIV" }; |
cb3c8b90 GOC |
679 | int timeout; |
680 | u32 status; | |
681 | ||
c767a54b | 682 | pr_info("Inquiring remote APIC 0x%x...\n", apicid); |
cb3c8b90 GOC |
683 | |
684 | for (i = 0; i < ARRAY_SIZE(regs); i++) { | |
c767a54b | 685 | pr_info("... APIC 0x%x %s: ", apicid, names[i]); |
cb3c8b90 GOC |
686 | |
687 | /* | |
688 | * Wait for idle. | |
689 | */ | |
690 | status = safe_apic_wait_icr_idle(); | |
691 | if (status) | |
c767a54b | 692 | pr_cont("a previous APIC delivery may have failed\n"); |
cb3c8b90 | 693 | |
1b374e4d | 694 | apic_icr_write(APIC_DM_REMRD | regs[i], apicid); |
cb3c8b90 GOC |
695 | |
696 | timeout = 0; | |
697 | do { | |
698 | udelay(100); | |
699 | status = apic_read(APIC_ICR) & APIC_ICR_RR_MASK; | |
700 | } while (status == APIC_ICR_RR_INPROG && timeout++ < 1000); | |
701 | ||
702 | switch (status) { | |
703 | case APIC_ICR_RR_VALID: | |
704 | status = apic_read(APIC_RRR); | |
c767a54b | 705 | pr_cont("%08x\n", status); |
cb3c8b90 GOC |
706 | break; |
707 | default: | |
c767a54b | 708 | pr_cont("failed\n"); |
cb3c8b90 GOC |
709 | } |
710 | } | |
711 | } | |
712 | ||
d68921f9 LB |
713 | /* |
714 | * The Multiprocessor Specification 1.4 (1997) example code suggests | |
715 | * that there should be a 10ms delay between the BSP asserting INIT | |
716 | * and de-asserting INIT, when starting a remote processor. | |
717 | * But that slows boot and resume on modern processors, which include | |
718 | * many cores and don't require that delay. | |
719 | * | |
720 | * Cmdline "init_cpu_udelay=" is available to over-ride this delay. | |
1a744cb3 | 721 | * Modern processor families are quirked to remove the delay entirely. |
d68921f9 LB |
722 | */ |
723 | #define UDELAY_10MS_DEFAULT 10000 | |
724 | ||
656279a1 | 725 | static unsigned int init_udelay = UINT_MAX; |
d68921f9 LB |
726 | |
727 | static int __init cpu_init_udelay(char *str) | |
728 | { | |
729 | get_option(&str, &init_udelay); | |
730 | ||
731 | return 0; | |
732 | } | |
733 | early_param("cpu_init_udelay", cpu_init_udelay); | |
734 | ||
1a744cb3 LB |
735 | static void __init smp_quirk_init_udelay(void) |
736 | { | |
737 | /* if cmdline changed it from default, leave it alone */ | |
656279a1 | 738 | if (init_udelay != UINT_MAX) |
1a744cb3 LB |
739 | return; |
740 | ||
741 | /* if modern processor, use no delay */ | |
742 | if (((boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) && (boot_cpu_data.x86 == 6)) || | |
0b13bec7 | 743 | ((boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) && (boot_cpu_data.x86 >= 0x18)) || |
656279a1 | 744 | ((boot_cpu_data.x86_vendor == X86_VENDOR_AMD) && (boot_cpu_data.x86 >= 0xF))) { |
1a744cb3 | 745 | init_udelay = 0; |
656279a1 LB |
746 | return; |
747 | } | |
f1ccd249 LB |
748 | /* else, use legacy delay */ |
749 | init_udelay = UDELAY_10MS_DEFAULT; | |
1a744cb3 LB |
750 | } |
751 | ||
cb3c8b90 GOC |
752 | /* |
753 | * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal | |
754 | * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this | |
755 | * won't ... remember to clear down the APIC, etc later. | |
756 | */ | |
148f9bb8 | 757 | int |
e1c467e6 | 758 | wakeup_secondary_cpu_via_nmi(int apicid, unsigned long start_eip) |
cb3c8b90 GOC |
759 | { |
760 | unsigned long send_status, accept_status = 0; | |
761 | int maxlvt; | |
762 | ||
763 | /* Target chip */ | |
cb3c8b90 GOC |
764 | /* Boot on the stack */ |
765 | /* Kick the second */ | |
e1c467e6 | 766 | apic_icr_write(APIC_DM_NMI | apic->dest_logical, apicid); |
cb3c8b90 | 767 | |
cfc1b9a6 | 768 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
769 | send_status = safe_apic_wait_icr_idle(); |
770 | ||
771 | /* | |
772 | * Give the other CPU some time to accept the IPI. | |
773 | */ | |
774 | udelay(200); | |
cff9ab2b | 775 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
59ef48a5 CG |
776 | maxlvt = lapic_get_maxlvt(); |
777 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ | |
778 | apic_write(APIC_ESR, 0); | |
779 | accept_status = (apic_read(APIC_ESR) & 0xEF); | |
780 | } | |
c767a54b | 781 | pr_debug("NMI sent\n"); |
cb3c8b90 GOC |
782 | |
783 | if (send_status) | |
c767a54b | 784 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 785 | if (accept_status) |
c767a54b | 786 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
787 | |
788 | return (send_status | accept_status); | |
789 | } | |
cb3c8b90 | 790 | |
148f9bb8 | 791 | static int |
569712b2 | 792 | wakeup_secondary_cpu_via_init(int phys_apicid, unsigned long start_eip) |
cb3c8b90 | 793 | { |
f5d6a52f | 794 | unsigned long send_status = 0, accept_status = 0; |
cb3c8b90 GOC |
795 | int maxlvt, num_starts, j; |
796 | ||
593f4a78 MR |
797 | maxlvt = lapic_get_maxlvt(); |
798 | ||
cb3c8b90 GOC |
799 | /* |
800 | * Be paranoid about clearing APIC errors. | |
801 | */ | |
cff9ab2b | 802 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
593f4a78 MR |
803 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
804 | apic_write(APIC_ESR, 0); | |
cb3c8b90 GOC |
805 | apic_read(APIC_ESR); |
806 | } | |
807 | ||
c767a54b | 808 | pr_debug("Asserting INIT\n"); |
cb3c8b90 GOC |
809 | |
810 | /* | |
811 | * Turn INIT on target chip | |
812 | */ | |
cb3c8b90 GOC |
813 | /* |
814 | * Send IPI | |
815 | */ | |
1b374e4d SS |
816 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_INT_ASSERT | APIC_DM_INIT, |
817 | phys_apicid); | |
cb3c8b90 | 818 | |
cfc1b9a6 | 819 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
820 | send_status = safe_apic_wait_icr_idle(); |
821 | ||
7cb68598 | 822 | udelay(init_udelay); |
cb3c8b90 | 823 | |
c767a54b | 824 | pr_debug("Deasserting INIT\n"); |
cb3c8b90 GOC |
825 | |
826 | /* Target chip */ | |
cb3c8b90 | 827 | /* Send IPI */ |
1b374e4d | 828 | apic_icr_write(APIC_INT_LEVELTRIG | APIC_DM_INIT, phys_apicid); |
cb3c8b90 | 829 | |
cfc1b9a6 | 830 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
831 | send_status = safe_apic_wait_icr_idle(); |
832 | ||
833 | mb(); | |
cb3c8b90 GOC |
834 | |
835 | /* | |
836 | * Should we send STARTUP IPIs ? | |
837 | * | |
838 | * Determine this based on the APIC version. | |
839 | * If we don't have an integrated APIC, don't send the STARTUP IPIs. | |
840 | */ | |
cff9ab2b | 841 | if (APIC_INTEGRATED(boot_cpu_apic_version)) |
cb3c8b90 GOC |
842 | num_starts = 2; |
843 | else | |
844 | num_starts = 0; | |
845 | ||
cb3c8b90 GOC |
846 | /* |
847 | * Run STARTUP IPI loop. | |
848 | */ | |
c767a54b | 849 | pr_debug("#startup loops: %d\n", num_starts); |
cb3c8b90 | 850 | |
cb3c8b90 | 851 | for (j = 1; j <= num_starts; j++) { |
c767a54b | 852 | pr_debug("Sending STARTUP #%d\n", j); |
593f4a78 MR |
853 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
854 | apic_write(APIC_ESR, 0); | |
cb3c8b90 | 855 | apic_read(APIC_ESR); |
c767a54b | 856 | pr_debug("After apic_write\n"); |
cb3c8b90 GOC |
857 | |
858 | /* | |
859 | * STARTUP IPI | |
860 | */ | |
861 | ||
862 | /* Target chip */ | |
cb3c8b90 GOC |
863 | /* Boot on the stack */ |
864 | /* Kick the second */ | |
1b374e4d SS |
865 | apic_icr_write(APIC_DM_STARTUP | (start_eip >> 12), |
866 | phys_apicid); | |
cb3c8b90 GOC |
867 | |
868 | /* | |
869 | * Give the other CPU some time to accept the IPI. | |
870 | */ | |
fcafddec LB |
871 | if (init_udelay == 0) |
872 | udelay(10); | |
873 | else | |
a9bcaa02 | 874 | udelay(300); |
cb3c8b90 | 875 | |
c767a54b | 876 | pr_debug("Startup point 1\n"); |
cb3c8b90 | 877 | |
cfc1b9a6 | 878 | pr_debug("Waiting for send to finish...\n"); |
cb3c8b90 GOC |
879 | send_status = safe_apic_wait_icr_idle(); |
880 | ||
881 | /* | |
882 | * Give the other CPU some time to accept the IPI. | |
883 | */ | |
fcafddec LB |
884 | if (init_udelay == 0) |
885 | udelay(10); | |
886 | else | |
a9bcaa02 | 887 | udelay(200); |
cb3c8b90 | 888 | |
593f4a78 | 889 | if (maxlvt > 3) /* Due to the Pentium erratum 3AP. */ |
cb3c8b90 | 890 | apic_write(APIC_ESR, 0); |
cb3c8b90 GOC |
891 | accept_status = (apic_read(APIC_ESR) & 0xEF); |
892 | if (send_status || accept_status) | |
893 | break; | |
894 | } | |
c767a54b | 895 | pr_debug("After Startup\n"); |
cb3c8b90 GOC |
896 | |
897 | if (send_status) | |
c767a54b | 898 | pr_err("APIC never delivered???\n"); |
cb3c8b90 | 899 | if (accept_status) |
c767a54b | 900 | pr_err("APIC delivery error (%lx)\n", accept_status); |
cb3c8b90 GOC |
901 | |
902 | return (send_status | accept_status); | |
903 | } | |
cb3c8b90 | 904 | |
2eaad1fd | 905 | /* reduce the number of lines printed when booting a large cpu count system */ |
148f9bb8 | 906 | static void announce_cpu(int cpu, int apicid) |
2eaad1fd | 907 | { |
98fa15f3 | 908 | static int current_node = NUMA_NO_NODE; |
4adc8b71 | 909 | int node = early_cpu_to_node(cpu); |
a17bce4d | 910 | static int width, node_width; |
646e29a1 BP |
911 | |
912 | if (!width) | |
913 | width = num_digits(num_possible_cpus()) + 1; /* + '#' sign */ | |
2eaad1fd | 914 | |
a17bce4d BP |
915 | if (!node_width) |
916 | node_width = num_digits(num_possible_nodes()) + 1; /* + '#' */ | |
917 | ||
918 | if (cpu == 1) | |
919 | printk(KERN_INFO "x86: Booting SMP configuration:\n"); | |
920 | ||
719b3680 | 921 | if (system_state < SYSTEM_RUNNING) { |
2eaad1fd MT |
922 | if (node != current_node) { |
923 | if (current_node > (-1)) | |
a17bce4d | 924 | pr_cont("\n"); |
2eaad1fd | 925 | current_node = node; |
a17bce4d BP |
926 | |
927 | printk(KERN_INFO ".... node %*s#%d, CPUs: ", | |
928 | node_width - num_digits(node), " ", node); | |
2eaad1fd | 929 | } |
646e29a1 BP |
930 | |
931 | /* Add padding for the BSP */ | |
932 | if (cpu == 1) | |
933 | pr_cont("%*s", width + 1, " "); | |
934 | ||
935 | pr_cont("%*s#%d", width - num_digits(cpu), " ", cpu); | |
936 | ||
2eaad1fd MT |
937 | } else |
938 | pr_info("Booting Node %d Processor %d APIC 0x%x\n", | |
939 | node, cpu, apicid); | |
940 | } | |
941 | ||
e1c467e6 FY |
942 | static int wakeup_cpu0_nmi(unsigned int cmd, struct pt_regs *regs) |
943 | { | |
944 | int cpu; | |
945 | ||
946 | cpu = smp_processor_id(); | |
947 | if (cpu == 0 && !cpu_online(cpu) && enable_start_cpu0) | |
948 | return NMI_HANDLED; | |
949 | ||
950 | return NMI_DONE; | |
951 | } | |
952 | ||
953 | /* | |
954 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
955 | * | |
956 | * Instead of waiting for STARTUP after INITs, BSP will execute the BIOS | |
957 | * boot-strap code which is not a desired behavior for waking up BSP. To | |
958 | * void the boot-strap code, wake up CPU0 by NMI instead. | |
959 | * | |
960 | * This works to wake up soft offlined CPU0 only. If CPU0 is hard offlined | |
961 | * (i.e. physically hot removed and then hot added), NMI won't wake it up. | |
962 | * We'll change this code in the future to wake up hard offlined CPU0 if | |
963 | * real platform and request are available. | |
964 | */ | |
148f9bb8 | 965 | static int |
e1c467e6 FY |
966 | wakeup_cpu_via_init_nmi(int cpu, unsigned long start_ip, int apicid, |
967 | int *cpu0_nmi_registered) | |
968 | { | |
969 | int id; | |
970 | int boot_error; | |
971 | ||
ea7bdc65 JK |
972 | preempt_disable(); |
973 | ||
e1c467e6 FY |
974 | /* |
975 | * Wake up AP by INIT, INIT, STARTUP sequence. | |
976 | */ | |
ea7bdc65 JK |
977 | if (cpu) { |
978 | boot_error = wakeup_secondary_cpu_via_init(apicid, start_ip); | |
979 | goto out; | |
980 | } | |
e1c467e6 FY |
981 | |
982 | /* | |
983 | * Wake up BSP by nmi. | |
984 | * | |
985 | * Register a NMI handler to help wake up CPU0. | |
986 | */ | |
987 | boot_error = register_nmi_handler(NMI_LOCAL, | |
988 | wakeup_cpu0_nmi, 0, "wake_cpu0"); | |
989 | ||
990 | if (!boot_error) { | |
991 | enable_start_cpu0 = 1; | |
992 | *cpu0_nmi_registered = 1; | |
993 | if (apic->dest_logical == APIC_DEST_LOGICAL) | |
994 | id = cpu0_logical_apicid; | |
995 | else | |
996 | id = apicid; | |
997 | boot_error = wakeup_secondary_cpu_via_nmi(id, start_ip); | |
998 | } | |
ea7bdc65 JK |
999 | |
1000 | out: | |
1001 | preempt_enable(); | |
e1c467e6 FY |
1002 | |
1003 | return boot_error; | |
1004 | } | |
1005 | ||
66c7ceb4 | 1006 | int common_cpu_up(unsigned int cpu, struct task_struct *idle) |
3f85483b | 1007 | { |
66c7ceb4 TG |
1008 | int ret; |
1009 | ||
3f85483b BO |
1010 | /* Just in case we booted with a single CPU. */ |
1011 | alternatives_enable_smp(); | |
1012 | ||
1013 | per_cpu(current_task, cpu) = idle; | |
1014 | ||
66c7ceb4 TG |
1015 | /* Initialize the interrupt stack(s) */ |
1016 | ret = irq_init_percpu_irqstack(cpu); | |
1017 | if (ret) | |
1018 | return ret; | |
1019 | ||
3f85483b BO |
1020 | #ifdef CONFIG_X86_32 |
1021 | /* Stack for startup_32 can be just as for start_secondary onwards */ | |
cd493a6d | 1022 | per_cpu(cpu_current_top_of_stack, cpu) = task_top_of_stack(idle); |
3f85483b | 1023 | #else |
3f85483b BO |
1024 | initial_gs = per_cpu_offset(cpu); |
1025 | #endif | |
66c7ceb4 | 1026 | return 0; |
3f85483b BO |
1027 | } |
1028 | ||
cb3c8b90 GOC |
1029 | /* |
1030 | * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad | |
1031 | * (ie clustered apic addressing mode), this is a LOGICAL apic ID. | |
1f5bcabf IM |
1032 | * Returns zero if CPU booted OK, else error code from |
1033 | * ->wakeup_secondary_cpu. | |
cb3c8b90 | 1034 | */ |
10e66760 VK |
1035 | static int do_boot_cpu(int apicid, int cpu, struct task_struct *idle, |
1036 | int *cpu0_nmi_registered) | |
cb3c8b90 | 1037 | { |
48927bbb | 1038 | /* start_ip had better be page-aligned! */ |
f37240f1 | 1039 | unsigned long start_ip = real_mode_header->trampoline_start; |
48927bbb | 1040 | |
cb3c8b90 | 1041 | unsigned long boot_error = 0; |
ce4b1b16 | 1042 | unsigned long timeout; |
cb3c8b90 | 1043 | |
b9b1a9c3 | 1044 | idle->thread.sp = (unsigned long)task_pt_regs(idle); |
69218e47 | 1045 | early_gdt_descr.address = (unsigned long)get_cpu_gdt_rw(cpu); |
3e970473 | 1046 | initial_code = (unsigned long)start_secondary; |
b32f96c7 | 1047 | initial_stack = idle->thread.sp; |
cb3c8b90 | 1048 | |
613e396b | 1049 | /* Enable the espfix hack for this CPU */ |
20d5e4a9 | 1050 | init_espfix_ap(cpu); |
20d5e4a9 | 1051 | |
2eaad1fd MT |
1052 | /* So we see what's up */ |
1053 | announce_cpu(cpu, apicid); | |
cb3c8b90 GOC |
1054 | |
1055 | /* | |
1056 | * This grunge runs the startup process for | |
1057 | * the targeted processor. | |
1058 | */ | |
1059 | ||
e348caef | 1060 | if (x86_platform.legacy.warm_reset) { |
cb3c8b90 | 1061 | |
cfc1b9a6 | 1062 | pr_debug("Setting warm reset code and vector.\n"); |
cb3c8b90 | 1063 | |
34d05591 JS |
1064 | smpboot_setup_warm_reset_vector(start_ip); |
1065 | /* | |
1066 | * Be paranoid about clearing APIC errors. | |
db96b0a0 | 1067 | */ |
cff9ab2b | 1068 | if (APIC_INTEGRATED(boot_cpu_apic_version)) { |
db96b0a0 CG |
1069 | apic_write(APIC_ESR, 0); |
1070 | apic_read(APIC_ESR); | |
1071 | } | |
34d05591 | 1072 | } |
cb3c8b90 | 1073 | |
ce4b1b16 IM |
1074 | /* |
1075 | * AP might wait on cpu_callout_mask in cpu_init() with | |
1076 | * cpu_initialized_mask set if previous attempt to online | |
1077 | * it timed-out. Clear cpu_initialized_mask so that after | |
1078 | * INIT/SIPI it could start with a clean state. | |
1079 | */ | |
1080 | cpumask_clear_cpu(cpu, cpu_initialized_mask); | |
1081 | smp_mb(); | |
1082 | ||
cb3c8b90 | 1083 | /* |
e1c467e6 FY |
1084 | * Wake up a CPU in difference cases: |
1085 | * - Use the method in the APIC driver if it's defined | |
1086 | * Otherwise, | |
1087 | * - Use an INIT boot APIC message for APs or NMI for BSP. | |
cb3c8b90 | 1088 | */ |
1f5bcabf IM |
1089 | if (apic->wakeup_secondary_cpu) |
1090 | boot_error = apic->wakeup_secondary_cpu(apicid, start_ip); | |
1091 | else | |
e1c467e6 | 1092 | boot_error = wakeup_cpu_via_init_nmi(cpu, start_ip, apicid, |
10e66760 | 1093 | cpu0_nmi_registered); |
cb3c8b90 GOC |
1094 | |
1095 | if (!boot_error) { | |
1096 | /* | |
6e38f1e7 | 1097 | * Wait 10s total for first sign of life from AP |
cb3c8b90 | 1098 | */ |
ce4b1b16 IM |
1099 | boot_error = -1; |
1100 | timeout = jiffies + 10*HZ; | |
1101 | while (time_before(jiffies, timeout)) { | |
1102 | if (cpumask_test_cpu(cpu, cpu_initialized_mask)) { | |
1103 | /* | |
1104 | * Tell AP to proceed with initialization | |
1105 | */ | |
1106 | cpumask_set_cpu(cpu, cpu_callout_mask); | |
1107 | boot_error = 0; | |
1108 | break; | |
1109 | } | |
ce4b1b16 IM |
1110 | schedule(); |
1111 | } | |
1112 | } | |
cb3c8b90 | 1113 | |
ce4b1b16 | 1114 | if (!boot_error) { |
cb3c8b90 | 1115 | /* |
ce4b1b16 | 1116 | * Wait till AP completes initial initialization |
cb3c8b90 | 1117 | */ |
ce4b1b16 | 1118 | while (!cpumask_test_cpu(cpu, cpu_callin_mask)) { |
68f202e4 SS |
1119 | /* |
1120 | * Allow other tasks to run while we wait for the | |
1121 | * AP to come online. This also gives a chance | |
1122 | * for the MTRR work(triggered by the AP coming online) | |
1123 | * to be completed in the stop machine context. | |
1124 | */ | |
1125 | schedule(); | |
cb3c8b90 | 1126 | } |
cb3c8b90 GOC |
1127 | } |
1128 | ||
e348caef | 1129 | if (x86_platform.legacy.warm_reset) { |
02421f98 YL |
1130 | /* |
1131 | * Cleanup possible dangling ends... | |
1132 | */ | |
1133 | smpboot_restore_warm_reset_vector(); | |
1134 | } | |
e1c467e6 | 1135 | |
cb3c8b90 GOC |
1136 | return boot_error; |
1137 | } | |
1138 | ||
148f9bb8 | 1139 | int native_cpu_up(unsigned int cpu, struct task_struct *tidle) |
cb3c8b90 | 1140 | { |
a21769a4 | 1141 | int apicid = apic->cpu_present_to_apicid(cpu); |
10e66760 | 1142 | int cpu0_nmi_registered = 0; |
cb3c8b90 | 1143 | unsigned long flags; |
10e66760 | 1144 | int err, ret = 0; |
cb3c8b90 | 1145 | |
7a10e2a9 | 1146 | lockdep_assert_irqs_enabled(); |
cb3c8b90 | 1147 | |
cfc1b9a6 | 1148 | pr_debug("++++++++++++++++++++=_---CPU UP %u\n", cpu); |
cb3c8b90 | 1149 | |
30106c17 | 1150 | if (apicid == BAD_APICID || |
c284b42a | 1151 | !physid_isset(apicid, phys_cpu_present_map) || |
fa63030e | 1152 | !apic->apic_id_valid(apicid)) { |
c767a54b | 1153 | pr_err("%s: bad cpu %d\n", __func__, cpu); |
cb3c8b90 GOC |
1154 | return -EINVAL; |
1155 | } | |
1156 | ||
1157 | /* | |
1158 | * Already booted CPU? | |
1159 | */ | |
c2d1cec1 | 1160 | if (cpumask_test_cpu(cpu, cpu_callin_mask)) { |
cfc1b9a6 | 1161 | pr_debug("do_boot_cpu %d Already started\n", cpu); |
cb3c8b90 GOC |
1162 | return -ENOSYS; |
1163 | } | |
1164 | ||
1165 | /* | |
1166 | * Save current MTRR state in case it was changed since early boot | |
1167 | * (e.g. by the ACPI SMI) to initialize new CPUs with MTRRs in sync: | |
1168 | */ | |
1169 | mtrr_save_state(); | |
1170 | ||
2a442c9c PM |
1171 | /* x86 CPUs take themselves offline, so delayed offline is OK. */ |
1172 | err = cpu_check_up_prepare(cpu); | |
1173 | if (err && err != -EBUSY) | |
1174 | return err; | |
cb3c8b90 | 1175 | |
644c1541 | 1176 | /* the FPU context is blank, nobody can own it */ |
317b622c | 1177 | per_cpu(fpu_fpregs_owner_ctx, cpu) = NULL; |
644c1541 | 1178 | |
66c7ceb4 TG |
1179 | err = common_cpu_up(cpu, tidle); |
1180 | if (err) | |
1181 | return err; | |
3f85483b | 1182 | |
10e66760 | 1183 | err = do_boot_cpu(apicid, cpu, tidle, &cpu0_nmi_registered); |
61165d7a | 1184 | if (err) { |
feef1e8e | 1185 | pr_err("do_boot_cpu failed(%d) to wakeup CPU#%u\n", err, cpu); |
10e66760 VK |
1186 | ret = -EIO; |
1187 | goto unreg_nmi; | |
cb3c8b90 GOC |
1188 | } |
1189 | ||
1190 | /* | |
1191 | * Check TSC synchronization with the AP (keep irqs disabled | |
1192 | * while doing so): | |
1193 | */ | |
1194 | local_irq_save(flags); | |
1195 | check_tsc_sync_source(cpu); | |
1196 | local_irq_restore(flags); | |
1197 | ||
7c04e64a | 1198 | while (!cpu_online(cpu)) { |
cb3c8b90 GOC |
1199 | cpu_relax(); |
1200 | touch_nmi_watchdog(); | |
1201 | } | |
1202 | ||
10e66760 VK |
1203 | unreg_nmi: |
1204 | /* | |
1205 | * Clean up the nmi handler. Do this after the callin and callout sync | |
1206 | * to avoid impact of possible long unregister time. | |
1207 | */ | |
1208 | if (cpu0_nmi_registered) | |
1209 | unregister_nmi_handler(NMI_LOCAL, "wake_cpu0"); | |
1210 | ||
1211 | return ret; | |
cb3c8b90 GOC |
1212 | } |
1213 | ||
7167d08e HK |
1214 | /** |
1215 | * arch_disable_smp_support() - disables SMP support for x86 at runtime | |
1216 | */ | |
1217 | void arch_disable_smp_support(void) | |
1218 | { | |
1219 | disable_ioapic_support(); | |
1220 | } | |
1221 | ||
8aef135c GOC |
1222 | /* |
1223 | * Fall back to non SMP mode after errors. | |
1224 | * | |
1225 | * RED-PEN audit/test this more. I bet there is more state messed up here. | |
1226 | */ | |
1227 | static __init void disable_smp(void) | |
1228 | { | |
613c25ef TG |
1229 | pr_info("SMP disabled\n"); |
1230 | ||
ef4c59a4 TG |
1231 | disable_ioapic_support(); |
1232 | ||
4f062896 RR |
1233 | init_cpu_present(cpumask_of(0)); |
1234 | init_cpu_possible(cpumask_of(0)); | |
0f385d1d | 1235 | |
8aef135c | 1236 | if (smp_found_config) |
b6df1b8b | 1237 | physid_set_mask_of_physid(boot_cpu_physical_apicid, &phys_cpu_present_map); |
8aef135c | 1238 | else |
b6df1b8b | 1239 | physid_set_mask_of_physid(0, &phys_cpu_present_map); |
7d79a7bd BG |
1240 | cpumask_set_cpu(0, topology_sibling_cpumask(0)); |
1241 | cpumask_set_cpu(0, topology_core_cpumask(0)); | |
2e4c54da | 1242 | cpumask_set_cpu(0, topology_die_cpumask(0)); |
8aef135c GOC |
1243 | } |
1244 | ||
1245 | /* | |
1246 | * Various sanity checks. | |
1247 | */ | |
4f45ed9f | 1248 | static void __init smp_sanity_check(void) |
8aef135c | 1249 | { |
ac23d4ee | 1250 | preempt_disable(); |
a58f03b0 | 1251 | |
1ff2f20d | 1252 | #if !defined(CONFIG_X86_BIGSMP) && defined(CONFIG_X86_32) |
a58f03b0 YL |
1253 | if (def_to_bigsmp && nr_cpu_ids > 8) { |
1254 | unsigned int cpu; | |
1255 | unsigned nr; | |
1256 | ||
c767a54b JP |
1257 | pr_warn("More than 8 CPUs detected - skipping them\n" |
1258 | "Use CONFIG_X86_BIGSMP\n"); | |
a58f03b0 YL |
1259 | |
1260 | nr = 0; | |
1261 | for_each_present_cpu(cpu) { | |
1262 | if (nr >= 8) | |
c2d1cec1 | 1263 | set_cpu_present(cpu, false); |
a58f03b0 YL |
1264 | nr++; |
1265 | } | |
1266 | ||
1267 | nr = 0; | |
1268 | for_each_possible_cpu(cpu) { | |
1269 | if (nr >= 8) | |
c2d1cec1 | 1270 | set_cpu_possible(cpu, false); |
a58f03b0 YL |
1271 | nr++; |
1272 | } | |
1273 | ||
1274 | nr_cpu_ids = 8; | |
1275 | } | |
1276 | #endif | |
1277 | ||
8aef135c | 1278 | if (!physid_isset(hard_smp_processor_id(), phys_cpu_present_map)) { |
c767a54b | 1279 | pr_warn("weird, boot CPU (#%d) not listed by the BIOS\n", |
55c395b4 MT |
1280 | hard_smp_processor_id()); |
1281 | ||
8aef135c GOC |
1282 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1283 | } | |
1284 | ||
8aef135c GOC |
1285 | /* |
1286 | * Should not be necessary because the MP table should list the boot | |
1287 | * CPU too, but we do it for the sake of robustness anyway. | |
1288 | */ | |
a27a6210 | 1289 | if (!apic->check_phys_apicid_present(boot_cpu_physical_apicid)) { |
c767a54b JP |
1290 | pr_notice("weird, boot CPU (#%d) not listed by the BIOS\n", |
1291 | boot_cpu_physical_apicid); | |
8aef135c GOC |
1292 | physid_set(hard_smp_processor_id(), phys_cpu_present_map); |
1293 | } | |
ac23d4ee | 1294 | preempt_enable(); |
8aef135c GOC |
1295 | } |
1296 | ||
1297 | static void __init smp_cpu_index_default(void) | |
1298 | { | |
1299 | int i; | |
1300 | struct cpuinfo_x86 *c; | |
1301 | ||
7c04e64a | 1302 | for_each_possible_cpu(i) { |
8aef135c GOC |
1303 | c = &cpu_data(i); |
1304 | /* mark all to hotplug */ | |
9628937d | 1305 | c->cpu_index = nr_cpu_ids; |
8aef135c GOC |
1306 | } |
1307 | } | |
1308 | ||
4b1244b4 DL |
1309 | static void __init smp_get_logical_apicid(void) |
1310 | { | |
1311 | if (x2apic_mode) | |
1312 | cpu0_logical_apicid = apic_read(APIC_LDR); | |
1313 | else | |
1314 | cpu0_logical_apicid = GET_APIC_LOGICAL_ID(apic_read(APIC_LDR)); | |
1315 | } | |
1316 | ||
8aef135c | 1317 | /* |
935356ce DL |
1318 | * Prepare for SMP bootup. |
1319 | * @max_cpus: configured maximum number of CPUs, It is a legacy parameter | |
1320 | * for common interface support. | |
8aef135c GOC |
1321 | */ |
1322 | void __init native_smp_prepare_cpus(unsigned int max_cpus) | |
1323 | { | |
7ad728f9 RR |
1324 | unsigned int i; |
1325 | ||
8aef135c | 1326 | smp_cpu_index_default(); |
792363d2 | 1327 | |
8aef135c GOC |
1328 | /* |
1329 | * Setup boot CPU information | |
1330 | */ | |
30106c17 | 1331 | smp_store_boot_cpu_info(); /* Final full version of the data */ |
792363d2 YL |
1332 | cpumask_copy(cpu_callin_mask, cpumask_of(0)); |
1333 | mb(); | |
bd22a2f1 | 1334 | |
7ad728f9 | 1335 | for_each_possible_cpu(i) { |
79f55997 LZ |
1336 | zalloc_cpumask_var(&per_cpu(cpu_sibling_map, i), GFP_KERNEL); |
1337 | zalloc_cpumask_var(&per_cpu(cpu_core_map, i), GFP_KERNEL); | |
2e4c54da | 1338 | zalloc_cpumask_var(&per_cpu(cpu_die_map, i), GFP_KERNEL); |
b3d7336d | 1339 | zalloc_cpumask_var(&per_cpu(cpu_llc_shared_map, i), GFP_KERNEL); |
7ad728f9 | 1340 | } |
8f37961c TC |
1341 | |
1342 | /* | |
1343 | * Set 'default' x86 topology, this matches default_topology() in that | |
1344 | * it has NUMA nodes as a topology level. See also | |
1345 | * native_smp_cpus_done(). | |
1346 | * | |
1347 | * Must be done before set_cpus_sibling_map() is ran. | |
1348 | */ | |
1349 | set_sched_topology(x86_topology); | |
1350 | ||
8aef135c | 1351 | set_cpu_sibling_map(0); |
b56e7d45 | 1352 | init_freq_invariance(false); |
4f45ed9f DL |
1353 | smp_sanity_check(); |
1354 | ||
1355 | switch (apic_intr_mode) { | |
1356 | case APIC_PIC: | |
1357 | case APIC_VIRTUAL_WIRE_NO_CONFIG: | |
613c25ef TG |
1358 | disable_smp(); |
1359 | return; | |
4f45ed9f | 1360 | case APIC_SYMMETRIC_IO_NO_ROUTING: |
613c25ef | 1361 | disable_smp(); |
a2510d15 DL |
1362 | /* Setup local timer */ |
1363 | x86_init.timers.setup_percpu_clockev(); | |
250a1ac6 | 1364 | return; |
4f45ed9f DL |
1365 | case APIC_VIRTUAL_WIRE: |
1366 | case APIC_SYMMETRIC_IO: | |
613c25ef | 1367 | break; |
8aef135c GOC |
1368 | } |
1369 | ||
a2510d15 DL |
1370 | /* Setup local timer */ |
1371 | x86_init.timers.setup_percpu_clockev(); | |
8aef135c | 1372 | |
4b1244b4 | 1373 | smp_get_logical_apicid(); |
ef4c59a4 | 1374 | |
d54ff31d | 1375 | pr_info("CPU0: "); |
8aef135c | 1376 | print_cpu_info(&cpu_data(0)); |
c4bd1fda | 1377 | |
9ec808a0 | 1378 | uv_system_init(); |
d0af9eed SS |
1379 | |
1380 | set_mtrr_aps_delayed_init(); | |
1a744cb3 LB |
1381 | |
1382 | smp_quirk_init_udelay(); | |
1f50ddb4 TG |
1383 | |
1384 | speculative_store_bypass_ht_init(); | |
8aef135c | 1385 | } |
d0af9eed SS |
1386 | |
1387 | void arch_enable_nonboot_cpus_begin(void) | |
1388 | { | |
1389 | set_mtrr_aps_delayed_init(); | |
1390 | } | |
1391 | ||
1392 | void arch_enable_nonboot_cpus_end(void) | |
1393 | { | |
1394 | mtrr_aps_init(); | |
1395 | } | |
1396 | ||
a8db8453 GOC |
1397 | /* |
1398 | * Early setup to make printk work. | |
1399 | */ | |
1400 | void __init native_smp_prepare_boot_cpu(void) | |
1401 | { | |
1402 | int me = smp_processor_id(); | |
552be871 | 1403 | switch_to_new_gdt(me); |
c2d1cec1 MT |
1404 | /* already set me in cpu_online_mask in boot_cpu_init() */ |
1405 | cpumask_set_cpu(me, cpu_callout_mask); | |
2a442c9c | 1406 | cpu_set_state_online(me); |
090d54bc | 1407 | native_pv_lock_init(); |
a8db8453 GOC |
1408 | } |
1409 | ||
63e708f8 | 1410 | void __init calculate_max_logical_packages(void) |
83f7eb9c | 1411 | { |
b4c0a732 PB |
1412 | int ncpus; |
1413 | ||
b4c0a732 PB |
1414 | /* |
1415 | * Today neither Intel nor AMD support heterogenous systems so | |
1416 | * extrapolate the boot cpu's data to all packages. | |
1417 | */ | |
947134d9 | 1418 | ncpus = cpu_data(0).booted_cores * topology_max_smt_threads(); |
aa02ef09 | 1419 | __max_logical_packages = DIV_ROUND_UP(total_cpus, ncpus); |
b4c0a732 | 1420 | pr_info("Max logical packages: %u\n", __max_logical_packages); |
63e708f8 PB |
1421 | } |
1422 | ||
1423 | void __init native_smp_cpus_done(unsigned int max_cpus) | |
1424 | { | |
1425 | pr_debug("Boot done\n"); | |
1426 | ||
1427 | calculate_max_logical_packages(); | |
83f7eb9c | 1428 | |
8f37961c TC |
1429 | if (x86_has_numa_in_package) |
1430 | set_sched_topology(x86_numa_in_package_topology); | |
1431 | ||
99e8b9ca | 1432 | nmi_selftest(); |
83f7eb9c | 1433 | impress_friends(); |
d0af9eed | 1434 | mtrr_aps_init(); |
83f7eb9c GOC |
1435 | } |
1436 | ||
3b11ce7f MT |
1437 | static int __initdata setup_possible_cpus = -1; |
1438 | static int __init _setup_possible_cpus(char *str) | |
1439 | { | |
1440 | get_option(&str, &setup_possible_cpus); | |
1441 | return 0; | |
1442 | } | |
1443 | early_param("possible_cpus", _setup_possible_cpus); | |
1444 | ||
1445 | ||
68a1c3f8 | 1446 | /* |
4f062896 | 1447 | * cpu_possible_mask should be static, it cannot change as cpu's |
68a1c3f8 | 1448 | * are onlined, or offlined. The reason is per-cpu data-structures |
4d1d0977 | 1449 | * are allocated by some modules at init time, and don't expect to |
68a1c3f8 | 1450 | * do this dynamically on cpu arrival/departure. |
4f062896 | 1451 | * cpu_present_mask on the other hand can change dynamically. |
68a1c3f8 GC |
1452 | * In case when cpu_hotplug is not compiled, then we resort to current |
1453 | * behaviour, which is cpu_possible == cpu_present. | |
1454 | * - Ashok Raj | |
1455 | * | |
1456 | * Three ways to find out the number of additional hotplug CPUs: | |
1457 | * - If the BIOS specified disabled CPUs in ACPI/mptables use that. | |
3b11ce7f | 1458 | * - The user can overwrite it with possible_cpus=NUM |
68a1c3f8 GC |
1459 | * - Otherwise don't reserve additional CPUs. |
1460 | * We do this because additional CPUs waste a lot of memory. | |
1461 | * -AK | |
1462 | */ | |
1463 | __init void prefill_possible_map(void) | |
1464 | { | |
cb48bb59 | 1465 | int i, possible; |
68a1c3f8 | 1466 | |
2a51fe08 PB |
1467 | /* No boot processor was found in mptable or ACPI MADT */ |
1468 | if (!num_processors) { | |
ff856051 VS |
1469 | if (boot_cpu_has(X86_FEATURE_APIC)) { |
1470 | int apicid = boot_cpu_physical_apicid; | |
1471 | int cpu = hard_smp_processor_id(); | |
2a51fe08 | 1472 | |
ff856051 | 1473 | pr_warn("Boot CPU (id %d) not listed by BIOS\n", cpu); |
2a51fe08 | 1474 | |
ff856051 VS |
1475 | /* Make sure boot cpu is enumerated */ |
1476 | if (apic->cpu_present_to_apicid(0) == BAD_APICID && | |
1477 | apic->apic_id_valid(apicid)) | |
1478 | generic_processor_info(apicid, boot_cpu_apic_version); | |
1479 | } | |
2a51fe08 PB |
1480 | |
1481 | if (!num_processors) | |
1482 | num_processors = 1; | |
1483 | } | |
329513a3 | 1484 | |
5f2eb550 JB |
1485 | i = setup_max_cpus ?: 1; |
1486 | if (setup_possible_cpus == -1) { | |
1487 | possible = num_processors; | |
1488 | #ifdef CONFIG_HOTPLUG_CPU | |
1489 | if (setup_max_cpus) | |
1490 | possible += disabled_cpus; | |
1491 | #else | |
1492 | if (possible > i) | |
1493 | possible = i; | |
1494 | #endif | |
1495 | } else | |
3b11ce7f MT |
1496 | possible = setup_possible_cpus; |
1497 | ||
730cf272 MT |
1498 | total_cpus = max_t(int, possible, num_processors + disabled_cpus); |
1499 | ||
2b633e3f YL |
1500 | /* nr_cpu_ids could be reduced via nr_cpus= */ |
1501 | if (possible > nr_cpu_ids) { | |
9b130ad5 | 1502 | pr_warn("%d Processors exceeds NR_CPUS limit of %u\n", |
2b633e3f YL |
1503 | possible, nr_cpu_ids); |
1504 | possible = nr_cpu_ids; | |
3b11ce7f | 1505 | } |
68a1c3f8 | 1506 | |
5f2eb550 JB |
1507 | #ifdef CONFIG_HOTPLUG_CPU |
1508 | if (!setup_max_cpus) | |
1509 | #endif | |
1510 | if (possible > i) { | |
c767a54b | 1511 | pr_warn("%d Processors exceeds max_cpus limit of %u\n", |
5f2eb550 JB |
1512 | possible, setup_max_cpus); |
1513 | possible = i; | |
1514 | } | |
1515 | ||
427d77a3 TG |
1516 | nr_cpu_ids = possible; |
1517 | ||
c767a54b | 1518 | pr_info("Allowing %d CPUs, %d hotplug CPUs\n", |
68a1c3f8 GC |
1519 | possible, max_t(int, possible - num_processors, 0)); |
1520 | ||
427d77a3 TG |
1521 | reset_cpu_possible_mask(); |
1522 | ||
68a1c3f8 | 1523 | for (i = 0; i < possible; i++) |
c2d1cec1 | 1524 | set_cpu_possible(i, true); |
68a1c3f8 | 1525 | } |
69c18c15 | 1526 | |
14adf855 CE |
1527 | #ifdef CONFIG_HOTPLUG_CPU |
1528 | ||
70b8301f AK |
1529 | /* Recompute SMT state for all CPUs on offline */ |
1530 | static void recompute_smt_state(void) | |
1531 | { | |
1532 | int max_threads, cpu; | |
1533 | ||
1534 | max_threads = 0; | |
1535 | for_each_online_cpu (cpu) { | |
1536 | int threads = cpumask_weight(topology_sibling_cpumask(cpu)); | |
1537 | ||
1538 | if (threads > max_threads) | |
1539 | max_threads = threads; | |
1540 | } | |
1541 | __max_smt_threads = max_threads; | |
1542 | } | |
1543 | ||
14adf855 CE |
1544 | static void remove_siblinginfo(int cpu) |
1545 | { | |
1546 | int sibling; | |
1547 | struct cpuinfo_x86 *c = &cpu_data(cpu); | |
1548 | ||
7d79a7bd BG |
1549 | for_each_cpu(sibling, topology_core_cpumask(cpu)) { |
1550 | cpumask_clear_cpu(cpu, topology_core_cpumask(sibling)); | |
14adf855 CE |
1551 | /*/ |
1552 | * last thread sibling in this cpu core going down | |
1553 | */ | |
7d79a7bd | 1554 | if (cpumask_weight(topology_sibling_cpumask(cpu)) == 1) |
14adf855 CE |
1555 | cpu_data(sibling).booted_cores--; |
1556 | } | |
1557 | ||
2e4c54da LB |
1558 | for_each_cpu(sibling, topology_die_cpumask(cpu)) |
1559 | cpumask_clear_cpu(cpu, topology_die_cpumask(sibling)); | |
7d79a7bd BG |
1560 | for_each_cpu(sibling, topology_sibling_cpumask(cpu)) |
1561 | cpumask_clear_cpu(cpu, topology_sibling_cpumask(sibling)); | |
03bd4e1f WL |
1562 | for_each_cpu(sibling, cpu_llc_shared_mask(cpu)) |
1563 | cpumask_clear_cpu(cpu, cpu_llc_shared_mask(sibling)); | |
1564 | cpumask_clear(cpu_llc_shared_mask(cpu)); | |
7d79a7bd BG |
1565 | cpumask_clear(topology_sibling_cpumask(cpu)); |
1566 | cpumask_clear(topology_core_cpumask(cpu)); | |
2e4c54da | 1567 | cpumask_clear(topology_die_cpumask(cpu)); |
14adf855 | 1568 | c->cpu_core_id = 0; |
45967493 | 1569 | c->booted_cores = 0; |
c2d1cec1 | 1570 | cpumask_clear_cpu(cpu, cpu_sibling_setup_mask); |
70b8301f | 1571 | recompute_smt_state(); |
14adf855 CE |
1572 | } |
1573 | ||
4daa832d | 1574 | static void remove_cpu_from_maps(int cpu) |
69c18c15 | 1575 | { |
c2d1cec1 MT |
1576 | set_cpu_online(cpu, false); |
1577 | cpumask_clear_cpu(cpu, cpu_callout_mask); | |
1578 | cpumask_clear_cpu(cpu, cpu_callin_mask); | |
69c18c15 | 1579 | /* was set by cpu_init() */ |
c2d1cec1 | 1580 | cpumask_clear_cpu(cpu, cpu_initialized_mask); |
23ca4bba | 1581 | numa_remove_cpu(cpu); |
69c18c15 GC |
1582 | } |
1583 | ||
8227dce7 | 1584 | void cpu_disable_common(void) |
69c18c15 GC |
1585 | { |
1586 | int cpu = smp_processor_id(); | |
69c18c15 | 1587 | |
69c18c15 GC |
1588 | remove_siblinginfo(cpu); |
1589 | ||
1590 | /* It's now safe to remove this processor from the online map */ | |
d388e5fd | 1591 | lock_vector_lock(); |
69c18c15 | 1592 | remove_cpu_from_maps(cpu); |
d388e5fd | 1593 | unlock_vector_lock(); |
d7b381bb | 1594 | fixup_irqs(); |
0fa115da | 1595 | lapic_offline(); |
8227dce7 AN |
1596 | } |
1597 | ||
1598 | int native_cpu_disable(void) | |
1599 | { | |
da6139e4 PB |
1600 | int ret; |
1601 | ||
2cffad7b | 1602 | ret = lapic_can_unplug_cpu(); |
da6139e4 PB |
1603 | if (ret) |
1604 | return ret; | |
1605 | ||
60dcaad5 TG |
1606 | /* |
1607 | * Disable the local APIC. Otherwise IPI broadcasts will reach | |
1608 | * it. It still responds normally to INIT, NMI, SMI, and SIPI | |
1609 | * messages. | |
1610 | */ | |
1611 | apic_soft_disable(); | |
8227dce7 | 1612 | cpu_disable_common(); |
2ed53c0d | 1613 | |
69c18c15 GC |
1614 | return 0; |
1615 | } | |
1616 | ||
2a442c9c | 1617 | int common_cpu_die(unsigned int cpu) |
54279552 | 1618 | { |
2a442c9c | 1619 | int ret = 0; |
54279552 | 1620 | |
69c18c15 | 1621 | /* We don't do anything here: idle task is faking death itself. */ |
54279552 | 1622 | |
2ed53c0d | 1623 | /* They ack this in play_dead() by setting CPU_DEAD */ |
2a442c9c | 1624 | if (cpu_wait_death(cpu, 5)) { |
2ed53c0d LT |
1625 | if (system_state == SYSTEM_RUNNING) |
1626 | pr_info("CPU %u is now offline\n", cpu); | |
1627 | } else { | |
1628 | pr_err("CPU %u didn't die...\n", cpu); | |
2a442c9c | 1629 | ret = -1; |
69c18c15 | 1630 | } |
2a442c9c PM |
1631 | |
1632 | return ret; | |
1633 | } | |
1634 | ||
1635 | void native_cpu_die(unsigned int cpu) | |
1636 | { | |
1637 | common_cpu_die(cpu); | |
69c18c15 | 1638 | } |
a21f5d88 AN |
1639 | |
1640 | void play_dead_common(void) | |
1641 | { | |
1642 | idle_task_exit(); | |
a21f5d88 | 1643 | |
a21f5d88 | 1644 | /* Ack it */ |
2a442c9c | 1645 | (void)cpu_report_death(); |
a21f5d88 AN |
1646 | |
1647 | /* | |
1648 | * With physical CPU hotplug, we should halt the cpu | |
1649 | */ | |
1650 | local_irq_disable(); | |
1651 | } | |
1652 | ||
e1c467e6 FY |
1653 | static bool wakeup_cpu0(void) |
1654 | { | |
1655 | if (smp_processor_id() == 0 && enable_start_cpu0) | |
1656 | return true; | |
1657 | ||
1658 | return false; | |
1659 | } | |
1660 | ||
ea530692 PA |
1661 | /* |
1662 | * We need to flush the caches before going to sleep, lest we have | |
1663 | * dirty data in our caches when we come back up. | |
1664 | */ | |
1665 | static inline void mwait_play_dead(void) | |
1666 | { | |
1667 | unsigned int eax, ebx, ecx, edx; | |
1668 | unsigned int highest_cstate = 0; | |
1669 | unsigned int highest_subcstate = 0; | |
ce5f6824 | 1670 | void *mwait_ptr; |
576cfb40 | 1671 | int i; |
ea530692 | 1672 | |
0b13bec7 PW |
1673 | if (boot_cpu_data.x86_vendor == X86_VENDOR_AMD || |
1674 | boot_cpu_data.x86_vendor == X86_VENDOR_HYGON) | |
da6fa7ef | 1675 | return; |
69fb3676 | 1676 | if (!this_cpu_has(X86_FEATURE_MWAIT)) |
ea530692 | 1677 | return; |
840d2830 | 1678 | if (!this_cpu_has(X86_FEATURE_CLFLUSH)) |
ce5f6824 | 1679 | return; |
7b543a53 | 1680 | if (__this_cpu_read(cpu_info.cpuid_level) < CPUID_MWAIT_LEAF) |
ea530692 PA |
1681 | return; |
1682 | ||
1683 | eax = CPUID_MWAIT_LEAF; | |
1684 | ecx = 0; | |
1685 | native_cpuid(&eax, &ebx, &ecx, &edx); | |
1686 | ||
1687 | /* | |
1688 | * eax will be 0 if EDX enumeration is not valid. | |
1689 | * Initialized below to cstate, sub_cstate value when EDX is valid. | |
1690 | */ | |
1691 | if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED)) { | |
1692 | eax = 0; | |
1693 | } else { | |
1694 | edx >>= MWAIT_SUBSTATE_SIZE; | |
1695 | for (i = 0; i < 7 && edx; i++, edx >>= MWAIT_SUBSTATE_SIZE) { | |
1696 | if (edx & MWAIT_SUBSTATE_MASK) { | |
1697 | highest_cstate = i; | |
1698 | highest_subcstate = edx & MWAIT_SUBSTATE_MASK; | |
1699 | } | |
1700 | } | |
1701 | eax = (highest_cstate << MWAIT_SUBSTATE_SIZE) | | |
1702 | (highest_subcstate - 1); | |
1703 | } | |
1704 | ||
ce5f6824 PA |
1705 | /* |
1706 | * This should be a memory location in a cache line which is | |
1707 | * unlikely to be touched by other processors. The actual | |
1708 | * content is immaterial as it is not actually modified in any way. | |
1709 | */ | |
1710 | mwait_ptr = ¤t_thread_info()->flags; | |
1711 | ||
a68e5c94 PA |
1712 | wbinvd(); |
1713 | ||
ea530692 | 1714 | while (1) { |
ce5f6824 PA |
1715 | /* |
1716 | * The CLFLUSH is a workaround for erratum AAI65 for | |
1717 | * the Xeon 7400 series. It's not clear it is actually | |
1718 | * needed, but it should be harmless in either case. | |
1719 | * The WBINVD is insufficient due to the spurious-wakeup | |
1720 | * case where we return around the loop. | |
1721 | */ | |
7d590cca | 1722 | mb(); |
ce5f6824 | 1723 | clflush(mwait_ptr); |
7d590cca | 1724 | mb(); |
ce5f6824 | 1725 | __monitor(mwait_ptr, 0, 0); |
ea530692 PA |
1726 | mb(); |
1727 | __mwait(eax, 0); | |
e1c467e6 FY |
1728 | /* |
1729 | * If NMI wants to wake up CPU0, start CPU0. | |
1730 | */ | |
1731 | if (wakeup_cpu0()) | |
1732 | start_cpu0(); | |
ea530692 PA |
1733 | } |
1734 | } | |
1735 | ||
406f992e | 1736 | void hlt_play_dead(void) |
ea530692 | 1737 | { |
7b543a53 | 1738 | if (__this_cpu_read(cpu_info.x86) >= 4) |
a68e5c94 PA |
1739 | wbinvd(); |
1740 | ||
ea530692 | 1741 | while (1) { |
ea530692 | 1742 | native_halt(); |
e1c467e6 FY |
1743 | /* |
1744 | * If NMI wants to wake up CPU0, start CPU0. | |
1745 | */ | |
1746 | if (wakeup_cpu0()) | |
1747 | start_cpu0(); | |
ea530692 PA |
1748 | } |
1749 | } | |
1750 | ||
a21f5d88 AN |
1751 | void native_play_dead(void) |
1752 | { | |
1753 | play_dead_common(); | |
86886e55 | 1754 | tboot_shutdown(TB_SHUTDOWN_WFS); |
ea530692 PA |
1755 | |
1756 | mwait_play_dead(); /* Only returns on failure */ | |
1a022e3f BO |
1757 | if (cpuidle_play_dead()) |
1758 | hlt_play_dead(); | |
a21f5d88 AN |
1759 | } |
1760 | ||
69c18c15 | 1761 | #else /* ... !CONFIG_HOTPLUG_CPU */ |
93be71b6 | 1762 | int native_cpu_disable(void) |
69c18c15 GC |
1763 | { |
1764 | return -ENOSYS; | |
1765 | } | |
1766 | ||
93be71b6 | 1767 | void native_cpu_die(unsigned int cpu) |
69c18c15 GC |
1768 | { |
1769 | /* We said "no" in __cpu_disable */ | |
1770 | BUG(); | |
1771 | } | |
a21f5d88 AN |
1772 | |
1773 | void native_play_dead(void) | |
1774 | { | |
1775 | BUG(); | |
1776 | } | |
1777 | ||
68a1c3f8 | 1778 | #endif |
1567c3e3 GG |
1779 | |
1780 | /* | |
1781 | * APERF/MPERF frequency ratio computation. | |
1782 | * | |
1783 | * The scheduler wants to do frequency invariant accounting and needs a <1 | |
1784 | * ratio to account for the 'current' frequency, corresponding to | |
1785 | * freq_curr / freq_max. | |
1786 | * | |
1787 | * Since the frequency freq_curr on x86 is controlled by micro-controller and | |
1788 | * our P-state setting is little more than a request/hint, we need to observe | |
1789 | * the effective frequency 'BusyMHz', i.e. the average frequency over a time | |
1790 | * interval after discarding idle time. This is given by: | |
1791 | * | |
1792 | * BusyMHz = delta_APERF / delta_MPERF * freq_base | |
1793 | * | |
1794 | * where freq_base is the max non-turbo P-state. | |
1795 | * | |
1796 | * The freq_max term has to be set to a somewhat arbitrary value, because we | |
1797 | * can't know which turbo states will be available at a given point in time: | |
1798 | * it all depends on the thermal headroom of the entire package. We set it to | |
1799 | * the turbo level with 4 cores active. | |
1800 | * | |
1801 | * Benchmarks show that's a good compromise between the 1C turbo ratio | |
1802 | * (freq_curr/freq_max would rarely reach 1) and something close to freq_base, | |
1803 | * which would ignore the entire turbo range (a conspicuous part, making | |
1804 | * freq_curr/freq_max always maxed out). | |
1805 | * | |
eacf0474 GG |
1806 | * An exception to the heuristic above is the Atom uarch, where we choose the |
1807 | * highest turbo level for freq_max since Atom's are generally oriented towards | |
1808 | * power efficiency. | |
1809 | * | |
1567c3e3 GG |
1810 | * Setting freq_max to anything less than the 1C turbo ratio makes the ratio |
1811 | * freq_curr / freq_max to eventually grow >1, in which case we clip it to 1. | |
1812 | */ | |
1813 | ||
1814 | DEFINE_STATIC_KEY_FALSE(arch_scale_freq_key); | |
1815 | ||
1816 | static DEFINE_PER_CPU(u64, arch_prev_aperf); | |
1817 | static DEFINE_PER_CPU(u64, arch_prev_mperf); | |
918229cd | 1818 | static u64 arch_turbo_freq_ratio = SCHED_CAPACITY_SCALE; |
1567c3e3 GG |
1819 | static u64 arch_max_freq_ratio = SCHED_CAPACITY_SCALE; |
1820 | ||
918229cd GG |
1821 | void arch_set_max_freq_ratio(bool turbo_disabled) |
1822 | { | |
1823 | arch_max_freq_ratio = turbo_disabled ? SCHED_CAPACITY_SCALE : | |
1824 | arch_turbo_freq_ratio; | |
1825 | } | |
1826 | ||
1567c3e3 GG |
1827 | static bool turbo_disabled(void) |
1828 | { | |
1829 | u64 misc_en; | |
1830 | int err; | |
1831 | ||
1832 | err = rdmsrl_safe(MSR_IA32_MISC_ENABLE, &misc_en); | |
1833 | if (err) | |
1834 | return false; | |
1835 | ||
1836 | return (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE); | |
1837 | } | |
1838 | ||
298c6f99 GG |
1839 | static bool slv_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq) |
1840 | { | |
1841 | int err; | |
1842 | ||
1843 | err = rdmsrl_safe(MSR_ATOM_CORE_RATIOS, base_freq); | |
1844 | if (err) | |
1845 | return false; | |
1846 | ||
1847 | err = rdmsrl_safe(MSR_ATOM_CORE_TURBO_RATIOS, turbo_freq); | |
1848 | if (err) | |
1849 | return false; | |
1850 | ||
1851 | *base_freq = (*base_freq >> 16) & 0x3F; /* max P state */ | |
1852 | *turbo_freq = *turbo_freq & 0x3F; /* 1C turbo */ | |
1853 | ||
1854 | return true; | |
1855 | } | |
1856 | ||
1567c3e3 GG |
1857 | #include <asm/cpu_device_id.h> |
1858 | #include <asm/intel-family.h> | |
1859 | ||
1860 | #define ICPU(model) \ | |
1861 | {X86_VENDOR_INTEL, 6, model, X86_FEATURE_APERFMPERF, 0} | |
1862 | ||
1863 | static const struct x86_cpu_id has_knl_turbo_ratio_limits[] = { | |
1864 | ICPU(INTEL_FAM6_XEON_PHI_KNL), | |
1865 | ICPU(INTEL_FAM6_XEON_PHI_KNM), | |
1866 | {} | |
1867 | }; | |
1868 | ||
1869 | static const struct x86_cpu_id has_skx_turbo_ratio_limits[] = { | |
1870 | ICPU(INTEL_FAM6_SKYLAKE_X), | |
1871 | {} | |
1872 | }; | |
1873 | ||
1874 | static const struct x86_cpu_id has_glm_turbo_ratio_limits[] = { | |
1875 | ICPU(INTEL_FAM6_ATOM_GOLDMONT), | |
1876 | ICPU(INTEL_FAM6_ATOM_GOLDMONT_D), | |
1877 | ICPU(INTEL_FAM6_ATOM_GOLDMONT_PLUS), | |
1878 | {} | |
1879 | }; | |
1880 | ||
8bea0dfb GG |
1881 | static bool knl_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, |
1882 | int num_delta_fratio) | |
1883 | { | |
1884 | int fratio, delta_fratio, found; | |
1885 | int err, i; | |
1886 | u64 msr; | |
1887 | ||
8bea0dfb GG |
1888 | err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); |
1889 | if (err) | |
1890 | return false; | |
1891 | ||
1892 | *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ | |
1893 | ||
1894 | err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); | |
1895 | if (err) | |
1896 | return false; | |
1897 | ||
1898 | fratio = (msr >> 8) & 0xFF; | |
1899 | i = 16; | |
1900 | found = 0; | |
1901 | do { | |
1902 | if (found >= num_delta_fratio) { | |
1903 | *turbo_freq = fratio; | |
1904 | return true; | |
1905 | } | |
1906 | ||
1907 | delta_fratio = (msr >> (i + 5)) & 0x7; | |
1908 | ||
1909 | if (delta_fratio) { | |
1910 | found += 1; | |
1911 | fratio -= delta_fratio; | |
1912 | } | |
1913 | ||
1914 | i += 8; | |
1915 | } while (i < 64); | |
1916 | ||
1917 | return true; | |
1918 | } | |
1919 | ||
2a0abc59 GG |
1920 | static bool skx_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq, int size) |
1921 | { | |
1922 | u64 ratios, counts; | |
1923 | u32 group_size; | |
1924 | int err, i; | |
1925 | ||
1926 | err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); | |
1927 | if (err) | |
1928 | return false; | |
1929 | ||
1930 | *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ | |
1931 | ||
1932 | err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &ratios); | |
1933 | if (err) | |
1934 | return false; | |
1935 | ||
1936 | err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT1, &counts); | |
1937 | if (err) | |
1938 | return false; | |
1939 | ||
1940 | for (i = 0; i < 64; i += 8) { | |
1941 | group_size = (counts >> i) & 0xFF; | |
1942 | if (group_size >= size) { | |
1943 | *turbo_freq = (ratios >> i) & 0xFF; | |
1944 | return true; | |
1945 | } | |
1946 | } | |
1947 | ||
1948 | return false; | |
1949 | } | |
1950 | ||
1951 | static bool core_set_max_freq_ratio(u64 *base_freq, u64 *turbo_freq) | |
1567c3e3 | 1952 | { |
23ccee22 | 1953 | u64 msr; |
1567c3e3 GG |
1954 | int err; |
1955 | ||
2a0abc59 | 1956 | err = rdmsrl_safe(MSR_PLATFORM_INFO, base_freq); |
1567c3e3 GG |
1957 | if (err) |
1958 | return false; | |
1959 | ||
23ccee22 | 1960 | err = rdmsrl_safe(MSR_TURBO_RATIO_LIMIT, &msr); |
1567c3e3 GG |
1961 | if (err) |
1962 | return false; | |
1963 | ||
23ccee22 GG |
1964 | *base_freq = (*base_freq >> 8) & 0xFF; /* max P state */ |
1965 | *turbo_freq = (msr >> 24) & 0xFF; /* 4C turbo */ | |
1966 | ||
1967 | /* The CPU may have less than 4 cores */ | |
1968 | if (!*turbo_freq) | |
1969 | *turbo_freq = msr & 0xFF; /* 1C turbo */ | |
1567c3e3 | 1970 | |
1567c3e3 GG |
1971 | return true; |
1972 | } | |
1973 | ||
1974 | static bool intel_set_max_freq_ratio(void) | |
1975 | { | |
918229cd | 1976 | u64 base_freq, turbo_freq; |
2a0abc59 | 1977 | |
298c6f99 GG |
1978 | if (slv_set_max_freq_ratio(&base_freq, &turbo_freq)) |
1979 | goto out; | |
1980 | ||
eacf0474 GG |
1981 | if (x86_match_cpu(has_glm_turbo_ratio_limits) && |
1982 | skx_set_max_freq_ratio(&base_freq, &turbo_freq, 1)) | |
1983 | goto out; | |
1984 | ||
db441bd9 GG |
1985 | if (x86_match_cpu(has_knl_turbo_ratio_limits) && |
1986 | knl_set_max_freq_ratio(&base_freq, &turbo_freq, 1)) | |
8bea0dfb GG |
1987 | goto out; |
1988 | ||
2a0abc59 GG |
1989 | if (x86_match_cpu(has_skx_turbo_ratio_limits) && |
1990 | skx_set_max_freq_ratio(&base_freq, &turbo_freq, 4)) | |
1991 | goto out; | |
1992 | ||
1993 | if (core_set_max_freq_ratio(&base_freq, &turbo_freq)) | |
1994 | goto out; | |
1567c3e3 GG |
1995 | |
1996 | return false; | |
2a0abc59 GG |
1997 | |
1998 | out: | |
9a6c2c3c GG |
1999 | /* |
2000 | * Some hypervisors advertise X86_FEATURE_APERFMPERF | |
2001 | * but then fill all MSR's with zeroes. | |
2002 | */ | |
2003 | if (!base_freq) { | |
2004 | pr_debug("Couldn't determine cpu base frequency, necessary for scale-invariant accounting.\n"); | |
2005 | return false; | |
2006 | } | |
2007 | ||
918229cd | 2008 | arch_turbo_freq_ratio = div_u64(turbo_freq * SCHED_CAPACITY_SCALE, |
2a0abc59 | 2009 | base_freq); |
918229cd | 2010 | arch_set_max_freq_ratio(turbo_disabled()); |
2a0abc59 | 2011 | return true; |
1567c3e3 GG |
2012 | } |
2013 | ||
b56e7d45 | 2014 | static void init_counter_refs(void) |
1567c3e3 GG |
2015 | { |
2016 | u64 aperf, mperf; | |
2017 | ||
2018 | rdmsrl(MSR_IA32_APERF, aperf); | |
2019 | rdmsrl(MSR_IA32_MPERF, mperf); | |
2020 | ||
2021 | this_cpu_write(arch_prev_aperf, aperf); | |
2022 | this_cpu_write(arch_prev_mperf, mperf); | |
2023 | } | |
2024 | ||
b56e7d45 | 2025 | static void init_freq_invariance(bool secondary) |
1567c3e3 GG |
2026 | { |
2027 | bool ret = false; | |
2028 | ||
b56e7d45 | 2029 | if (!boot_cpu_has(X86_FEATURE_APERFMPERF)) |
1567c3e3 GG |
2030 | return; |
2031 | ||
b56e7d45 PZI |
2032 | if (secondary) { |
2033 | if (static_branch_likely(&arch_scale_freq_key)) { | |
2034 | init_counter_refs(); | |
2035 | } | |
2036 | return; | |
2037 | } | |
2038 | ||
1567c3e3 GG |
2039 | if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL) |
2040 | ret = intel_set_max_freq_ratio(); | |
2041 | ||
2042 | if (ret) { | |
b56e7d45 | 2043 | init_counter_refs(); |
1567c3e3 GG |
2044 | static_branch_enable(&arch_scale_freq_key); |
2045 | } else { | |
2046 | pr_debug("Couldn't determine max cpu frequency, necessary for scale-invariant accounting.\n"); | |
2047 | } | |
2048 | } | |
2049 | ||
2050 | DEFINE_PER_CPU(unsigned long, arch_freq_scale) = SCHED_CAPACITY_SCALE; | |
2051 | ||
2052 | void arch_scale_freq_tick(void) | |
2053 | { | |
2054 | u64 freq_scale; | |
2055 | u64 aperf, mperf; | |
2056 | u64 acnt, mcnt; | |
2057 | ||
2058 | if (!arch_scale_freq_invariant()) | |
2059 | return; | |
2060 | ||
2061 | rdmsrl(MSR_IA32_APERF, aperf); | |
2062 | rdmsrl(MSR_IA32_MPERF, mperf); | |
2063 | ||
2064 | acnt = aperf - this_cpu_read(arch_prev_aperf); | |
2065 | mcnt = mperf - this_cpu_read(arch_prev_mperf); | |
2066 | if (!mcnt) | |
2067 | return; | |
2068 | ||
2069 | this_cpu_write(arch_prev_aperf, aperf); | |
2070 | this_cpu_write(arch_prev_mperf, mperf); | |
2071 | ||
2072 | acnt <<= 2*SCHED_CAPACITY_SHIFT; | |
2073 | mcnt *= arch_max_freq_ratio; | |
2074 | ||
2075 | freq_scale = div64_u64(acnt, mcnt); | |
2076 | ||
2077 | if (freq_scale > SCHED_CAPACITY_SCALE) | |
2078 | freq_scale = SCHED_CAPACITY_SCALE; | |
2079 | ||
2080 | this_cpu_write(arch_freq_scale, freq_scale); | |
2081 | } |