]> git.ipfire.org Git - thirdparty/linux.git/blame - arch/x86/kvm/lapic.c
projects / thirdparty / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
jump_labels: API for flushing deferred jump label updates
[thirdparty/linux.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
9611c187 8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.
97222cc8
ED		 9 *
10 * Authors:
11 * Dor Laor <dor.laor@qumranet.com>
12 * Gregory Haskins <ghaskins@novell.com>
13 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
14 *
15 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
16 *
17 * This work is licensed under the terms of the GNU GPL, version 2. See
18 * the COPYING file in the top-level directory.
19 */
20
edf88417 21#include <linux/kvm_host.h>
97222cc8
ED		 22#include <linux/kvm.h>
23#include <linux/mm.h>
24#include <linux/highmem.h>
25#include <linux/smp.h>
26#include <linux/hrtimer.h>
27#include <linux/io.h>
1767e931 28#include <linux/export.h>
6f6d6a1a 29#include <linux/math64.h>
5a0e3ad6 30#include <linux/slab.h>
97222cc8
ED		 31#include <asm/processor.h>
32#include <asm/msr.h>
33#include <asm/page.h>
34#include <asm/current.h>
35#include <asm/apicdef.h>
d0659d94 36#include <asm/delay.h>
60063497 37#include <linux/atomic.h>
c5cc421b 38#include <linux/jump_label.h>
5fdbf976 39#include "kvm_cache_regs.h"
97222cc8 40#include "irq.h"
229456fc 41#include "trace.h"
fc61b800 42#include "x86.h"
00b27a3e 43#include "cpuid.h"
5c919412 44#include "hyperv.h"
97222cc8 45
b682b814
MT		 46#ifndef CONFIG_X86_64
47#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
48#else
49#define mod_64(x, y) ((x) % (y))
50#endif
51
97222cc8
ED		 52#define PRId64 "d"
53#define PRIx64 "llx"
54#define PRIu64 "u"
55#define PRIo64 "o"
56
57#define APIC_BUS_CYCLE_NS 1
58
59/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
60#define apic_debug(fmt, arg...)
61
97222cc8 62/* 14 is the version for Xeon and Pentium 8.4.8*/
1e6e2755 63#define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16))
97222cc8
ED		 64#define LAPIC_MMIO_LENGTH (1 << 12)
65/* followed define is not in apicdef.h */
66#define APIC_SHORT_MASK 0xc0000
67#define APIC_DEST_NOSHORT 0x0
68#define APIC_DEST_MASK 0x800
69#define MAX_APIC_VECTOR 256
ecba9a52 70#define APIC_VECTORS_PER_REG 32
97222cc8 71
394457a9
NA		 72#define APIC_BROADCAST 0xFF
73#define X2APIC_BROADCAST 0xFFFFFFFFul
74
a0c9a822
MT		 75static inline int apic_test_vector(int vec, void *bitmap)
76{
77 return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
78}
79
10606919
YZ		 80bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector)
81{
82 struct kvm_lapic *apic = vcpu->arch.apic;
83
84 return apic_test_vector(vector, apic->regs + APIC_ISR) ||
85 apic_test_vector(vector, apic->regs + APIC_IRR);
86}
87
97222cc8
ED		 88static inline void apic_clear_vector(int vec, void *bitmap)
89{
90 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
91}
92
8680b94b
MT		 93static inline int __apic_test_and_set_vector(int vec, void *bitmap)
94{
95 return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
96}
97
98static inline int __apic_test_and_clear_vector(int vec, void *bitmap)
99{
100 return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
101}
102
c5cc421b 103struct static_key_deferred apic_hw_disabled __read_mostly;
f8c1ea10
GN		 104struct static_key_deferred apic_sw_disabled __read_mostly;
105
97222cc8
ED		 106static inline int apic_enabled(struct kvm_lapic *apic)
107{
c48f1496 108 return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic);
54e9818f
GN		 109}
110
97222cc8
ED		 111#define LVT_MASK \
112 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
113
114#define LINT_MASK \
115 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
116 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
117
e45115b6
RK		 118static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map,
119 u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) {
120 switch (map->mode) {
121 case KVM_APIC_MODE_X2APIC: {
122 u32 offset = (dest_id >> 16) * 16;
0ca52e7b 123 u32 max_apic_id = map->max_apic_id;
e45115b6
RK		 124
125 if (offset <= max_apic_id) {
126 u8 cluster_size = min(max_apic_id - offset + 1, 16U);
127
128 *cluster = &map->phys_map[offset];
129 *mask = dest_id & (0xffff >> (16 - cluster_size));
130 } else {
131 *mask = 0;
132 }
3b5a5ffa 133
e45115b6
RK		 134 return true;
135 }
136 case KVM_APIC_MODE_XAPIC_FLAT:
137 *cluster = map->xapic_flat_map;
138 *mask = dest_id & 0xff;
139 return true;
140 case KVM_APIC_MODE_XAPIC_CLUSTER:
444fdad8 141 *cluster = map->xapic_cluster_map[(dest_id >> 4) & 0xf];
e45115b6
RK		 142 *mask = dest_id & 0xf;
143 return true;
144 default:
145 /* Not optimized. */
146 return false;
147 }
3548a259
RK		 148}
149
af1bae54 150static void kvm_apic_map_free(struct rcu_head *rcu)
3b5a5ffa 151{
af1bae54 152 struct kvm_apic_map *map = container_of(rcu, struct kvm_apic_map, rcu);
3b5a5ffa 153
af1bae54 154 kvfree(map);
3b5a5ffa
RK		 155}
156
1e08ec4a
GN		 157static void recalculate_apic_map(struct kvm *kvm)
158{
159 struct kvm_apic_map *new, *old = NULL;
160 struct kvm_vcpu *vcpu;
161 int i;
0ca52e7b 162 u32 max_id = 255;
1e08ec4a
GN		 163
164 mutex_lock(&kvm->arch.apic_map_lock);
165
0ca52e7b
RK		 166 kvm_for_each_vcpu(i, vcpu, kvm)
167 if (kvm_apic_present(vcpu))
168 max_id = max(max_id, kvm_apic_id(vcpu->arch.apic));
169
af1bae54
RK		 170 new = kvm_kvzalloc(sizeof(struct kvm_apic_map) +
171 sizeof(struct kvm_lapic *) * ((u64)max_id + 1));
0ca52e7b 172
1e08ec4a
GN		 173 if (!new)
174 goto out;
175
0ca52e7b
RK		 176 new->max_apic_id = max_id;
177
173beedc
NA		 178 kvm_for_each_vcpu(i, vcpu, kvm) {
179 struct kvm_lapic *apic = vcpu->arch.apic;
e45115b6
RK		 180 struct kvm_lapic **cluster;
181 u16 mask;
25995e5b 182 u32 ldr, aid;
1e08ec4a 183
df04d1d1
RK		 184 if (!kvm_apic_present(vcpu))
185 continue;
186
25995e5b 187 aid = kvm_apic_id(apic);
dfb95954 188 ldr = kvm_lapic_get_reg(apic, APIC_LDR);
1e08ec4a 189
0ca52e7b 190 if (aid <= new->max_apic_id)
25995e5b 191 new->phys_map[aid] = apic;
3548a259 192
3b5a5ffa
RK		 193 if (apic_x2apic_mode(apic)) {
194 new->mode |= KVM_APIC_MODE_X2APIC;
195 } else if (ldr) {
196 ldr = GET_APIC_LOGICAL_ID(ldr);
dfb95954 197 if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT)
3b5a5ffa
RK		 198 new->mode |= KVM_APIC_MODE_XAPIC_FLAT;
199 else
200 new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER;
201 }
202
e45115b6 203 if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask))
3548a259
RK		 204 continue;
205
e45115b6
RK		 206 if (mask)
207 cluster[ffs(mask) - 1] = apic;
1e08ec4a
GN		 208 }
209out:
210 old = rcu_dereference_protected(kvm->arch.apic_map,
211 lockdep_is_held(&kvm->arch.apic_map_lock));
212 rcu_assign_pointer(kvm->arch.apic_map, new);
213 mutex_unlock(&kvm->arch.apic_map_lock);
214
215 if (old)
af1bae54 216 call_rcu(&old->rcu, kvm_apic_map_free);
c7c9c56c 217
b053b2ae 218 kvm_make_scan_ioapic_request(kvm);
1e08ec4a
GN		 219}
220
1e1b6c26
NA		 221static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val)
222{
e462755c 223 bool enabled = val & APIC_SPIV_APIC_ENABLED;
1e1b6c26 224
1e6e2755 225 kvm_lapic_set_reg(apic, APIC_SPIV, val);
e462755c
RK		 226
227 if (enabled != apic->sw_enabled) {
228 apic->sw_enabled = enabled;
229 if (enabled) {
1e1b6c26
NA		 230 static_key_slow_dec_deferred(&apic_sw_disabled);
231 recalculate_apic_map(apic->vcpu->kvm);
232 } else
233 static_key_slow_inc(&apic_sw_disabled.key);
234 }
235}
236
a92e2543 237static inline void kvm_apic_set_xapic_id(struct kvm_lapic *apic, u8 id)
1e08ec4a 238{
1e6e2755 239 kvm_lapic_set_reg(apic, APIC_ID, id << 24);
1e08ec4a
GN		 240 recalculate_apic_map(apic->vcpu->kvm);
241}
242
243static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id)
244{
1e6e2755 245 kvm_lapic_set_reg(apic, APIC_LDR, id);
1e08ec4a
GN		 246 recalculate_apic_map(apic->vcpu->kvm);
247}
248
a92e2543 249static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u32 id)
257b9a5f
RK		 250{
251 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
252
a92e2543 253 kvm_lapic_set_reg(apic, APIC_ID, id);
1e6e2755 254 kvm_lapic_set_reg(apic, APIC_LDR, ldr);
257b9a5f
RK		 255 recalculate_apic_map(apic->vcpu->kvm);
256}
257
97222cc8
ED		 258static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
259{
dfb95954 260 return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
97222cc8
ED		 261}
262
263static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
264{
dfb95954 265 return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
97222cc8
ED		 266}
267
a3e06bbe
LJ		 268static inline int apic_lvtt_oneshot(struct kvm_lapic *apic)
269{
f30ebc31 270 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT;
a3e06bbe
LJ		 271}
272
97222cc8
ED		 273static inline int apic_lvtt_period(struct kvm_lapic *apic)
274{
f30ebc31 275 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC;
a3e06bbe
LJ		 276}
277
278static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic)
279{
f30ebc31 280 return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE;
97222cc8
ED		 281}
282
cc6e462c
JK		 283static inline int apic_lvt_nmi_mode(u32 lvt_val)
284{
285 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
286}
287
fc61b800
GN		 288void kvm_apic_set_version(struct kvm_vcpu *vcpu)
289{
290 struct kvm_lapic *apic = vcpu->arch.apic;
291 struct kvm_cpuid_entry2 *feat;
292 u32 v = APIC_VERSION;
293
bce87cce 294 if (!lapic_in_kernel(vcpu))
fc61b800
GN		 295 return;
296
297 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
298 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
299 v |= APIC_LVR_DIRECTED_EOI;
1e6e2755 300 kvm_lapic_set_reg(apic, APIC_LVR, v);
fc61b800
GN		 301}
302
1e6e2755 303static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = {
a3e06bbe 304 LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */
97222cc8
ED		 305 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
306 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
307 LINT_MASK, LINT_MASK, /* LVT0-1 */
308 LVT_MASK /* LVTERR */
309};
310
311static int find_highest_vector(void *bitmap)
312{
ecba9a52
TY		 313 int vec;
314 u32 *reg;
97222cc8 315
ecba9a52
TY		 316 for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG;
317 vec >= 0; vec -= APIC_VECTORS_PER_REG) {
318 reg = bitmap + REG_POS(vec);
319 if (*reg)
320 return fls(*reg) - 1 + vec;
321 }
97222cc8 322
ecba9a52 323 return -1;
97222cc8
ED		 324}
325
8680b94b
MT		 326static u8 count_vectors(void *bitmap)
327{
ecba9a52
TY		 328 int vec;
329 u32 *reg;
8680b94b 330 u8 count = 0;
ecba9a52
TY		 331
332 for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) {
333 reg = bitmap + REG_POS(vec);
334 count += hweight32(*reg);
335 }
336
8680b94b
MT		 337 return count;
338}
339
705699a1 340void __kvm_apic_update_irr(u32 *pir, void *regs)
a20ed54d
YZ		 341{
342 u32 i, pir_val;
a20ed54d
YZ		 343
344 for (i = 0; i <= 7; i++) {
ad361091
PB		 345 pir_val = READ_ONCE(pir[i]);
346 if (pir_val) {
347 pir_val = xchg(&pir[i], 0);
705699a1 348 *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val;
ad361091 349 }
a20ed54d
YZ		 350 }
351}
705699a1
WV		 352EXPORT_SYMBOL_GPL(__kvm_apic_update_irr);
353
354void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir)
355{
356 struct kvm_lapic *apic = vcpu->arch.apic;
357
358 __kvm_apic_update_irr(pir, apic->regs);
c77f3fab
RK		 359
360 kvm_make_request(KVM_REQ_EVENT, vcpu);
705699a1 361}
a20ed54d
YZ		 362EXPORT_SYMBOL_GPL(kvm_apic_update_irr);
363
33e4c686 364static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 365{
33e4c686 366 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 367}
368
369static inline int apic_find_highest_irr(struct kvm_lapic *apic)
370{
371 int result;
372
c7c9c56c
YZ		 373 /*
374 * Note that irr_pending is just a hint. It will be always
375 * true with virtual interrupt delivery enabled.
376 */
33e4c686
GN		 377 if (!apic->irr_pending)
378 return -1;
379
d62caabb
AS		 380 if (apic->vcpu->arch.apicv_active)
381 kvm_x86_ops->sync_pir_to_irr(apic->vcpu);
33e4c686 382 result = apic_search_irr(apic);
97222cc8
ED		 383 ASSERT(result == -1 || result >= 16);
384
385 return result;
386}
387
33e4c686
GN		 388static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
389{
56cc2406
WL		 390 struct kvm_vcpu *vcpu;
391
392 vcpu = apic->vcpu;
393
d62caabb 394 if (unlikely(vcpu->arch.apicv_active)) {
56cc2406 395 /* try to update RVI */
f210f757 396 apic_clear_vector(vec, apic->regs + APIC_IRR);
56cc2406 397 kvm_make_request(KVM_REQ_EVENT, vcpu);
f210f757
NA		 398 } else {
399 apic->irr_pending = false;
400 apic_clear_vector(vec, apic->regs + APIC_IRR);
401 if (apic_search_irr(apic) != -1)
402 apic->irr_pending = true;
56cc2406 403 }
33e4c686
GN		 404}
405
8680b94b
MT		 406static inline void apic_set_isr(int vec, struct kvm_lapic *apic)
407{
56cc2406
WL		 408 struct kvm_vcpu *vcpu;
409
410 if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR))
411 return;
412
413 vcpu = apic->vcpu;
fc57ac2c 414
8680b94b 415 /*
56cc2406
WL		 416 * With APIC virtualization enabled, all caching is disabled
417 * because the processor can modify ISR under the hood. Instead
418 * just set SVI.
8680b94b 419 */
d62caabb 420 if (unlikely(vcpu->arch.apicv_active))
67c9dddc 421 kvm_x86_ops->hwapic_isr_update(vcpu, vec);
56cc2406
WL		 422 else {
423 ++apic->isr_count;
424 BUG_ON(apic->isr_count > MAX_APIC_VECTOR);
425 /*
426 * ISR (in service register) bit is set when injecting an interrupt.
427 * The highest vector is injected. Thus the latest bit set matches
428 * the highest bit in ISR.
429 */
430 apic->highest_isr_cache = vec;
431 }
8680b94b
MT		 432}
433
fc57ac2c
PB		 434static inline int apic_find_highest_isr(struct kvm_lapic *apic)
435{
436 int result;
437
438 /*
439 * Note that isr_count is always 1, and highest_isr_cache
440 * is always -1, with APIC virtualization enabled.
441 */
442 if (!apic->isr_count)
443 return -1;
444 if (likely(apic->highest_isr_cache != -1))
445 return apic->highest_isr_cache;
446
447 result = find_highest_vector(apic->regs + APIC_ISR);
448 ASSERT(result == -1 || result >= 16);
449
450 return result;
451}
452
8680b94b
MT		 453static inline void apic_clear_isr(int vec, struct kvm_lapic *apic)
454{
fc57ac2c
PB		 455 struct kvm_vcpu *vcpu;
456 if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR))
457 return;
458
459 vcpu = apic->vcpu;
460
461 /*
462 * We do get here for APIC virtualization enabled if the guest
463 * uses the Hyper-V APIC enlightenment. In this case we may need
464 * to trigger a new interrupt delivery by writing the SVI field;
465 * on the other hand isr_count and highest_isr_cache are unused
466 * and must be left alone.
467 */
d62caabb 468 if (unlikely(vcpu->arch.apicv_active))
67c9dddc 469 kvm_x86_ops->hwapic_isr_update(vcpu,
fc57ac2c
PB		 470 apic_find_highest_isr(apic));
471 else {
8680b94b 472 --apic->isr_count;
fc57ac2c
PB		 473 BUG_ON(apic->isr_count < 0);
474 apic->highest_isr_cache = -1;
475 }
8680b94b
MT		 476}
477
6e5d865c
YS		 478int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
479{
33e4c686
GN		 480 /* This may race with setting of irr in __apic_accept_irq() and
481 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
482 * will cause vmexit immediately and the value will be recalculated
483 * on the next vmentry.
484 */
f8543d6a 485 return apic_find_highest_irr(vcpu->arch.apic);
6e5d865c 486}
6e5d865c 487
6da7e3f6 488static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c 489 int vector, int level, int trig_mode,
9e4aabe2 490 struct dest_map *dest_map);
6da7e3f6 491
b4f2225c 492int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq,
9e4aabe2 493 struct dest_map *dest_map)
97222cc8 494{
ad312c7c 495 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 496
58c2dde1 497 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
b4f2225c 498 irq->level, irq->trig_mode, dest_map);
97222cc8
ED		 499}
500
ae7a2a3f
MT		 501static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val)
502{
503
504 return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val,
505 sizeof(val));
506}
507
508static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val)
509{
510
511 return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val,
512 sizeof(*val));
513}
514
515static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu)
516{
517 return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED;
518}
519
520static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu)
521{
522 u8 val;
523 if (pv_eoi_get_user(vcpu, &val) < 0)
524 apic_debug("Can't read EOI MSR value: 0x%llx\n",
96893977 525 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 526 return val & 0x1;
527}
528
529static void pv_eoi_set_pending(struct kvm_vcpu *vcpu)
530{
531 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) {
532 apic_debug("Can't set EOI MSR value: 0x%llx\n",
96893977 533 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 534 return;
535 }
536 __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
537}
538
539static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu)
540{
541 if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) {
542 apic_debug("Can't clear EOI MSR value: 0x%llx\n",
96893977 543 (unsigned long long)vcpu->arch.pv_eoi.msr_val);
ae7a2a3f
MT		 544 return;
545 }
546 __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention);
547}
548
97222cc8
ED		 549static void apic_update_ppr(struct kvm_lapic *apic)
550{
3842d135 551 u32 tpr, isrv, ppr, old_ppr;
97222cc8
ED		 552 int isr;
553
dfb95954
SS		 554 old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI);
555 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI);
97222cc8
ED		 556 isr = apic_find_highest_isr(apic);
557 isrv = (isr != -1) ? isr : 0;
558
559 if ((tpr & 0xf0) >= (isrv & 0xf0))
560 ppr = tpr & 0xff;
561 else
562 ppr = isrv & 0xf0;
563
564 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
565 apic, ppr, isr, isrv);
566
3842d135 567 if (old_ppr != ppr) {
1e6e2755 568 kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr);
83bcacb1
AK		 569 if (ppr < old_ppr)
570 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
3842d135 571 }
97222cc8
ED		 572}
573
574static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
575{
1e6e2755 576 kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr);
97222cc8
ED		 577 apic_update_ppr(apic);
578}
579
03d2249e 580static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda)
394457a9 581{
03d2249e
RK		 582 if (apic_x2apic_mode(apic))
583 return mda == X2APIC_BROADCAST;
584
585 return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST;
394457a9
NA		 586}
587
03d2249e 588static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 589{
03d2249e
RK		 590 if (kvm_apic_broadcast(apic, mda))
591 return true;
592
593 if (apic_x2apic_mode(apic))
594 return mda == kvm_apic_id(apic);
595
596 return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic));
97222cc8
ED		 597}
598
52c233a4 599static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda)
97222cc8 600{
0105d1a5
GN		 601 u32 logical_id;
602
394457a9 603 if (kvm_apic_broadcast(apic, mda))
9368b567 604 return true;
394457a9 605
dfb95954 606 logical_id = kvm_lapic_get_reg(apic, APIC_LDR);
97222cc8 607
9368b567 608 if (apic_x2apic_mode(apic))
8a395363
RK		 609 return ((logical_id >> 16) == (mda >> 16))
610 && (logical_id & mda & 0xffff) != 0;
97222cc8 611
9368b567 612 logical_id = GET_APIC_LOGICAL_ID(logical_id);
03d2249e 613 mda = GET_APIC_DEST_FIELD(mda);
97222cc8 614
dfb95954 615 switch (kvm_lapic_get_reg(apic, APIC_DFR)) {
97222cc8 616 case APIC_DFR_FLAT:
9368b567 617 return (logical_id & mda) != 0;
97222cc8 618 case APIC_DFR_CLUSTER:
9368b567
RK		 619 return ((logical_id >> 4) == (mda >> 4))
620 && (logical_id & mda & 0xf) != 0;
97222cc8 621 default:
7712de87 622 apic_debug("Bad DFR vcpu %d: %08x\n",
dfb95954 623 apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR));
9368b567 624 return false;
97222cc8 625 }
97222cc8
ED		 626}
627
c519265f
RK		 628/* The KVM local APIC implementation has two quirks:
629 *
630 * - the xAPIC MDA stores the destination at bits 24-31, while this
631 * is not true of struct kvm_lapic_irq's dest_id field. This is
632 * just a quirk in the API and is not problematic.
633 *
634 * - in-kernel IOAPIC messages have to be delivered directly to
635 * x2APIC, because the kernel does not support interrupt remapping.
636 * In order to support broadcast without interrupt remapping, x2APIC
637 * rewrites the destination of non-IPI messages from APIC_BROADCAST
638 * to X2APIC_BROADCAST.
639 *
640 * The broadcast quirk can be disabled with KVM_CAP_X2APIC_API. This is
641 * important when userspace wants to use x2APIC-format MSIs, because
642 * APIC_BROADCAST (0xff) is a legal route for "cluster 0, CPUs 0-7".
03d2249e 643 */
c519265f
RK		 644static u32 kvm_apic_mda(struct kvm_vcpu *vcpu, unsigned int dest_id,
645 struct kvm_lapic *source, struct kvm_lapic *target)
03d2249e
RK		 646{
647 bool ipi = source != NULL;
648 bool x2apic_mda = apic_x2apic_mode(ipi ? source : target);
649
c519265f
RK		 650 if (!vcpu->kvm->arch.x2apic_broadcast_quirk_disabled &&
651 !ipi && dest_id == APIC_BROADCAST && x2apic_mda)
03d2249e
RK		 652 return X2APIC_BROADCAST;
653
654 return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id);
655}
656
52c233a4 657bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
394457a9 658 int short_hand, unsigned int dest, int dest_mode)
97222cc8 659{
ad312c7c 660 struct kvm_lapic *target = vcpu->arch.apic;
c519265f 661 u32 mda = kvm_apic_mda(vcpu, dest, source, target);
97222cc8
ED		 662
663 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 664 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 665 target, source, dest, dest_mode, short_hand);
666
bd371396 667 ASSERT(target);
97222cc8
ED		 668 switch (short_hand) {
669 case APIC_DEST_NOSHORT:
3697f302 670 if (dest_mode == APIC_DEST_PHYSICAL)
03d2249e 671 return kvm_apic_match_physical_addr(target, mda);
343f94fe 672 else
03d2249e 673 return kvm_apic_match_logical_addr(target, mda);
97222cc8 674 case APIC_DEST_SELF:
9368b567 675 return target == source;
97222cc8 676 case APIC_DEST_ALLINC:
9368b567 677 return true;
97222cc8 678 case APIC_DEST_ALLBUT:
9368b567 679 return target != source;
97222cc8 680 default:
7712de87
JK		 681 apic_debug("kvm: apic: Bad dest shorthand value %x\n",
682 short_hand);
9368b567 683 return false;
97222cc8 684 }
97222cc8 685}
1e6e2755 686EXPORT_SYMBOL_GPL(kvm_apic_match_dest);
97222cc8 687
52004014
FW		 688int kvm_vector_to_index(u32 vector, u32 dest_vcpus,
689 const unsigned long *bitmap, u32 bitmap_size)
690{
691 u32 mod;
692 int i, idx = -1;
693
694 mod = vector % dest_vcpus;
695
696 for (i = 0; i <= mod; i++) {
697 idx = find_next_bit(bitmap, bitmap_size, idx + 1);
698 BUG_ON(idx == bitmap_size);
699 }
700
701 return idx;
702}
703
4efd805f
RK		 704static void kvm_apic_disabled_lapic_found(struct kvm *kvm)
705{
706 if (!kvm->arch.disabled_lapic_found) {
707 kvm->arch.disabled_lapic_found = true;
708 printk(KERN_INFO
709 "Disabled LAPIC found during irq injection\n");
710 }
711}
712
c519265f
RK		 713static bool kvm_apic_is_broadcast_dest(struct kvm *kvm, struct kvm_lapic **src,
714 struct kvm_lapic_irq *irq, struct kvm_apic_map *map)
1e08ec4a 715{
c519265f
RK		 716 if (kvm->arch.x2apic_broadcast_quirk_disabled) {
717 if ((irq->dest_id == APIC_BROADCAST &&
718 map->mode != KVM_APIC_MODE_X2APIC))
719 return true;
720 if (irq->dest_id == X2APIC_BROADCAST)
721 return true;
722 } else {
723 bool x2apic_ipi = src && *src && apic_x2apic_mode(*src);
724 if (irq->dest_id == (x2apic_ipi ?
725 X2APIC_BROADCAST : APIC_BROADCAST))
726 return true;
727 }
1e08ec4a 728
c519265f
RK		 729 return false;
730}
1e08ec4a 731
64aa47bf
RK		 732/* Return true if the interrupt can be handled by using *bitmap as index mask
733 * for valid destinations in *dst array.
734 * Return false if kvm_apic_map_get_dest_lapic did nothing useful.
735 * Note: we may have zero kvm_lapic destinations when we return true, which
736 * means that the interrupt should be dropped. In this case, *bitmap would be
737 * zero and *dst undefined.
738 */
739static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm,
740 struct kvm_lapic **src, struct kvm_lapic_irq *irq,
741 struct kvm_apic_map *map, struct kvm_lapic ***dst,
742 unsigned long *bitmap)
743{
744 int i, lowest;
1e08ec4a 745
64aa47bf
RK		 746 if (irq->shorthand == APIC_DEST_SELF && src) {
747 *dst = src;
748 *bitmap = 1;
749 return true;
750 } else if (irq->shorthand)
1e08ec4a
GN		 751 return false;
752
c519265f 753 if (!map || kvm_apic_is_broadcast_dest(kvm, src, irq, map))
9ea369b0
RK		 754 return false;
755
64aa47bf 756 if (irq->dest_mode == APIC_DEST_PHYSICAL) {
0ca52e7b 757 if (irq->dest_id > map->max_apic_id) {
64aa47bf
RK		 758 *bitmap = 0;
759 } else {
760 *dst = &map->phys_map[irq->dest_id];
761 *bitmap = 1;
762 }
1e08ec4a 763 return true;
bea15428 764 }
698f9755 765
e45115b6
RK		 766 *bitmap = 0;
767 if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst,
768 (u16 *)bitmap))
1e08ec4a 769 return false;
fa834e91 770
64aa47bf
RK		 771 if (!kvm_lowest_prio_delivery(irq))
772 return true;
3548a259 773
64aa47bf
RK		 774 if (!kvm_vector_hashing_enabled()) {
775 lowest = -1;
776 for_each_set_bit(i, bitmap, 16) {
777 if (!(*dst)[i])
778 continue;
779 if (lowest < 0)
780 lowest = i;
781 else if (kvm_apic_compare_prio((*dst)[i]->vcpu,
782 (*dst)[lowest]->vcpu) < 0)
783 lowest = i;
3548a259 784 }
64aa47bf
RK		 785 } else {
786 if (!*bitmap)
787 return true;
3548a259 788
64aa47bf
RK		 789 lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap),
790 bitmap, 16);
45c3094a 791
64aa47bf
RK		 792 if (!(*dst)[lowest]) {
793 kvm_apic_disabled_lapic_found(kvm);
794 *bitmap = 0;
795 return true;
796 }
797 }
1e08ec4a 798
64aa47bf 799 *bitmap = (lowest >= 0) ? 1 << lowest : 0;
1e08ec4a 800
64aa47bf
RK		 801 return true;
802}
52004014 803
64aa47bf
RK		 804bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src,
805 struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map)
806{
807 struct kvm_apic_map *map;
808 unsigned long bitmap;
809 struct kvm_lapic **dst = NULL;
810 int i;
811 bool ret;
52004014 812
64aa47bf 813 *r = -1;
52004014 814
64aa47bf
RK		 815 if (irq->shorthand == APIC_DEST_SELF) {
816 *r = kvm_apic_set_irq(src->vcpu, irq, dest_map);
817 return true;
818 }
52004014 819
64aa47bf
RK		 820 rcu_read_lock();
821 map = rcu_dereference(kvm->arch.apic_map);
52004014 822
64aa47bf
RK		 823 ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap);
824 if (ret)
825 for_each_set_bit(i, &bitmap, 16) {
826 if (!dst[i])
827 continue;
828 if (*r < 0)
829 *r = 0;
830 *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map);
1e08ec4a 831 }
1e08ec4a 832
1e08ec4a
GN		 833 rcu_read_unlock();
834 return ret;
835}
836
6228a0da
FW		 837/*
838 * This routine tries to handler interrupts in posted mode, here is how
839 * it deals with different cases:
840 * - For single-destination interrupts, handle it in posted mode
841 * - Else if vector hashing is enabled and it is a lowest-priority
842 * interrupt, handle it in posted mode and use the following mechanism
843 * to find the destinaiton vCPU.
844 * 1. For lowest-priority interrupts, store all the possible
845 * destination vCPUs in an array.
846 * 2. Use "guest vector % max number of destination vCPUs" to find
847 * the right destination vCPU in the array for the lowest-priority
848 * interrupt.
849 * - Otherwise, use remapped mode to inject the interrupt.
850 */
8feb4a04
FW		 851bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq,
852 struct kvm_vcpu **dest_vcpu)
853{
854 struct kvm_apic_map *map;
64aa47bf
RK		 855 unsigned long bitmap;
856 struct kvm_lapic **dst = NULL;
8feb4a04 857 bool ret = false;
8feb4a04
FW		 858
859 if (irq->shorthand)
860 return false;
861
862 rcu_read_lock();
863 map = rcu_dereference(kvm->arch.apic_map);
864
64aa47bf
RK		 865 if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) &&
866 hweight16(bitmap) == 1) {
867 unsigned long i = find_first_bit(&bitmap, 16);
6228a0da 868
64aa47bf
RK		 869 if (dst[i]) {
870 *dest_vcpu = dst[i]->vcpu;
871 ret = true;
6228a0da 872 }
8feb4a04
FW		 873 }
874
8feb4a04
FW		 875 rcu_read_unlock();
876 return ret;
877}
878
97222cc8
ED		 879/*
880 * Add a pending IRQ into lapic.
881 * Return 1 if successfully added and 0 if discarded.
882 */
883static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
b4f2225c 884 int vector, int level, int trig_mode,
9e4aabe2 885 struct dest_map *dest_map)
97222cc8 886{
6da7e3f6 887 int result = 0;
c5ec1534 888 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8 889
a183b638
PB		 890 trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode,
891 trig_mode, vector);
97222cc8 892 switch (delivery_mode) {
97222cc8 893 case APIC_DM_LOWEST:
e1035715
GN		 894 vcpu->arch.apic_arb_prio++;
895 case APIC_DM_FIXED:
bdaffe1d
PB		 896 if (unlikely(trig_mode && !level))
897 break;
898
97222cc8
ED		 899 /* FIXME add logic for vcpu on reset */
900 if (unlikely(!apic_enabled(apic)))
901 break;
902
11f5cc05
JK		 903 result = 1;
904
9daa5007 905 if (dest_map) {
9e4aabe2 906 __set_bit(vcpu->vcpu_id, dest_map->map);
9daa5007
JR		 907 dest_map->vectors[vcpu->vcpu_id] = vector;
908 }
a5d36f82 909
bdaffe1d
PB		 910 if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) {
911 if (trig_mode)
1e6e2755 912 kvm_lapic_set_vector(vector, apic->regs + APIC_TMR);
bdaffe1d
PB		 913 else
914 apic_clear_vector(vector, apic->regs + APIC_TMR);
915 }
916
d62caabb 917 if (vcpu->arch.apicv_active)
5a71785d 918 kvm_x86_ops->deliver_posted_interrupt(vcpu, vector);
11f5cc05 919 else {
1e6e2755 920 kvm_lapic_set_irr(vector, apic);
5a71785d
YZ		 921
922 kvm_make_request(KVM_REQ_EVENT, vcpu);
923 kvm_vcpu_kick(vcpu);
924 }
97222cc8
ED		 925 break;
926
927 case APIC_DM_REMRD:
24d2166b
R		 928 result = 1;
929 vcpu->arch.pv.pv_unhalted = 1;
930 kvm_make_request(KVM_REQ_EVENT, vcpu);
931 kvm_vcpu_kick(vcpu);
97222cc8
ED		 932 break;
933
934 case APIC_DM_SMI:
64d60670
PB		 935 result = 1;
936 kvm_make_request(KVM_REQ_SMI, vcpu);
937 kvm_vcpu_kick(vcpu);
97222cc8 938 break;
3419ffc8 939
97222cc8 940 case APIC_DM_NMI:
6da7e3f6 941 result = 1;
3419ffc8 942 kvm_inject_nmi(vcpu);
26df99c6 943 kvm_vcpu_kick(vcpu);
97222cc8
ED		 944 break;
945
946 case APIC_DM_INIT:
a52315e1 947 if (!trig_mode || level) {
6da7e3f6 948 result = 1;
66450a21
JK		 949 /* assumes that there are only KVM_APIC_INIT/SIPI */
950 apic->pending_events = (1UL << KVM_APIC_INIT);
951 /* make sure pending_events is visible before sending
952 * the request */
953 smp_wmb();
3842d135 954 kvm_make_request(KVM_REQ_EVENT, vcpu);
c5ec1534
HQ		 955 kvm_vcpu_kick(vcpu);
956 } else {
1b10bf31
JK		 957 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
958 vcpu->vcpu_id);
c5ec1534 959 }
97222cc8
ED		 960 break;
961
962 case APIC_DM_STARTUP:
1b10bf31
JK		 963 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
964 vcpu->vcpu_id, vector);
66450a21
JK		 965 result = 1;
966 apic->sipi_vector = vector;
967 /* make sure sipi_vector is visible for the receiver */
968 smp_wmb();
969 set_bit(KVM_APIC_SIPI, &apic->pending_events);
970 kvm_make_request(KVM_REQ_EVENT, vcpu);
971 kvm_vcpu_kick(vcpu);
97222cc8
ED		 972 break;
973
23930f95
JK		 974 case APIC_DM_EXTINT:
975 /*
976 * Should only be called by kvm_apic_local_deliver() with LVT0,
977 * before NMI watchdog was enabled. Already handled by
978 * kvm_apic_accept_pic_intr().
979 */
980 break;
981
97222cc8
ED		 982 default:
983 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
984 delivery_mode);
985 break;
986 }
987 return result;
988}
989
e1035715 990int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 991{
e1035715 992 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 993}
994
3bb345f3
PB		 995static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector)
996{
6308630b 997 return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors);
3bb345f3
PB		 998}
999
c7c9c56c
YZ		 1000static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector)
1001{
7543a635
SR		 1002 int trigger_mode;
1003
1004 /* Eoi the ioapic only if the ioapic doesn't own the vector. */
1005 if (!kvm_ioapic_handles_vector(apic, vector))
1006 return;
3bb345f3 1007
7543a635
SR		 1008 /* Request a KVM exit to inform the userspace IOAPIC. */
1009 if (irqchip_split(apic->vcpu->kvm)) {
1010 apic->vcpu->arch.pending_ioapic_eoi = vector;
1011 kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu);
1012 return;
c7c9c56c 1013 }
7543a635
SR		 1014
1015 if (apic_test_vector(vector, apic->regs + APIC_TMR))
1016 trigger_mode = IOAPIC_LEVEL_TRIG;
1017 else
1018 trigger_mode = IOAPIC_EDGE_TRIG;
1019
1020 kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode);
c7c9c56c
YZ		 1021}
1022
ae7a2a3f 1023static int apic_set_eoi(struct kvm_lapic *apic)
97222cc8
ED		 1024{
1025 int vector = apic_find_highest_isr(apic);
ae7a2a3f
MT		 1026
1027 trace_kvm_eoi(apic, vector);
1028
97222cc8
ED		 1029 /*
1030 * Not every write EOI will has corresponding ISR,
1031 * one example is when Kernel check timer on setup_IO_APIC
1032 */
1033 if (vector == -1)
ae7a2a3f 1034 return vector;
97222cc8 1035
8680b94b 1036 apic_clear_isr(vector, apic);
97222cc8
ED		 1037 apic_update_ppr(apic);
1038
5c919412
AS		 1039 if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap))
1040 kvm_hv_synic_send_eoi(apic->vcpu, vector);
1041
c7c9c56c 1042 kvm_ioapic_send_eoi(apic, vector);
3842d135 1043 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
ae7a2a3f 1044 return vector;
97222cc8
ED		 1045}
1046
c7c9c56c
YZ		 1047/*
1048 * this interface assumes a trap-like exit, which has already finished
1049 * desired side effect including vISR and vPPR update.
1050 */
1051void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector)
1052{
1053 struct kvm_lapic *apic = vcpu->arch.apic;
1054
1055 trace_kvm_eoi(apic, vector);
1056
1057 kvm_ioapic_send_eoi(apic, vector);
1058 kvm_make_request(KVM_REQ_EVENT, apic->vcpu);
1059}
1060EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated);
1061
97222cc8
ED		 1062static void apic_send_ipi(struct kvm_lapic *apic)
1063{
dfb95954
SS		 1064 u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR);
1065 u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2);
58c2dde1 1066 struct kvm_lapic_irq irq;
97222cc8 1067
58c2dde1
GN		 1068 irq.vector = icr_low & APIC_VECTOR_MASK;
1069 irq.delivery_mode = icr_low & APIC_MODE_MASK;
1070 irq.dest_mode = icr_low & APIC_DEST_MASK;
b7cb2231 1071 irq.level = (icr_low & APIC_INT_ASSERT) != 0;
58c2dde1
GN		 1072 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
1073 irq.shorthand = icr_low & APIC_SHORT_MASK;
93bbf0b8 1074 irq.msi_redir_hint = false;
0105d1a5
GN		 1075 if (apic_x2apic_mode(apic))
1076 irq.dest_id = icr_high;
1077 else
1078 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8 1079
1000ff8d
GN		 1080 trace_kvm_apic_ipi(icr_low, irq.dest_id);
1081
97222cc8
ED		 1082 apic_debug("icr_high 0x%x, icr_low 0x%x, "
1083 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
93bbf0b8
JS		 1084 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, "
1085 "msi_redir_hint 0x%x\n",
9b5843dd 1086 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1 1087 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
93bbf0b8 1088 irq.vector, irq.msi_redir_hint);
58c2dde1 1089
b4f2225c 1090 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL);
97222cc8
ED		 1091}
1092
1093static u32 apic_get_tmcct(struct kvm_lapic *apic)
1094{
8003c9ae 1095 ktime_t remaining, now;
b682b814 1096 s64 ns;
9da8f4e8 1097 u32 tmcct;
97222cc8
ED		 1098
1099 ASSERT(apic != NULL);
1100
9da8f4e8 1101 /* if initial count is 0, current count should also be 0 */
dfb95954 1102 if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 ||
b963a22e 1103 apic->lapic_timer.period == 0)
9da8f4e8
KP		 1104 return 0;
1105
5587859f 1106 now = ktime_get();
8003c9ae 1107 remaining = ktime_sub(apic->lapic_timer.target_expiration, now);
b682b814 1108 if (ktime_to_ns(remaining) < 0)
8b0e1953 1109 remaining = 0;
b682b814 1110
d3c7b77d
MT		 1111 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
1112 tmcct = div64_u64(ns,
1113 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 1114
1115 return tmcct;
1116}
1117
b209749f
AK		 1118static void __report_tpr_access(struct kvm_lapic *apic, bool write)
1119{
1120 struct kvm_vcpu *vcpu = apic->vcpu;
1121 struct kvm_run *run = vcpu->run;
1122
a8eeb04a 1123 kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu);
5fdbf976 1124 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 1125 run->tpr_access.is_write = write;
1126}
1127
1128static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
1129{
1130 if (apic->vcpu->arch.tpr_access_reporting)
1131 __report_tpr_access(apic, write);
1132}
1133
97222cc8
ED		 1134static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
1135{
1136 u32 val = 0;
1137
1138 if (offset >= LAPIC_MMIO_LENGTH)
1139 return 0;
1140
1141 switch (offset) {
1142 case APIC_ARBPRI:
7712de87 1143 apic_debug("Access APIC ARBPRI register which is for P6\n");
97222cc8
ED		 1144 break;
1145
1146 case APIC_TMCCT: /* Timer CCR */
a3e06bbe
LJ		 1147 if (apic_lvtt_tscdeadline(apic))
1148 return 0;
1149
97222cc8
ED		 1150 val = apic_get_tmcct(apic);
1151 break;
4a4541a4
AK		 1152 case APIC_PROCPRI:
1153 apic_update_ppr(apic);
dfb95954 1154 val = kvm_lapic_get_reg(apic, offset);
4a4541a4 1155 break;
b209749f
AK		 1156 case APIC_TASKPRI:
1157 report_tpr_access(apic, false);
1158 /* fall thru */
97222cc8 1159 default:
dfb95954 1160 val = kvm_lapic_get_reg(apic, offset);
97222cc8
ED		 1161 break;
1162 }
1163
1164 return val;
1165}
1166
d76685c4
GH		 1167static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
1168{
1169 return container_of(dev, struct kvm_lapic, dev);
1170}
1171
1e6e2755 1172int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len,
0105d1a5 1173 void *data)
97222cc8 1174{
97222cc8
ED		 1175 unsigned char alignment = offset & 0xf;
1176 u32 result;
d5b0b5b1 1177 /* this bitmask has a bit cleared for each reserved register */
0105d1a5 1178 static const u64 rmask = 0x43ff01ffffffe70cULL;
97222cc8
ED		 1179
1180 if ((alignment + len) > 4) {
4088bb3c
GN		 1181 apic_debug("KVM_APIC_READ: alignment error %x %d\n",
1182 offset, len);
0105d1a5 1183 return 1;
97222cc8 1184 }
0105d1a5
GN		 1185
1186 if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) {
4088bb3c
GN		 1187 apic_debug("KVM_APIC_READ: read reserved register %x\n",
1188 offset);
0105d1a5
GN		 1189 return 1;
1190 }
1191
97222cc8
ED		 1192 result = __apic_read(apic, offset & ~0xf);
1193
229456fc
MT		 1194 trace_kvm_apic_read(offset, result);
1195
97222cc8
ED		 1196 switch (len) {
1197 case 1:
1198 case 2:
1199 case 4:
1200 memcpy(data, (char *)&result + alignment, len);
1201 break;
1202 default:
1203 printk(KERN_ERR "Local APIC read with len = %x, "
1204 "should be 1,2, or 4 instead\n", len);
1205 break;
1206 }
bda9020e 1207 return 0;
97222cc8 1208}
1e6e2755 1209EXPORT_SYMBOL_GPL(kvm_lapic_reg_read);
97222cc8 1210
0105d1a5
GN		 1211static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
1212{
c48f1496 1213 return kvm_apic_hw_enabled(apic) &&
0105d1a5
GN		 1214 addr >= apic->base_address &&
1215 addr < apic->base_address + LAPIC_MMIO_LENGTH;
1216}
1217
e32edf4f 1218static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1219 gpa_t address, int len, void *data)
1220{
1221 struct kvm_lapic *apic = to_lapic(this);
1222 u32 offset = address - apic->base_address;
1223
1224 if (!apic_mmio_in_range(apic, address))
1225 return -EOPNOTSUPP;
1226
1e6e2755 1227 kvm_lapic_reg_read(apic, offset, len, data);
0105d1a5
GN		 1228
1229 return 0;
1230}
1231
97222cc8
ED		 1232static void update_divide_count(struct kvm_lapic *apic)
1233{
1234 u32 tmp1, tmp2, tdcr;
1235
dfb95954 1236 tdcr = kvm_lapic_get_reg(apic, APIC_TDCR);
97222cc8
ED		 1237 tmp1 = tdcr & 0xf;
1238 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 1239 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 1240
1241 apic_debug("timer divide count is 0x%x\n",
9b5843dd 1242 apic->divide_count);
97222cc8
ED		 1243}
1244
b6ac0695
RK		 1245static void apic_update_lvtt(struct kvm_lapic *apic)
1246{
dfb95954 1247 u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) &
b6ac0695
RK		 1248 apic->lapic_timer.timer_mode_mask;
1249
1250 if (apic->lapic_timer.timer_mode != timer_mode) {
1251 apic->lapic_timer.timer_mode = timer_mode;
1252 hrtimer_cancel(&apic->lapic_timer.timer);
1253 }
1254}
1255
5d87db71
RK		 1256static void apic_timer_expired(struct kvm_lapic *apic)
1257{
1258 struct kvm_vcpu *vcpu = apic->vcpu;
8577370f 1259 struct swait_queue_head *q = &vcpu->wq;
d0659d94 1260 struct kvm_timer *ktimer = &apic->lapic_timer;
5d87db71 1261
5d87db71
RK		 1262 if (atomic_read(&apic->lapic_timer.pending))
1263 return;
1264
1265 atomic_inc(&apic->lapic_timer.pending);
bab5bb39 1266 kvm_set_pending_timer(vcpu);
5d87db71 1267
8577370f
MT		 1268 if (swait_active(q))
1269 swake_up(q);
d0659d94
MT		 1270
1271 if (apic_lvtt_tscdeadline(apic))
1272 ktimer->expired_tscdeadline = ktimer->tscdeadline;
1273}
1274
1275/*
1276 * On APICv, this test will cause a busy wait
1277 * during a higher-priority task.
1278 */
1279
1280static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu)
1281{
1282 struct kvm_lapic *apic = vcpu->arch.apic;
dfb95954 1283 u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT);
d0659d94
MT		 1284
1285 if (kvm_apic_hw_enabled(apic)) {
1286 int vec = reg & APIC_VECTOR_MASK;
f9339860 1287 void *bitmap = apic->regs + APIC_ISR;
d0659d94 1288
d62caabb 1289 if (vcpu->arch.apicv_active)
f9339860
MT		 1290 bitmap = apic->regs + APIC_IRR;
1291
1292 if (apic_test_vector(vec, bitmap))
1293 return true;
d0659d94
MT		 1294 }
1295 return false;
1296}
1297
1298void wait_lapic_expire(struct kvm_vcpu *vcpu)
1299{
1300 struct kvm_lapic *apic = vcpu->arch.apic;
1301 u64 guest_tsc, tsc_deadline;
1302
bce87cce 1303 if (!lapic_in_kernel(vcpu))
d0659d94
MT		 1304 return;
1305
1306 if (apic->lapic_timer.expired_tscdeadline == 0)
1307 return;
1308
1309 if (!lapic_timer_int_injected(vcpu))
1310 return;
1311
1312 tsc_deadline = apic->lapic_timer.expired_tscdeadline;
1313 apic->lapic_timer.expired_tscdeadline = 0;
4ba76538 1314 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
6c19b753 1315 trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline);
d0659d94
MT		 1316
1317 /* __delay is delay_tsc whenever the hardware has TSC, thus always. */
1318 if (guest_tsc < tsc_deadline)
b606f189
MT		 1319 __delay(min(tsc_deadline - guest_tsc,
1320 nsec_to_cycles(vcpu, lapic_timer_advance_ns)));
5d87db71
RK		 1321}
1322
53f9eedf
YJ		 1323static void start_sw_tscdeadline(struct kvm_lapic *apic)
1324{
1325 u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline;
1326 u64 ns = 0;
1327 ktime_t expire;
1328 struct kvm_vcpu *vcpu = apic->vcpu;
1329 unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz;
1330 unsigned long flags;
1331 ktime_t now;
1332
1333 if (unlikely(!tscdeadline || !this_tsc_khz))
1334 return;
1335
1336 local_irq_save(flags);
1337
5587859f 1338 now = ktime_get();
53f9eedf
YJ		 1339 guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc());
1340 if (likely(tscdeadline > guest_tsc)) {
1341 ns = (tscdeadline - guest_tsc) * 1000000ULL;
1342 do_div(ns, this_tsc_khz);
1343 expire = ktime_add_ns(now, ns);
1344 expire = ktime_sub_ns(expire, lapic_timer_advance_ns);
1345 hrtimer_start(&apic->lapic_timer.timer,
1346 expire, HRTIMER_MODE_ABS_PINNED);
1347 } else
1348 apic_timer_expired(apic);
1349
1350 local_irq_restore(flags);
1351}
1352
7d7f7da2 1353static void start_sw_period(struct kvm_lapic *apic)
8003c9ae
WL		 1354{
1355 if (!apic->lapic_timer.period)
1356 return;
1357
1358 if (apic_lvtt_oneshot(apic) &&
5587859f 1359 ktime_after(ktime_get(),
8003c9ae
WL		 1360 apic->lapic_timer.target_expiration)) {
1361 apic_timer_expired(apic);
1362 return;
1363 }
1364
1365 hrtimer_start(&apic->lapic_timer.timer,
1366 apic->lapic_timer.target_expiration,
1367 HRTIMER_MODE_ABS_PINNED);
1368}
1369
1370static bool set_target_expiration(struct kvm_lapic *apic)
7d7f7da2
WL		 1371{
1372 ktime_t now;
8003c9ae 1373 u64 tscl = rdtsc();
7d7f7da2 1374
5587859f 1375 now = ktime_get();
7d7f7da2 1376 apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT)
8003c9ae 1377 * APIC_BUS_CYCLE_NS * apic->divide_count;
7d7f7da2
WL		 1378
1379 if (!apic->lapic_timer.period)
8003c9ae
WL		 1380 return false;
1381
7d7f7da2
WL		 1382 /*
1383 * Do not allow the guest to program periodic timers with small
1384 * interval, since the hrtimers are not throttled by the host
1385 * scheduler.
1386 */
1387 if (apic_lvtt_period(apic)) {
1388 s64 min_period = min_timer_period_us * 1000LL;
1389
1390 if (apic->lapic_timer.period < min_period) {
1391 pr_info_ratelimited(
1392 "kvm: vcpu %i: requested %lld ns "
1393 "lapic timer period limited to %lld ns\n",
1394 apic->vcpu->vcpu_id,
1395 apic->lapic_timer.period, min_period);
1396 apic->lapic_timer.period = min_period;
1397 }
1398 }
1399
7d7f7da2
WL		 1400 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
1401 PRIx64 ", "
1402 "timer initial count 0x%x, period %lldns, "
1403 "expire @ 0x%016" PRIx64 ".\n", __func__,
1404 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
1405 kvm_lapic_get_reg(apic, APIC_TMICT),
1406 apic->lapic_timer.period,
1407 ktime_to_ns(ktime_add_ns(now,
1408 apic->lapic_timer.period)));
8003c9ae
WL		 1409
1410 apic->lapic_timer.tscdeadline = kvm_read_l1_tsc(apic->vcpu, tscl) +
1411 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1412 apic->lapic_timer.target_expiration = ktime_add_ns(now, apic->lapic_timer.period);
1413
1414 return true;
1415}
1416
1417static void advance_periodic_target_expiration(struct kvm_lapic *apic)
1418{
1419 apic->lapic_timer.tscdeadline +=
1420 nsec_to_cycles(apic->vcpu, apic->lapic_timer.period);
1421 apic->lapic_timer.target_expiration =
1422 ktime_add_ns(apic->lapic_timer.target_expiration,
1423 apic->lapic_timer.period);
7d7f7da2
WL		 1424}
1425
ce7a058a
YJ		 1426bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu)
1427{
91005300
WL		 1428 if (!lapic_in_kernel(vcpu))
1429 return false;
1430
ce7a058a
YJ		 1431 return vcpu->arch.apic->lapic_timer.hv_timer_in_use;
1432}
1433EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use);
1434
7e810a38 1435static void cancel_hv_timer(struct kvm_lapic *apic)
bd97ad0e
WL		 1436{
1437 kvm_x86_ops->cancel_hv_timer(apic->vcpu);
1438 apic->lapic_timer.hv_timer_in_use = false;
1439}
1440
7e810a38 1441static bool start_hv_timer(struct kvm_lapic *apic)
196f20ca
WL		 1442{
1443 u64 tscdeadline = apic->lapic_timer.tscdeadline;
1444
8003c9ae
WL		 1445 if ((atomic_read(&apic->lapic_timer.pending) &&
1446 !apic_lvtt_period(apic)) ||
196f20ca
WL		 1447 kvm_x86_ops->set_hv_timer(apic->vcpu, tscdeadline)) {
1448 if (apic->lapic_timer.hv_timer_in_use)
7e810a38 1449 cancel_hv_timer(apic);
196f20ca
WL		 1450 } else {
1451 apic->lapic_timer.hv_timer_in_use = true;
1452 hrtimer_cancel(&apic->lapic_timer.timer);
1453
1454 /* In case the sw timer triggered in the window */
8003c9ae
WL		 1455 if (atomic_read(&apic->lapic_timer.pending) &&
1456 !apic_lvtt_period(apic))
7e810a38 1457 cancel_hv_timer(apic);
196f20ca
WL		 1458 }
1459 trace_kvm_hv_timer_state(apic->vcpu->vcpu_id,
1460 apic->lapic_timer.hv_timer_in_use);
1461 return apic->lapic_timer.hv_timer_in_use;
1462}
1463
8003c9ae
WL		 1464void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu)
1465{
1466 struct kvm_lapic *apic = vcpu->arch.apic;
1467
1468 WARN_ON(!apic->lapic_timer.hv_timer_in_use);
1469 WARN_ON(swait_active(&vcpu->wq));
1470 cancel_hv_timer(apic);
1471 apic_timer_expired(apic);
1472
1473 if (apic_lvtt_period(apic) && apic->lapic_timer.period) {
1474 advance_periodic_target_expiration(apic);
1475 if (!start_hv_timer(apic))
1476 start_sw_period(apic);
1477 }
1478}
1479EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer);
1480
ce7a058a
YJ		 1481void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu)
1482{
1483 struct kvm_lapic *apic = vcpu->arch.apic;
1484
1485 WARN_ON(apic->lapic_timer.hv_timer_in_use);
1486
8003c9ae 1487 start_hv_timer(apic);
ce7a058a
YJ		 1488}
1489EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer);
1490
1491void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu)
1492{
1493 struct kvm_lapic *apic = vcpu->arch.apic;
1494
1495 /* Possibly the TSC deadline timer is not enabled yet */
1496 if (!apic->lapic_timer.hv_timer_in_use)
1497 return;
1498
7e810a38 1499 cancel_hv_timer(apic);
ce7a058a
YJ		 1500
1501 if (atomic_read(&apic->lapic_timer.pending))
1502 return;
1503
8003c9ae
WL		 1504 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic))
1505 start_sw_period(apic);
1506 else if (apic_lvtt_tscdeadline(apic))
1507 start_sw_tscdeadline(apic);
ce7a058a
YJ		 1508}
1509EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer);
1510
97222cc8
ED		 1511static void start_apic_timer(struct kvm_lapic *apic)
1512{
d3c7b77d 1513 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 1514
a3e06bbe 1515 if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) {
8003c9ae
WL		 1516 if (set_target_expiration(apic) &&
1517 !(kvm_x86_ops->set_hv_timer && start_hv_timer(apic)))
1518 start_sw_period(apic);
a3e06bbe 1519 } else if (apic_lvtt_tscdeadline(apic)) {
7e810a38 1520 if (!(kvm_x86_ops->set_hv_timer && start_hv_timer(apic)))
ce7a058a 1521 start_sw_tscdeadline(apic);
a3e06bbe 1522 }
97222cc8
ED		 1523}
1524
cc6e462c
JK		 1525static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
1526{
59fd1323 1527 bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val);
cc6e462c 1528
59fd1323
RK		 1529 if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) {
1530 apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode;
1531 if (lvt0_in_nmi_mode) {
cc6e462c
JK		 1532 apic_debug("Receive NMI setting on APIC_LVT0 "
1533 "for cpu %d\n", apic->vcpu->vcpu_id);
42720138 1534 atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
59fd1323
RK		 1535 } else
1536 atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode);
1537 }
cc6e462c
JK		 1538}
1539
1e6e2755 1540int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val)
97222cc8 1541{
0105d1a5 1542 int ret = 0;
97222cc8 1543
0105d1a5 1544 trace_kvm_apic_write(reg, val);
97222cc8 1545
0105d1a5 1546 switch (reg) {
97222cc8 1547 case APIC_ID: /* Local APIC ID */
0105d1a5 1548 if (!apic_x2apic_mode(apic))
a92e2543 1549 kvm_apic_set_xapic_id(apic, val >> 24);
0105d1a5
GN		 1550 else
1551 ret = 1;
97222cc8
ED		 1552 break;
1553
1554 case APIC_TASKPRI:
b209749f 1555 report_tpr_access(apic, true);
97222cc8
ED		 1556 apic_set_tpr(apic, val & 0xff);
1557 break;
1558
1559 case APIC_EOI:
1560 apic_set_eoi(apic);
1561 break;
1562
1563 case APIC_LDR:
0105d1a5 1564 if (!apic_x2apic_mode(apic))
1e08ec4a 1565 kvm_apic_set_ldr(apic, val & APIC_LDR_MASK);
0105d1a5
GN		 1566 else
1567 ret = 1;
97222cc8
ED		 1568 break;
1569
1570 case APIC_DFR:
1e08ec4a 1571 if (!apic_x2apic_mode(apic)) {
1e6e2755 1572 kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
1e08ec4a
GN		 1573 recalculate_apic_map(apic->vcpu->kvm);
1574 } else
0105d1a5 1575 ret = 1;
97222cc8
ED		 1576 break;
1577
fc61b800
GN		 1578 case APIC_SPIV: {
1579 u32 mask = 0x3ff;
dfb95954 1580 if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
fc61b800 1581 mask |= APIC_SPIV_DIRECTED_EOI;
f8c1ea10 1582 apic_set_spiv(apic, val & mask);
97222cc8
ED		 1583 if (!(val & APIC_SPIV_APIC_ENABLED)) {
1584 int i;
1585 u32 lvt_val;
1586
1e6e2755 1587 for (i = 0; i < KVM_APIC_LVT_NUM; i++) {
dfb95954 1588 lvt_val = kvm_lapic_get_reg(apic,
97222cc8 1589 APIC_LVTT + 0x10 * i);
1e6e2755 1590 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i,
97222cc8
ED		 1591 lvt_val | APIC_LVT_MASKED);
1592 }
b6ac0695 1593 apic_update_lvtt(apic);
d3c7b77d 1594 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 1595
1596 }
1597 break;
fc61b800 1598 }
97222cc8
ED		 1599 case APIC_ICR:
1600 /* No delay here, so we always clear the pending bit */
1e6e2755 1601 kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
97222cc8
ED		 1602 apic_send_ipi(apic);
1603 break;
1604
1605 case APIC_ICR2:
0105d1a5
GN		 1606 if (!apic_x2apic_mode(apic))
1607 val &= 0xff000000;
1e6e2755 1608 kvm_lapic_set_reg(apic, APIC_ICR2, val);
97222cc8
ED		 1609 break;
1610
23930f95 1611 case APIC_LVT0:
cc6e462c 1612 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 1613 case APIC_LVTTHMR:
1614 case APIC_LVTPC:
97222cc8
ED		 1615 case APIC_LVT1:
1616 case APIC_LVTERR:
1617 /* TODO: Check vector */
c48f1496 1618 if (!kvm_apic_sw_enabled(apic))
97222cc8
ED		 1619 val |= APIC_LVT_MASKED;
1620
0105d1a5 1621 val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4];
1e6e2755 1622 kvm_lapic_set_reg(apic, reg, val);
97222cc8
ED		 1623
1624 break;
1625
b6ac0695 1626 case APIC_LVTT:
c48f1496 1627 if (!kvm_apic_sw_enabled(apic))
a3e06bbe
LJ		 1628 val |= APIC_LVT_MASKED;
1629 val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask);
1e6e2755 1630 kvm_lapic_set_reg(apic, APIC_LVTT, val);
b6ac0695 1631 apic_update_lvtt(apic);
a3e06bbe
LJ		 1632 break;
1633
97222cc8 1634 case APIC_TMICT:
a3e06bbe
LJ		 1635 if (apic_lvtt_tscdeadline(apic))
1636 break;
1637
d3c7b77d 1638 hrtimer_cancel(&apic->lapic_timer.timer);
1e6e2755 1639 kvm_lapic_set_reg(apic, APIC_TMICT, val);
97222cc8 1640 start_apic_timer(apic);
0105d1a5 1641 break;
97222cc8
ED		 1642
1643 case APIC_TDCR:
1644 if (val & 4)
7712de87 1645 apic_debug("KVM_WRITE:TDCR %x\n", val);
1e6e2755 1646 kvm_lapic_set_reg(apic, APIC_TDCR, val);
97222cc8
ED		 1647 update_divide_count(apic);
1648 break;
1649
0105d1a5
GN		 1650 case APIC_ESR:
1651 if (apic_x2apic_mode(apic) && val != 0) {
7712de87 1652 apic_debug("KVM_WRITE:ESR not zero %x\n", val);
0105d1a5
GN		 1653 ret = 1;
1654 }
1655 break;
1656
1657 case APIC_SELF_IPI:
1658 if (apic_x2apic_mode(apic)) {
1e6e2755 1659 kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff));
0105d1a5
GN		 1660 } else
1661 ret = 1;
1662 break;
97222cc8 1663 default:
0105d1a5 1664 ret = 1;
97222cc8
ED		 1665 break;
1666 }
0105d1a5
GN		 1667 if (ret)
1668 apic_debug("Local APIC Write to read-only register %x\n", reg);
1669 return ret;
1670}
1e6e2755 1671EXPORT_SYMBOL_GPL(kvm_lapic_reg_write);
0105d1a5 1672
e32edf4f 1673static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this,
0105d1a5
GN		 1674 gpa_t address, int len, const void *data)
1675{
1676 struct kvm_lapic *apic = to_lapic(this);
1677 unsigned int offset = address - apic->base_address;
1678 u32 val;
1679
1680 if (!apic_mmio_in_range(apic, address))
1681 return -EOPNOTSUPP;
1682
1683 /*
1684 * APIC register must be aligned on 128-bits boundary.
1685 * 32/64/128 bits registers must be accessed thru 32 bits.
1686 * Refer SDM 8.4.1
1687 */
1688 if (len != 4 || (offset & 0xf)) {
1689 /* Don't shout loud, $infamous_os would cause only noise. */
1690 apic_debug("apic write: bad size=%d %lx\n", len, (long)address);
756975bb 1691 return 0;
0105d1a5
GN		 1692 }
1693
1694 val = *(u32*)data;
1695
1696 /* too common printing */
1697 if (offset != APIC_EOI)
1698 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
1699 "0x%x\n", __func__, offset, len, val);
1700
1e6e2755 1701 kvm_lapic_reg_write(apic, offset & 0xff0, val);
0105d1a5 1702
bda9020e 1703 return 0;
97222cc8
ED		 1704}
1705
58fbbf26
KT		 1706void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu)
1707{
1e6e2755 1708 kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0);
58fbbf26
KT		 1709}
1710EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi);
1711
83d4c286
YZ		 1712/* emulate APIC access in a trap manner */
1713void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset)
1714{
1715 u32 val = 0;
1716
1717 /* hw has done the conditional check and inst decode */
1718 offset &= 0xff0;
1719
1e6e2755 1720 kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val);
83d4c286
YZ		 1721
1722 /* TODO: optimize to just emulate side effect w/o one more write */
1e6e2755 1723 kvm_lapic_reg_write(vcpu->arch.apic, offset, val);
83d4c286
YZ		 1724}
1725EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode);
1726
d589444e 1727void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 1728{
f8c1ea10
GN		 1729 struct kvm_lapic *apic = vcpu->arch.apic;
1730
ad312c7c 1731 if (!vcpu->arch.apic)
97222cc8
ED		 1732 return;
1733
f8c1ea10 1734 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1735
c5cc421b
GN		 1736 if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE))
1737 static_key_slow_dec_deferred(&apic_hw_disabled);
1738
e462755c 1739 if (!apic->sw_enabled)
f8c1ea10 1740 static_key_slow_dec_deferred(&apic_sw_disabled);
97222cc8 1741
f8c1ea10
GN		 1742 if (apic->regs)
1743 free_page((unsigned long)apic->regs);
1744
1745 kfree(apic);
97222cc8
ED		 1746}
1747
1748/*
1749 *----------------------------------------------------------------------
1750 * LAPIC interface
1751 *----------------------------------------------------------------------
1752 */
498f8162
WL		 1753u64 kvm_get_lapic_target_expiration_tsc(struct kvm_vcpu *vcpu)
1754{
1755 struct kvm_lapic *apic = vcpu->arch.apic;
1756
1757 if (!lapic_in_kernel(vcpu))
1758 return 0;
1759
1760 return apic->lapic_timer.tscdeadline;
1761}
97222cc8 1762
a3e06bbe
LJ		 1763u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu)
1764{
1765 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1766
a10388e1
WL		 1767 if (!lapic_in_kernel(vcpu) ||
1768 !apic_lvtt_tscdeadline(apic))
a3e06bbe
LJ		 1769 return 0;
1770
1771 return apic->lapic_timer.tscdeadline;
1772}
1773
1774void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data)
1775{
1776 struct kvm_lapic *apic = vcpu->arch.apic;
a3e06bbe 1777
bce87cce 1778 if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) ||
54e9818f 1779 apic_lvtt_period(apic))
a3e06bbe
LJ		 1780 return;
1781
1782 hrtimer_cancel(&apic->lapic_timer.timer);
1783 apic->lapic_timer.tscdeadline = data;
1784 start_apic_timer(apic);
1785}
1786
97222cc8
ED		 1787void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
1788{
ad312c7c 1789 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 1790
b93463aa 1791 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
dfb95954 1792 | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 1793}
1794
1795u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
1796{
97222cc8
ED		 1797 u64 tpr;
1798
dfb95954 1799 tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
97222cc8
ED		 1800
1801 return (tpr & 0xf0) >> 4;
1802}
1803
1804void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1805{
8d14695f 1806 u64 old_value = vcpu->arch.apic_base;
ad312c7c 1807 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8 1808
c7dd15b3 1809 if (!apic)
97222cc8 1810 value |= MSR_IA32_APICBASE_BSP;
c5af89b6 1811
e66d2ae7
JK		 1812 vcpu->arch.apic_base = value;
1813
c7dd15b3
JM		 1814 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE)
1815 kvm_update_cpuid(vcpu);
1816
1817 if (!apic)
1818 return;
1819
c5cc421b 1820 /* update jump label if enable bit changes */
0dce7cd6 1821 if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) {
49bd29ba
RK		 1822 if (value & MSR_IA32_APICBASE_ENABLE) {
1823 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
c5cc421b 1824 static_key_slow_dec_deferred(&apic_hw_disabled);
187ca84b 1825 } else {
c5cc421b 1826 static_key_slow_inc(&apic_hw_disabled.key);
187ca84b
WL		 1827 recalculate_apic_map(vcpu->kvm);
1828 }
c5cc421b
GN		 1829 }
1830
8d14695f
YZ		 1831 if ((old_value ^ value) & X2APIC_ENABLE) {
1832 if (value & X2APIC_ENABLE) {
257b9a5f 1833 kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id);
8d14695f
YZ		 1834 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1835 } else
1836 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
0105d1a5 1837 }
8d14695f 1838
ad312c7c 1839 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 1840 MSR_IA32_APICBASE_BASE;
1841
db324fe6
NA		 1842 if ((value & MSR_IA32_APICBASE_ENABLE) &&
1843 apic->base_address != APIC_DEFAULT_PHYS_BASE)
1844 pr_warn_once("APIC base relocation is unsupported by KVM");
1845
97222cc8
ED		 1846 /* with FSB delivery interrupt, we can restart APIC functionality */
1847 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 1848 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1849
1850}
1851
d28bc9dd 1852void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event)
97222cc8
ED		 1853{
1854 struct kvm_lapic *apic;
1855 int i;
1856
b8688d51 1857 apic_debug("%s\n", __func__);
97222cc8
ED		 1858
1859 ASSERT(vcpu);
ad312c7c 1860 apic = vcpu->arch.apic;
97222cc8
ED		 1861 ASSERT(apic != NULL);
1862
1863 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 1864 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8 1865
4d8e772b
RK		 1866 if (!init_event) {
1867 kvm_lapic_set_base(vcpu, APIC_DEFAULT_PHYS_BASE |
1868 MSR_IA32_APICBASE_ENABLE);
a92e2543 1869 kvm_apic_set_xapic_id(apic, vcpu->vcpu_id);
4d8e772b 1870 }
fc61b800 1871 kvm_apic_set_version(apic->vcpu);
97222cc8 1872
1e6e2755
SS		 1873 for (i = 0; i < KVM_APIC_LVT_NUM; i++)
1874 kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
b6ac0695 1875 apic_update_lvtt(apic);
0da029ed 1876 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED))
1e6e2755 1877 kvm_lapic_set_reg(apic, APIC_LVT0,
90de4a18 1878 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
dfb95954 1879 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
97222cc8 1880
1e6e2755 1881 kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU);
f8c1ea10 1882 apic_set_spiv(apic, 0xff);
1e6e2755 1883 kvm_lapic_set_reg(apic, APIC_TASKPRI, 0);
c028dd6b
RK		 1884 if (!apic_x2apic_mode(apic))
1885 kvm_apic_set_ldr(apic, 0);
1e6e2755
SS		 1886 kvm_lapic_set_reg(apic, APIC_ESR, 0);
1887 kvm_lapic_set_reg(apic, APIC_ICR, 0);
1888 kvm_lapic_set_reg(apic, APIC_ICR2, 0);
1889 kvm_lapic_set_reg(apic, APIC_TDCR, 0);
1890 kvm_lapic_set_reg(apic, APIC_TMICT, 0);
97222cc8 1891 for (i = 0; i < 8; i++) {
1e6e2755
SS		 1892 kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
1893 kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
1894 kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
97222cc8 1895 }
d62caabb
AS		 1896 apic->irr_pending = vcpu->arch.apicv_active;
1897 apic->isr_count = vcpu->arch.apicv_active ? 1 : 0;
8680b94b 1898 apic->highest_isr_cache = -1;
b33ac88b 1899 update_divide_count(apic);
d3c7b77d 1900 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 1901 if (kvm_vcpu_is_bsp(vcpu))
5dbc8f3f
GN		 1902 kvm_lapic_set_base(vcpu,
1903 vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP);
ae7a2a3f 1904 vcpu->arch.pv_eoi.msr_val = 0;
97222cc8
ED		 1905 apic_update_ppr(apic);
1906
e1035715 1907 vcpu->arch.apic_arb_prio = 0;
41383771 1908 vcpu->arch.apic_attention = 0;
e1035715 1909
98eff52a 1910 apic_debug("%s: vcpu=%p, id=%d, base_msr="
b8688d51 1911 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 1912 vcpu, kvm_apic_id(apic),
ad312c7c 1913 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 1914}
1915
97222cc8
ED		 1916/*
1917 *----------------------------------------------------------------------
1918 * timer interface
1919 *----------------------------------------------------------------------
1920 */
1b9778da 1921
2a6eac96 1922static bool lapic_is_periodic(struct kvm_lapic *apic)
97222cc8 1923{
d3c7b77d 1924 return apic_lvtt_period(apic);
97222cc8
ED		 1925}
1926
3d80840d
MT		 1927int apic_has_pending_timer(struct kvm_vcpu *vcpu)
1928{
54e9818f 1929 struct kvm_lapic *apic = vcpu->arch.apic;
3d80840d 1930
1e3161b4 1931 if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT))
54e9818f 1932 return atomic_read(&apic->lapic_timer.pending);
3d80840d
MT		 1933
1934 return 0;
1935}
1936
89342082 1937int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 1938{
dfb95954 1939 u32 reg = kvm_lapic_get_reg(apic, lvt_type);
23930f95 1940 int vector, mode, trig_mode;
23930f95 1941
c48f1496 1942 if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 1943 vector = reg & APIC_VECTOR_MASK;
1944 mode = reg & APIC_MODE_MASK;
1945 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
b4f2225c
YZ		 1946 return __apic_accept_irq(apic, mode, vector, 1, trig_mode,
1947 NULL);
23930f95
JK		 1948 }
1949 return 0;
1950}
1b9778da 1951
8fdb2351 1952void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 1953{
8fdb2351
JK		 1954 struct kvm_lapic *apic = vcpu->arch.apic;
1955
1956 if (apic)
1957 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 1958}
1959
d76685c4
GH		 1960static const struct kvm_io_device_ops apic_mmio_ops = {
1961 .read = apic_mmio_read,
1962 .write = apic_mmio_write,
d76685c4
GH		 1963};
1964
e9d90d47
AK		 1965static enum hrtimer_restart apic_timer_fn(struct hrtimer *data)
1966{
1967 struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer);
2a6eac96 1968 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer);
e9d90d47 1969
5d87db71 1970 apic_timer_expired(apic);
e9d90d47 1971
2a6eac96 1972 if (lapic_is_periodic(apic)) {
8003c9ae 1973 advance_periodic_target_expiration(apic);
e9d90d47
AK		 1974 hrtimer_add_expires_ns(&ktimer->timer, ktimer->period);
1975 return HRTIMER_RESTART;
1976 } else
1977 return HRTIMER_NORESTART;
1978}
1979
97222cc8
ED		 1980int kvm_create_lapic(struct kvm_vcpu *vcpu)
1981{
1982 struct kvm_lapic *apic;
1983
1984 ASSERT(vcpu != NULL);
1985 apic_debug("apic_init %d\n", vcpu->vcpu_id);
1986
1987 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
1988 if (!apic)
1989 goto nomem;
1990
ad312c7c 1991 vcpu->arch.apic = apic;
97222cc8 1992
afc20184
TY		 1993 apic->regs = (void *)get_zeroed_page(GFP_KERNEL);
1994 if (!apic->regs) {
97222cc8
ED		 1995 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
1996 vcpu->vcpu_id);
d589444e 1997 goto nomem_free_apic;
97222cc8 1998 }
97222cc8
ED		 1999 apic->vcpu = vcpu;
2000
d3c7b77d 2001 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
61abdbe0 2002 HRTIMER_MODE_ABS_PINNED);
e9d90d47 2003 apic->lapic_timer.timer.function = apic_timer_fn;
d3c7b77d 2004
c5cc421b
GN		 2005 /*
2006 * APIC is created enabled. This will prevent kvm_lapic_set_base from
2007 * thinking that APIC satet has changed.
2008 */
2009 vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE;
f8c1ea10 2010 static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */
d28bc9dd 2011 kvm_lapic_reset(vcpu, false);
d76685c4 2012 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 2013
2014 return 0;
d589444e
RR		 2015nomem_free_apic:
2016 kfree(apic);
97222cc8 2017nomem:
97222cc8
ED		 2018 return -ENOMEM;
2019}
97222cc8
ED		 2020
2021int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
2022{
ad312c7c 2023 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 2024 int highest_irr;
2025
f8543d6a 2026 if (!apic_enabled(apic))
97222cc8
ED		 2027 return -1;
2028
6e5d865c 2029 apic_update_ppr(apic);
97222cc8
ED		 2030 highest_irr = apic_find_highest_irr(apic);
2031 if ((highest_irr == -1) ||
dfb95954 2032 ((highest_irr & 0xF0) <= kvm_lapic_get_reg(apic, APIC_PROCPRI)))
97222cc8
ED		 2033 return -1;
2034 return highest_irr;
2035}
2036
40487c68
QH		 2037int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
2038{
dfb95954 2039 u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 2040 int r = 0;
2041
c48f1496 2042 if (!kvm_apic_hw_enabled(vcpu->arch.apic))
e7dca5c0
CL		 2043 r = 1;
2044 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
2045 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
2046 r = 1;
40487c68
QH		 2047 return r;
2048}
2049
1b9778da
ED		 2050void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
2051{
ad312c7c 2052 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 2053
54e9818f 2054 if (atomic_read(&apic->lapic_timer.pending) > 0) {
f1ed0450 2055 kvm_apic_local_deliver(apic, APIC_LVTT);
fae0ba21
NA		 2056 if (apic_lvtt_tscdeadline(apic))
2057 apic->lapic_timer.tscdeadline = 0;
8003c9ae
WL		 2058 if (apic_lvtt_oneshot(apic)) {
2059 apic->lapic_timer.tscdeadline = 0;
8b0e1953 2060 apic->lapic_timer.target_expiration = 0;
8003c9ae 2061 }
f1ed0450 2062 atomic_set(&apic->lapic_timer.pending, 0);
1b9778da
ED		 2063 }
2064}
2065
97222cc8
ED		 2066int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
2067{
2068 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 2069 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 2070
2071 if (vector == -1)
2072 return -1;
2073
56cc2406
WL		 2074 /*
2075 * We get here even with APIC virtualization enabled, if doing
2076 * nested virtualization and L1 runs with the "acknowledge interrupt
2077 * on exit" mode. Then we cannot inject the interrupt via RVI,
2078 * because the process would deliver it through the IDT.
2079 */
2080
8680b94b 2081 apic_set_isr(vector, apic);
97222cc8
ED		 2082 apic_update_ppr(apic);
2083 apic_clear_irr(vector, apic);
5c919412
AS		 2084
2085 if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) {
2086 apic_clear_isr(vector, apic);
2087 apic_update_ppr(apic);
2088 }
2089
97222cc8
ED		 2090 return vector;
2091}
96ad2cc6 2092
a92e2543
RK		 2093static int kvm_apic_state_fixup(struct kvm_vcpu *vcpu,
2094 struct kvm_lapic_state *s, bool set)
2095{
2096 if (apic_x2apic_mode(vcpu->arch.apic)) {
2097 u32 *id = (u32 *)(s->regs + APIC_ID);
2098
37131313
RK		 2099 if (vcpu->kvm->arch.x2apic_format) {
2100 if (*id != vcpu->vcpu_id)
2101 return -EINVAL;
2102 } else {
2103 if (set)
2104 *id >>= 24;
2105 else
2106 *id <<= 24;
2107 }
a92e2543
RK		 2108 }
2109
2110 return 0;
2111}
2112
2113int kvm_apic_get_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
2114{
2115 memcpy(s->regs, vcpu->arch.apic->regs, sizeof(*s));
2116 return kvm_apic_state_fixup(vcpu, s, false);
2117}
2118
2119int kvm_apic_set_state(struct kvm_vcpu *vcpu, struct kvm_lapic_state *s)
96ad2cc6 2120{
ad312c7c 2121 struct kvm_lapic *apic = vcpu->arch.apic;
a92e2543
RK		 2122 int r;
2123
96ad2cc6 2124
5dbc8f3f 2125 kvm_lapic_set_base(vcpu, vcpu->arch.apic_base);
64eb0620
GN		 2126 /* set SPIV separately to get count of SW disabled APICs right */
2127 apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV)));
a92e2543
RK		 2128
2129 r = kvm_apic_state_fixup(vcpu, s, true);
2130 if (r)
2131 return r;
64eb0620 2132 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
a92e2543
RK		 2133
2134 recalculate_apic_map(vcpu->kvm);
fc61b800
GN		 2135 kvm_apic_set_version(vcpu);
2136
96ad2cc6 2137 apic_update_ppr(apic);
d3c7b77d 2138 hrtimer_cancel(&apic->lapic_timer.timer);
b6ac0695 2139 apic_update_lvtt(apic);
dfb95954 2140 apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0));
96ad2cc6
ED		 2141 update_divide_count(apic);
2142 start_apic_timer(apic);
6e24a6ef 2143 apic->irr_pending = true;
d62caabb 2144 apic->isr_count = vcpu->arch.apicv_active ?
c7c9c56c 2145 1 : count_vectors(apic->regs + APIC_ISR);
8680b94b 2146 apic->highest_isr_cache = -1;
d62caabb 2147 if (vcpu->arch.apicv_active) {
be8ca170
SS		 2148 if (kvm_x86_ops->apicv_post_state_restore)
2149 kvm_x86_ops->apicv_post_state_restore(vcpu);
4114c27d
WW		 2150 kvm_x86_ops->hwapic_irr_update(vcpu,
2151 apic_find_highest_irr(apic));
67c9dddc 2152 kvm_x86_ops->hwapic_isr_update(vcpu,
b4eef9b3 2153 apic_find_highest_isr(apic));
d62caabb 2154 }
3842d135 2155 kvm_make_request(KVM_REQ_EVENT, vcpu);
49df6397
SR		 2156 if (ioapic_in_kernel(vcpu->kvm))
2157 kvm_rtc_eoi_tracking_restore_one(vcpu);
0669a510
RK		 2158
2159 vcpu->arch.apic_arb_prio = 0;
a92e2543
RK		 2160
2161 return 0;
96ad2cc6 2162}
a3d7f85f 2163
2f52d58c 2164void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 2165{
a3d7f85f
ED		 2166 struct hrtimer *timer;
2167
bce87cce 2168 if (!lapic_in_kernel(vcpu))
a3d7f85f
ED		 2169 return;
2170
54e9818f 2171 timer = &vcpu->arch.apic->lapic_timer.timer;
a3d7f85f 2172 if (hrtimer_cancel(timer))
61abdbe0 2173 hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED);
a3d7f85f 2174}
b93463aa 2175
ae7a2a3f
MT		 2176/*
2177 * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt
2178 *
2179 * Detect whether guest triggered PV EOI since the
2180 * last entry. If yes, set EOI on guests's behalf.
2181 * Clear PV EOI in guest memory in any case.
2182 */
2183static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu,
2184 struct kvm_lapic *apic)
2185{
2186 bool pending;
2187 int vector;
2188 /*
2189 * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host
2190 * and KVM_PV_EOI_ENABLED in guest memory as follows:
2191 *
2192 * KVM_APIC_PV_EOI_PENDING is unset:
2193 * -> host disabled PV EOI.
2194 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set:
2195 * -> host enabled PV EOI, guest did not execute EOI yet.
2196 * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset:
2197 * -> host enabled PV EOI, guest executed EOI.
2198 */
2199 BUG_ON(!pv_eoi_enabled(vcpu));
2200 pending = pv_eoi_get_pending(vcpu);
2201 /*
2202 * Clear pending bit in any case: it will be set again on vmentry.
2203 * While this might not be ideal from performance point of view,
2204 * this makes sure pv eoi is only enabled when we know it's safe.
2205 */
2206 pv_eoi_clr_pending(vcpu);
2207 if (pending)
2208 return;
2209 vector = apic_set_eoi(apic);
2210 trace_kvm_pv_eoi(apic, vector);
2211}
2212
b93463aa
AK		 2213void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
2214{
2215 u32 data;
b93463aa 2216
ae7a2a3f
MT		 2217 if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention))
2218 apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic);
2219
41383771 2220 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 2221 return;
2222
603242a8
NK		 2223 if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2224 sizeof(u32)))
2225 return;
b93463aa
AK		 2226
2227 apic_set_tpr(vcpu->arch.apic, data & 0xff);
2228}
2229
ae7a2a3f
MT		 2230/*
2231 * apic_sync_pv_eoi_to_guest - called before vmentry
2232 *
2233 * Detect whether it's safe to enable PV EOI and
2234 * if yes do so.
2235 */
2236static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu,
2237 struct kvm_lapic *apic)
2238{
2239 if (!pv_eoi_enabled(vcpu) ||
2240 /* IRR set or many bits in ISR: could be nested. */
2241 apic->irr_pending ||
2242 /* Cache not set: could be safe but we don't bother. */
2243 apic->highest_isr_cache == -1 ||
2244 /* Need EOI to update ioapic. */
3bb345f3 2245 kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) {
ae7a2a3f
MT		 2246 /*
2247 * PV EOI was disabled by apic_sync_pv_eoi_from_guest
2248 * so we need not do anything here.
2249 */
2250 return;
2251 }
2252
2253 pv_eoi_set_pending(apic->vcpu);
2254}
2255
b93463aa
AK		 2256void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
2257{
2258 u32 data, tpr;
2259 int max_irr, max_isr;
ae7a2a3f 2260 struct kvm_lapic *apic = vcpu->arch.apic;
b93463aa 2261
ae7a2a3f
MT		 2262 apic_sync_pv_eoi_to_guest(vcpu, apic);
2263
41383771 2264 if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention))
b93463aa
AK		 2265 return;
2266
dfb95954 2267 tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff;
b93463aa
AK		 2268 max_irr = apic_find_highest_irr(apic);
2269 if (max_irr < 0)
2270 max_irr = 0;
2271 max_isr = apic_find_highest_isr(apic);
2272 if (max_isr < 0)
2273 max_isr = 0;
2274 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
2275
fda4e2e8
AH		 2276 kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data,
2277 sizeof(u32));
b93463aa
AK		 2278}
2279
fda4e2e8 2280int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
b93463aa 2281{
fda4e2e8
AH		 2282 if (vapic_addr) {
2283 if (kvm_gfn_to_hva_cache_init(vcpu->kvm,
2284 &vcpu->arch.apic->vapic_cache,
2285 vapic_addr, sizeof(u32)))
2286 return -EINVAL;
41383771 2287 __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8 2288 } else {
41383771 2289 __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention);
fda4e2e8
AH		 2290 }
2291
2292 vcpu->arch.apic->vapic_addr = vapic_addr;
2293 return 0;
b93463aa 2294}
0105d1a5
GN		 2295
2296int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data)
2297{
2298 struct kvm_lapic *apic = vcpu->arch.apic;
2299 u32 reg = (msr - APIC_BASE_MSR) << 4;
2300
35754c98 2301 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
0105d1a5
GN		 2302 return 1;
2303
c69d3d9b
NA		 2304 if (reg == APIC_ICR2)
2305 return 1;
2306
0105d1a5 2307 /* if this is ICR write vector before command */
decdc283 2308 if (reg == APIC_ICR)
1e6e2755
SS		 2309 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2310 return kvm_lapic_reg_write(apic, reg, (u32)data);
0105d1a5
GN		 2311}
2312
2313int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data)
2314{
2315 struct kvm_lapic *apic = vcpu->arch.apic;
2316 u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0;
2317
35754c98 2318 if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic))
0105d1a5
GN		 2319 return 1;
2320
c69d3d9b
NA		 2321 if (reg == APIC_DFR || reg == APIC_ICR2) {
2322 apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n",
2323 reg);
2324 return 1;
2325 }
2326
1e6e2755 2327 if (kvm_lapic_reg_read(apic, reg, 4, &low))
0105d1a5 2328 return 1;
decdc283 2329 if (reg == APIC_ICR)
1e6e2755 2330 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
0105d1a5
GN		 2331
2332 *data = (((u64)high) << 32) | low;
2333
2334 return 0;
2335}
10388a07
GN		 2336
2337int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data)
2338{
2339 struct kvm_lapic *apic = vcpu->arch.apic;
2340
bce87cce 2341 if (!lapic_in_kernel(vcpu))
10388a07
GN		 2342 return 1;
2343
2344 /* if this is ICR write vector before command */
2345 if (reg == APIC_ICR)
1e6e2755
SS		 2346 kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32));
2347 return kvm_lapic_reg_write(apic, reg, (u32)data);
10388a07
GN		 2348}
2349
2350int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data)
2351{
2352 struct kvm_lapic *apic = vcpu->arch.apic;
2353 u32 low, high = 0;
2354
bce87cce 2355 if (!lapic_in_kernel(vcpu))
10388a07
GN		 2356 return 1;
2357
1e6e2755 2358 if (kvm_lapic_reg_read(apic, reg, 4, &low))
10388a07
GN		 2359 return 1;
2360 if (reg == APIC_ICR)
1e6e2755 2361 kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high);
10388a07
GN		 2362
2363 *data = (((u64)high) << 32) | low;
2364
2365 return 0;
2366}
ae7a2a3f
MT		 2367
2368int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data)
2369{
2370 u64 addr = data & ~KVM_MSR_ENABLED;
2371 if (!IS_ALIGNED(addr, 4))
2372 return 1;
2373
2374 vcpu->arch.pv_eoi.msr_val = data;
2375 if (!pv_eoi_enabled(vcpu))
2376 return 0;
2377 return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data,
8f964525 2378 addr, sizeof(u8));
ae7a2a3f 2379}
c5cc421b 2380
66450a21
JK		 2381void kvm_apic_accept_events(struct kvm_vcpu *vcpu)
2382{
2383 struct kvm_lapic *apic = vcpu->arch.apic;
2b4a273b 2384 u8 sipi_vector;
299018f4 2385 unsigned long pe;
66450a21 2386
bce87cce 2387 if (!lapic_in_kernel(vcpu) || !apic->pending_events)
66450a21
JK		 2388 return;
2389
cd7764fe
PB		 2390 /*
2391 * INITs are latched while in SMM. Because an SMM CPU cannot
2392 * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs
2393 * and delay processing of INIT until the next RSM.
2394 */
2395 if (is_smm(vcpu)) {
2396 WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED);
2397 if (test_bit(KVM_APIC_SIPI, &apic->pending_events))
2398 clear_bit(KVM_APIC_SIPI, &apic->pending_events);
2399 return;
2400 }
299018f4 2401
cd7764fe 2402 pe = xchg(&apic->pending_events, 0);
299018f4 2403 if (test_bit(KVM_APIC_INIT, &pe)) {
d28bc9dd
NA		 2404 kvm_lapic_reset(vcpu, true);
2405 kvm_vcpu_reset(vcpu, true);
66450a21
JK		 2406 if (kvm_vcpu_is_bsp(apic->vcpu))
2407 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2408 else
2409 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
2410 }
299018f4 2411 if (test_bit(KVM_APIC_SIPI, &pe) &&
66450a21
JK		 2412 vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
2413 /* evaluate pending_events before reading the vector */
2414 smp_rmb();
2415 sipi_vector = apic->sipi_vector;
98eff52a 2416 apic_debug("vcpu %d received sipi with vector # %x\n",
66450a21
JK		 2417 vcpu->vcpu_id, sipi_vector);
2418 kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector);
2419 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
2420 }
2421}
2422
c5cc421b
GN		 2423void kvm_lapic_init(void)
2424{
2425 /* do not patch jump label more than once per second */
2426 jump_label_rate_limit(&apic_hw_disabled, HZ);
f8c1ea10 2427 jump_label_rate_limit(&apic_sw_disabled, HZ);
c5cc421b 2428}
A mirror of Linus' kernel repository