]>
Commit | Line | Data |
---|---|---|
97222cc8 ED |
1 | |
2 | /* | |
3 | * Local APIC virtualization | |
4 | * | |
5 | * Copyright (C) 2006 Qumranet, Inc. | |
6 | * Copyright (C) 2007 Novell | |
7 | * Copyright (C) 2007 Intel | |
9611c187 | 8 | * Copyright 2009 Red Hat, Inc. and/or its affiliates. |
97222cc8 ED |
9 | * |
10 | * Authors: | |
11 | * Dor Laor <dor.laor@qumranet.com> | |
12 | * Gregory Haskins <ghaskins@novell.com> | |
13 | * Yaozu (Eddie) Dong <eddie.dong@intel.com> | |
14 | * | |
15 | * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation. | |
16 | * | |
17 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
18 | * the COPYING file in the top-level directory. | |
19 | */ | |
20 | ||
edf88417 | 21 | #include <linux/kvm_host.h> |
97222cc8 ED |
22 | #include <linux/kvm.h> |
23 | #include <linux/mm.h> | |
24 | #include <linux/highmem.h> | |
25 | #include <linux/smp.h> | |
26 | #include <linux/hrtimer.h> | |
27 | #include <linux/io.h> | |
28 | #include <linux/module.h> | |
6f6d6a1a | 29 | #include <linux/math64.h> |
5a0e3ad6 | 30 | #include <linux/slab.h> |
97222cc8 ED |
31 | #include <asm/processor.h> |
32 | #include <asm/msr.h> | |
33 | #include <asm/page.h> | |
34 | #include <asm/current.h> | |
35 | #include <asm/apicdef.h> | |
d0659d94 | 36 | #include <asm/delay.h> |
60063497 | 37 | #include <linux/atomic.h> |
c5cc421b | 38 | #include <linux/jump_label.h> |
5fdbf976 | 39 | #include "kvm_cache_regs.h" |
97222cc8 | 40 | #include "irq.h" |
229456fc | 41 | #include "trace.h" |
fc61b800 | 42 | #include "x86.h" |
00b27a3e | 43 | #include "cpuid.h" |
5c919412 | 44 | #include "hyperv.h" |
97222cc8 | 45 | |
b682b814 MT |
46 | #ifndef CONFIG_X86_64 |
47 | #define mod_64(x, y) ((x) - (y) * div64_u64(x, y)) | |
48 | #else | |
49 | #define mod_64(x, y) ((x) % (y)) | |
50 | #endif | |
51 | ||
97222cc8 ED |
52 | #define PRId64 "d" |
53 | #define PRIx64 "llx" | |
54 | #define PRIu64 "u" | |
55 | #define PRIo64 "o" | |
56 | ||
57 | #define APIC_BUS_CYCLE_NS 1 | |
58 | ||
59 | /* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */ | |
60 | #define apic_debug(fmt, arg...) | |
61 | ||
97222cc8 | 62 | /* 14 is the version for Xeon and Pentium 8.4.8*/ |
1e6e2755 | 63 | #define APIC_VERSION (0x14UL | ((KVM_APIC_LVT_NUM - 1) << 16)) |
97222cc8 ED |
64 | #define LAPIC_MMIO_LENGTH (1 << 12) |
65 | /* followed define is not in apicdef.h */ | |
66 | #define APIC_SHORT_MASK 0xc0000 | |
67 | #define APIC_DEST_NOSHORT 0x0 | |
68 | #define APIC_DEST_MASK 0x800 | |
69 | #define MAX_APIC_VECTOR 256 | |
ecba9a52 | 70 | #define APIC_VECTORS_PER_REG 32 |
97222cc8 | 71 | |
394457a9 NA |
72 | #define APIC_BROADCAST 0xFF |
73 | #define X2APIC_BROADCAST 0xFFFFFFFFul | |
74 | ||
a0c9a822 MT |
75 | static inline int apic_test_vector(int vec, void *bitmap) |
76 | { | |
77 | return test_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
78 | } | |
79 | ||
10606919 YZ |
80 | bool kvm_apic_pending_eoi(struct kvm_vcpu *vcpu, int vector) |
81 | { | |
82 | struct kvm_lapic *apic = vcpu->arch.apic; | |
83 | ||
84 | return apic_test_vector(vector, apic->regs + APIC_ISR) || | |
85 | apic_test_vector(vector, apic->regs + APIC_IRR); | |
86 | } | |
87 | ||
97222cc8 ED |
88 | static inline void apic_clear_vector(int vec, void *bitmap) |
89 | { | |
90 | clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
91 | } | |
92 | ||
8680b94b MT |
93 | static inline int __apic_test_and_set_vector(int vec, void *bitmap) |
94 | { | |
95 | return __test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
96 | } | |
97 | ||
98 | static inline int __apic_test_and_clear_vector(int vec, void *bitmap) | |
99 | { | |
100 | return __test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec)); | |
101 | } | |
102 | ||
c5cc421b | 103 | struct static_key_deferred apic_hw_disabled __read_mostly; |
f8c1ea10 GN |
104 | struct static_key_deferred apic_sw_disabled __read_mostly; |
105 | ||
97222cc8 ED |
106 | static inline int apic_enabled(struct kvm_lapic *apic) |
107 | { | |
c48f1496 | 108 | return kvm_apic_sw_enabled(apic) && kvm_apic_hw_enabled(apic); |
54e9818f GN |
109 | } |
110 | ||
97222cc8 ED |
111 | #define LVT_MASK \ |
112 | (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK) | |
113 | ||
114 | #define LINT_MASK \ | |
115 | (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \ | |
116 | APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER) | |
117 | ||
e45115b6 RK |
118 | static inline bool kvm_apic_map_get_logical_dest(struct kvm_apic_map *map, |
119 | u32 dest_id, struct kvm_lapic ***cluster, u16 *mask) { | |
120 | switch (map->mode) { | |
121 | case KVM_APIC_MODE_X2APIC: { | |
122 | u32 offset = (dest_id >> 16) * 16; | |
123 | u32 max_apic_id = ARRAY_SIZE(map->phys_map) - 1; | |
124 | ||
125 | if (offset <= max_apic_id) { | |
126 | u8 cluster_size = min(max_apic_id - offset + 1, 16U); | |
127 | ||
128 | *cluster = &map->phys_map[offset]; | |
129 | *mask = dest_id & (0xffff >> (16 - cluster_size)); | |
130 | } else { | |
131 | *mask = 0; | |
132 | } | |
3b5a5ffa | 133 | |
e45115b6 RK |
134 | return true; |
135 | } | |
136 | case KVM_APIC_MODE_XAPIC_FLAT: | |
137 | *cluster = map->xapic_flat_map; | |
138 | *mask = dest_id & 0xff; | |
139 | return true; | |
140 | case KVM_APIC_MODE_XAPIC_CLUSTER: | |
141 | *cluster = map->xapic_cluster_map[dest_id >> 4]; | |
142 | *mask = dest_id & 0xf; | |
143 | return true; | |
144 | default: | |
145 | /* Not optimized. */ | |
146 | return false; | |
147 | } | |
3b5a5ffa RK |
148 | } |
149 | ||
1e08ec4a GN |
150 | static void recalculate_apic_map(struct kvm *kvm) |
151 | { | |
152 | struct kvm_apic_map *new, *old = NULL; | |
153 | struct kvm_vcpu *vcpu; | |
154 | int i; | |
155 | ||
156 | new = kzalloc(sizeof(struct kvm_apic_map), GFP_KERNEL); | |
157 | ||
158 | mutex_lock(&kvm->arch.apic_map_lock); | |
159 | ||
160 | if (!new) | |
161 | goto out; | |
162 | ||
173beedc NA |
163 | kvm_for_each_vcpu(i, vcpu, kvm) { |
164 | struct kvm_lapic *apic = vcpu->arch.apic; | |
e45115b6 RK |
165 | struct kvm_lapic **cluster; |
166 | u16 mask; | |
25995e5b | 167 | u32 ldr, aid; |
1e08ec4a | 168 | |
df04d1d1 RK |
169 | if (!kvm_apic_present(vcpu)) |
170 | continue; | |
171 | ||
25995e5b | 172 | aid = kvm_apic_id(apic); |
dfb95954 | 173 | ldr = kvm_lapic_get_reg(apic, APIC_LDR); |
1e08ec4a | 174 | |
25995e5b RK |
175 | if (aid < ARRAY_SIZE(new->phys_map)) |
176 | new->phys_map[aid] = apic; | |
3548a259 | 177 | |
3b5a5ffa RK |
178 | if (apic_x2apic_mode(apic)) { |
179 | new->mode |= KVM_APIC_MODE_X2APIC; | |
180 | } else if (ldr) { | |
181 | ldr = GET_APIC_LOGICAL_ID(ldr); | |
dfb95954 | 182 | if (kvm_lapic_get_reg(apic, APIC_DFR) == APIC_DFR_FLAT) |
3b5a5ffa RK |
183 | new->mode |= KVM_APIC_MODE_XAPIC_FLAT; |
184 | else | |
185 | new->mode |= KVM_APIC_MODE_XAPIC_CLUSTER; | |
186 | } | |
187 | ||
e45115b6 | 188 | if (!kvm_apic_map_get_logical_dest(new, ldr, &cluster, &mask)) |
3548a259 RK |
189 | continue; |
190 | ||
e45115b6 RK |
191 | if (mask) |
192 | cluster[ffs(mask) - 1] = apic; | |
1e08ec4a GN |
193 | } |
194 | out: | |
195 | old = rcu_dereference_protected(kvm->arch.apic_map, | |
196 | lockdep_is_held(&kvm->arch.apic_map_lock)); | |
197 | rcu_assign_pointer(kvm->arch.apic_map, new); | |
198 | mutex_unlock(&kvm->arch.apic_map_lock); | |
199 | ||
200 | if (old) | |
201 | kfree_rcu(old, rcu); | |
c7c9c56c | 202 | |
b053b2ae | 203 | kvm_make_scan_ioapic_request(kvm); |
1e08ec4a GN |
204 | } |
205 | ||
1e1b6c26 NA |
206 | static inline void apic_set_spiv(struct kvm_lapic *apic, u32 val) |
207 | { | |
e462755c | 208 | bool enabled = val & APIC_SPIV_APIC_ENABLED; |
1e1b6c26 | 209 | |
1e6e2755 | 210 | kvm_lapic_set_reg(apic, APIC_SPIV, val); |
e462755c RK |
211 | |
212 | if (enabled != apic->sw_enabled) { | |
213 | apic->sw_enabled = enabled; | |
214 | if (enabled) { | |
1e1b6c26 NA |
215 | static_key_slow_dec_deferred(&apic_sw_disabled); |
216 | recalculate_apic_map(apic->vcpu->kvm); | |
217 | } else | |
218 | static_key_slow_inc(&apic_sw_disabled.key); | |
219 | } | |
220 | } | |
221 | ||
1e08ec4a GN |
222 | static inline void kvm_apic_set_id(struct kvm_lapic *apic, u8 id) |
223 | { | |
1e6e2755 | 224 | kvm_lapic_set_reg(apic, APIC_ID, id << 24); |
1e08ec4a GN |
225 | recalculate_apic_map(apic->vcpu->kvm); |
226 | } | |
227 | ||
228 | static inline void kvm_apic_set_ldr(struct kvm_lapic *apic, u32 id) | |
229 | { | |
1e6e2755 | 230 | kvm_lapic_set_reg(apic, APIC_LDR, id); |
1e08ec4a GN |
231 | recalculate_apic_map(apic->vcpu->kvm); |
232 | } | |
233 | ||
257b9a5f RK |
234 | static inline void kvm_apic_set_x2apic_id(struct kvm_lapic *apic, u8 id) |
235 | { | |
236 | u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf)); | |
237 | ||
1e6e2755 SS |
238 | kvm_lapic_set_reg(apic, APIC_ID, id << 24); |
239 | kvm_lapic_set_reg(apic, APIC_LDR, ldr); | |
257b9a5f RK |
240 | recalculate_apic_map(apic->vcpu->kvm); |
241 | } | |
242 | ||
97222cc8 ED |
243 | static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type) |
244 | { | |
dfb95954 | 245 | return !(kvm_lapic_get_reg(apic, lvt_type) & APIC_LVT_MASKED); |
97222cc8 ED |
246 | } |
247 | ||
248 | static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type) | |
249 | { | |
dfb95954 | 250 | return kvm_lapic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK; |
97222cc8 ED |
251 | } |
252 | ||
a3e06bbe LJ |
253 | static inline int apic_lvtt_oneshot(struct kvm_lapic *apic) |
254 | { | |
f30ebc31 | 255 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_ONESHOT; |
a3e06bbe LJ |
256 | } |
257 | ||
97222cc8 ED |
258 | static inline int apic_lvtt_period(struct kvm_lapic *apic) |
259 | { | |
f30ebc31 | 260 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_PERIODIC; |
a3e06bbe LJ |
261 | } |
262 | ||
263 | static inline int apic_lvtt_tscdeadline(struct kvm_lapic *apic) | |
264 | { | |
f30ebc31 | 265 | return apic->lapic_timer.timer_mode == APIC_LVT_TIMER_TSCDEADLINE; |
97222cc8 ED |
266 | } |
267 | ||
cc6e462c JK |
268 | static inline int apic_lvt_nmi_mode(u32 lvt_val) |
269 | { | |
270 | return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI; | |
271 | } | |
272 | ||
fc61b800 GN |
273 | void kvm_apic_set_version(struct kvm_vcpu *vcpu) |
274 | { | |
275 | struct kvm_lapic *apic = vcpu->arch.apic; | |
276 | struct kvm_cpuid_entry2 *feat; | |
277 | u32 v = APIC_VERSION; | |
278 | ||
bce87cce | 279 | if (!lapic_in_kernel(vcpu)) |
fc61b800 GN |
280 | return; |
281 | ||
282 | feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0); | |
283 | if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31)))) | |
284 | v |= APIC_LVR_DIRECTED_EOI; | |
1e6e2755 | 285 | kvm_lapic_set_reg(apic, APIC_LVR, v); |
fc61b800 GN |
286 | } |
287 | ||
1e6e2755 | 288 | static const unsigned int apic_lvt_mask[KVM_APIC_LVT_NUM] = { |
a3e06bbe | 289 | LVT_MASK , /* part LVTT mask, timer mode mask added at runtime */ |
97222cc8 ED |
290 | LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */ |
291 | LVT_MASK | APIC_MODE_MASK, /* LVTPC */ | |
292 | LINT_MASK, LINT_MASK, /* LVT0-1 */ | |
293 | LVT_MASK /* LVTERR */ | |
294 | }; | |
295 | ||
296 | static int find_highest_vector(void *bitmap) | |
297 | { | |
ecba9a52 TY |
298 | int vec; |
299 | u32 *reg; | |
97222cc8 | 300 | |
ecba9a52 TY |
301 | for (vec = MAX_APIC_VECTOR - APIC_VECTORS_PER_REG; |
302 | vec >= 0; vec -= APIC_VECTORS_PER_REG) { | |
303 | reg = bitmap + REG_POS(vec); | |
304 | if (*reg) | |
305 | return fls(*reg) - 1 + vec; | |
306 | } | |
97222cc8 | 307 | |
ecba9a52 | 308 | return -1; |
97222cc8 ED |
309 | } |
310 | ||
8680b94b MT |
311 | static u8 count_vectors(void *bitmap) |
312 | { | |
ecba9a52 TY |
313 | int vec; |
314 | u32 *reg; | |
8680b94b | 315 | u8 count = 0; |
ecba9a52 TY |
316 | |
317 | for (vec = 0; vec < MAX_APIC_VECTOR; vec += APIC_VECTORS_PER_REG) { | |
318 | reg = bitmap + REG_POS(vec); | |
319 | count += hweight32(*reg); | |
320 | } | |
321 | ||
8680b94b MT |
322 | return count; |
323 | } | |
324 | ||
705699a1 | 325 | void __kvm_apic_update_irr(u32 *pir, void *regs) |
a20ed54d YZ |
326 | { |
327 | u32 i, pir_val; | |
a20ed54d YZ |
328 | |
329 | for (i = 0; i <= 7; i++) { | |
330 | pir_val = xchg(&pir[i], 0); | |
331 | if (pir_val) | |
705699a1 | 332 | *((u32 *)(regs + APIC_IRR + i * 0x10)) |= pir_val; |
a20ed54d YZ |
333 | } |
334 | } | |
705699a1 WV |
335 | EXPORT_SYMBOL_GPL(__kvm_apic_update_irr); |
336 | ||
337 | void kvm_apic_update_irr(struct kvm_vcpu *vcpu, u32 *pir) | |
338 | { | |
339 | struct kvm_lapic *apic = vcpu->arch.apic; | |
340 | ||
341 | __kvm_apic_update_irr(pir, apic->regs); | |
c77f3fab RK |
342 | |
343 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
705699a1 | 344 | } |
a20ed54d YZ |
345 | EXPORT_SYMBOL_GPL(kvm_apic_update_irr); |
346 | ||
33e4c686 | 347 | static inline int apic_search_irr(struct kvm_lapic *apic) |
97222cc8 | 348 | { |
33e4c686 | 349 | return find_highest_vector(apic->regs + APIC_IRR); |
97222cc8 ED |
350 | } |
351 | ||
352 | static inline int apic_find_highest_irr(struct kvm_lapic *apic) | |
353 | { | |
354 | int result; | |
355 | ||
c7c9c56c YZ |
356 | /* |
357 | * Note that irr_pending is just a hint. It will be always | |
358 | * true with virtual interrupt delivery enabled. | |
359 | */ | |
33e4c686 GN |
360 | if (!apic->irr_pending) |
361 | return -1; | |
362 | ||
d62caabb AS |
363 | if (apic->vcpu->arch.apicv_active) |
364 | kvm_x86_ops->sync_pir_to_irr(apic->vcpu); | |
33e4c686 | 365 | result = apic_search_irr(apic); |
97222cc8 ED |
366 | ASSERT(result == -1 || result >= 16); |
367 | ||
368 | return result; | |
369 | } | |
370 | ||
33e4c686 GN |
371 | static inline void apic_clear_irr(int vec, struct kvm_lapic *apic) |
372 | { | |
56cc2406 WL |
373 | struct kvm_vcpu *vcpu; |
374 | ||
375 | vcpu = apic->vcpu; | |
376 | ||
d62caabb | 377 | if (unlikely(vcpu->arch.apicv_active)) { |
56cc2406 | 378 | /* try to update RVI */ |
f210f757 | 379 | apic_clear_vector(vec, apic->regs + APIC_IRR); |
56cc2406 | 380 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
f210f757 NA |
381 | } else { |
382 | apic->irr_pending = false; | |
383 | apic_clear_vector(vec, apic->regs + APIC_IRR); | |
384 | if (apic_search_irr(apic) != -1) | |
385 | apic->irr_pending = true; | |
56cc2406 | 386 | } |
33e4c686 GN |
387 | } |
388 | ||
8680b94b MT |
389 | static inline void apic_set_isr(int vec, struct kvm_lapic *apic) |
390 | { | |
56cc2406 WL |
391 | struct kvm_vcpu *vcpu; |
392 | ||
393 | if (__apic_test_and_set_vector(vec, apic->regs + APIC_ISR)) | |
394 | return; | |
395 | ||
396 | vcpu = apic->vcpu; | |
fc57ac2c | 397 | |
8680b94b | 398 | /* |
56cc2406 WL |
399 | * With APIC virtualization enabled, all caching is disabled |
400 | * because the processor can modify ISR under the hood. Instead | |
401 | * just set SVI. | |
8680b94b | 402 | */ |
d62caabb | 403 | if (unlikely(vcpu->arch.apicv_active)) |
67c9dddc | 404 | kvm_x86_ops->hwapic_isr_update(vcpu, vec); |
56cc2406 WL |
405 | else { |
406 | ++apic->isr_count; | |
407 | BUG_ON(apic->isr_count > MAX_APIC_VECTOR); | |
408 | /* | |
409 | * ISR (in service register) bit is set when injecting an interrupt. | |
410 | * The highest vector is injected. Thus the latest bit set matches | |
411 | * the highest bit in ISR. | |
412 | */ | |
413 | apic->highest_isr_cache = vec; | |
414 | } | |
8680b94b MT |
415 | } |
416 | ||
fc57ac2c PB |
417 | static inline int apic_find_highest_isr(struct kvm_lapic *apic) |
418 | { | |
419 | int result; | |
420 | ||
421 | /* | |
422 | * Note that isr_count is always 1, and highest_isr_cache | |
423 | * is always -1, with APIC virtualization enabled. | |
424 | */ | |
425 | if (!apic->isr_count) | |
426 | return -1; | |
427 | if (likely(apic->highest_isr_cache != -1)) | |
428 | return apic->highest_isr_cache; | |
429 | ||
430 | result = find_highest_vector(apic->regs + APIC_ISR); | |
431 | ASSERT(result == -1 || result >= 16); | |
432 | ||
433 | return result; | |
434 | } | |
435 | ||
8680b94b MT |
436 | static inline void apic_clear_isr(int vec, struct kvm_lapic *apic) |
437 | { | |
fc57ac2c PB |
438 | struct kvm_vcpu *vcpu; |
439 | if (!__apic_test_and_clear_vector(vec, apic->regs + APIC_ISR)) | |
440 | return; | |
441 | ||
442 | vcpu = apic->vcpu; | |
443 | ||
444 | /* | |
445 | * We do get here for APIC virtualization enabled if the guest | |
446 | * uses the Hyper-V APIC enlightenment. In this case we may need | |
447 | * to trigger a new interrupt delivery by writing the SVI field; | |
448 | * on the other hand isr_count and highest_isr_cache are unused | |
449 | * and must be left alone. | |
450 | */ | |
d62caabb | 451 | if (unlikely(vcpu->arch.apicv_active)) |
67c9dddc | 452 | kvm_x86_ops->hwapic_isr_update(vcpu, |
fc57ac2c PB |
453 | apic_find_highest_isr(apic)); |
454 | else { | |
8680b94b | 455 | --apic->isr_count; |
fc57ac2c PB |
456 | BUG_ON(apic->isr_count < 0); |
457 | apic->highest_isr_cache = -1; | |
458 | } | |
8680b94b MT |
459 | } |
460 | ||
6e5d865c YS |
461 | int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu) |
462 | { | |
33e4c686 GN |
463 | /* This may race with setting of irr in __apic_accept_irq() and |
464 | * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq | |
465 | * will cause vmexit immediately and the value will be recalculated | |
466 | * on the next vmentry. | |
467 | */ | |
f8543d6a | 468 | return apic_find_highest_irr(vcpu->arch.apic); |
6e5d865c | 469 | } |
6e5d865c | 470 | |
6da7e3f6 | 471 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, |
b4f2225c | 472 | int vector, int level, int trig_mode, |
9e4aabe2 | 473 | struct dest_map *dest_map); |
6da7e3f6 | 474 | |
b4f2225c | 475 | int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq, |
9e4aabe2 | 476 | struct dest_map *dest_map) |
97222cc8 | 477 | { |
ad312c7c | 478 | struct kvm_lapic *apic = vcpu->arch.apic; |
8be5453f | 479 | |
58c2dde1 | 480 | return __apic_accept_irq(apic, irq->delivery_mode, irq->vector, |
b4f2225c | 481 | irq->level, irq->trig_mode, dest_map); |
97222cc8 ED |
482 | } |
483 | ||
ae7a2a3f MT |
484 | static int pv_eoi_put_user(struct kvm_vcpu *vcpu, u8 val) |
485 | { | |
486 | ||
487 | return kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, &val, | |
488 | sizeof(val)); | |
489 | } | |
490 | ||
491 | static int pv_eoi_get_user(struct kvm_vcpu *vcpu, u8 *val) | |
492 | { | |
493 | ||
494 | return kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.pv_eoi.data, val, | |
495 | sizeof(*val)); | |
496 | } | |
497 | ||
498 | static inline bool pv_eoi_enabled(struct kvm_vcpu *vcpu) | |
499 | { | |
500 | return vcpu->arch.pv_eoi.msr_val & KVM_MSR_ENABLED; | |
501 | } | |
502 | ||
503 | static bool pv_eoi_get_pending(struct kvm_vcpu *vcpu) | |
504 | { | |
505 | u8 val; | |
506 | if (pv_eoi_get_user(vcpu, &val) < 0) | |
507 | apic_debug("Can't read EOI MSR value: 0x%llx\n", | |
96893977 | 508 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
509 | return val & 0x1; |
510 | } | |
511 | ||
512 | static void pv_eoi_set_pending(struct kvm_vcpu *vcpu) | |
513 | { | |
514 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_ENABLED) < 0) { | |
515 | apic_debug("Can't set EOI MSR value: 0x%llx\n", | |
96893977 | 516 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
517 | return; |
518 | } | |
519 | __set_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
520 | } | |
521 | ||
522 | static void pv_eoi_clr_pending(struct kvm_vcpu *vcpu) | |
523 | { | |
524 | if (pv_eoi_put_user(vcpu, KVM_PV_EOI_DISABLED) < 0) { | |
525 | apic_debug("Can't clear EOI MSR value: 0x%llx\n", | |
96893977 | 526 | (unsigned long long)vcpu->arch.pv_eoi.msr_val); |
ae7a2a3f MT |
527 | return; |
528 | } | |
529 | __clear_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention); | |
530 | } | |
531 | ||
97222cc8 ED |
532 | static void apic_update_ppr(struct kvm_lapic *apic) |
533 | { | |
3842d135 | 534 | u32 tpr, isrv, ppr, old_ppr; |
97222cc8 ED |
535 | int isr; |
536 | ||
dfb95954 SS |
537 | old_ppr = kvm_lapic_get_reg(apic, APIC_PROCPRI); |
538 | tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI); | |
97222cc8 ED |
539 | isr = apic_find_highest_isr(apic); |
540 | isrv = (isr != -1) ? isr : 0; | |
541 | ||
542 | if ((tpr & 0xf0) >= (isrv & 0xf0)) | |
543 | ppr = tpr & 0xff; | |
544 | else | |
545 | ppr = isrv & 0xf0; | |
546 | ||
547 | apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x", | |
548 | apic, ppr, isr, isrv); | |
549 | ||
3842d135 | 550 | if (old_ppr != ppr) { |
1e6e2755 | 551 | kvm_lapic_set_reg(apic, APIC_PROCPRI, ppr); |
83bcacb1 AK |
552 | if (ppr < old_ppr) |
553 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
3842d135 | 554 | } |
97222cc8 ED |
555 | } |
556 | ||
557 | static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr) | |
558 | { | |
1e6e2755 | 559 | kvm_lapic_set_reg(apic, APIC_TASKPRI, tpr); |
97222cc8 ED |
560 | apic_update_ppr(apic); |
561 | } | |
562 | ||
03d2249e | 563 | static bool kvm_apic_broadcast(struct kvm_lapic *apic, u32 mda) |
394457a9 | 564 | { |
03d2249e RK |
565 | if (apic_x2apic_mode(apic)) |
566 | return mda == X2APIC_BROADCAST; | |
567 | ||
568 | return GET_APIC_DEST_FIELD(mda) == APIC_BROADCAST; | |
394457a9 NA |
569 | } |
570 | ||
03d2249e | 571 | static bool kvm_apic_match_physical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 572 | { |
03d2249e RK |
573 | if (kvm_apic_broadcast(apic, mda)) |
574 | return true; | |
575 | ||
576 | if (apic_x2apic_mode(apic)) | |
577 | return mda == kvm_apic_id(apic); | |
578 | ||
579 | return mda == SET_APIC_DEST_FIELD(kvm_apic_id(apic)); | |
97222cc8 ED |
580 | } |
581 | ||
52c233a4 | 582 | static bool kvm_apic_match_logical_addr(struct kvm_lapic *apic, u32 mda) |
97222cc8 | 583 | { |
0105d1a5 GN |
584 | u32 logical_id; |
585 | ||
394457a9 | 586 | if (kvm_apic_broadcast(apic, mda)) |
9368b567 | 587 | return true; |
394457a9 | 588 | |
dfb95954 | 589 | logical_id = kvm_lapic_get_reg(apic, APIC_LDR); |
97222cc8 | 590 | |
9368b567 | 591 | if (apic_x2apic_mode(apic)) |
8a395363 RK |
592 | return ((logical_id >> 16) == (mda >> 16)) |
593 | && (logical_id & mda & 0xffff) != 0; | |
97222cc8 | 594 | |
9368b567 | 595 | logical_id = GET_APIC_LOGICAL_ID(logical_id); |
03d2249e | 596 | mda = GET_APIC_DEST_FIELD(mda); |
97222cc8 | 597 | |
dfb95954 | 598 | switch (kvm_lapic_get_reg(apic, APIC_DFR)) { |
97222cc8 | 599 | case APIC_DFR_FLAT: |
9368b567 | 600 | return (logical_id & mda) != 0; |
97222cc8 | 601 | case APIC_DFR_CLUSTER: |
9368b567 RK |
602 | return ((logical_id >> 4) == (mda >> 4)) |
603 | && (logical_id & mda & 0xf) != 0; | |
97222cc8 | 604 | default: |
7712de87 | 605 | apic_debug("Bad DFR vcpu %d: %08x\n", |
dfb95954 | 606 | apic->vcpu->vcpu_id, kvm_lapic_get_reg(apic, APIC_DFR)); |
9368b567 | 607 | return false; |
97222cc8 | 608 | } |
97222cc8 ED |
609 | } |
610 | ||
03d2249e RK |
611 | /* KVM APIC implementation has two quirks |
612 | * - dest always begins at 0 while xAPIC MDA has offset 24, | |
613 | * - IOxAPIC messages have to be delivered (directly) to x2APIC. | |
614 | */ | |
615 | static u32 kvm_apic_mda(unsigned int dest_id, struct kvm_lapic *source, | |
616 | struct kvm_lapic *target) | |
617 | { | |
618 | bool ipi = source != NULL; | |
619 | bool x2apic_mda = apic_x2apic_mode(ipi ? source : target); | |
620 | ||
621 | if (!ipi && dest_id == APIC_BROADCAST && x2apic_mda) | |
622 | return X2APIC_BROADCAST; | |
623 | ||
624 | return x2apic_mda ? dest_id : SET_APIC_DEST_FIELD(dest_id); | |
625 | } | |
626 | ||
52c233a4 | 627 | bool kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source, |
394457a9 | 628 | int short_hand, unsigned int dest, int dest_mode) |
97222cc8 | 629 | { |
ad312c7c | 630 | struct kvm_lapic *target = vcpu->arch.apic; |
03d2249e | 631 | u32 mda = kvm_apic_mda(dest, source, target); |
97222cc8 ED |
632 | |
633 | apic_debug("target %p, source %p, dest 0x%x, " | |
343f94fe | 634 | "dest_mode 0x%x, short_hand 0x%x\n", |
97222cc8 ED |
635 | target, source, dest, dest_mode, short_hand); |
636 | ||
bd371396 | 637 | ASSERT(target); |
97222cc8 ED |
638 | switch (short_hand) { |
639 | case APIC_DEST_NOSHORT: | |
3697f302 | 640 | if (dest_mode == APIC_DEST_PHYSICAL) |
03d2249e | 641 | return kvm_apic_match_physical_addr(target, mda); |
343f94fe | 642 | else |
03d2249e | 643 | return kvm_apic_match_logical_addr(target, mda); |
97222cc8 | 644 | case APIC_DEST_SELF: |
9368b567 | 645 | return target == source; |
97222cc8 | 646 | case APIC_DEST_ALLINC: |
9368b567 | 647 | return true; |
97222cc8 | 648 | case APIC_DEST_ALLBUT: |
9368b567 | 649 | return target != source; |
97222cc8 | 650 | default: |
7712de87 JK |
651 | apic_debug("kvm: apic: Bad dest shorthand value %x\n", |
652 | short_hand); | |
9368b567 | 653 | return false; |
97222cc8 | 654 | } |
97222cc8 | 655 | } |
1e6e2755 | 656 | EXPORT_SYMBOL_GPL(kvm_apic_match_dest); |
97222cc8 | 657 | |
52004014 FW |
658 | int kvm_vector_to_index(u32 vector, u32 dest_vcpus, |
659 | const unsigned long *bitmap, u32 bitmap_size) | |
660 | { | |
661 | u32 mod; | |
662 | int i, idx = -1; | |
663 | ||
664 | mod = vector % dest_vcpus; | |
665 | ||
666 | for (i = 0; i <= mod; i++) { | |
667 | idx = find_next_bit(bitmap, bitmap_size, idx + 1); | |
668 | BUG_ON(idx == bitmap_size); | |
669 | } | |
670 | ||
671 | return idx; | |
672 | } | |
673 | ||
4efd805f RK |
674 | static void kvm_apic_disabled_lapic_found(struct kvm *kvm) |
675 | { | |
676 | if (!kvm->arch.disabled_lapic_found) { | |
677 | kvm->arch.disabled_lapic_found = true; | |
678 | printk(KERN_INFO | |
679 | "Disabled LAPIC found during irq injection\n"); | |
680 | } | |
681 | } | |
682 | ||
64aa47bf RK |
683 | /* Return true if the interrupt can be handled by using *bitmap as index mask |
684 | * for valid destinations in *dst array. | |
685 | * Return false if kvm_apic_map_get_dest_lapic did nothing useful. | |
686 | * Note: we may have zero kvm_lapic destinations when we return true, which | |
687 | * means that the interrupt should be dropped. In this case, *bitmap would be | |
688 | * zero and *dst undefined. | |
689 | */ | |
690 | static inline bool kvm_apic_map_get_dest_lapic(struct kvm *kvm, | |
691 | struct kvm_lapic **src, struct kvm_lapic_irq *irq, | |
692 | struct kvm_apic_map *map, struct kvm_lapic ***dst, | |
693 | unsigned long *bitmap) | |
694 | { | |
695 | int i, lowest; | |
696 | bool x2apic_ipi; | |
64aa47bf RK |
697 | |
698 | if (irq->shorthand == APIC_DEST_SELF && src) { | |
699 | *dst = src; | |
700 | *bitmap = 1; | |
701 | return true; | |
702 | } else if (irq->shorthand) | |
703 | return false; | |
1e08ec4a | 704 | |
64aa47bf RK |
705 | x2apic_ipi = src && *src && apic_x2apic_mode(*src); |
706 | if (irq->dest_id == (x2apic_ipi ? X2APIC_BROADCAST : APIC_BROADCAST)) | |
707 | return false; | |
1e08ec4a | 708 | |
64aa47bf RK |
709 | if (!map) |
710 | return false; | |
711 | ||
712 | if (irq->dest_mode == APIC_DEST_PHYSICAL) { | |
713 | if (irq->dest_id >= ARRAY_SIZE(map->phys_map)) { | |
714 | *bitmap = 0; | |
715 | } else { | |
716 | *dst = &map->phys_map[irq->dest_id]; | |
717 | *bitmap = 1; | |
718 | } | |
1e08ec4a GN |
719 | return true; |
720 | } | |
721 | ||
e45115b6 RK |
722 | *bitmap = 0; |
723 | if (!kvm_apic_map_get_logical_dest(map, irq->dest_id, dst, | |
724 | (u16 *)bitmap)) | |
1e08ec4a GN |
725 | return false; |
726 | ||
64aa47bf RK |
727 | if (!kvm_lowest_prio_delivery(irq)) |
728 | return true; | |
3548a259 | 729 | |
64aa47bf RK |
730 | if (!kvm_vector_hashing_enabled()) { |
731 | lowest = -1; | |
732 | for_each_set_bit(i, bitmap, 16) { | |
733 | if (!(*dst)[i]) | |
734 | continue; | |
735 | if (lowest < 0) | |
736 | lowest = i; | |
737 | else if (kvm_apic_compare_prio((*dst)[i]->vcpu, | |
738 | (*dst)[lowest]->vcpu) < 0) | |
739 | lowest = i; | |
3548a259 | 740 | } |
64aa47bf RK |
741 | } else { |
742 | if (!*bitmap) | |
743 | return true; | |
3548a259 | 744 | |
64aa47bf RK |
745 | lowest = kvm_vector_to_index(irq->vector, hweight16(*bitmap), |
746 | bitmap, 16); | |
45c3094a | 747 | |
64aa47bf RK |
748 | if (!(*dst)[lowest]) { |
749 | kvm_apic_disabled_lapic_found(kvm); | |
750 | *bitmap = 0; | |
751 | return true; | |
752 | } | |
753 | } | |
1e08ec4a | 754 | |
64aa47bf | 755 | *bitmap = (lowest >= 0) ? 1 << lowest : 0; |
1e08ec4a | 756 | |
64aa47bf RK |
757 | return true; |
758 | } | |
52004014 | 759 | |
64aa47bf RK |
760 | bool kvm_irq_delivery_to_apic_fast(struct kvm *kvm, struct kvm_lapic *src, |
761 | struct kvm_lapic_irq *irq, int *r, struct dest_map *dest_map) | |
762 | { | |
763 | struct kvm_apic_map *map; | |
764 | unsigned long bitmap; | |
765 | struct kvm_lapic **dst = NULL; | |
766 | int i; | |
767 | bool ret; | |
52004014 | 768 | |
64aa47bf | 769 | *r = -1; |
52004014 | 770 | |
64aa47bf RK |
771 | if (irq->shorthand == APIC_DEST_SELF) { |
772 | *r = kvm_apic_set_irq(src->vcpu, irq, dest_map); | |
773 | return true; | |
774 | } | |
52004014 | 775 | |
64aa47bf RK |
776 | rcu_read_lock(); |
777 | map = rcu_dereference(kvm->arch.apic_map); | |
52004014 | 778 | |
64aa47bf RK |
779 | ret = kvm_apic_map_get_dest_lapic(kvm, &src, irq, map, &dst, &bitmap); |
780 | if (ret) | |
781 | for_each_set_bit(i, &bitmap, 16) { | |
782 | if (!dst[i]) | |
783 | continue; | |
784 | if (*r < 0) | |
785 | *r = 0; | |
786 | *r += kvm_apic_set_irq(dst[i]->vcpu, irq, dest_map); | |
1e08ec4a | 787 | } |
1e08ec4a | 788 | |
1e08ec4a GN |
789 | rcu_read_unlock(); |
790 | return ret; | |
791 | } | |
792 | ||
6228a0da FW |
793 | /* |
794 | * This routine tries to handler interrupts in posted mode, here is how | |
795 | * it deals with different cases: | |
796 | * - For single-destination interrupts, handle it in posted mode | |
797 | * - Else if vector hashing is enabled and it is a lowest-priority | |
798 | * interrupt, handle it in posted mode and use the following mechanism | |
799 | * to find the destinaiton vCPU. | |
800 | * 1. For lowest-priority interrupts, store all the possible | |
801 | * destination vCPUs in an array. | |
802 | * 2. Use "guest vector % max number of destination vCPUs" to find | |
803 | * the right destination vCPU in the array for the lowest-priority | |
804 | * interrupt. | |
805 | * - Otherwise, use remapped mode to inject the interrupt. | |
806 | */ | |
8feb4a04 FW |
807 | bool kvm_intr_is_single_vcpu_fast(struct kvm *kvm, struct kvm_lapic_irq *irq, |
808 | struct kvm_vcpu **dest_vcpu) | |
809 | { | |
810 | struct kvm_apic_map *map; | |
64aa47bf RK |
811 | unsigned long bitmap; |
812 | struct kvm_lapic **dst = NULL; | |
8feb4a04 | 813 | bool ret = false; |
8feb4a04 FW |
814 | |
815 | if (irq->shorthand) | |
816 | return false; | |
817 | ||
818 | rcu_read_lock(); | |
819 | map = rcu_dereference(kvm->arch.apic_map); | |
820 | ||
64aa47bf RK |
821 | if (kvm_apic_map_get_dest_lapic(kvm, NULL, irq, map, &dst, &bitmap) && |
822 | hweight16(bitmap) == 1) { | |
823 | unsigned long i = find_first_bit(&bitmap, 16); | |
8feb4a04 | 824 | |
64aa47bf RK |
825 | if (dst[i]) { |
826 | *dest_vcpu = dst[i]->vcpu; | |
827 | ret = true; | |
6228a0da | 828 | } |
8feb4a04 FW |
829 | } |
830 | ||
8feb4a04 FW |
831 | rcu_read_unlock(); |
832 | return ret; | |
833 | } | |
834 | ||
97222cc8 ED |
835 | /* |
836 | * Add a pending IRQ into lapic. | |
837 | * Return 1 if successfully added and 0 if discarded. | |
838 | */ | |
839 | static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode, | |
b4f2225c | 840 | int vector, int level, int trig_mode, |
9e4aabe2 | 841 | struct dest_map *dest_map) |
97222cc8 | 842 | { |
6da7e3f6 | 843 | int result = 0; |
c5ec1534 | 844 | struct kvm_vcpu *vcpu = apic->vcpu; |
97222cc8 | 845 | |
a183b638 PB |
846 | trace_kvm_apic_accept_irq(vcpu->vcpu_id, delivery_mode, |
847 | trig_mode, vector); | |
97222cc8 | 848 | switch (delivery_mode) { |
97222cc8 | 849 | case APIC_DM_LOWEST: |
e1035715 GN |
850 | vcpu->arch.apic_arb_prio++; |
851 | case APIC_DM_FIXED: | |
bdaffe1d PB |
852 | if (unlikely(trig_mode && !level)) |
853 | break; | |
854 | ||
97222cc8 ED |
855 | /* FIXME add logic for vcpu on reset */ |
856 | if (unlikely(!apic_enabled(apic))) | |
857 | break; | |
858 | ||
11f5cc05 JK |
859 | result = 1; |
860 | ||
9daa5007 | 861 | if (dest_map) { |
9e4aabe2 | 862 | __set_bit(vcpu->vcpu_id, dest_map->map); |
9daa5007 JR |
863 | dest_map->vectors[vcpu->vcpu_id] = vector; |
864 | } | |
a5d36f82 | 865 | |
bdaffe1d PB |
866 | if (apic_test_vector(vector, apic->regs + APIC_TMR) != !!trig_mode) { |
867 | if (trig_mode) | |
1e6e2755 | 868 | kvm_lapic_set_vector(vector, apic->regs + APIC_TMR); |
bdaffe1d PB |
869 | else |
870 | apic_clear_vector(vector, apic->regs + APIC_TMR); | |
871 | } | |
872 | ||
d62caabb | 873 | if (vcpu->arch.apicv_active) |
5a71785d | 874 | kvm_x86_ops->deliver_posted_interrupt(vcpu, vector); |
11f5cc05 | 875 | else { |
1e6e2755 | 876 | kvm_lapic_set_irr(vector, apic); |
5a71785d YZ |
877 | |
878 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
879 | kvm_vcpu_kick(vcpu); | |
880 | } | |
97222cc8 ED |
881 | break; |
882 | ||
883 | case APIC_DM_REMRD: | |
24d2166b R |
884 | result = 1; |
885 | vcpu->arch.pv.pv_unhalted = 1; | |
886 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
887 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
888 | break; |
889 | ||
890 | case APIC_DM_SMI: | |
64d60670 PB |
891 | result = 1; |
892 | kvm_make_request(KVM_REQ_SMI, vcpu); | |
893 | kvm_vcpu_kick(vcpu); | |
97222cc8 | 894 | break; |
3419ffc8 | 895 | |
97222cc8 | 896 | case APIC_DM_NMI: |
6da7e3f6 | 897 | result = 1; |
3419ffc8 | 898 | kvm_inject_nmi(vcpu); |
26df99c6 | 899 | kvm_vcpu_kick(vcpu); |
97222cc8 ED |
900 | break; |
901 | ||
902 | case APIC_DM_INIT: | |
a52315e1 | 903 | if (!trig_mode || level) { |
6da7e3f6 | 904 | result = 1; |
66450a21 JK |
905 | /* assumes that there are only KVM_APIC_INIT/SIPI */ |
906 | apic->pending_events = (1UL << KVM_APIC_INIT); | |
907 | /* make sure pending_events is visible before sending | |
908 | * the request */ | |
909 | smp_wmb(); | |
3842d135 | 910 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
c5ec1534 HQ |
911 | kvm_vcpu_kick(vcpu); |
912 | } else { | |
1b10bf31 JK |
913 | apic_debug("Ignoring de-assert INIT to vcpu %d\n", |
914 | vcpu->vcpu_id); | |
c5ec1534 | 915 | } |
97222cc8 ED |
916 | break; |
917 | ||
918 | case APIC_DM_STARTUP: | |
1b10bf31 JK |
919 | apic_debug("SIPI to vcpu %d vector 0x%02x\n", |
920 | vcpu->vcpu_id, vector); | |
66450a21 JK |
921 | result = 1; |
922 | apic->sipi_vector = vector; | |
923 | /* make sure sipi_vector is visible for the receiver */ | |
924 | smp_wmb(); | |
925 | set_bit(KVM_APIC_SIPI, &apic->pending_events); | |
926 | kvm_make_request(KVM_REQ_EVENT, vcpu); | |
927 | kvm_vcpu_kick(vcpu); | |
97222cc8 ED |
928 | break; |
929 | ||
23930f95 JK |
930 | case APIC_DM_EXTINT: |
931 | /* | |
932 | * Should only be called by kvm_apic_local_deliver() with LVT0, | |
933 | * before NMI watchdog was enabled. Already handled by | |
934 | * kvm_apic_accept_pic_intr(). | |
935 | */ | |
936 | break; | |
937 | ||
97222cc8 ED |
938 | default: |
939 | printk(KERN_ERR "TODO: unsupported delivery mode %x\n", | |
940 | delivery_mode); | |
941 | break; | |
942 | } | |
943 | return result; | |
944 | } | |
945 | ||
e1035715 | 946 | int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2) |
8be5453f | 947 | { |
e1035715 | 948 | return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio; |
8be5453f ZX |
949 | } |
950 | ||
3bb345f3 PB |
951 | static bool kvm_ioapic_handles_vector(struct kvm_lapic *apic, int vector) |
952 | { | |
6308630b | 953 | return test_bit(vector, apic->vcpu->arch.ioapic_handled_vectors); |
3bb345f3 PB |
954 | } |
955 | ||
c7c9c56c YZ |
956 | static void kvm_ioapic_send_eoi(struct kvm_lapic *apic, int vector) |
957 | { | |
7543a635 SR |
958 | int trigger_mode; |
959 | ||
960 | /* Eoi the ioapic only if the ioapic doesn't own the vector. */ | |
961 | if (!kvm_ioapic_handles_vector(apic, vector)) | |
962 | return; | |
3bb345f3 | 963 | |
7543a635 SR |
964 | /* Request a KVM exit to inform the userspace IOAPIC. */ |
965 | if (irqchip_split(apic->vcpu->kvm)) { | |
966 | apic->vcpu->arch.pending_ioapic_eoi = vector; | |
967 | kvm_make_request(KVM_REQ_IOAPIC_EOI_EXIT, apic->vcpu); | |
968 | return; | |
c7c9c56c | 969 | } |
7543a635 SR |
970 | |
971 | if (apic_test_vector(vector, apic->regs + APIC_TMR)) | |
972 | trigger_mode = IOAPIC_LEVEL_TRIG; | |
973 | else | |
974 | trigger_mode = IOAPIC_EDGE_TRIG; | |
975 | ||
976 | kvm_ioapic_update_eoi(apic->vcpu, vector, trigger_mode); | |
c7c9c56c YZ |
977 | } |
978 | ||
ae7a2a3f | 979 | static int apic_set_eoi(struct kvm_lapic *apic) |
97222cc8 ED |
980 | { |
981 | int vector = apic_find_highest_isr(apic); | |
ae7a2a3f MT |
982 | |
983 | trace_kvm_eoi(apic, vector); | |
984 | ||
97222cc8 ED |
985 | /* |
986 | * Not every write EOI will has corresponding ISR, | |
987 | * one example is when Kernel check timer on setup_IO_APIC | |
988 | */ | |
989 | if (vector == -1) | |
ae7a2a3f | 990 | return vector; |
97222cc8 | 991 | |
8680b94b | 992 | apic_clear_isr(vector, apic); |
97222cc8 ED |
993 | apic_update_ppr(apic); |
994 | ||
5c919412 AS |
995 | if (test_bit(vector, vcpu_to_synic(apic->vcpu)->vec_bitmap)) |
996 | kvm_hv_synic_send_eoi(apic->vcpu, vector); | |
997 | ||
c7c9c56c | 998 | kvm_ioapic_send_eoi(apic, vector); |
3842d135 | 999 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); |
ae7a2a3f | 1000 | return vector; |
97222cc8 ED |
1001 | } |
1002 | ||
c7c9c56c YZ |
1003 | /* |
1004 | * this interface assumes a trap-like exit, which has already finished | |
1005 | * desired side effect including vISR and vPPR update. | |
1006 | */ | |
1007 | void kvm_apic_set_eoi_accelerated(struct kvm_vcpu *vcpu, int vector) | |
1008 | { | |
1009 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1010 | ||
1011 | trace_kvm_eoi(apic, vector); | |
1012 | ||
1013 | kvm_ioapic_send_eoi(apic, vector); | |
1014 | kvm_make_request(KVM_REQ_EVENT, apic->vcpu); | |
1015 | } | |
1016 | EXPORT_SYMBOL_GPL(kvm_apic_set_eoi_accelerated); | |
1017 | ||
97222cc8 ED |
1018 | static void apic_send_ipi(struct kvm_lapic *apic) |
1019 | { | |
dfb95954 SS |
1020 | u32 icr_low = kvm_lapic_get_reg(apic, APIC_ICR); |
1021 | u32 icr_high = kvm_lapic_get_reg(apic, APIC_ICR2); | |
58c2dde1 | 1022 | struct kvm_lapic_irq irq; |
97222cc8 | 1023 | |
58c2dde1 GN |
1024 | irq.vector = icr_low & APIC_VECTOR_MASK; |
1025 | irq.delivery_mode = icr_low & APIC_MODE_MASK; | |
1026 | irq.dest_mode = icr_low & APIC_DEST_MASK; | |
b7cb2231 | 1027 | irq.level = (icr_low & APIC_INT_ASSERT) != 0; |
58c2dde1 GN |
1028 | irq.trig_mode = icr_low & APIC_INT_LEVELTRIG; |
1029 | irq.shorthand = icr_low & APIC_SHORT_MASK; | |
93bbf0b8 | 1030 | irq.msi_redir_hint = false; |
0105d1a5 GN |
1031 | if (apic_x2apic_mode(apic)) |
1032 | irq.dest_id = icr_high; | |
1033 | else | |
1034 | irq.dest_id = GET_APIC_DEST_FIELD(icr_high); | |
97222cc8 | 1035 | |
1000ff8d GN |
1036 | trace_kvm_apic_ipi(icr_low, irq.dest_id); |
1037 | ||
97222cc8 ED |
1038 | apic_debug("icr_high 0x%x, icr_low 0x%x, " |
1039 | "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, " | |
93bbf0b8 JS |
1040 | "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x, " |
1041 | "msi_redir_hint 0x%x\n", | |
9b5843dd | 1042 | icr_high, icr_low, irq.shorthand, irq.dest_id, |
58c2dde1 | 1043 | irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode, |
93bbf0b8 | 1044 | irq.vector, irq.msi_redir_hint); |
58c2dde1 | 1045 | |
b4f2225c | 1046 | kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq, NULL); |
97222cc8 ED |
1047 | } |
1048 | ||
1049 | static u32 apic_get_tmcct(struct kvm_lapic *apic) | |
1050 | { | |
b682b814 MT |
1051 | ktime_t remaining; |
1052 | s64 ns; | |
9da8f4e8 | 1053 | u32 tmcct; |
97222cc8 ED |
1054 | |
1055 | ASSERT(apic != NULL); | |
1056 | ||
9da8f4e8 | 1057 | /* if initial count is 0, current count should also be 0 */ |
dfb95954 | 1058 | if (kvm_lapic_get_reg(apic, APIC_TMICT) == 0 || |
b963a22e | 1059 | apic->lapic_timer.period == 0) |
9da8f4e8 KP |
1060 | return 0; |
1061 | ||
ace15464 | 1062 | remaining = hrtimer_get_remaining(&apic->lapic_timer.timer); |
b682b814 MT |
1063 | if (ktime_to_ns(remaining) < 0) |
1064 | remaining = ktime_set(0, 0); | |
1065 | ||
d3c7b77d MT |
1066 | ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period); |
1067 | tmcct = div64_u64(ns, | |
1068 | (APIC_BUS_CYCLE_NS * apic->divide_count)); | |
97222cc8 ED |
1069 | |
1070 | return tmcct; | |
1071 | } | |
1072 | ||
b209749f AK |
1073 | static void __report_tpr_access(struct kvm_lapic *apic, bool write) |
1074 | { | |
1075 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1076 | struct kvm_run *run = vcpu->run; | |
1077 | ||
a8eeb04a | 1078 | kvm_make_request(KVM_REQ_REPORT_TPR_ACCESS, vcpu); |
5fdbf976 | 1079 | run->tpr_access.rip = kvm_rip_read(vcpu); |
b209749f AK |
1080 | run->tpr_access.is_write = write; |
1081 | } | |
1082 | ||
1083 | static inline void report_tpr_access(struct kvm_lapic *apic, bool write) | |
1084 | { | |
1085 | if (apic->vcpu->arch.tpr_access_reporting) | |
1086 | __report_tpr_access(apic, write); | |
1087 | } | |
1088 | ||
97222cc8 ED |
1089 | static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset) |
1090 | { | |
1091 | u32 val = 0; | |
1092 | ||
1093 | if (offset >= LAPIC_MMIO_LENGTH) | |
1094 | return 0; | |
1095 | ||
1096 | switch (offset) { | |
0105d1a5 GN |
1097 | case APIC_ID: |
1098 | if (apic_x2apic_mode(apic)) | |
1099 | val = kvm_apic_id(apic); | |
1100 | else | |
1101 | val = kvm_apic_id(apic) << 24; | |
1102 | break; | |
97222cc8 | 1103 | case APIC_ARBPRI: |
7712de87 | 1104 | apic_debug("Access APIC ARBPRI register which is for P6\n"); |
97222cc8 ED |
1105 | break; |
1106 | ||
1107 | case APIC_TMCCT: /* Timer CCR */ | |
a3e06bbe LJ |
1108 | if (apic_lvtt_tscdeadline(apic)) |
1109 | return 0; | |
1110 | ||
97222cc8 ED |
1111 | val = apic_get_tmcct(apic); |
1112 | break; | |
4a4541a4 AK |
1113 | case APIC_PROCPRI: |
1114 | apic_update_ppr(apic); | |
dfb95954 | 1115 | val = kvm_lapic_get_reg(apic, offset); |
4a4541a4 | 1116 | break; |
b209749f AK |
1117 | case APIC_TASKPRI: |
1118 | report_tpr_access(apic, false); | |
1119 | /* fall thru */ | |
97222cc8 | 1120 | default: |
dfb95954 | 1121 | val = kvm_lapic_get_reg(apic, offset); |
97222cc8 ED |
1122 | break; |
1123 | } | |
1124 | ||
1125 | return val; | |
1126 | } | |
1127 | ||
d76685c4 GH |
1128 | static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev) |
1129 | { | |
1130 | return container_of(dev, struct kvm_lapic, dev); | |
1131 | } | |
1132 | ||
1e6e2755 | 1133 | int kvm_lapic_reg_read(struct kvm_lapic *apic, u32 offset, int len, |
0105d1a5 | 1134 | void *data) |
97222cc8 | 1135 | { |
97222cc8 ED |
1136 | unsigned char alignment = offset & 0xf; |
1137 | u32 result; | |
d5b0b5b1 | 1138 | /* this bitmask has a bit cleared for each reserved register */ |
0105d1a5 | 1139 | static const u64 rmask = 0x43ff01ffffffe70cULL; |
97222cc8 ED |
1140 | |
1141 | if ((alignment + len) > 4) { | |
4088bb3c GN |
1142 | apic_debug("KVM_APIC_READ: alignment error %x %d\n", |
1143 | offset, len); | |
0105d1a5 | 1144 | return 1; |
97222cc8 | 1145 | } |
0105d1a5 GN |
1146 | |
1147 | if (offset > 0x3f0 || !(rmask & (1ULL << (offset >> 4)))) { | |
4088bb3c GN |
1148 | apic_debug("KVM_APIC_READ: read reserved register %x\n", |
1149 | offset); | |
0105d1a5 GN |
1150 | return 1; |
1151 | } | |
1152 | ||
97222cc8 ED |
1153 | result = __apic_read(apic, offset & ~0xf); |
1154 | ||
229456fc MT |
1155 | trace_kvm_apic_read(offset, result); |
1156 | ||
97222cc8 ED |
1157 | switch (len) { |
1158 | case 1: | |
1159 | case 2: | |
1160 | case 4: | |
1161 | memcpy(data, (char *)&result + alignment, len); | |
1162 | break; | |
1163 | default: | |
1164 | printk(KERN_ERR "Local APIC read with len = %x, " | |
1165 | "should be 1,2, or 4 instead\n", len); | |
1166 | break; | |
1167 | } | |
bda9020e | 1168 | return 0; |
97222cc8 | 1169 | } |
1e6e2755 | 1170 | EXPORT_SYMBOL_GPL(kvm_lapic_reg_read); |
97222cc8 | 1171 | |
0105d1a5 GN |
1172 | static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr) |
1173 | { | |
c48f1496 | 1174 | return kvm_apic_hw_enabled(apic) && |
0105d1a5 GN |
1175 | addr >= apic->base_address && |
1176 | addr < apic->base_address + LAPIC_MMIO_LENGTH; | |
1177 | } | |
1178 | ||
e32edf4f | 1179 | static int apic_mmio_read(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1180 | gpa_t address, int len, void *data) |
1181 | { | |
1182 | struct kvm_lapic *apic = to_lapic(this); | |
1183 | u32 offset = address - apic->base_address; | |
1184 | ||
1185 | if (!apic_mmio_in_range(apic, address)) | |
1186 | return -EOPNOTSUPP; | |
1187 | ||
1e6e2755 | 1188 | kvm_lapic_reg_read(apic, offset, len, data); |
0105d1a5 GN |
1189 | |
1190 | return 0; | |
1191 | } | |
1192 | ||
97222cc8 ED |
1193 | static void update_divide_count(struct kvm_lapic *apic) |
1194 | { | |
1195 | u32 tmp1, tmp2, tdcr; | |
1196 | ||
dfb95954 | 1197 | tdcr = kvm_lapic_get_reg(apic, APIC_TDCR); |
97222cc8 ED |
1198 | tmp1 = tdcr & 0xf; |
1199 | tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1; | |
d3c7b77d | 1200 | apic->divide_count = 0x1 << (tmp2 & 0x7); |
97222cc8 ED |
1201 | |
1202 | apic_debug("timer divide count is 0x%x\n", | |
9b5843dd | 1203 | apic->divide_count); |
97222cc8 ED |
1204 | } |
1205 | ||
b6ac0695 RK |
1206 | static void apic_update_lvtt(struct kvm_lapic *apic) |
1207 | { | |
dfb95954 | 1208 | u32 timer_mode = kvm_lapic_get_reg(apic, APIC_LVTT) & |
b6ac0695 RK |
1209 | apic->lapic_timer.timer_mode_mask; |
1210 | ||
1211 | if (apic->lapic_timer.timer_mode != timer_mode) { | |
1212 | apic->lapic_timer.timer_mode = timer_mode; | |
1213 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1214 | } | |
1215 | } | |
1216 | ||
5d87db71 RK |
1217 | static void apic_timer_expired(struct kvm_lapic *apic) |
1218 | { | |
1219 | struct kvm_vcpu *vcpu = apic->vcpu; | |
8577370f | 1220 | struct swait_queue_head *q = &vcpu->wq; |
d0659d94 | 1221 | struct kvm_timer *ktimer = &apic->lapic_timer; |
5d87db71 | 1222 | |
5d87db71 RK |
1223 | if (atomic_read(&apic->lapic_timer.pending)) |
1224 | return; | |
1225 | ||
1226 | atomic_inc(&apic->lapic_timer.pending); | |
bab5bb39 | 1227 | kvm_set_pending_timer(vcpu); |
5d87db71 | 1228 | |
8577370f MT |
1229 | if (swait_active(q)) |
1230 | swake_up(q); | |
d0659d94 MT |
1231 | |
1232 | if (apic_lvtt_tscdeadline(apic)) | |
1233 | ktimer->expired_tscdeadline = ktimer->tscdeadline; | |
1234 | } | |
1235 | ||
1236 | /* | |
1237 | * On APICv, this test will cause a busy wait | |
1238 | * during a higher-priority task. | |
1239 | */ | |
1240 | ||
1241 | static bool lapic_timer_int_injected(struct kvm_vcpu *vcpu) | |
1242 | { | |
1243 | struct kvm_lapic *apic = vcpu->arch.apic; | |
dfb95954 | 1244 | u32 reg = kvm_lapic_get_reg(apic, APIC_LVTT); |
d0659d94 MT |
1245 | |
1246 | if (kvm_apic_hw_enabled(apic)) { | |
1247 | int vec = reg & APIC_VECTOR_MASK; | |
f9339860 | 1248 | void *bitmap = apic->regs + APIC_ISR; |
d0659d94 | 1249 | |
d62caabb | 1250 | if (vcpu->arch.apicv_active) |
f9339860 MT |
1251 | bitmap = apic->regs + APIC_IRR; |
1252 | ||
1253 | if (apic_test_vector(vec, bitmap)) | |
1254 | return true; | |
d0659d94 MT |
1255 | } |
1256 | return false; | |
1257 | } | |
1258 | ||
1259 | void wait_lapic_expire(struct kvm_vcpu *vcpu) | |
1260 | { | |
1261 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1262 | u64 guest_tsc, tsc_deadline; | |
1263 | ||
bce87cce | 1264 | if (!lapic_in_kernel(vcpu)) |
d0659d94 MT |
1265 | return; |
1266 | ||
1267 | if (apic->lapic_timer.expired_tscdeadline == 0) | |
1268 | return; | |
1269 | ||
1270 | if (!lapic_timer_int_injected(vcpu)) | |
1271 | return; | |
1272 | ||
1273 | tsc_deadline = apic->lapic_timer.expired_tscdeadline; | |
1274 | apic->lapic_timer.expired_tscdeadline = 0; | |
4ba76538 | 1275 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); |
6c19b753 | 1276 | trace_kvm_wait_lapic_expire(vcpu->vcpu_id, guest_tsc - tsc_deadline); |
d0659d94 MT |
1277 | |
1278 | /* __delay is delay_tsc whenever the hardware has TSC, thus always. */ | |
1279 | if (guest_tsc < tsc_deadline) | |
1280 | __delay(tsc_deadline - guest_tsc); | |
5d87db71 RK |
1281 | } |
1282 | ||
53f9eedf YJ |
1283 | static void start_sw_tscdeadline(struct kvm_lapic *apic) |
1284 | { | |
1285 | u64 guest_tsc, tscdeadline = apic->lapic_timer.tscdeadline; | |
1286 | u64 ns = 0; | |
1287 | ktime_t expire; | |
1288 | struct kvm_vcpu *vcpu = apic->vcpu; | |
1289 | unsigned long this_tsc_khz = vcpu->arch.virtual_tsc_khz; | |
1290 | unsigned long flags; | |
1291 | ktime_t now; | |
1292 | ||
1293 | if (unlikely(!tscdeadline || !this_tsc_khz)) | |
1294 | return; | |
1295 | ||
1296 | local_irq_save(flags); | |
1297 | ||
1298 | now = apic->lapic_timer.timer.base->get_time(); | |
1299 | guest_tsc = kvm_read_l1_tsc(vcpu, rdtsc()); | |
1300 | if (likely(tscdeadline > guest_tsc)) { | |
1301 | ns = (tscdeadline - guest_tsc) * 1000000ULL; | |
1302 | do_div(ns, this_tsc_khz); | |
1303 | expire = ktime_add_ns(now, ns); | |
1304 | expire = ktime_sub_ns(expire, lapic_timer_advance_ns); | |
1305 | hrtimer_start(&apic->lapic_timer.timer, | |
1306 | expire, HRTIMER_MODE_ABS_PINNED); | |
1307 | } else | |
1308 | apic_timer_expired(apic); | |
1309 | ||
1310 | local_irq_restore(flags); | |
1311 | } | |
1312 | ||
ce7a058a YJ |
1313 | bool kvm_lapic_hv_timer_in_use(struct kvm_vcpu *vcpu) |
1314 | { | |
1315 | return vcpu->arch.apic->lapic_timer.hv_timer_in_use; | |
1316 | } | |
1317 | EXPORT_SYMBOL_GPL(kvm_lapic_hv_timer_in_use); | |
1318 | ||
bd97ad0e WL |
1319 | static void cancel_hv_tscdeadline(struct kvm_lapic *apic) |
1320 | { | |
1321 | kvm_x86_ops->cancel_hv_timer(apic->vcpu); | |
1322 | apic->lapic_timer.hv_timer_in_use = false; | |
1323 | } | |
1324 | ||
ce7a058a YJ |
1325 | void kvm_lapic_expired_hv_timer(struct kvm_vcpu *vcpu) |
1326 | { | |
1327 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1328 | ||
1329 | WARN_ON(!apic->lapic_timer.hv_timer_in_use); | |
1330 | WARN_ON(swait_active(&vcpu->wq)); | |
bd97ad0e | 1331 | cancel_hv_tscdeadline(apic); |
ce7a058a YJ |
1332 | apic_timer_expired(apic); |
1333 | } | |
1334 | EXPORT_SYMBOL_GPL(kvm_lapic_expired_hv_timer); | |
1335 | ||
196f20ca WL |
1336 | static bool start_hv_tscdeadline(struct kvm_lapic *apic) |
1337 | { | |
1338 | u64 tscdeadline = apic->lapic_timer.tscdeadline; | |
1339 | ||
1340 | if (atomic_read(&apic->lapic_timer.pending) || | |
1341 | kvm_x86_ops->set_hv_timer(apic->vcpu, tscdeadline)) { | |
1342 | if (apic->lapic_timer.hv_timer_in_use) | |
1343 | cancel_hv_tscdeadline(apic); | |
1344 | } else { | |
1345 | apic->lapic_timer.hv_timer_in_use = true; | |
1346 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1347 | ||
1348 | /* In case the sw timer triggered in the window */ | |
1349 | if (atomic_read(&apic->lapic_timer.pending)) | |
1350 | cancel_hv_tscdeadline(apic); | |
1351 | } | |
1352 | trace_kvm_hv_timer_state(apic->vcpu->vcpu_id, | |
1353 | apic->lapic_timer.hv_timer_in_use); | |
1354 | return apic->lapic_timer.hv_timer_in_use; | |
1355 | } | |
1356 | ||
ce7a058a YJ |
1357 | void kvm_lapic_switch_to_hv_timer(struct kvm_vcpu *vcpu) |
1358 | { | |
1359 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1360 | ||
1361 | WARN_ON(apic->lapic_timer.hv_timer_in_use); | |
1362 | ||
196f20ca WL |
1363 | if (apic_lvtt_tscdeadline(apic)) |
1364 | start_hv_tscdeadline(apic); | |
ce7a058a YJ |
1365 | } |
1366 | EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_hv_timer); | |
1367 | ||
1368 | void kvm_lapic_switch_to_sw_timer(struct kvm_vcpu *vcpu) | |
1369 | { | |
1370 | struct kvm_lapic *apic = vcpu->arch.apic; | |
1371 | ||
1372 | /* Possibly the TSC deadline timer is not enabled yet */ | |
1373 | if (!apic->lapic_timer.hv_timer_in_use) | |
1374 | return; | |
1375 | ||
bd97ad0e | 1376 | cancel_hv_tscdeadline(apic); |
ce7a058a YJ |
1377 | |
1378 | if (atomic_read(&apic->lapic_timer.pending)) | |
1379 | return; | |
1380 | ||
1381 | start_sw_tscdeadline(apic); | |
1382 | } | |
1383 | EXPORT_SYMBOL_GPL(kvm_lapic_switch_to_sw_timer); | |
1384 | ||
97222cc8 ED |
1385 | static void start_apic_timer(struct kvm_lapic *apic) |
1386 | { | |
a3e06bbe | 1387 | ktime_t now; |
d0659d94 | 1388 | |
d3c7b77d | 1389 | atomic_set(&apic->lapic_timer.pending, 0); |
0b975a3c | 1390 | |
a3e06bbe | 1391 | if (apic_lvtt_period(apic) || apic_lvtt_oneshot(apic)) { |
d5b0b5b1 | 1392 | /* lapic timer in oneshot or periodic mode */ |
a3e06bbe | 1393 | now = apic->lapic_timer.timer.base->get_time(); |
dfb95954 | 1394 | apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) |
a3e06bbe LJ |
1395 | * APIC_BUS_CYCLE_NS * apic->divide_count; |
1396 | ||
1397 | if (!apic->lapic_timer.period) | |
1398 | return; | |
1399 | /* | |
1400 | * Do not allow the guest to program periodic timers with small | |
1401 | * interval, since the hrtimers are not throttled by the host | |
1402 | * scheduler. | |
1403 | */ | |
1404 | if (apic_lvtt_period(apic)) { | |
1405 | s64 min_period = min_timer_period_us * 1000LL; | |
1406 | ||
1407 | if (apic->lapic_timer.period < min_period) { | |
1408 | pr_info_ratelimited( | |
1409 | "kvm: vcpu %i: requested %lld ns " | |
1410 | "lapic timer period limited to %lld ns\n", | |
1411 | apic->vcpu->vcpu_id, | |
1412 | apic->lapic_timer.period, min_period); | |
1413 | apic->lapic_timer.period = min_period; | |
1414 | } | |
9bc5791d | 1415 | } |
0b975a3c | 1416 | |
a3e06bbe LJ |
1417 | hrtimer_start(&apic->lapic_timer.timer, |
1418 | ktime_add_ns(now, apic->lapic_timer.period), | |
61abdbe0 | 1419 | HRTIMER_MODE_ABS_PINNED); |
97222cc8 | 1420 | |
a3e06bbe | 1421 | apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016" |
97222cc8 ED |
1422 | PRIx64 ", " |
1423 | "timer initial count 0x%x, period %lldns, " | |
b8688d51 | 1424 | "expire @ 0x%016" PRIx64 ".\n", __func__, |
97222cc8 | 1425 | APIC_BUS_CYCLE_NS, ktime_to_ns(now), |
dfb95954 | 1426 | kvm_lapic_get_reg(apic, APIC_TMICT), |
d3c7b77d | 1427 | apic->lapic_timer.period, |
97222cc8 | 1428 | ktime_to_ns(ktime_add_ns(now, |
d3c7b77d | 1429 | apic->lapic_timer.period))); |
a3e06bbe | 1430 | } else if (apic_lvtt_tscdeadline(apic)) { |
196f20ca | 1431 | if (!(kvm_x86_ops->set_hv_timer && start_hv_tscdeadline(apic))) |
ce7a058a | 1432 | start_sw_tscdeadline(apic); |
a3e06bbe | 1433 | } |
97222cc8 ED |
1434 | } |
1435 | ||
cc6e462c JK |
1436 | static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val) |
1437 | { | |
59fd1323 | 1438 | bool lvt0_in_nmi_mode = apic_lvt_nmi_mode(lvt0_val); |
cc6e462c | 1439 | |
59fd1323 RK |
1440 | if (apic->lvt0_in_nmi_mode != lvt0_in_nmi_mode) { |
1441 | apic->lvt0_in_nmi_mode = lvt0_in_nmi_mode; | |
1442 | if (lvt0_in_nmi_mode) { | |
cc6e462c JK |
1443 | apic_debug("Receive NMI setting on APIC_LVT0 " |
1444 | "for cpu %d\n", apic->vcpu->vcpu_id); | |
42720138 | 1445 | atomic_inc(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); |
59fd1323 RK |
1446 | } else |
1447 | atomic_dec(&apic->vcpu->kvm->arch.vapics_in_nmi_mode); | |
1448 | } | |
cc6e462c JK |
1449 | } |
1450 | ||
1e6e2755 | 1451 | int kvm_lapic_reg_write(struct kvm_lapic *apic, u32 reg, u32 val) |
97222cc8 | 1452 | { |
0105d1a5 | 1453 | int ret = 0; |
97222cc8 | 1454 | |
0105d1a5 | 1455 | trace_kvm_apic_write(reg, val); |
97222cc8 | 1456 | |
0105d1a5 | 1457 | switch (reg) { |
97222cc8 | 1458 | case APIC_ID: /* Local APIC ID */ |
0105d1a5 | 1459 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1460 | kvm_apic_set_id(apic, val >> 24); |
0105d1a5 GN |
1461 | else |
1462 | ret = 1; | |
97222cc8 ED |
1463 | break; |
1464 | ||
1465 | case APIC_TASKPRI: | |
b209749f | 1466 | report_tpr_access(apic, true); |
97222cc8 ED |
1467 | apic_set_tpr(apic, val & 0xff); |
1468 | break; | |
1469 | ||
1470 | case APIC_EOI: | |
1471 | apic_set_eoi(apic); | |
1472 | break; | |
1473 | ||
1474 | case APIC_LDR: | |
0105d1a5 | 1475 | if (!apic_x2apic_mode(apic)) |
1e08ec4a | 1476 | kvm_apic_set_ldr(apic, val & APIC_LDR_MASK); |
0105d1a5 GN |
1477 | else |
1478 | ret = 1; | |
97222cc8 ED |
1479 | break; |
1480 | ||
1481 | case APIC_DFR: | |
1e08ec4a | 1482 | if (!apic_x2apic_mode(apic)) { |
1e6e2755 | 1483 | kvm_lapic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF); |
1e08ec4a GN |
1484 | recalculate_apic_map(apic->vcpu->kvm); |
1485 | } else | |
0105d1a5 | 1486 | ret = 1; |
97222cc8 ED |
1487 | break; |
1488 | ||
fc61b800 GN |
1489 | case APIC_SPIV: { |
1490 | u32 mask = 0x3ff; | |
dfb95954 | 1491 | if (kvm_lapic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI) |
fc61b800 | 1492 | mask |= APIC_SPIV_DIRECTED_EOI; |
f8c1ea10 | 1493 | apic_set_spiv(apic, val & mask); |
97222cc8 ED |
1494 | if (!(val & APIC_SPIV_APIC_ENABLED)) { |
1495 | int i; | |
1496 | u32 lvt_val; | |
1497 | ||
1e6e2755 | 1498 | for (i = 0; i < KVM_APIC_LVT_NUM; i++) { |
dfb95954 | 1499 | lvt_val = kvm_lapic_get_reg(apic, |
97222cc8 | 1500 | APIC_LVTT + 0x10 * i); |
1e6e2755 | 1501 | kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, |
97222cc8 ED |
1502 | lvt_val | APIC_LVT_MASKED); |
1503 | } | |
b6ac0695 | 1504 | apic_update_lvtt(apic); |
d3c7b77d | 1505 | atomic_set(&apic->lapic_timer.pending, 0); |
97222cc8 ED |
1506 | |
1507 | } | |
1508 | break; | |
fc61b800 | 1509 | } |
97222cc8 ED |
1510 | case APIC_ICR: |
1511 | /* No delay here, so we always clear the pending bit */ | |
1e6e2755 | 1512 | kvm_lapic_set_reg(apic, APIC_ICR, val & ~(1 << 12)); |
97222cc8 ED |
1513 | apic_send_ipi(apic); |
1514 | break; | |
1515 | ||
1516 | case APIC_ICR2: | |
0105d1a5 GN |
1517 | if (!apic_x2apic_mode(apic)) |
1518 | val &= 0xff000000; | |
1e6e2755 | 1519 | kvm_lapic_set_reg(apic, APIC_ICR2, val); |
97222cc8 ED |
1520 | break; |
1521 | ||
23930f95 | 1522 | case APIC_LVT0: |
cc6e462c | 1523 | apic_manage_nmi_watchdog(apic, val); |
97222cc8 ED |
1524 | case APIC_LVTTHMR: |
1525 | case APIC_LVTPC: | |
97222cc8 ED |
1526 | case APIC_LVT1: |
1527 | case APIC_LVTERR: | |
1528 | /* TODO: Check vector */ | |
c48f1496 | 1529 | if (!kvm_apic_sw_enabled(apic)) |
97222cc8 ED |
1530 | val |= APIC_LVT_MASKED; |
1531 | ||
0105d1a5 | 1532 | val &= apic_lvt_mask[(reg - APIC_LVTT) >> 4]; |
1e6e2755 | 1533 | kvm_lapic_set_reg(apic, reg, val); |
97222cc8 ED |
1534 | |
1535 | break; | |
1536 | ||
b6ac0695 | 1537 | case APIC_LVTT: |
c48f1496 | 1538 | if (!kvm_apic_sw_enabled(apic)) |
a3e06bbe LJ |
1539 | val |= APIC_LVT_MASKED; |
1540 | val &= (apic_lvt_mask[0] | apic->lapic_timer.timer_mode_mask); | |
1e6e2755 | 1541 | kvm_lapic_set_reg(apic, APIC_LVTT, val); |
b6ac0695 | 1542 | apic_update_lvtt(apic); |
a3e06bbe LJ |
1543 | break; |
1544 | ||
97222cc8 | 1545 | case APIC_TMICT: |
a3e06bbe LJ |
1546 | if (apic_lvtt_tscdeadline(apic)) |
1547 | break; | |
1548 | ||
d3c7b77d | 1549 | hrtimer_cancel(&apic->lapic_timer.timer); |
1e6e2755 | 1550 | kvm_lapic_set_reg(apic, APIC_TMICT, val); |
97222cc8 | 1551 | start_apic_timer(apic); |
0105d1a5 | 1552 | break; |
97222cc8 ED |
1553 | |
1554 | case APIC_TDCR: | |
1555 | if (val & 4) | |
7712de87 | 1556 | apic_debug("KVM_WRITE:TDCR %x\n", val); |
1e6e2755 | 1557 | kvm_lapic_set_reg(apic, APIC_TDCR, val); |
97222cc8 ED |
1558 | update_divide_count(apic); |
1559 | break; | |
1560 | ||
0105d1a5 GN |
1561 | case APIC_ESR: |
1562 | if (apic_x2apic_mode(apic) && val != 0) { | |
7712de87 | 1563 | apic_debug("KVM_WRITE:ESR not zero %x\n", val); |
0105d1a5 GN |
1564 | ret = 1; |
1565 | } | |
1566 | break; | |
1567 | ||
1568 | case APIC_SELF_IPI: | |
1569 | if (apic_x2apic_mode(apic)) { | |
1e6e2755 | 1570 | kvm_lapic_reg_write(apic, APIC_ICR, 0x40000 | (val & 0xff)); |
0105d1a5 GN |
1571 | } else |
1572 | ret = 1; | |
1573 | break; | |
97222cc8 | 1574 | default: |
0105d1a5 | 1575 | ret = 1; |
97222cc8 ED |
1576 | break; |
1577 | } | |
0105d1a5 GN |
1578 | if (ret) |
1579 | apic_debug("Local APIC Write to read-only register %x\n", reg); | |
1580 | return ret; | |
1581 | } | |
1e6e2755 | 1582 | EXPORT_SYMBOL_GPL(kvm_lapic_reg_write); |
0105d1a5 | 1583 | |
e32edf4f | 1584 | static int apic_mmio_write(struct kvm_vcpu *vcpu, struct kvm_io_device *this, |
0105d1a5 GN |
1585 | gpa_t address, int len, const void *data) |
1586 | { | |
1587 | struct kvm_lapic *apic = to_lapic(this); | |
1588 | unsigned int offset = address - apic->base_address; | |
1589 | u32 val; | |
1590 | ||
1591 | if (!apic_mmio_in_range(apic, address)) | |
1592 | return -EOPNOTSUPP; | |
1593 | ||
1594 | /* | |
1595 | * APIC register must be aligned on 128-bits boundary. | |
1596 | * 32/64/128 bits registers must be accessed thru 32 bits. | |
1597 | * Refer SDM 8.4.1 | |
1598 | */ | |
1599 | if (len != 4 || (offset & 0xf)) { | |
1600 | /* Don't shout loud, $infamous_os would cause only noise. */ | |
1601 | apic_debug("apic write: bad size=%d %lx\n", len, (long)address); | |
756975bb | 1602 | return 0; |
0105d1a5 GN |
1603 | } |
1604 | ||
1605 | val = *(u32*)data; | |
1606 | ||
1607 | /* too common printing */ | |
1608 | if (offset != APIC_EOI) | |
1609 | apic_debug("%s: offset 0x%x with length 0x%x, and value is " | |
1610 | "0x%x\n", __func__, offset, len, val); | |
1611 | ||
1e6e2755 | 1612 | kvm_lapic_reg_write(apic, offset & 0xff0, val); |
0105d1a5 | 1613 | |
bda9020e | 1614 | return 0; |
97222cc8 ED |
1615 | } |
1616 | ||
58fbbf26 KT |
1617 | void kvm_lapic_set_eoi(struct kvm_vcpu *vcpu) |
1618 | { | |
1e6e2755 | 1619 | kvm_lapic_reg_write(vcpu->arch.apic, APIC_EOI, 0); |
58fbbf26 KT |
1620 | } |
1621 | EXPORT_SYMBOL_GPL(kvm_lapic_set_eoi); | |
1622 | ||
83d4c286 YZ |
1623 | /* emulate APIC access in a trap manner */ |
1624 | void kvm_apic_write_nodecode(struct kvm_vcpu *vcpu, u32 offset) | |
1625 | { | |
1626 | u32 val = 0; | |
1627 | ||
1628 | /* hw has done the conditional check and inst decode */ | |
1629 | offset &= 0xff0; | |
1630 | ||
1e6e2755 | 1631 | kvm_lapic_reg_read(vcpu->arch.apic, offset, 4, &val); |
83d4c286 YZ |
1632 | |
1633 | /* TODO: optimize to just emulate side effect w/o one more write */ | |
1e6e2755 | 1634 | kvm_lapic_reg_write(vcpu->arch.apic, offset, val); |
83d4c286 YZ |
1635 | } |
1636 | EXPORT_SYMBOL_GPL(kvm_apic_write_nodecode); | |
1637 | ||
d589444e | 1638 | void kvm_free_lapic(struct kvm_vcpu *vcpu) |
97222cc8 | 1639 | { |
f8c1ea10 GN |
1640 | struct kvm_lapic *apic = vcpu->arch.apic; |
1641 | ||
ad312c7c | 1642 | if (!vcpu->arch.apic) |
97222cc8 ED |
1643 | return; |
1644 | ||
f8c1ea10 | 1645 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1646 | |
c5cc421b GN |
1647 | if (!(vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE)) |
1648 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1649 | ||
e462755c | 1650 | if (!apic->sw_enabled) |
f8c1ea10 | 1651 | static_key_slow_dec_deferred(&apic_sw_disabled); |
97222cc8 | 1652 | |
f8c1ea10 GN |
1653 | if (apic->regs) |
1654 | free_page((unsigned long)apic->regs); | |
1655 | ||
1656 | kfree(apic); | |
97222cc8 ED |
1657 | } |
1658 | ||
1659 | /* | |
1660 | *---------------------------------------------------------------------- | |
1661 | * LAPIC interface | |
1662 | *---------------------------------------------------------------------- | |
1663 | */ | |
1664 | ||
a3e06bbe LJ |
1665 | u64 kvm_get_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu) |
1666 | { | |
1667 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1668 | |
bce87cce | 1669 | if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1670 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1671 | return 0; |
1672 | ||
1673 | return apic->lapic_timer.tscdeadline; | |
1674 | } | |
1675 | ||
1676 | void kvm_set_lapic_tscdeadline_msr(struct kvm_vcpu *vcpu, u64 data) | |
1677 | { | |
1678 | struct kvm_lapic *apic = vcpu->arch.apic; | |
a3e06bbe | 1679 | |
bce87cce | 1680 | if (!lapic_in_kernel(vcpu) || apic_lvtt_oneshot(apic) || |
54e9818f | 1681 | apic_lvtt_period(apic)) |
a3e06bbe LJ |
1682 | return; |
1683 | ||
1684 | hrtimer_cancel(&apic->lapic_timer.timer); | |
1685 | apic->lapic_timer.tscdeadline = data; | |
1686 | start_apic_timer(apic); | |
1687 | } | |
1688 | ||
97222cc8 ED |
1689 | void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8) |
1690 | { | |
ad312c7c | 1691 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 | 1692 | |
b93463aa | 1693 | apic_set_tpr(apic, ((cr8 & 0x0f) << 4) |
dfb95954 | 1694 | | (kvm_lapic_get_reg(apic, APIC_TASKPRI) & 4)); |
97222cc8 ED |
1695 | } |
1696 | ||
1697 | u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu) | |
1698 | { | |
97222cc8 ED |
1699 | u64 tpr; |
1700 | ||
dfb95954 | 1701 | tpr = (u64) kvm_lapic_get_reg(vcpu->arch.apic, APIC_TASKPRI); |
97222cc8 ED |
1702 | |
1703 | return (tpr & 0xf0) >> 4; | |
1704 | } | |
1705 | ||
1706 | void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value) | |
1707 | { | |
8d14695f | 1708 | u64 old_value = vcpu->arch.apic_base; |
ad312c7c | 1709 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1710 | |
1711 | if (!apic) { | |
1712 | value |= MSR_IA32_APICBASE_BSP; | |
ad312c7c | 1713 | vcpu->arch.apic_base = value; |
97222cc8 ED |
1714 | return; |
1715 | } | |
c5af89b6 | 1716 | |
e66d2ae7 JK |
1717 | vcpu->arch.apic_base = value; |
1718 | ||
c5cc421b | 1719 | /* update jump label if enable bit changes */ |
0dce7cd6 | 1720 | if ((old_value ^ value) & MSR_IA32_APICBASE_ENABLE) { |
c5cc421b GN |
1721 | if (value & MSR_IA32_APICBASE_ENABLE) |
1722 | static_key_slow_dec_deferred(&apic_hw_disabled); | |
1723 | else | |
1724 | static_key_slow_inc(&apic_hw_disabled.key); | |
1e08ec4a | 1725 | recalculate_apic_map(vcpu->kvm); |
c5cc421b GN |
1726 | } |
1727 | ||
8d14695f YZ |
1728 | if ((old_value ^ value) & X2APIC_ENABLE) { |
1729 | if (value & X2APIC_ENABLE) { | |
257b9a5f | 1730 | kvm_apic_set_x2apic_id(apic, vcpu->vcpu_id); |
8d14695f YZ |
1731 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true); |
1732 | } else | |
1733 | kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false); | |
0105d1a5 | 1734 | } |
8d14695f | 1735 | |
ad312c7c | 1736 | apic->base_address = apic->vcpu->arch.apic_base & |
97222cc8 ED |
1737 | MSR_IA32_APICBASE_BASE; |
1738 | ||
db324fe6 NA |
1739 | if ((value & MSR_IA32_APICBASE_ENABLE) && |
1740 | apic->base_address != APIC_DEFAULT_PHYS_BASE) | |
1741 | pr_warn_once("APIC base relocation is unsupported by KVM"); | |
1742 | ||
97222cc8 ED |
1743 | /* with FSB delivery interrupt, we can restart APIC functionality */ |
1744 | apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is " | |
ad312c7c | 1745 | "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1746 | |
1747 | } | |
1748 | ||
d28bc9dd | 1749 | void kvm_lapic_reset(struct kvm_vcpu *vcpu, bool init_event) |
97222cc8 ED |
1750 | { |
1751 | struct kvm_lapic *apic; | |
1752 | int i; | |
1753 | ||
b8688d51 | 1754 | apic_debug("%s\n", __func__); |
97222cc8 ED |
1755 | |
1756 | ASSERT(vcpu); | |
ad312c7c | 1757 | apic = vcpu->arch.apic; |
97222cc8 ED |
1758 | ASSERT(apic != NULL); |
1759 | ||
1760 | /* Stop the timer in case it's a reset to an active apic */ | |
d3c7b77d | 1761 | hrtimer_cancel(&apic->lapic_timer.timer); |
97222cc8 | 1762 | |
d28bc9dd NA |
1763 | if (!init_event) |
1764 | kvm_apic_set_id(apic, vcpu->vcpu_id); | |
fc61b800 | 1765 | kvm_apic_set_version(apic->vcpu); |
97222cc8 | 1766 | |
1e6e2755 SS |
1767 | for (i = 0; i < KVM_APIC_LVT_NUM; i++) |
1768 | kvm_lapic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED); | |
b6ac0695 | 1769 | apic_update_lvtt(apic); |
0da029ed | 1770 | if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_LINT0_REENABLED)) |
1e6e2755 | 1771 | kvm_lapic_set_reg(apic, APIC_LVT0, |
90de4a18 | 1772 | SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT)); |
dfb95954 | 1773 | apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); |
97222cc8 | 1774 | |
1e6e2755 | 1775 | kvm_lapic_set_reg(apic, APIC_DFR, 0xffffffffU); |
f8c1ea10 | 1776 | apic_set_spiv(apic, 0xff); |
1e6e2755 | 1777 | kvm_lapic_set_reg(apic, APIC_TASKPRI, 0); |
c028dd6b RK |
1778 | if (!apic_x2apic_mode(apic)) |
1779 | kvm_apic_set_ldr(apic, 0); | |
1e6e2755 SS |
1780 | kvm_lapic_set_reg(apic, APIC_ESR, 0); |
1781 | kvm_lapic_set_reg(apic, APIC_ICR, 0); | |
1782 | kvm_lapic_set_reg(apic, APIC_ICR2, 0); | |
1783 | kvm_lapic_set_reg(apic, APIC_TDCR, 0); | |
1784 | kvm_lapic_set_reg(apic, APIC_TMICT, 0); | |
97222cc8 | 1785 | for (i = 0; i < 8; i++) { |
1e6e2755 SS |
1786 | kvm_lapic_set_reg(apic, APIC_IRR + 0x10 * i, 0); |
1787 | kvm_lapic_set_reg(apic, APIC_ISR + 0x10 * i, 0); | |
1788 | kvm_lapic_set_reg(apic, APIC_TMR + 0x10 * i, 0); | |
97222cc8 | 1789 | } |
d62caabb AS |
1790 | apic->irr_pending = vcpu->arch.apicv_active; |
1791 | apic->isr_count = vcpu->arch.apicv_active ? 1 : 0; | |
8680b94b | 1792 | apic->highest_isr_cache = -1; |
b33ac88b | 1793 | update_divide_count(apic); |
d3c7b77d | 1794 | atomic_set(&apic->lapic_timer.pending, 0); |
c5af89b6 | 1795 | if (kvm_vcpu_is_bsp(vcpu)) |
5dbc8f3f GN |
1796 | kvm_lapic_set_base(vcpu, |
1797 | vcpu->arch.apic_base | MSR_IA32_APICBASE_BSP); | |
ae7a2a3f | 1798 | vcpu->arch.pv_eoi.msr_val = 0; |
97222cc8 ED |
1799 | apic_update_ppr(apic); |
1800 | ||
e1035715 | 1801 | vcpu->arch.apic_arb_prio = 0; |
41383771 | 1802 | vcpu->arch.apic_attention = 0; |
e1035715 | 1803 | |
98eff52a | 1804 | apic_debug("%s: vcpu=%p, id=%d, base_msr=" |
b8688d51 | 1805 | "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__, |
97222cc8 | 1806 | vcpu, kvm_apic_id(apic), |
ad312c7c | 1807 | vcpu->arch.apic_base, apic->base_address); |
97222cc8 ED |
1808 | } |
1809 | ||
97222cc8 ED |
1810 | /* |
1811 | *---------------------------------------------------------------------- | |
1812 | * timer interface | |
1813 | *---------------------------------------------------------------------- | |
1814 | */ | |
1b9778da | 1815 | |
2a6eac96 | 1816 | static bool lapic_is_periodic(struct kvm_lapic *apic) |
97222cc8 | 1817 | { |
d3c7b77d | 1818 | return apic_lvtt_period(apic); |
97222cc8 ED |
1819 | } |
1820 | ||
3d80840d MT |
1821 | int apic_has_pending_timer(struct kvm_vcpu *vcpu) |
1822 | { | |
54e9818f | 1823 | struct kvm_lapic *apic = vcpu->arch.apic; |
3d80840d | 1824 | |
1e3161b4 | 1825 | if (apic_enabled(apic) && apic_lvt_enabled(apic, APIC_LVTT)) |
54e9818f | 1826 | return atomic_read(&apic->lapic_timer.pending); |
3d80840d MT |
1827 | |
1828 | return 0; | |
1829 | } | |
1830 | ||
89342082 | 1831 | int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type) |
1b9778da | 1832 | { |
dfb95954 | 1833 | u32 reg = kvm_lapic_get_reg(apic, lvt_type); |
23930f95 | 1834 | int vector, mode, trig_mode; |
23930f95 | 1835 | |
c48f1496 | 1836 | if (kvm_apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) { |
23930f95 JK |
1837 | vector = reg & APIC_VECTOR_MASK; |
1838 | mode = reg & APIC_MODE_MASK; | |
1839 | trig_mode = reg & APIC_LVT_LEVEL_TRIGGER; | |
b4f2225c YZ |
1840 | return __apic_accept_irq(apic, mode, vector, 1, trig_mode, |
1841 | NULL); | |
23930f95 JK |
1842 | } |
1843 | return 0; | |
1844 | } | |
1b9778da | 1845 | |
8fdb2351 | 1846 | void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu) |
23930f95 | 1847 | { |
8fdb2351 JK |
1848 | struct kvm_lapic *apic = vcpu->arch.apic; |
1849 | ||
1850 | if (apic) | |
1851 | kvm_apic_local_deliver(apic, APIC_LVT0); | |
1b9778da ED |
1852 | } |
1853 | ||
d76685c4 GH |
1854 | static const struct kvm_io_device_ops apic_mmio_ops = { |
1855 | .read = apic_mmio_read, | |
1856 | .write = apic_mmio_write, | |
d76685c4 GH |
1857 | }; |
1858 | ||
e9d90d47 AK |
1859 | static enum hrtimer_restart apic_timer_fn(struct hrtimer *data) |
1860 | { | |
1861 | struct kvm_timer *ktimer = container_of(data, struct kvm_timer, timer); | |
2a6eac96 | 1862 | struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic, lapic_timer); |
e9d90d47 | 1863 | |
5d87db71 | 1864 | apic_timer_expired(apic); |
e9d90d47 | 1865 | |
2a6eac96 | 1866 | if (lapic_is_periodic(apic)) { |
e9d90d47 AK |
1867 | hrtimer_add_expires_ns(&ktimer->timer, ktimer->period); |
1868 | return HRTIMER_RESTART; | |
1869 | } else | |
1870 | return HRTIMER_NORESTART; | |
1871 | } | |
1872 | ||
97222cc8 ED |
1873 | int kvm_create_lapic(struct kvm_vcpu *vcpu) |
1874 | { | |
1875 | struct kvm_lapic *apic; | |
1876 | ||
1877 | ASSERT(vcpu != NULL); | |
1878 | apic_debug("apic_init %d\n", vcpu->vcpu_id); | |
1879 | ||
1880 | apic = kzalloc(sizeof(*apic), GFP_KERNEL); | |
1881 | if (!apic) | |
1882 | goto nomem; | |
1883 | ||
ad312c7c | 1884 | vcpu->arch.apic = apic; |
97222cc8 | 1885 | |
afc20184 TY |
1886 | apic->regs = (void *)get_zeroed_page(GFP_KERNEL); |
1887 | if (!apic->regs) { | |
97222cc8 ED |
1888 | printk(KERN_ERR "malloc apic regs error for vcpu %x\n", |
1889 | vcpu->vcpu_id); | |
d589444e | 1890 | goto nomem_free_apic; |
97222cc8 | 1891 | } |
97222cc8 ED |
1892 | apic->vcpu = vcpu; |
1893 | ||
d3c7b77d | 1894 | hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC, |
61abdbe0 | 1895 | HRTIMER_MODE_ABS_PINNED); |
e9d90d47 | 1896 | apic->lapic_timer.timer.function = apic_timer_fn; |
d3c7b77d | 1897 | |
c5cc421b GN |
1898 | /* |
1899 | * APIC is created enabled. This will prevent kvm_lapic_set_base from | |
1900 | * thinking that APIC satet has changed. | |
1901 | */ | |
1902 | vcpu->arch.apic_base = MSR_IA32_APICBASE_ENABLE; | |
6aed64a8 GN |
1903 | kvm_lapic_set_base(vcpu, |
1904 | APIC_DEFAULT_PHYS_BASE | MSR_IA32_APICBASE_ENABLE); | |
97222cc8 | 1905 | |
f8c1ea10 | 1906 | static_key_slow_inc(&apic_sw_disabled.key); /* sw disabled at reset */ |
d28bc9dd | 1907 | kvm_lapic_reset(vcpu, false); |
d76685c4 | 1908 | kvm_iodevice_init(&apic->dev, &apic_mmio_ops); |
97222cc8 ED |
1909 | |
1910 | return 0; | |
d589444e RR |
1911 | nomem_free_apic: |
1912 | kfree(apic); | |
97222cc8 | 1913 | nomem: |
97222cc8 ED |
1914 | return -ENOMEM; |
1915 | } | |
97222cc8 ED |
1916 | |
1917 | int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu) | |
1918 | { | |
ad312c7c | 1919 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1920 | int highest_irr; |
1921 | ||
f8543d6a | 1922 | if (!apic_enabled(apic)) |
97222cc8 ED |
1923 | return -1; |
1924 | ||
6e5d865c | 1925 | apic_update_ppr(apic); |
97222cc8 ED |
1926 | highest_irr = apic_find_highest_irr(apic); |
1927 | if ((highest_irr == -1) || | |
dfb95954 | 1928 | ((highest_irr & 0xF0) <= kvm_lapic_get_reg(apic, APIC_PROCPRI))) |
97222cc8 ED |
1929 | return -1; |
1930 | return highest_irr; | |
1931 | } | |
1932 | ||
40487c68 QH |
1933 | int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu) |
1934 | { | |
dfb95954 | 1935 | u32 lvt0 = kvm_lapic_get_reg(vcpu->arch.apic, APIC_LVT0); |
40487c68 QH |
1936 | int r = 0; |
1937 | ||
c48f1496 | 1938 | if (!kvm_apic_hw_enabled(vcpu->arch.apic)) |
e7dca5c0 CL |
1939 | r = 1; |
1940 | if ((lvt0 & APIC_LVT_MASKED) == 0 && | |
1941 | GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT) | |
1942 | r = 1; | |
40487c68 QH |
1943 | return r; |
1944 | } | |
1945 | ||
1b9778da ED |
1946 | void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu) |
1947 | { | |
ad312c7c | 1948 | struct kvm_lapic *apic = vcpu->arch.apic; |
1b9778da | 1949 | |
54e9818f | 1950 | if (atomic_read(&apic->lapic_timer.pending) > 0) { |
f1ed0450 | 1951 | kvm_apic_local_deliver(apic, APIC_LVTT); |
fae0ba21 NA |
1952 | if (apic_lvtt_tscdeadline(apic)) |
1953 | apic->lapic_timer.tscdeadline = 0; | |
f1ed0450 | 1954 | atomic_set(&apic->lapic_timer.pending, 0); |
1b9778da ED |
1955 | } |
1956 | } | |
1957 | ||
97222cc8 ED |
1958 | int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu) |
1959 | { | |
1960 | int vector = kvm_apic_has_interrupt(vcpu); | |
ad312c7c | 1961 | struct kvm_lapic *apic = vcpu->arch.apic; |
97222cc8 ED |
1962 | |
1963 | if (vector == -1) | |
1964 | return -1; | |
1965 | ||
56cc2406 WL |
1966 | /* |
1967 | * We get here even with APIC virtualization enabled, if doing | |
1968 | * nested virtualization and L1 runs with the "acknowledge interrupt | |
1969 | * on exit" mode. Then we cannot inject the interrupt via RVI, | |
1970 | * because the process would deliver it through the IDT. | |
1971 | */ | |
1972 | ||
8680b94b | 1973 | apic_set_isr(vector, apic); |
97222cc8 ED |
1974 | apic_update_ppr(apic); |
1975 | apic_clear_irr(vector, apic); | |
5c919412 AS |
1976 | |
1977 | if (test_bit(vector, vcpu_to_synic(vcpu)->auto_eoi_bitmap)) { | |
1978 | apic_clear_isr(vector, apic); | |
1979 | apic_update_ppr(apic); | |
1980 | } | |
1981 | ||
97222cc8 ED |
1982 | return vector; |
1983 | } | |
96ad2cc6 | 1984 | |
64eb0620 GN |
1985 | void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu, |
1986 | struct kvm_lapic_state *s) | |
96ad2cc6 | 1987 | { |
ad312c7c | 1988 | struct kvm_lapic *apic = vcpu->arch.apic; |
96ad2cc6 | 1989 | |
5dbc8f3f | 1990 | kvm_lapic_set_base(vcpu, vcpu->arch.apic_base); |
64eb0620 GN |
1991 | /* set SPIV separately to get count of SW disabled APICs right */ |
1992 | apic_set_spiv(apic, *((u32 *)(s->regs + APIC_SPIV))); | |
1993 | memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s); | |
1e08ec4a GN |
1994 | /* call kvm_apic_set_id() to put apic into apic_map */ |
1995 | kvm_apic_set_id(apic, kvm_apic_id(apic)); | |
fc61b800 GN |
1996 | kvm_apic_set_version(vcpu); |
1997 | ||
96ad2cc6 | 1998 | apic_update_ppr(apic); |
d3c7b77d | 1999 | hrtimer_cancel(&apic->lapic_timer.timer); |
b6ac0695 | 2000 | apic_update_lvtt(apic); |
dfb95954 | 2001 | apic_manage_nmi_watchdog(apic, kvm_lapic_get_reg(apic, APIC_LVT0)); |
96ad2cc6 ED |
2002 | update_divide_count(apic); |
2003 | start_apic_timer(apic); | |
6e24a6ef | 2004 | apic->irr_pending = true; |
d62caabb | 2005 | apic->isr_count = vcpu->arch.apicv_active ? |
c7c9c56c | 2006 | 1 : count_vectors(apic->regs + APIC_ISR); |
8680b94b | 2007 | apic->highest_isr_cache = -1; |
d62caabb | 2008 | if (vcpu->arch.apicv_active) { |
be8ca170 SS |
2009 | if (kvm_x86_ops->apicv_post_state_restore) |
2010 | kvm_x86_ops->apicv_post_state_restore(vcpu); | |
4114c27d WW |
2011 | kvm_x86_ops->hwapic_irr_update(vcpu, |
2012 | apic_find_highest_irr(apic)); | |
67c9dddc | 2013 | kvm_x86_ops->hwapic_isr_update(vcpu, |
b4eef9b3 | 2014 | apic_find_highest_isr(apic)); |
d62caabb | 2015 | } |
3842d135 | 2016 | kvm_make_request(KVM_REQ_EVENT, vcpu); |
49df6397 SR |
2017 | if (ioapic_in_kernel(vcpu->kvm)) |
2018 | kvm_rtc_eoi_tracking_restore_one(vcpu); | |
0669a510 RK |
2019 | |
2020 | vcpu->arch.apic_arb_prio = 0; | |
96ad2cc6 | 2021 | } |
a3d7f85f | 2022 | |
2f52d58c | 2023 | void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu) |
a3d7f85f | 2024 | { |
a3d7f85f ED |
2025 | struct hrtimer *timer; |
2026 | ||
bce87cce | 2027 | if (!lapic_in_kernel(vcpu)) |
a3d7f85f ED |
2028 | return; |
2029 | ||
54e9818f | 2030 | timer = &vcpu->arch.apic->lapic_timer.timer; |
a3d7f85f | 2031 | if (hrtimer_cancel(timer)) |
61abdbe0 | 2032 | hrtimer_start_expires(timer, HRTIMER_MODE_ABS_PINNED); |
a3d7f85f | 2033 | } |
b93463aa | 2034 | |
ae7a2a3f MT |
2035 | /* |
2036 | * apic_sync_pv_eoi_from_guest - called on vmexit or cancel interrupt | |
2037 | * | |
2038 | * Detect whether guest triggered PV EOI since the | |
2039 | * last entry. If yes, set EOI on guests's behalf. | |
2040 | * Clear PV EOI in guest memory in any case. | |
2041 | */ | |
2042 | static void apic_sync_pv_eoi_from_guest(struct kvm_vcpu *vcpu, | |
2043 | struct kvm_lapic *apic) | |
2044 | { | |
2045 | bool pending; | |
2046 | int vector; | |
2047 | /* | |
2048 | * PV EOI state is derived from KVM_APIC_PV_EOI_PENDING in host | |
2049 | * and KVM_PV_EOI_ENABLED in guest memory as follows: | |
2050 | * | |
2051 | * KVM_APIC_PV_EOI_PENDING is unset: | |
2052 | * -> host disabled PV EOI. | |
2053 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is set: | |
2054 | * -> host enabled PV EOI, guest did not execute EOI yet. | |
2055 | * KVM_APIC_PV_EOI_PENDING is set, KVM_PV_EOI_ENABLED is unset: | |
2056 | * -> host enabled PV EOI, guest executed EOI. | |
2057 | */ | |
2058 | BUG_ON(!pv_eoi_enabled(vcpu)); | |
2059 | pending = pv_eoi_get_pending(vcpu); | |
2060 | /* | |
2061 | * Clear pending bit in any case: it will be set again on vmentry. | |
2062 | * While this might not be ideal from performance point of view, | |
2063 | * this makes sure pv eoi is only enabled when we know it's safe. | |
2064 | */ | |
2065 | pv_eoi_clr_pending(vcpu); | |
2066 | if (pending) | |
2067 | return; | |
2068 | vector = apic_set_eoi(apic); | |
2069 | trace_kvm_pv_eoi(apic, vector); | |
2070 | } | |
2071 | ||
b93463aa AK |
2072 | void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu) |
2073 | { | |
2074 | u32 data; | |
b93463aa | 2075 | |
ae7a2a3f MT |
2076 | if (test_bit(KVM_APIC_PV_EOI_PENDING, &vcpu->arch.apic_attention)) |
2077 | apic_sync_pv_eoi_from_guest(vcpu, vcpu->arch.apic); | |
2078 | ||
41383771 | 2079 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
2080 | return; |
2081 | ||
603242a8 NK |
2082 | if (kvm_read_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
2083 | sizeof(u32))) | |
2084 | return; | |
b93463aa AK |
2085 | |
2086 | apic_set_tpr(vcpu->arch.apic, data & 0xff); | |
2087 | } | |
2088 | ||
ae7a2a3f MT |
2089 | /* |
2090 | * apic_sync_pv_eoi_to_guest - called before vmentry | |
2091 | * | |
2092 | * Detect whether it's safe to enable PV EOI and | |
2093 | * if yes do so. | |
2094 | */ | |
2095 | static void apic_sync_pv_eoi_to_guest(struct kvm_vcpu *vcpu, | |
2096 | struct kvm_lapic *apic) | |
2097 | { | |
2098 | if (!pv_eoi_enabled(vcpu) || | |
2099 | /* IRR set or many bits in ISR: could be nested. */ | |
2100 | apic->irr_pending || | |
2101 | /* Cache not set: could be safe but we don't bother. */ | |
2102 | apic->highest_isr_cache == -1 || | |
2103 | /* Need EOI to update ioapic. */ | |
3bb345f3 | 2104 | kvm_ioapic_handles_vector(apic, apic->highest_isr_cache)) { |
ae7a2a3f MT |
2105 | /* |
2106 | * PV EOI was disabled by apic_sync_pv_eoi_from_guest | |
2107 | * so we need not do anything here. | |
2108 | */ | |
2109 | return; | |
2110 | } | |
2111 | ||
2112 | pv_eoi_set_pending(apic->vcpu); | |
2113 | } | |
2114 | ||
b93463aa AK |
2115 | void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu) |
2116 | { | |
2117 | u32 data, tpr; | |
2118 | int max_irr, max_isr; | |
ae7a2a3f | 2119 | struct kvm_lapic *apic = vcpu->arch.apic; |
b93463aa | 2120 | |
ae7a2a3f MT |
2121 | apic_sync_pv_eoi_to_guest(vcpu, apic); |
2122 | ||
41383771 | 2123 | if (!test_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention)) |
b93463aa AK |
2124 | return; |
2125 | ||
dfb95954 | 2126 | tpr = kvm_lapic_get_reg(apic, APIC_TASKPRI) & 0xff; |
b93463aa AK |
2127 | max_irr = apic_find_highest_irr(apic); |
2128 | if (max_irr < 0) | |
2129 | max_irr = 0; | |
2130 | max_isr = apic_find_highest_isr(apic); | |
2131 | if (max_isr < 0) | |
2132 | max_isr = 0; | |
2133 | data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24); | |
2134 | ||
fda4e2e8 AH |
2135 | kvm_write_guest_cached(vcpu->kvm, &vcpu->arch.apic->vapic_cache, &data, |
2136 | sizeof(u32)); | |
b93463aa AK |
2137 | } |
2138 | ||
fda4e2e8 | 2139 | int kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr) |
b93463aa | 2140 | { |
fda4e2e8 AH |
2141 | if (vapic_addr) { |
2142 | if (kvm_gfn_to_hva_cache_init(vcpu->kvm, | |
2143 | &vcpu->arch.apic->vapic_cache, | |
2144 | vapic_addr, sizeof(u32))) | |
2145 | return -EINVAL; | |
41383771 | 2146 | __set_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 | 2147 | } else { |
41383771 | 2148 | __clear_bit(KVM_APIC_CHECK_VAPIC, &vcpu->arch.apic_attention); |
fda4e2e8 AH |
2149 | } |
2150 | ||
2151 | vcpu->arch.apic->vapic_addr = vapic_addr; | |
2152 | return 0; | |
b93463aa | 2153 | } |
0105d1a5 GN |
2154 | |
2155 | int kvm_x2apic_msr_write(struct kvm_vcpu *vcpu, u32 msr, u64 data) | |
2156 | { | |
2157 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2158 | u32 reg = (msr - APIC_BASE_MSR) << 4; | |
2159 | ||
35754c98 | 2160 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2161 | return 1; |
2162 | ||
c69d3d9b NA |
2163 | if (reg == APIC_ICR2) |
2164 | return 1; | |
2165 | ||
0105d1a5 | 2166 | /* if this is ICR write vector before command */ |
decdc283 | 2167 | if (reg == APIC_ICR) |
1e6e2755 SS |
2168 | kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
2169 | return kvm_lapic_reg_write(apic, reg, (u32)data); | |
0105d1a5 GN |
2170 | } |
2171 | ||
2172 | int kvm_x2apic_msr_read(struct kvm_vcpu *vcpu, u32 msr, u64 *data) | |
2173 | { | |
2174 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2175 | u32 reg = (msr - APIC_BASE_MSR) << 4, low, high = 0; | |
2176 | ||
35754c98 | 2177 | if (!lapic_in_kernel(vcpu) || !apic_x2apic_mode(apic)) |
0105d1a5 GN |
2178 | return 1; |
2179 | ||
c69d3d9b NA |
2180 | if (reg == APIC_DFR || reg == APIC_ICR2) { |
2181 | apic_debug("KVM_APIC_READ: read x2apic reserved register %x\n", | |
2182 | reg); | |
2183 | return 1; | |
2184 | } | |
2185 | ||
1e6e2755 | 2186 | if (kvm_lapic_reg_read(apic, reg, 4, &low)) |
0105d1a5 | 2187 | return 1; |
decdc283 | 2188 | if (reg == APIC_ICR) |
1e6e2755 | 2189 | kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); |
0105d1a5 GN |
2190 | |
2191 | *data = (((u64)high) << 32) | low; | |
2192 | ||
2193 | return 0; | |
2194 | } | |
10388a07 GN |
2195 | |
2196 | int kvm_hv_vapic_msr_write(struct kvm_vcpu *vcpu, u32 reg, u64 data) | |
2197 | { | |
2198 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2199 | ||
bce87cce | 2200 | if (!lapic_in_kernel(vcpu)) |
10388a07 GN |
2201 | return 1; |
2202 | ||
2203 | /* if this is ICR write vector before command */ | |
2204 | if (reg == APIC_ICR) | |
1e6e2755 SS |
2205 | kvm_lapic_reg_write(apic, APIC_ICR2, (u32)(data >> 32)); |
2206 | return kvm_lapic_reg_write(apic, reg, (u32)data); | |
10388a07 GN |
2207 | } |
2208 | ||
2209 | int kvm_hv_vapic_msr_read(struct kvm_vcpu *vcpu, u32 reg, u64 *data) | |
2210 | { | |
2211 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2212 | u32 low, high = 0; | |
2213 | ||
bce87cce | 2214 | if (!lapic_in_kernel(vcpu)) |
10388a07 GN |
2215 | return 1; |
2216 | ||
1e6e2755 | 2217 | if (kvm_lapic_reg_read(apic, reg, 4, &low)) |
10388a07 GN |
2218 | return 1; |
2219 | if (reg == APIC_ICR) | |
1e6e2755 | 2220 | kvm_lapic_reg_read(apic, APIC_ICR2, 4, &high); |
10388a07 GN |
2221 | |
2222 | *data = (((u64)high) << 32) | low; | |
2223 | ||
2224 | return 0; | |
2225 | } | |
ae7a2a3f MT |
2226 | |
2227 | int kvm_lapic_enable_pv_eoi(struct kvm_vcpu *vcpu, u64 data) | |
2228 | { | |
2229 | u64 addr = data & ~KVM_MSR_ENABLED; | |
2230 | if (!IS_ALIGNED(addr, 4)) | |
2231 | return 1; | |
2232 | ||
2233 | vcpu->arch.pv_eoi.msr_val = data; | |
2234 | if (!pv_eoi_enabled(vcpu)) | |
2235 | return 0; | |
2236 | return kvm_gfn_to_hva_cache_init(vcpu->kvm, &vcpu->arch.pv_eoi.data, | |
8f964525 | 2237 | addr, sizeof(u8)); |
ae7a2a3f | 2238 | } |
c5cc421b | 2239 | |
66450a21 JK |
2240 | void kvm_apic_accept_events(struct kvm_vcpu *vcpu) |
2241 | { | |
2242 | struct kvm_lapic *apic = vcpu->arch.apic; | |
2b4a273b | 2243 | u8 sipi_vector; |
299018f4 | 2244 | unsigned long pe; |
66450a21 | 2245 | |
bce87cce | 2246 | if (!lapic_in_kernel(vcpu) || !apic->pending_events) |
66450a21 JK |
2247 | return; |
2248 | ||
cd7764fe PB |
2249 | /* |
2250 | * INITs are latched while in SMM. Because an SMM CPU cannot | |
2251 | * be in KVM_MP_STATE_INIT_RECEIVED state, just eat SIPIs | |
2252 | * and delay processing of INIT until the next RSM. | |
2253 | */ | |
2254 | if (is_smm(vcpu)) { | |
2255 | WARN_ON_ONCE(vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED); | |
2256 | if (test_bit(KVM_APIC_SIPI, &apic->pending_events)) | |
2257 | clear_bit(KVM_APIC_SIPI, &apic->pending_events); | |
2258 | return; | |
2259 | } | |
299018f4 | 2260 | |
cd7764fe | 2261 | pe = xchg(&apic->pending_events, 0); |
299018f4 | 2262 | if (test_bit(KVM_APIC_INIT, &pe)) { |
d28bc9dd NA |
2263 | kvm_lapic_reset(vcpu, true); |
2264 | kvm_vcpu_reset(vcpu, true); | |
66450a21 JK |
2265 | if (kvm_vcpu_is_bsp(apic->vcpu)) |
2266 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2267 | else | |
2268 | vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED; | |
2269 | } | |
299018f4 | 2270 | if (test_bit(KVM_APIC_SIPI, &pe) && |
66450a21 JK |
2271 | vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) { |
2272 | /* evaluate pending_events before reading the vector */ | |
2273 | smp_rmb(); | |
2274 | sipi_vector = apic->sipi_vector; | |
98eff52a | 2275 | apic_debug("vcpu %d received sipi with vector # %x\n", |
66450a21 JK |
2276 | vcpu->vcpu_id, sipi_vector); |
2277 | kvm_vcpu_deliver_sipi_vector(vcpu, sipi_vector); | |
2278 | vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE; | |
2279 | } | |
2280 | } | |
2281 | ||
c5cc421b GN |
2282 | void kvm_lapic_init(void) |
2283 | { | |
2284 | /* do not patch jump label more than once per second */ | |
2285 | jump_label_rate_limit(&apic_hw_disabled, HZ); | |
f8c1ea10 | 2286 | jump_label_rate_limit(&apic_sw_disabled, HZ); |
c5cc421b | 2287 | } |