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KVM: Add Directed EOI support to APIC emulation
[thirdparty/linux.git] / arch / x86 / kvm / lapic.c
CommitLineData
97222cc8
ED		 1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 *
9 * Authors:
10 * Dor Laor <dor.laor@qumranet.com>
11 * Gregory Haskins <ghaskins@novell.com>
12 * Yaozu (Eddie) Dong <eddie.dong@intel.com>
13 *
14 * Based on Xen 3.1 code, Copyright (c) 2004, Intel Corporation.
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 */
19
edf88417 20#include <linux/kvm_host.h>
97222cc8
ED		 21#include <linux/kvm.h>
22#include <linux/mm.h>
23#include <linux/highmem.h>
24#include <linux/smp.h>
25#include <linux/hrtimer.h>
26#include <linux/io.h>
27#include <linux/module.h>
6f6d6a1a 28#include <linux/math64.h>
97222cc8
ED		 29#include <asm/processor.h>
30#include <asm/msr.h>
31#include <asm/page.h>
32#include <asm/current.h>
33#include <asm/apicdef.h>
34#include <asm/atomic.h>
5fdbf976 35#include "kvm_cache_regs.h"
97222cc8 36#include "irq.h"
229456fc 37#include "trace.h"
fc61b800 38#include "x86.h"
97222cc8 39
b682b814
MT		 40#ifndef CONFIG_X86_64
41#define mod_64(x, y) ((x) - (y) * div64_u64(x, y))
42#else
43#define mod_64(x, y) ((x) % (y))
44#endif
45
97222cc8
ED		 46#define PRId64 "d"
47#define PRIx64 "llx"
48#define PRIu64 "u"
49#define PRIo64 "o"
50
51#define APIC_BUS_CYCLE_NS 1
52
53/* #define apic_debug(fmt,arg...) printk(KERN_WARNING fmt,##arg) */
54#define apic_debug(fmt, arg...)
55
56#define APIC_LVT_NUM 6
57/* 14 is the version for Xeon and Pentium 8.4.8*/
58#define APIC_VERSION (0x14UL | ((APIC_LVT_NUM - 1) << 16))
59#define LAPIC_MMIO_LENGTH (1 << 12)
60/* followed define is not in apicdef.h */
61#define APIC_SHORT_MASK 0xc0000
62#define APIC_DEST_NOSHORT 0x0
63#define APIC_DEST_MASK 0x800
64#define MAX_APIC_VECTOR 256
65
66#define VEC_POS(v) ((v) & (32 - 1))
67#define REG_POS(v) (((v) >> 5) << 4)
ad312c7c 68
97222cc8
ED		 69static inline u32 apic_get_reg(struct kvm_lapic *apic, int reg_off)
70{
71 return *((u32 *) (apic->regs + reg_off));
72}
73
74static inline void apic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val)
75{
76 *((u32 *) (apic->regs + reg_off)) = val;
77}
78
79static inline int apic_test_and_set_vector(int vec, void *bitmap)
80{
81 return test_and_set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
82}
83
84static inline int apic_test_and_clear_vector(int vec, void *bitmap)
85{
86 return test_and_clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
87}
88
89static inline void apic_set_vector(int vec, void *bitmap)
90{
91 set_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
92}
93
94static inline void apic_clear_vector(int vec, void *bitmap)
95{
96 clear_bit(VEC_POS(vec), (bitmap) + REG_POS(vec));
97}
98
99static inline int apic_hw_enabled(struct kvm_lapic *apic)
100{
ad312c7c 101 return (apic)->vcpu->arch.apic_base & MSR_IA32_APICBASE_ENABLE;
97222cc8
ED		 102}
103
104static inline int apic_sw_enabled(struct kvm_lapic *apic)
105{
106 return apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_APIC_ENABLED;
107}
108
109static inline int apic_enabled(struct kvm_lapic *apic)
110{
111 return apic_sw_enabled(apic) && apic_hw_enabled(apic);
112}
113
114#define LVT_MASK \
115 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
116
117#define LINT_MASK \
118 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
119 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
120
121static inline int kvm_apic_id(struct kvm_lapic *apic)
122{
123 return (apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
124}
125
126static inline int apic_lvt_enabled(struct kvm_lapic *apic, int lvt_type)
127{
128 return !(apic_get_reg(apic, lvt_type) & APIC_LVT_MASKED);
129}
130
131static inline int apic_lvt_vector(struct kvm_lapic *apic, int lvt_type)
132{
133 return apic_get_reg(apic, lvt_type) & APIC_VECTOR_MASK;
134}
135
136static inline int apic_lvtt_period(struct kvm_lapic *apic)
137{
138 return apic_get_reg(apic, APIC_LVTT) & APIC_LVT_TIMER_PERIODIC;
139}
140
cc6e462c
JK		 141static inline int apic_lvt_nmi_mode(u32 lvt_val)
142{
143 return (lvt_val & (APIC_MODE_MASK | APIC_LVT_MASKED)) == APIC_DM_NMI;
144}
145
fc61b800
GN		 146void kvm_apic_set_version(struct kvm_vcpu *vcpu)
147{
148 struct kvm_lapic *apic = vcpu->arch.apic;
149 struct kvm_cpuid_entry2 *feat;
150 u32 v = APIC_VERSION;
151
152 if (!irqchip_in_kernel(vcpu->kvm))
153 return;
154
155 feat = kvm_find_cpuid_entry(apic->vcpu, 0x1, 0);
156 if (feat && (feat->ecx & (1 << (X86_FEATURE_X2APIC & 31))))
157 v |= APIC_LVR_DIRECTED_EOI;
158 apic_set_reg(apic, APIC_LVR, v);
159}
160
97222cc8
ED		 161static unsigned int apic_lvt_mask[APIC_LVT_NUM] = {
162 LVT_MASK | APIC_LVT_TIMER_PERIODIC, /* LVTT */
163 LVT_MASK | APIC_MODE_MASK, /* LVTTHMR */
164 LVT_MASK | APIC_MODE_MASK, /* LVTPC */
165 LINT_MASK, LINT_MASK, /* LVT0-1 */
166 LVT_MASK /* LVTERR */
167};
168
169static int find_highest_vector(void *bitmap)
170{
171 u32 *word = bitmap;
172 int word_offset = MAX_APIC_VECTOR >> 5;
173
174 while ((word_offset != 0) && (word[(--word_offset) << 2] == 0))
175 continue;
176
177 if (likely(!word_offset && !word[0]))
178 return -1;
179 else
180 return fls(word[word_offset << 2]) - 1 + (word_offset << 5);
181}
182
183static inline int apic_test_and_set_irr(int vec, struct kvm_lapic *apic)
184{
33e4c686 185 apic->irr_pending = true;
97222cc8
ED		 186 return apic_test_and_set_vector(vec, apic->regs + APIC_IRR);
187}
188
33e4c686 189static inline int apic_search_irr(struct kvm_lapic *apic)
97222cc8 190{
33e4c686 191 return find_highest_vector(apic->regs + APIC_IRR);
97222cc8
ED		 192}
193
194static inline int apic_find_highest_irr(struct kvm_lapic *apic)
195{
196 int result;
197
33e4c686
GN		 198 if (!apic->irr_pending)
199 return -1;
200
201 result = apic_search_irr(apic);
97222cc8
ED		 202 ASSERT(result == -1 || result >= 16);
203
204 return result;
205}
206
33e4c686
GN		 207static inline void apic_clear_irr(int vec, struct kvm_lapic *apic)
208{
209 apic->irr_pending = false;
210 apic_clear_vector(vec, apic->regs + APIC_IRR);
211 if (apic_search_irr(apic) != -1)
212 apic->irr_pending = true;
213}
214
6e5d865c
YS		 215int kvm_lapic_find_highest_irr(struct kvm_vcpu *vcpu)
216{
ad312c7c 217 struct kvm_lapic *apic = vcpu->arch.apic;
6e5d865c
YS		 218 int highest_irr;
219
33e4c686
GN		 220 /* This may race with setting of irr in __apic_accept_irq() and
221 * value returned may be wrong, but kvm_vcpu_kick() in __apic_accept_irq
222 * will cause vmexit immediately and the value will be recalculated
223 * on the next vmentry.
224 */
6e5d865c
YS		 225 if (!apic)
226 return 0;
227 highest_irr = apic_find_highest_irr(apic);
228
229 return highest_irr;
230}
6e5d865c 231
6da7e3f6
GN		 232static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
233 int vector, int level, int trig_mode);
234
58c2dde1 235int kvm_apic_set_irq(struct kvm_vcpu *vcpu, struct kvm_lapic_irq *irq)
97222cc8 236{
ad312c7c 237 struct kvm_lapic *apic = vcpu->arch.apic;
8be5453f 238
58c2dde1
GN		 239 return __apic_accept_irq(apic, irq->delivery_mode, irq->vector,
240 irq->level, irq->trig_mode);
97222cc8
ED		 241}
242
243static inline int apic_find_highest_isr(struct kvm_lapic *apic)
244{
245 int result;
246
247 result = find_highest_vector(apic->regs + APIC_ISR);
248 ASSERT(result == -1 || result >= 16);
249
250 return result;
251}
252
253static void apic_update_ppr(struct kvm_lapic *apic)
254{
255 u32 tpr, isrv, ppr;
256 int isr;
257
258 tpr = apic_get_reg(apic, APIC_TASKPRI);
259 isr = apic_find_highest_isr(apic);
260 isrv = (isr != -1) ? isr : 0;
261
262 if ((tpr & 0xf0) >= (isrv & 0xf0))
263 ppr = tpr & 0xff;
264 else
265 ppr = isrv & 0xf0;
266
267 apic_debug("vlapic %p, ppr 0x%x, isr 0x%x, isrv 0x%x",
268 apic, ppr, isr, isrv);
269
270 apic_set_reg(apic, APIC_PROCPRI, ppr);
271}
272
273static void apic_set_tpr(struct kvm_lapic *apic, u32 tpr)
274{
275 apic_set_reg(apic, APIC_TASKPRI, tpr);
276 apic_update_ppr(apic);
277}
278
279int kvm_apic_match_physical_addr(struct kvm_lapic *apic, u16 dest)
280{
343f94fe 281 return dest == 0xff || kvm_apic_id(apic) == dest;
97222cc8
ED		 282}
283
284int kvm_apic_match_logical_addr(struct kvm_lapic *apic, u8 mda)
285{
286 int result = 0;
287 u8 logical_id;
288
289 logical_id = GET_APIC_LOGICAL_ID(apic_get_reg(apic, APIC_LDR));
290
291 switch (apic_get_reg(apic, APIC_DFR)) {
292 case APIC_DFR_FLAT:
293 if (logical_id & mda)
294 result = 1;
295 break;
296 case APIC_DFR_CLUSTER:
297 if (((logical_id >> 4) == (mda >> 0x4))
298 && (logical_id & mda & 0xf))
299 result = 1;
300 break;
301 default:
302 printk(KERN_WARNING "Bad DFR vcpu %d: %08x\n",
303 apic->vcpu->vcpu_id, apic_get_reg(apic, APIC_DFR));
304 break;
305 }
306
307 return result;
308}
309
343f94fe 310int kvm_apic_match_dest(struct kvm_vcpu *vcpu, struct kvm_lapic *source,
97222cc8
ED		 311 int short_hand, int dest, int dest_mode)
312{
313 int result = 0;
ad312c7c 314 struct kvm_lapic *target = vcpu->arch.apic;
97222cc8
ED		 315
316 apic_debug("target %p, source %p, dest 0x%x, "
343f94fe 317 "dest_mode 0x%x, short_hand 0x%x\n",
97222cc8
ED		 318 target, source, dest, dest_mode, short_hand);
319
320 ASSERT(!target);
321 switch (short_hand) {
322 case APIC_DEST_NOSHORT:
343f94fe 323 if (dest_mode == 0)
97222cc8 324 /* Physical mode. */
343f94fe
GN		 325 result = kvm_apic_match_physical_addr(target, dest);
326 else
97222cc8
ED		 327 /* Logical mode. */
328 result = kvm_apic_match_logical_addr(target, dest);
329 break;
330 case APIC_DEST_SELF:
343f94fe 331 result = (target == source);
97222cc8
ED		 332 break;
333 case APIC_DEST_ALLINC:
334 result = 1;
335 break;
336 case APIC_DEST_ALLBUT:
343f94fe 337 result = (target != source);
97222cc8
ED		 338 break;
339 default:
340 printk(KERN_WARNING "Bad dest shorthand value %x\n",
341 short_hand);
342 break;
343 }
344
345 return result;
346}
347
348/*
349 * Add a pending IRQ into lapic.
350 * Return 1 if successfully added and 0 if discarded.
351 */
352static int __apic_accept_irq(struct kvm_lapic *apic, int delivery_mode,
353 int vector, int level, int trig_mode)
354{
6da7e3f6 355 int result = 0;
c5ec1534 356 struct kvm_vcpu *vcpu = apic->vcpu;
97222cc8
ED		 357
358 switch (delivery_mode) {
97222cc8 359 case APIC_DM_LOWEST:
e1035715
GN		 360 vcpu->arch.apic_arb_prio++;
361 case APIC_DM_FIXED:
97222cc8
ED		 362 /* FIXME add logic for vcpu on reset */
363 if (unlikely(!apic_enabled(apic)))
364 break;
365
6da7e3f6
GN		 366 result = !apic_test_and_set_irr(vector, apic);
367 if (!result) {
368 if (trig_mode)
369 apic_debug("level trig mode repeatedly for "
370 "vector %d", vector);
97222cc8
ED		 371 break;
372 }
373
374 if (trig_mode) {
375 apic_debug("level trig mode for vector %d", vector);
376 apic_set_vector(vector, apic->regs + APIC_TMR);
377 } else
378 apic_clear_vector(vector, apic->regs + APIC_TMR);
d7690175 379 kvm_vcpu_kick(vcpu);
97222cc8
ED		 380 break;
381
382 case APIC_DM_REMRD:
383 printk(KERN_DEBUG "Ignoring delivery mode 3\n");
384 break;
385
386 case APIC_DM_SMI:
387 printk(KERN_DEBUG "Ignoring guest SMI\n");
388 break;
3419ffc8 389
97222cc8 390 case APIC_DM_NMI:
6da7e3f6 391 result = 1;
3419ffc8 392 kvm_inject_nmi(vcpu);
26df99c6 393 kvm_vcpu_kick(vcpu);
97222cc8
ED		 394 break;
395
396 case APIC_DM_INIT:
c5ec1534 397 if (level) {
6da7e3f6 398 result = 1;
a4535290 399 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
c5ec1534
HQ		 400 printk(KERN_DEBUG
401 "INIT on a runnable vcpu %d\n",
402 vcpu->vcpu_id);
a4535290 403 vcpu->arch.mp_state = KVM_MP_STATE_INIT_RECEIVED;
c5ec1534
HQ		 404 kvm_vcpu_kick(vcpu);
405 } else {
1b10bf31
JK		 406 apic_debug("Ignoring de-assert INIT to vcpu %d\n",
407 vcpu->vcpu_id);
c5ec1534 408 }
97222cc8
ED		 409 break;
410
411 case APIC_DM_STARTUP:
1b10bf31
JK		 412 apic_debug("SIPI to vcpu %d vector 0x%02x\n",
413 vcpu->vcpu_id, vector);
a4535290 414 if (vcpu->arch.mp_state == KVM_MP_STATE_INIT_RECEIVED) {
6da7e3f6 415 result = 1;
ad312c7c 416 vcpu->arch.sipi_vector = vector;
a4535290 417 vcpu->arch.mp_state = KVM_MP_STATE_SIPI_RECEIVED;
d7690175 418 kvm_vcpu_kick(vcpu);
c5ec1534 419 }
97222cc8
ED		 420 break;
421
23930f95
JK		 422 case APIC_DM_EXTINT:
423 /*
424 * Should only be called by kvm_apic_local_deliver() with LVT0,
425 * before NMI watchdog was enabled. Already handled by
426 * kvm_apic_accept_pic_intr().
427 */
428 break;
429
97222cc8
ED		 430 default:
431 printk(KERN_ERR "TODO: unsupported delivery mode %x\n",
432 delivery_mode);
433 break;
434 }
435 return result;
436}
437
e1035715 438int kvm_apic_compare_prio(struct kvm_vcpu *vcpu1, struct kvm_vcpu *vcpu2)
8be5453f 439{
e1035715 440 return vcpu1->arch.apic_arb_prio - vcpu2->arch.apic_arb_prio;
8be5453f
ZX		 441}
442
97222cc8
ED		 443static void apic_set_eoi(struct kvm_lapic *apic)
444{
445 int vector = apic_find_highest_isr(apic);
f5244726 446 int trigger_mode;
97222cc8
ED		 447 /*
448 * Not every write EOI will has corresponding ISR,
449 * one example is when Kernel check timer on setup_IO_APIC
450 */
451 if (vector == -1)
452 return;
453
454 apic_clear_vector(vector, apic->regs + APIC_ISR);
455 apic_update_ppr(apic);
456
457 if (apic_test_and_clear_vector(vector, apic->regs + APIC_TMR))
f5244726
MT		 458 trigger_mode = IOAPIC_LEVEL_TRIG;
459 else
460 trigger_mode = IOAPIC_EDGE_TRIG;
fc61b800
GN		 461 if (!(apic_get_reg(apic, APIC_SPIV) & APIC_SPIV_DIRECTED_EOI)) {
462 mutex_lock(&apic->vcpu->kvm->irq_lock);
463 kvm_ioapic_update_eoi(apic->vcpu->kvm, vector, trigger_mode);
464 mutex_unlock(&apic->vcpu->kvm->irq_lock);
465 }
97222cc8
ED		 466}
467
468static void apic_send_ipi(struct kvm_lapic *apic)
469{
470 u32 icr_low = apic_get_reg(apic, APIC_ICR);
471 u32 icr_high = apic_get_reg(apic, APIC_ICR2);
58c2dde1 472 struct kvm_lapic_irq irq;
97222cc8 473
58c2dde1
GN		 474 irq.vector = icr_low & APIC_VECTOR_MASK;
475 irq.delivery_mode = icr_low & APIC_MODE_MASK;
476 irq.dest_mode = icr_low & APIC_DEST_MASK;
477 irq.level = icr_low & APIC_INT_ASSERT;
478 irq.trig_mode = icr_low & APIC_INT_LEVELTRIG;
479 irq.shorthand = icr_low & APIC_SHORT_MASK;
480 irq.dest_id = GET_APIC_DEST_FIELD(icr_high);
97222cc8
ED		 481
482 apic_debug("icr_high 0x%x, icr_low 0x%x, "
483 "short_hand 0x%x, dest 0x%x, trig_mode 0x%x, level 0x%x, "
484 "dest_mode 0x%x, delivery_mode 0x%x, vector 0x%x\n",
9b5843dd 485 icr_high, icr_low, irq.shorthand, irq.dest_id,
58c2dde1
GN		 486 irq.trig_mode, irq.level, irq.dest_mode, irq.delivery_mode,
487 irq.vector);
488
fa40a821 489 mutex_lock(&apic->vcpu->kvm->irq_lock);
58c2dde1 490 kvm_irq_delivery_to_apic(apic->vcpu->kvm, apic, &irq);
fa40a821 491 mutex_unlock(&apic->vcpu->kvm->irq_lock);
97222cc8
ED		 492}
493
494static u32 apic_get_tmcct(struct kvm_lapic *apic)
495{
b682b814
MT		 496 ktime_t remaining;
497 s64 ns;
9da8f4e8 498 u32 tmcct;
97222cc8
ED		 499
500 ASSERT(apic != NULL);
501
9da8f4e8 502 /* if initial count is 0, current count should also be 0 */
b682b814 503 if (apic_get_reg(apic, APIC_TMICT) == 0)
9da8f4e8
KP		 504 return 0;
505
d3c7b77d 506 remaining = hrtimer_expires_remaining(&apic->lapic_timer.timer);
b682b814
MT		 507 if (ktime_to_ns(remaining) < 0)
508 remaining = ktime_set(0, 0);
509
d3c7b77d
MT		 510 ns = mod_64(ktime_to_ns(remaining), apic->lapic_timer.period);
511 tmcct = div64_u64(ns,
512 (APIC_BUS_CYCLE_NS * apic->divide_count));
97222cc8
ED		 513
514 return tmcct;
515}
516
b209749f
AK		 517static void __report_tpr_access(struct kvm_lapic *apic, bool write)
518{
519 struct kvm_vcpu *vcpu = apic->vcpu;
520 struct kvm_run *run = vcpu->run;
521
522 set_bit(KVM_REQ_REPORT_TPR_ACCESS, &vcpu->requests);
5fdbf976 523 run->tpr_access.rip = kvm_rip_read(vcpu);
b209749f
AK		 524 run->tpr_access.is_write = write;
525}
526
527static inline void report_tpr_access(struct kvm_lapic *apic, bool write)
528{
529 if (apic->vcpu->arch.tpr_access_reporting)
530 __report_tpr_access(apic, write);
531}
532
97222cc8
ED		 533static u32 __apic_read(struct kvm_lapic *apic, unsigned int offset)
534{
535 u32 val = 0;
536
537 if (offset >= LAPIC_MMIO_LENGTH)
538 return 0;
539
540 switch (offset) {
541 case APIC_ARBPRI:
542 printk(KERN_WARNING "Access APIC ARBPRI register "
543 "which is for P6\n");
544 break;
545
546 case APIC_TMCCT: /* Timer CCR */
547 val = apic_get_tmcct(apic);
548 break;
549
b209749f
AK		 550 case APIC_TASKPRI:
551 report_tpr_access(apic, false);
552 /* fall thru */
97222cc8 553 default:
6e5d865c 554 apic_update_ppr(apic);
97222cc8
ED		 555 val = apic_get_reg(apic, offset);
556 break;
557 }
558
559 return val;
560}
561
d76685c4
GH		 562static inline struct kvm_lapic *to_lapic(struct kvm_io_device *dev)
563{
564 return container_of(dev, struct kvm_lapic, dev);
565}
566
bda9020e
MT		 567static int apic_mmio_in_range(struct kvm_lapic *apic, gpa_t addr)
568{
569 return apic_hw_enabled(apic) &&
570 addr >= apic->base_address &&
571 addr < apic->base_address + LAPIC_MMIO_LENGTH;
572}
573
574static int apic_mmio_read(struct kvm_io_device *this,
575 gpa_t address, int len, void *data)
97222cc8 576{
d76685c4 577 struct kvm_lapic *apic = to_lapic(this);
97222cc8
ED		 578 unsigned int offset = address - apic->base_address;
579 unsigned char alignment = offset & 0xf;
580 u32 result;
bda9020e
MT		 581 if (!apic_mmio_in_range(apic, address))
582 return -EOPNOTSUPP;
97222cc8
ED		 583
584 if ((alignment + len) > 4) {
585 printk(KERN_ERR "KVM_APIC_READ: alignment error %lx %d",
586 (unsigned long)address, len);
bda9020e 587 return 0;
97222cc8
ED		 588 }
589 result = __apic_read(apic, offset & ~0xf);
590
229456fc
MT		 591 trace_kvm_apic_read(offset, result);
592
97222cc8
ED		 593 switch (len) {
594 case 1:
595 case 2:
596 case 4:
597 memcpy(data, (char *)&result + alignment, len);
598 break;
599 default:
600 printk(KERN_ERR "Local APIC read with len = %x, "
601 "should be 1,2, or 4 instead\n", len);
602 break;
603 }
bda9020e 604 return 0;
97222cc8
ED		 605}
606
607static void update_divide_count(struct kvm_lapic *apic)
608{
609 u32 tmp1, tmp2, tdcr;
610
611 tdcr = apic_get_reg(apic, APIC_TDCR);
612 tmp1 = tdcr & 0xf;
613 tmp2 = ((tmp1 & 0x3) | ((tmp1 & 0x8) >> 1)) + 1;
d3c7b77d 614 apic->divide_count = 0x1 << (tmp2 & 0x7);
97222cc8
ED		 615
616 apic_debug("timer divide count is 0x%x\n",
9b5843dd 617 apic->divide_count);
97222cc8
ED		 618}
619
620static void start_apic_timer(struct kvm_lapic *apic)
621{
d3c7b77d 622 ktime_t now = apic->lapic_timer.timer.base->get_time();
97222cc8 623
d3c7b77d
MT		 624 apic->lapic_timer.period = apic_get_reg(apic, APIC_TMICT) *
625 APIC_BUS_CYCLE_NS * apic->divide_count;
626 atomic_set(&apic->lapic_timer.pending, 0);
0b975a3c 627
d3c7b77d 628 if (!apic->lapic_timer.period)
0b975a3c
AK		 629 return;
630
d3c7b77d
MT		 631 hrtimer_start(&apic->lapic_timer.timer,
632 ktime_add_ns(now, apic->lapic_timer.period),
97222cc8
ED		 633 HRTIMER_MODE_ABS);
634
635 apic_debug("%s: bus cycle is %" PRId64 "ns, now 0x%016"
636 PRIx64 ", "
637 "timer initial count 0x%x, period %lldns, "
b8688d51 638 "expire @ 0x%016" PRIx64 ".\n", __func__,
97222cc8
ED		 639 APIC_BUS_CYCLE_NS, ktime_to_ns(now),
640 apic_get_reg(apic, APIC_TMICT),
d3c7b77d 641 apic->lapic_timer.period,
97222cc8 642 ktime_to_ns(ktime_add_ns(now,
d3c7b77d 643 apic->lapic_timer.period)));
97222cc8
ED		 644}
645
cc6e462c
JK		 646static void apic_manage_nmi_watchdog(struct kvm_lapic *apic, u32 lvt0_val)
647{
648 int nmi_wd_enabled = apic_lvt_nmi_mode(apic_get_reg(apic, APIC_LVT0));
649
650 if (apic_lvt_nmi_mode(lvt0_val)) {
651 if (!nmi_wd_enabled) {
652 apic_debug("Receive NMI setting on APIC_LVT0 "
653 "for cpu %d\n", apic->vcpu->vcpu_id);
654 apic->vcpu->kvm->arch.vapics_in_nmi_mode++;
655 }
656 } else if (nmi_wd_enabled)
657 apic->vcpu->kvm->arch.vapics_in_nmi_mode--;
658}
659
bda9020e
MT		 660static int apic_mmio_write(struct kvm_io_device *this,
661 gpa_t address, int len, const void *data)
97222cc8 662{
d76685c4 663 struct kvm_lapic *apic = to_lapic(this);
97222cc8
ED		 664 unsigned int offset = address - apic->base_address;
665 unsigned char alignment = offset & 0xf;
666 u32 val;
bda9020e
MT		 667 if (!apic_mmio_in_range(apic, address))
668 return -EOPNOTSUPP;
97222cc8
ED		 669
670 /*
671 * APIC register must be aligned on 128-bits boundary.
672 * 32/64/128 bits registers must be accessed thru 32 bits.
673 * Refer SDM 8.4.1
674 */
675 if (len != 4 || alignment) {
1b10bf31
JK		 676 /* Don't shout loud, $infamous_os would cause only noise. */
677 apic_debug("apic write: bad size=%d %lx\n",
678 len, (long)address);
bda9020e 679 return 0;
97222cc8
ED		 680 }
681
682 val = *(u32 *) data;
683
684 /* too common printing */
685 if (offset != APIC_EOI)
686 apic_debug("%s: offset 0x%x with length 0x%x, and value is "
b8688d51 687 "0x%x\n", __func__, offset, len, val);
97222cc8
ED		 688
689 offset &= 0xff0;
690
229456fc 691 trace_kvm_apic_write(offset, val);
c7bf23ba 692
97222cc8
ED		 693 switch (offset) {
694 case APIC_ID: /* Local APIC ID */
695 apic_set_reg(apic, APIC_ID, val);
696 break;
697
698 case APIC_TASKPRI:
b209749f 699 report_tpr_access(apic, true);
97222cc8
ED		 700 apic_set_tpr(apic, val & 0xff);
701 break;
702
703 case APIC_EOI:
704 apic_set_eoi(apic);
705 break;
706
707 case APIC_LDR:
708 apic_set_reg(apic, APIC_LDR, val & APIC_LDR_MASK);
709 break;
710
711 case APIC_DFR:
712 apic_set_reg(apic, APIC_DFR, val | 0x0FFFFFFF);
713 break;
714
fc61b800
GN		 715 case APIC_SPIV: {
716 u32 mask = 0x3ff;
717 if (apic_get_reg(apic, APIC_LVR) & APIC_LVR_DIRECTED_EOI)
718 mask |= APIC_SPIV_DIRECTED_EOI;
719 apic_set_reg(apic, APIC_SPIV, val & mask);
97222cc8
ED		 720 if (!(val & APIC_SPIV_APIC_ENABLED)) {
721 int i;
722 u32 lvt_val;
723
724 for (i = 0; i < APIC_LVT_NUM; i++) {
725 lvt_val = apic_get_reg(apic,
726 APIC_LVTT + 0x10 * i);
727 apic_set_reg(apic, APIC_LVTT + 0x10 * i,
728 lvt_val | APIC_LVT_MASKED);
729 }
d3c7b77d 730 atomic_set(&apic->lapic_timer.pending, 0);
97222cc8
ED		 731
732 }
733 break;
fc61b800 734 }
97222cc8
ED		 735 case APIC_ICR:
736 /* No delay here, so we always clear the pending bit */
737 apic_set_reg(apic, APIC_ICR, val & ~(1 << 12));
738 apic_send_ipi(apic);
739 break;
740
741 case APIC_ICR2:
742 apic_set_reg(apic, APIC_ICR2, val & 0xff000000);
743 break;
744
23930f95 745 case APIC_LVT0:
cc6e462c 746 apic_manage_nmi_watchdog(apic, val);
97222cc8
ED		 747 case APIC_LVTT:
748 case APIC_LVTTHMR:
749 case APIC_LVTPC:
97222cc8
ED		 750 case APIC_LVT1:
751 case APIC_LVTERR:
752 /* TODO: Check vector */
753 if (!apic_sw_enabled(apic))
754 val |= APIC_LVT_MASKED;
755
756 val &= apic_lvt_mask[(offset - APIC_LVTT) >> 4];
757 apic_set_reg(apic, offset, val);
758
759 break;
760
761 case APIC_TMICT:
d3c7b77d 762 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 763 apic_set_reg(apic, APIC_TMICT, val);
764 start_apic_timer(apic);
bda9020e 765 return 0;
97222cc8
ED		 766
767 case APIC_TDCR:
768 if (val & 4)
769 printk(KERN_ERR "KVM_WRITE:TDCR %x\n", val);
770 apic_set_reg(apic, APIC_TDCR, val);
771 update_divide_count(apic);
772 break;
773
774 default:
775 apic_debug("Local APIC Write to read-only register %x\n",
776 offset);
777 break;
778 }
bda9020e 779 return 0;
97222cc8
ED		 780}
781
d589444e 782void kvm_free_lapic(struct kvm_vcpu *vcpu)
97222cc8 783{
ad312c7c 784 if (!vcpu->arch.apic)
97222cc8
ED		 785 return;
786
d3c7b77d 787 hrtimer_cancel(&vcpu->arch.apic->lapic_timer.timer);
97222cc8 788
ad312c7c
ZX		 789 if (vcpu->arch.apic->regs_page)
790 __free_page(vcpu->arch.apic->regs_page);
97222cc8 791
ad312c7c 792 kfree(vcpu->arch.apic);
97222cc8
ED		 793}
794
795/*
796 *----------------------------------------------------------------------
797 * LAPIC interface
798 *----------------------------------------------------------------------
799 */
800
801void kvm_lapic_set_tpr(struct kvm_vcpu *vcpu, unsigned long cr8)
802{
ad312c7c 803 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 804
805 if (!apic)
806 return;
b93463aa
AK		 807 apic_set_tpr(apic, ((cr8 & 0x0f) << 4)
808 | (apic_get_reg(apic, APIC_TASKPRI) & 4));
97222cc8
ED		 809}
810
811u64 kvm_lapic_get_cr8(struct kvm_vcpu *vcpu)
812{
ad312c7c 813 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 814 u64 tpr;
815
816 if (!apic)
817 return 0;
818 tpr = (u64) apic_get_reg(apic, APIC_TASKPRI);
819
820 return (tpr & 0xf0) >> 4;
821}
822
823void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
824{
ad312c7c 825 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 826
827 if (!apic) {
828 value |= MSR_IA32_APICBASE_BSP;
ad312c7c 829 vcpu->arch.apic_base = value;
97222cc8
ED		 830 return;
831 }
c5af89b6
GN		 832
833 if (!kvm_vcpu_is_bsp(apic->vcpu))
97222cc8
ED		 834 value &= ~MSR_IA32_APICBASE_BSP;
835
ad312c7c
ZX		 836 vcpu->arch.apic_base = value;
837 apic->base_address = apic->vcpu->arch.apic_base &
97222cc8
ED		 838 MSR_IA32_APICBASE_BASE;
839
840 /* with FSB delivery interrupt, we can restart APIC functionality */
841 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
ad312c7c 842 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 843
844}
845
c5ec1534 846void kvm_lapic_reset(struct kvm_vcpu *vcpu)
97222cc8
ED		 847{
848 struct kvm_lapic *apic;
849 int i;
850
b8688d51 851 apic_debug("%s\n", __func__);
97222cc8
ED		 852
853 ASSERT(vcpu);
ad312c7c 854 apic = vcpu->arch.apic;
97222cc8
ED		 855 ASSERT(apic != NULL);
856
857 /* Stop the timer in case it's a reset to an active apic */
d3c7b77d 858 hrtimer_cancel(&apic->lapic_timer.timer);
97222cc8
ED		 859
860 apic_set_reg(apic, APIC_ID, vcpu->vcpu_id << 24);
fc61b800 861 kvm_apic_set_version(apic->vcpu);
97222cc8
ED		 862
863 for (i = 0; i < APIC_LVT_NUM; i++)
864 apic_set_reg(apic, APIC_LVTT + 0x10 * i, APIC_LVT_MASKED);
40487c68
QH		 865 apic_set_reg(apic, APIC_LVT0,
866 SET_APIC_DELIVERY_MODE(0, APIC_MODE_EXTINT));
97222cc8
ED		 867
868 apic_set_reg(apic, APIC_DFR, 0xffffffffU);
869 apic_set_reg(apic, APIC_SPIV, 0xff);
870 apic_set_reg(apic, APIC_TASKPRI, 0);
871 apic_set_reg(apic, APIC_LDR, 0);
872 apic_set_reg(apic, APIC_ESR, 0);
873 apic_set_reg(apic, APIC_ICR, 0);
874 apic_set_reg(apic, APIC_ICR2, 0);
875 apic_set_reg(apic, APIC_TDCR, 0);
876 apic_set_reg(apic, APIC_TMICT, 0);
877 for (i = 0; i < 8; i++) {
878 apic_set_reg(apic, APIC_IRR + 0x10 * i, 0);
879 apic_set_reg(apic, APIC_ISR + 0x10 * i, 0);
880 apic_set_reg(apic, APIC_TMR + 0x10 * i, 0);
881 }
33e4c686 882 apic->irr_pending = false;
b33ac88b 883 update_divide_count(apic);
d3c7b77d 884 atomic_set(&apic->lapic_timer.pending, 0);
c5af89b6 885 if (kvm_vcpu_is_bsp(vcpu))
ad312c7c 886 vcpu->arch.apic_base |= MSR_IA32_APICBASE_BSP;
97222cc8
ED		 887 apic_update_ppr(apic);
888
e1035715
GN		 889 vcpu->arch.apic_arb_prio = 0;
890
97222cc8 891 apic_debug(KERN_INFO "%s: vcpu=%p, id=%d, base_msr="
b8688d51 892 "0x%016" PRIx64 ", base_address=0x%0lx.\n", __func__,
97222cc8 893 vcpu, kvm_apic_id(apic),
ad312c7c 894 vcpu->arch.apic_base, apic->base_address);
97222cc8
ED		 895}
896
343f94fe 897bool kvm_apic_present(struct kvm_vcpu *vcpu)
97222cc8 898{
343f94fe
GN		 899 return vcpu->arch.apic && apic_hw_enabled(vcpu->arch.apic);
900}
97222cc8 901
343f94fe
GN		 902int kvm_lapic_enabled(struct kvm_vcpu *vcpu)
903{
904 return kvm_apic_present(vcpu) && apic_sw_enabled(vcpu->arch.apic);
97222cc8
ED		 905}
906
907/*
908 *----------------------------------------------------------------------
909 * timer interface
910 *----------------------------------------------------------------------
911 */
1b9778da 912
d3c7b77d 913static bool lapic_is_periodic(struct kvm_timer *ktimer)
97222cc8 914{
d3c7b77d
MT		 915 struct kvm_lapic *apic = container_of(ktimer, struct kvm_lapic,
916 lapic_timer);
917 return apic_lvtt_period(apic);
97222cc8
ED		 918}
919
3d80840d
MT		 920int apic_has_pending_timer(struct kvm_vcpu *vcpu)
921{
922 struct kvm_lapic *lapic = vcpu->arch.apic;
923
54aaacee 924 if (lapic && apic_enabled(lapic) && apic_lvt_enabled(lapic, APIC_LVTT))
d3c7b77d 925 return atomic_read(&lapic->lapic_timer.pending);
3d80840d
MT		 926
927 return 0;
928}
929
8fdb2351 930static int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type)
1b9778da 931{
8fdb2351 932 u32 reg = apic_get_reg(apic, lvt_type);
23930f95 933 int vector, mode, trig_mode;
23930f95 934
8fdb2351 935 if (apic_hw_enabled(apic) && !(reg & APIC_LVT_MASKED)) {
23930f95
JK		 936 vector = reg & APIC_VECTOR_MASK;
937 mode = reg & APIC_MODE_MASK;
938 trig_mode = reg & APIC_LVT_LEVEL_TRIGGER;
939 return __apic_accept_irq(apic, mode, vector, 1, trig_mode);
940 }
941 return 0;
942}
1b9778da 943
8fdb2351 944void kvm_apic_nmi_wd_deliver(struct kvm_vcpu *vcpu)
23930f95 945{
8fdb2351
JK		 946 struct kvm_lapic *apic = vcpu->arch.apic;
947
948 if (apic)
949 kvm_apic_local_deliver(apic, APIC_LVT0);
1b9778da
ED		 950}
951
386eb6e8 952static struct kvm_timer_ops lapic_timer_ops = {
d3c7b77d
MT		 953 .is_periodic = lapic_is_periodic,
954};
97222cc8 955
d76685c4
GH		 956static const struct kvm_io_device_ops apic_mmio_ops = {
957 .read = apic_mmio_read,
958 .write = apic_mmio_write,
d76685c4
GH		 959};
960
97222cc8
ED		 961int kvm_create_lapic(struct kvm_vcpu *vcpu)
962{
963 struct kvm_lapic *apic;
964
965 ASSERT(vcpu != NULL);
966 apic_debug("apic_init %d\n", vcpu->vcpu_id);
967
968 apic = kzalloc(sizeof(*apic), GFP_KERNEL);
969 if (!apic)
970 goto nomem;
971
ad312c7c 972 vcpu->arch.apic = apic;
97222cc8
ED		 973
974 apic->regs_page = alloc_page(GFP_KERNEL);
975 if (apic->regs_page == NULL) {
976 printk(KERN_ERR "malloc apic regs error for vcpu %x\n",
977 vcpu->vcpu_id);
d589444e 978 goto nomem_free_apic;
97222cc8
ED		 979 }
980 apic->regs = page_address(apic->regs_page);
981 memset(apic->regs, 0, PAGE_SIZE);
982 apic->vcpu = vcpu;
983
d3c7b77d
MT		 984 hrtimer_init(&apic->lapic_timer.timer, CLOCK_MONOTONIC,
985 HRTIMER_MODE_ABS);
986 apic->lapic_timer.timer.function = kvm_timer_fn;
987 apic->lapic_timer.t_ops = &lapic_timer_ops;
988 apic->lapic_timer.kvm = vcpu->kvm;
1ed0ce00 989 apic->lapic_timer.vcpu = vcpu;
d3c7b77d 990
97222cc8 991 apic->base_address = APIC_DEFAULT_PHYS_BASE;
ad312c7c 992 vcpu->arch.apic_base = APIC_DEFAULT_PHYS_BASE;
97222cc8 993
c5ec1534 994 kvm_lapic_reset(vcpu);
d76685c4 995 kvm_iodevice_init(&apic->dev, &apic_mmio_ops);
97222cc8
ED		 996
997 return 0;
d589444e
RR		 998nomem_free_apic:
999 kfree(apic);
97222cc8 1000nomem:
97222cc8
ED		 1001 return -ENOMEM;
1002}
97222cc8
ED		 1003
1004int kvm_apic_has_interrupt(struct kvm_vcpu *vcpu)
1005{
ad312c7c 1006 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1007 int highest_irr;
1008
1009 if (!apic || !apic_enabled(apic))
1010 return -1;
1011
6e5d865c 1012 apic_update_ppr(apic);
97222cc8
ED		 1013 highest_irr = apic_find_highest_irr(apic);
1014 if ((highest_irr == -1) ||
1015 ((highest_irr & 0xF0) <= apic_get_reg(apic, APIC_PROCPRI)))
1016 return -1;
1017 return highest_irr;
1018}
1019
40487c68
QH		 1020int kvm_apic_accept_pic_intr(struct kvm_vcpu *vcpu)
1021{
ad312c7c 1022 u32 lvt0 = apic_get_reg(vcpu->arch.apic, APIC_LVT0);
40487c68
QH		 1023 int r = 0;
1024
c5af89b6 1025 if (kvm_vcpu_is_bsp(vcpu)) {
ad312c7c 1026 if (!apic_hw_enabled(vcpu->arch.apic))
40487c68
QH		 1027 r = 1;
1028 if ((lvt0 & APIC_LVT_MASKED) == 0 &&
1029 GET_APIC_DELIVERY_MODE(lvt0) == APIC_MODE_EXTINT)
1030 r = 1;
1031 }
1032 return r;
1033}
1034
1b9778da
ED		 1035void kvm_inject_apic_timer_irqs(struct kvm_vcpu *vcpu)
1036{
ad312c7c 1037 struct kvm_lapic *apic = vcpu->arch.apic;
1b9778da 1038
d3c7b77d 1039 if (apic && atomic_read(&apic->lapic_timer.pending) > 0) {
8fdb2351 1040 if (kvm_apic_local_deliver(apic, APIC_LVTT))
d3c7b77d 1041 atomic_dec(&apic->lapic_timer.pending);
1b9778da
ED		 1042 }
1043}
1044
97222cc8
ED		 1045int kvm_get_apic_interrupt(struct kvm_vcpu *vcpu)
1046{
1047 int vector = kvm_apic_has_interrupt(vcpu);
ad312c7c 1048 struct kvm_lapic *apic = vcpu->arch.apic;
97222cc8
ED		 1049
1050 if (vector == -1)
1051 return -1;
1052
1053 apic_set_vector(vector, apic->regs + APIC_ISR);
1054 apic_update_ppr(apic);
1055 apic_clear_irr(vector, apic);
1056 return vector;
1057}
96ad2cc6
ED		 1058
1059void kvm_apic_post_state_restore(struct kvm_vcpu *vcpu)
1060{
ad312c7c 1061 struct kvm_lapic *apic = vcpu->arch.apic;
96ad2cc6 1062
ad312c7c 1063 apic->base_address = vcpu->arch.apic_base &
96ad2cc6 1064 MSR_IA32_APICBASE_BASE;
fc61b800
GN		 1065 kvm_apic_set_version(vcpu);
1066
96ad2cc6 1067 apic_update_ppr(apic);
d3c7b77d 1068 hrtimer_cancel(&apic->lapic_timer.timer);
96ad2cc6
ED		 1069 update_divide_count(apic);
1070 start_apic_timer(apic);
1071}
a3d7f85f 1072
2f52d58c 1073void __kvm_migrate_apic_timer(struct kvm_vcpu *vcpu)
a3d7f85f 1074{
ad312c7c 1075 struct kvm_lapic *apic = vcpu->arch.apic;
a3d7f85f
ED		 1076 struct hrtimer *timer;
1077
1078 if (!apic)
1079 return;
1080
d3c7b77d 1081 timer = &apic->lapic_timer.timer;
a3d7f85f 1082 if (hrtimer_cancel(timer))
beb20d52 1083 hrtimer_start_expires(timer, HRTIMER_MODE_ABS);
a3d7f85f 1084}
b93463aa
AK		 1085
1086void kvm_lapic_sync_from_vapic(struct kvm_vcpu *vcpu)
1087{
1088 u32 data;
1089 void *vapic;
1090
1091 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1092 return;
1093
1094 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1095 data = *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr));
1096 kunmap_atomic(vapic, KM_USER0);
1097
1098 apic_set_tpr(vcpu->arch.apic, data & 0xff);
1099}
1100
1101void kvm_lapic_sync_to_vapic(struct kvm_vcpu *vcpu)
1102{
1103 u32 data, tpr;
1104 int max_irr, max_isr;
1105 struct kvm_lapic *apic;
1106 void *vapic;
1107
1108 if (!irqchip_in_kernel(vcpu->kvm) || !vcpu->arch.apic->vapic_addr)
1109 return;
1110
1111 apic = vcpu->arch.apic;
1112 tpr = apic_get_reg(apic, APIC_TASKPRI) & 0xff;
1113 max_irr = apic_find_highest_irr(apic);
1114 if (max_irr < 0)
1115 max_irr = 0;
1116 max_isr = apic_find_highest_isr(apic);
1117 if (max_isr < 0)
1118 max_isr = 0;
1119 data = (tpr & 0xff) | ((max_isr & 0xf0) << 8) | (max_irr << 24);
1120
1121 vapic = kmap_atomic(vcpu->arch.apic->vapic_page, KM_USER0);
1122 *(u32 *)(vapic + offset_in_page(vcpu->arch.apic->vapic_addr)) = data;
1123 kunmap_atomic(vapic, KM_USER0);
1124}
1125
1126void kvm_lapic_set_vapic_addr(struct kvm_vcpu *vcpu, gpa_t vapic_addr)
1127{
1128 if (!irqchip_in_kernel(vcpu->kvm))
1129 return;
1130
1131 vcpu->arch.apic->vapic_addr = vapic_addr;
1132}
A mirror of Linus' kernel repository