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Commit | Line | Data |
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6aa8b732 AK |
1 | /* |
2 | * Kernel-based Virtual Machine driver for Linux | |
3 | * | |
4 | * This module enables machines with Intel VT-x extensions to run virtual | |
5 | * machines without emulation or binary translation. | |
6 | * | |
7 | * MMU support | |
8 | * | |
9 | * Copyright (C) 2006 Qumranet, Inc. | |
9611c187 | 10 | * Copyright 2010 Red Hat, Inc. and/or its affiliates. |
6aa8b732 AK |
11 | * |
12 | * Authors: | |
13 | * Yaniv Kamay <yaniv@qumranet.com> | |
14 | * Avi Kivity <avi@qumranet.com> | |
15 | * | |
16 | * This work is licensed under the terms of the GNU GPL, version 2. See | |
17 | * the COPYING file in the top-level directory. | |
18 | * | |
19 | */ | |
e495606d | 20 | |
af585b92 | 21 | #include "irq.h" |
1d737c8a | 22 | #include "mmu.h" |
836a1b3c | 23 | #include "x86.h" |
6de4f3ad | 24 | #include "kvm_cache_regs.h" |
5f7dde7b | 25 | #include "cpuid.h" |
e495606d | 26 | |
edf88417 | 27 | #include <linux/kvm_host.h> |
6aa8b732 AK |
28 | #include <linux/types.h> |
29 | #include <linux/string.h> | |
6aa8b732 AK |
30 | #include <linux/mm.h> |
31 | #include <linux/highmem.h> | |
1767e931 PG |
32 | #include <linux/moduleparam.h> |
33 | #include <linux/export.h> | |
448353ca | 34 | #include <linux/swap.h> |
05da4558 | 35 | #include <linux/hugetlb.h> |
2f333bcb | 36 | #include <linux/compiler.h> |
bc6678a3 | 37 | #include <linux/srcu.h> |
5a0e3ad6 | 38 | #include <linux/slab.h> |
3f07c014 | 39 | #include <linux/sched/signal.h> |
bf998156 | 40 | #include <linux/uaccess.h> |
114df303 | 41 | #include <linux/hash.h> |
f160c7b7 | 42 | #include <linux/kern_levels.h> |
6aa8b732 | 43 | |
e495606d | 44 | #include <asm/page.h> |
aa2e063a | 45 | #include <asm/pat.h> |
e495606d | 46 | #include <asm/cmpxchg.h> |
4e542370 | 47 | #include <asm/io.h> |
13673a90 | 48 | #include <asm/vmx.h> |
3d0c27ad | 49 | #include <asm/kvm_page_track.h> |
1261bfa3 | 50 | #include "trace.h" |
6aa8b732 | 51 | |
18552672 JR |
52 | /* |
53 | * When setting this variable to true it enables Two-Dimensional-Paging | |
54 | * where the hardware walks 2 page tables: | |
55 | * 1. the guest-virtual to guest-physical | |
56 | * 2. while doing 1. it walks guest-physical to host-physical | |
57 | * If the hardware supports that we don't need to do shadow paging. | |
58 | */ | |
2f333bcb | 59 | bool tdp_enabled = false; |
18552672 | 60 | |
8b1fe17c XG |
61 | enum { |
62 | AUDIT_PRE_PAGE_FAULT, | |
63 | AUDIT_POST_PAGE_FAULT, | |
64 | AUDIT_PRE_PTE_WRITE, | |
6903074c XG |
65 | AUDIT_POST_PTE_WRITE, |
66 | AUDIT_PRE_SYNC, | |
67 | AUDIT_POST_SYNC | |
8b1fe17c | 68 | }; |
37a7d8b0 | 69 | |
8b1fe17c | 70 | #undef MMU_DEBUG |
37a7d8b0 AK |
71 | |
72 | #ifdef MMU_DEBUG | |
fa4a2c08 PB |
73 | static bool dbg = 0; |
74 | module_param(dbg, bool, 0644); | |
37a7d8b0 AK |
75 | |
76 | #define pgprintk(x...) do { if (dbg) printk(x); } while (0) | |
77 | #define rmap_printk(x...) do { if (dbg) printk(x); } while (0) | |
fa4a2c08 | 78 | #define MMU_WARN_ON(x) WARN_ON(x) |
37a7d8b0 | 79 | #else |
37a7d8b0 AK |
80 | #define pgprintk(x...) do { } while (0) |
81 | #define rmap_printk(x...) do { } while (0) | |
fa4a2c08 | 82 | #define MMU_WARN_ON(x) do { } while (0) |
d6c69ee9 | 83 | #endif |
6aa8b732 | 84 | |
957ed9ef XG |
85 | #define PTE_PREFETCH_NUM 8 |
86 | ||
00763e41 | 87 | #define PT_FIRST_AVAIL_BITS_SHIFT 10 |
6aa8b732 AK |
88 | #define PT64_SECOND_AVAIL_BITS_SHIFT 52 |
89 | ||
6aa8b732 AK |
90 | #define PT64_LEVEL_BITS 9 |
91 | ||
92 | #define PT64_LEVEL_SHIFT(level) \ | |
d77c26fc | 93 | (PAGE_SHIFT + (level - 1) * PT64_LEVEL_BITS) |
6aa8b732 | 94 | |
6aa8b732 AK |
95 | #define PT64_INDEX(address, level)\ |
96 | (((address) >> PT64_LEVEL_SHIFT(level)) & ((1 << PT64_LEVEL_BITS) - 1)) | |
97 | ||
98 | ||
99 | #define PT32_LEVEL_BITS 10 | |
100 | ||
101 | #define PT32_LEVEL_SHIFT(level) \ | |
d77c26fc | 102 | (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS) |
6aa8b732 | 103 | |
e04da980 JR |
104 | #define PT32_LVL_OFFSET_MASK(level) \ |
105 | (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
106 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
107 | |
108 | #define PT32_INDEX(address, level)\ | |
109 | (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1)) | |
110 | ||
111 | ||
8acc0993 KH |
112 | #ifdef CONFIG_DYNAMIC_PHYSICAL_MASK |
113 | #define PT64_BASE_ADDR_MASK (physical_mask & ~(u64)(PAGE_SIZE-1)) | |
114 | #else | |
115 | #define PT64_BASE_ADDR_MASK (((1ULL << 52) - 1) & ~(u64)(PAGE_SIZE-1)) | |
116 | #endif | |
e04da980 JR |
117 | #define PT64_LVL_ADDR_MASK(level) \ |
118 | (PT64_BASE_ADDR_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
119 | * PT64_LEVEL_BITS))) - 1)) | |
120 | #define PT64_LVL_OFFSET_MASK(level) \ | |
121 | (PT64_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
122 | * PT64_LEVEL_BITS))) - 1)) | |
6aa8b732 AK |
123 | |
124 | #define PT32_BASE_ADDR_MASK PAGE_MASK | |
125 | #define PT32_DIR_BASE_ADDR_MASK \ | |
126 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1)) | |
e04da980 JR |
127 | #define PT32_LVL_ADDR_MASK(level) \ |
128 | (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \ | |
129 | * PT32_LEVEL_BITS))) - 1)) | |
6aa8b732 | 130 | |
53166229 | 131 | #define PT64_PERM_MASK (PT_PRESENT_MASK | PT_WRITABLE_MASK | shadow_user_mask \ |
d0ec49d4 | 132 | | shadow_x_mask | shadow_nx_mask | shadow_me_mask) |
6aa8b732 | 133 | |
fe135d2c AK |
134 | #define ACC_EXEC_MASK 1 |
135 | #define ACC_WRITE_MASK PT_WRITABLE_MASK | |
136 | #define ACC_USER_MASK PT_USER_MASK | |
137 | #define ACC_ALL (ACC_EXEC_MASK | ACC_WRITE_MASK | ACC_USER_MASK) | |
138 | ||
f160c7b7 JS |
139 | /* The mask for the R/X bits in EPT PTEs */ |
140 | #define PT64_EPT_READABLE_MASK 0x1ull | |
141 | #define PT64_EPT_EXECUTABLE_MASK 0x4ull | |
142 | ||
90bb6fc5 AK |
143 | #include <trace/events/kvm.h> |
144 | ||
07420171 AK |
145 | #define CREATE_TRACE_POINTS |
146 | #include "mmutrace.h" | |
147 | ||
49fde340 XG |
148 | #define SPTE_HOST_WRITEABLE (1ULL << PT_FIRST_AVAIL_BITS_SHIFT) |
149 | #define SPTE_MMU_WRITEABLE (1ULL << (PT_FIRST_AVAIL_BITS_SHIFT + 1)) | |
1403283a | 150 | |
135f8c2b AK |
151 | #define SHADOW_PT_INDEX(addr, level) PT64_INDEX(addr, level) |
152 | ||
220f773a TY |
153 | /* make pte_list_desc fit well in cache line */ |
154 | #define PTE_LIST_EXT 3 | |
155 | ||
9b8ebbdb PB |
156 | /* |
157 | * Return values of handle_mmio_page_fault and mmu.page_fault: | |
158 | * RET_PF_RETRY: let CPU fault again on the address. | |
159 | * RET_PF_EMULATE: mmio page fault, emulate the instruction directly. | |
160 | * | |
161 | * For handle_mmio_page_fault only: | |
162 | * RET_PF_INVALID: the spte is invalid, let the real page fault path update it. | |
163 | */ | |
164 | enum { | |
165 | RET_PF_RETRY = 0, | |
166 | RET_PF_EMULATE = 1, | |
167 | RET_PF_INVALID = 2, | |
168 | }; | |
169 | ||
53c07b18 XG |
170 | struct pte_list_desc { |
171 | u64 *sptes[PTE_LIST_EXT]; | |
172 | struct pte_list_desc *more; | |
cd4a4e53 AK |
173 | }; |
174 | ||
2d11123a AK |
175 | struct kvm_shadow_walk_iterator { |
176 | u64 addr; | |
177 | hpa_t shadow_addr; | |
2d11123a | 178 | u64 *sptep; |
dd3bfd59 | 179 | int level; |
2d11123a AK |
180 | unsigned index; |
181 | }; | |
182 | ||
9fa72119 JS |
183 | static const union kvm_mmu_page_role mmu_base_role_mask = { |
184 | .cr0_wp = 1, | |
185 | .cr4_pae = 1, | |
186 | .nxe = 1, | |
187 | .smep_andnot_wp = 1, | |
188 | .smap_andnot_wp = 1, | |
189 | .smm = 1, | |
190 | .guest_mode = 1, | |
191 | .ad_disabled = 1, | |
192 | }; | |
193 | ||
7eb77e9f JS |
194 | #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \ |
195 | for (shadow_walk_init_using_root(&(_walker), (_vcpu), \ | |
196 | (_root), (_addr)); \ | |
197 | shadow_walk_okay(&(_walker)); \ | |
198 | shadow_walk_next(&(_walker))) | |
199 | ||
200 | #define for_each_shadow_entry(_vcpu, _addr, _walker) \ | |
2d11123a AK |
201 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ |
202 | shadow_walk_okay(&(_walker)); \ | |
203 | shadow_walk_next(&(_walker))) | |
204 | ||
c2a2ac2b XG |
205 | #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \ |
206 | for (shadow_walk_init(&(_walker), _vcpu, _addr); \ | |
207 | shadow_walk_okay(&(_walker)) && \ | |
208 | ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \ | |
209 | __shadow_walk_next(&(_walker), spte)) | |
210 | ||
53c07b18 | 211 | static struct kmem_cache *pte_list_desc_cache; |
d3d25b04 | 212 | static struct kmem_cache *mmu_page_header_cache; |
45221ab6 | 213 | static struct percpu_counter kvm_total_used_mmu_pages; |
b5a33a75 | 214 | |
7b52345e SY |
215 | static u64 __read_mostly shadow_nx_mask; |
216 | static u64 __read_mostly shadow_x_mask; /* mutual exclusive with nx_mask */ | |
217 | static u64 __read_mostly shadow_user_mask; | |
218 | static u64 __read_mostly shadow_accessed_mask; | |
219 | static u64 __read_mostly shadow_dirty_mask; | |
ce88decf | 220 | static u64 __read_mostly shadow_mmio_mask; |
dcdca5fe | 221 | static u64 __read_mostly shadow_mmio_value; |
ffb128c8 | 222 | static u64 __read_mostly shadow_present_mask; |
d0ec49d4 | 223 | static u64 __read_mostly shadow_me_mask; |
ce88decf | 224 | |
f160c7b7 | 225 | /* |
ac8d57e5 PF |
226 | * SPTEs used by MMUs without A/D bits are marked with shadow_acc_track_value. |
227 | * Non-present SPTEs with shadow_acc_track_value set are in place for access | |
228 | * tracking. | |
f160c7b7 JS |
229 | */ |
230 | static u64 __read_mostly shadow_acc_track_mask; | |
231 | static const u64 shadow_acc_track_value = SPTE_SPECIAL_MASK; | |
232 | ||
233 | /* | |
234 | * The mask/shift to use for saving the original R/X bits when marking the PTE | |
235 | * as not-present for access tracking purposes. We do not save the W bit as the | |
236 | * PTEs being access tracked also need to be dirty tracked, so the W bit will be | |
237 | * restored only when a write is attempted to the page. | |
238 | */ | |
239 | static const u64 shadow_acc_track_saved_bits_mask = PT64_EPT_READABLE_MASK | | |
240 | PT64_EPT_EXECUTABLE_MASK; | |
241 | static const u64 shadow_acc_track_saved_bits_shift = PT64_SECOND_AVAIL_BITS_SHIFT; | |
242 | ||
28a1f3ac JS |
243 | /* |
244 | * This mask must be set on all non-zero Non-Present or Reserved SPTEs in order | |
245 | * to guard against L1TF attacks. | |
246 | */ | |
247 | static u64 __read_mostly shadow_nonpresent_or_rsvd_mask; | |
248 | ||
249 | /* | |
250 | * The number of high-order 1 bits to use in the mask above. | |
251 | */ | |
252 | static const u64 shadow_nonpresent_or_rsvd_mask_len = 5; | |
253 | ||
daa07cbc SC |
254 | /* |
255 | * In some cases, we need to preserve the GFN of a non-present or reserved | |
256 | * SPTE when we usurp the upper five bits of the physical address space to | |
257 | * defend against L1TF, e.g. for MMIO SPTEs. To preserve the GFN, we'll | |
258 | * shift bits of the GFN that overlap with shadow_nonpresent_or_rsvd_mask | |
259 | * left into the reserved bits, i.e. the GFN in the SPTE will be split into | |
260 | * high and low parts. This mask covers the lower bits of the GFN. | |
261 | */ | |
262 | static u64 __read_mostly shadow_nonpresent_or_rsvd_lower_gfn_mask; | |
263 | ||
264 | ||
ce88decf | 265 | static void mmu_spte_set(u64 *sptep, u64 spte); |
9fa72119 JS |
266 | static union kvm_mmu_page_role |
267 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu); | |
ce88decf | 268 | |
40ef75a7 LT |
269 | |
270 | static inline bool kvm_available_flush_tlb_with_range(void) | |
271 | { | |
272 | return kvm_x86_ops->tlb_remote_flush_with_range; | |
273 | } | |
274 | ||
275 | static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm, | |
276 | struct kvm_tlb_range *range) | |
277 | { | |
278 | int ret = -ENOTSUPP; | |
279 | ||
280 | if (range && kvm_x86_ops->tlb_remote_flush_with_range) | |
281 | ret = kvm_x86_ops->tlb_remote_flush_with_range(kvm, range); | |
282 | ||
283 | if (ret) | |
284 | kvm_flush_remote_tlbs(kvm); | |
285 | } | |
286 | ||
287 | static void kvm_flush_remote_tlbs_with_address(struct kvm *kvm, | |
288 | u64 start_gfn, u64 pages) | |
289 | { | |
290 | struct kvm_tlb_range range; | |
291 | ||
292 | range.start_gfn = start_gfn; | |
293 | range.pages = pages; | |
294 | ||
295 | kvm_flush_remote_tlbs_with_range(kvm, &range); | |
296 | } | |
297 | ||
dcdca5fe | 298 | void kvm_mmu_set_mmio_spte_mask(u64 mmio_mask, u64 mmio_value) |
ce88decf | 299 | { |
dcdca5fe PF |
300 | BUG_ON((mmio_mask & mmio_value) != mmio_value); |
301 | shadow_mmio_value = mmio_value | SPTE_SPECIAL_MASK; | |
312b616b | 302 | shadow_mmio_mask = mmio_mask | SPTE_SPECIAL_MASK; |
ce88decf XG |
303 | } |
304 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mmio_spte_mask); | |
305 | ||
ac8d57e5 PF |
306 | static inline bool sp_ad_disabled(struct kvm_mmu_page *sp) |
307 | { | |
308 | return sp->role.ad_disabled; | |
309 | } | |
310 | ||
311 | static inline bool spte_ad_enabled(u64 spte) | |
312 | { | |
313 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
314 | return !(spte & shadow_acc_track_value); | |
315 | } | |
316 | ||
317 | static inline u64 spte_shadow_accessed_mask(u64 spte) | |
318 | { | |
319 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
320 | return spte_ad_enabled(spte) ? shadow_accessed_mask : 0; | |
321 | } | |
322 | ||
323 | static inline u64 spte_shadow_dirty_mask(u64 spte) | |
324 | { | |
325 | MMU_WARN_ON((spte & shadow_mmio_mask) == shadow_mmio_value); | |
326 | return spte_ad_enabled(spte) ? shadow_dirty_mask : 0; | |
327 | } | |
328 | ||
f160c7b7 JS |
329 | static inline bool is_access_track_spte(u64 spte) |
330 | { | |
ac8d57e5 | 331 | return !spte_ad_enabled(spte) && (spte & shadow_acc_track_mask) == 0; |
f160c7b7 JS |
332 | } |
333 | ||
f2fd125d | 334 | /* |
cae7ed3c SC |
335 | * Due to limited space in PTEs, the MMIO generation is a 19 bit subset of |
336 | * the memslots generation and is derived as follows: | |
ee3d1570 | 337 | * |
164bf7e5 SC |
338 | * Bits 0-8 of the MMIO generation are propagated to spte bits 3-11 |
339 | * Bits 9-18 of the MMIO generation are propagated to spte bits 52-61 | |
cae7ed3c | 340 | * |
164bf7e5 SC |
341 | * The KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS flag is intentionally not included in |
342 | * the MMIO generation number, as doing so would require stealing a bit from | |
343 | * the "real" generation number and thus effectively halve the maximum number | |
344 | * of MMIO generations that can be handled before encountering a wrap (which | |
345 | * requires a full MMU zap). The flag is instead explicitly queried when | |
346 | * checking for MMIO spte cache hits. | |
f2fd125d | 347 | */ |
164bf7e5 | 348 | #define MMIO_SPTE_GEN_MASK GENMASK_ULL(18, 0) |
cae7ed3c SC |
349 | |
350 | #define MMIO_SPTE_GEN_LOW_START 3 | |
351 | #define MMIO_SPTE_GEN_LOW_END 11 | |
352 | #define MMIO_SPTE_GEN_LOW_MASK GENMASK_ULL(MMIO_SPTE_GEN_LOW_END, \ | |
353 | MMIO_SPTE_GEN_LOW_START) | |
354 | ||
355 | #define MMIO_SPTE_GEN_HIGH_START 52 | |
356 | #define MMIO_SPTE_GEN_HIGH_END 61 | |
357 | #define MMIO_SPTE_GEN_HIGH_MASK GENMASK_ULL(MMIO_SPTE_GEN_HIGH_END, \ | |
358 | MMIO_SPTE_GEN_HIGH_START) | |
5192f9b9 | 359 | static u64 generation_mmio_spte_mask(u64 gen) |
f2fd125d XG |
360 | { |
361 | u64 mask; | |
362 | ||
cae7ed3c | 363 | WARN_ON(gen & ~MMIO_SPTE_GEN_MASK); |
f2fd125d | 364 | |
cae7ed3c SC |
365 | mask = (gen << MMIO_SPTE_GEN_LOW_START) & MMIO_SPTE_GEN_LOW_MASK; |
366 | mask |= (gen << MMIO_SPTE_GEN_HIGH_START) & MMIO_SPTE_GEN_HIGH_MASK; | |
f2fd125d XG |
367 | return mask; |
368 | } | |
369 | ||
5192f9b9 | 370 | static u64 get_mmio_spte_generation(u64 spte) |
f2fd125d | 371 | { |
5192f9b9 | 372 | u64 gen; |
f2fd125d XG |
373 | |
374 | spte &= ~shadow_mmio_mask; | |
375 | ||
cae7ed3c SC |
376 | gen = (spte & MMIO_SPTE_GEN_LOW_MASK) >> MMIO_SPTE_GEN_LOW_START; |
377 | gen |= (spte & MMIO_SPTE_GEN_HIGH_MASK) >> MMIO_SPTE_GEN_HIGH_START; | |
164bf7e5 | 378 | return gen; |
f8f55942 XG |
379 | } |
380 | ||
54bf36aa | 381 | static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn, |
f2fd125d | 382 | unsigned access) |
ce88decf | 383 | { |
cae7ed3c | 384 | u64 gen = kvm_vcpu_memslots(vcpu)->generation & MMIO_SPTE_GEN_MASK; |
f8f55942 | 385 | u64 mask = generation_mmio_spte_mask(gen); |
28a1f3ac | 386 | u64 gpa = gfn << PAGE_SHIFT; |
95b0430d | 387 | |
ce88decf | 388 | access &= ACC_WRITE_MASK | ACC_USER_MASK; |
28a1f3ac JS |
389 | mask |= shadow_mmio_value | access; |
390 | mask |= gpa | shadow_nonpresent_or_rsvd_mask; | |
391 | mask |= (gpa & shadow_nonpresent_or_rsvd_mask) | |
392 | << shadow_nonpresent_or_rsvd_mask_len; | |
f2fd125d | 393 | |
f8f55942 | 394 | trace_mark_mmio_spte(sptep, gfn, access, gen); |
f2fd125d | 395 | mmu_spte_set(sptep, mask); |
ce88decf XG |
396 | } |
397 | ||
398 | static bool is_mmio_spte(u64 spte) | |
399 | { | |
dcdca5fe | 400 | return (spte & shadow_mmio_mask) == shadow_mmio_value; |
ce88decf XG |
401 | } |
402 | ||
403 | static gfn_t get_mmio_spte_gfn(u64 spte) | |
404 | { | |
daa07cbc | 405 | u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask; |
28a1f3ac JS |
406 | |
407 | gpa |= (spte >> shadow_nonpresent_or_rsvd_mask_len) | |
408 | & shadow_nonpresent_or_rsvd_mask; | |
409 | ||
410 | return gpa >> PAGE_SHIFT; | |
ce88decf XG |
411 | } |
412 | ||
413 | static unsigned get_mmio_spte_access(u64 spte) | |
414 | { | |
cae7ed3c | 415 | u64 mask = generation_mmio_spte_mask(MMIO_SPTE_GEN_MASK) | shadow_mmio_mask; |
f2fd125d | 416 | return (spte & ~mask) & ~PAGE_MASK; |
ce88decf XG |
417 | } |
418 | ||
54bf36aa | 419 | static bool set_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
ba049e93 | 420 | kvm_pfn_t pfn, unsigned access) |
ce88decf XG |
421 | { |
422 | if (unlikely(is_noslot_pfn(pfn))) { | |
54bf36aa | 423 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
424 | return true; |
425 | } | |
426 | ||
427 | return false; | |
428 | } | |
c7addb90 | 429 | |
54bf36aa | 430 | static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte) |
f8f55942 | 431 | { |
cae7ed3c SC |
432 | u64 kvm_gen, spte_gen, gen; |
433 | ||
434 | gen = kvm_vcpu_memslots(vcpu)->generation; | |
435 | if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS)) | |
436 | return false; | |
089504c0 | 437 | |
cae7ed3c | 438 | kvm_gen = gen & MMIO_SPTE_GEN_MASK; |
089504c0 XG |
439 | spte_gen = get_mmio_spte_generation(spte); |
440 | ||
441 | trace_check_mmio_spte(spte, kvm_gen, spte_gen); | |
442 | return likely(kvm_gen == spte_gen); | |
f8f55942 XG |
443 | } |
444 | ||
ce00053b PF |
445 | /* |
446 | * Sets the shadow PTE masks used by the MMU. | |
447 | * | |
448 | * Assumptions: | |
449 | * - Setting either @accessed_mask or @dirty_mask requires setting both | |
450 | * - At least one of @accessed_mask or @acc_track_mask must be set | |
451 | */ | |
7b52345e | 452 | void kvm_mmu_set_mask_ptes(u64 user_mask, u64 accessed_mask, |
f160c7b7 | 453 | u64 dirty_mask, u64 nx_mask, u64 x_mask, u64 p_mask, |
d0ec49d4 | 454 | u64 acc_track_mask, u64 me_mask) |
7b52345e | 455 | { |
ce00053b PF |
456 | BUG_ON(!dirty_mask != !accessed_mask); |
457 | BUG_ON(!accessed_mask && !acc_track_mask); | |
ac8d57e5 | 458 | BUG_ON(acc_track_mask & shadow_acc_track_value); |
312b616b | 459 | |
7b52345e SY |
460 | shadow_user_mask = user_mask; |
461 | shadow_accessed_mask = accessed_mask; | |
462 | shadow_dirty_mask = dirty_mask; | |
463 | shadow_nx_mask = nx_mask; | |
464 | shadow_x_mask = x_mask; | |
ffb128c8 | 465 | shadow_present_mask = p_mask; |
f160c7b7 | 466 | shadow_acc_track_mask = acc_track_mask; |
d0ec49d4 | 467 | shadow_me_mask = me_mask; |
7b52345e SY |
468 | } |
469 | EXPORT_SYMBOL_GPL(kvm_mmu_set_mask_ptes); | |
470 | ||
28a1f3ac | 471 | static void kvm_mmu_reset_all_pte_masks(void) |
f160c7b7 | 472 | { |
daa07cbc SC |
473 | u8 low_phys_bits; |
474 | ||
f160c7b7 JS |
475 | shadow_user_mask = 0; |
476 | shadow_accessed_mask = 0; | |
477 | shadow_dirty_mask = 0; | |
478 | shadow_nx_mask = 0; | |
479 | shadow_x_mask = 0; | |
480 | shadow_mmio_mask = 0; | |
481 | shadow_present_mask = 0; | |
482 | shadow_acc_track_mask = 0; | |
28a1f3ac JS |
483 | |
484 | /* | |
485 | * If the CPU has 46 or less physical address bits, then set an | |
486 | * appropriate mask to guard against L1TF attacks. Otherwise, it is | |
487 | * assumed that the CPU is not vulnerable to L1TF. | |
488 | */ | |
daa07cbc | 489 | low_phys_bits = boot_cpu_data.x86_phys_bits; |
28a1f3ac | 490 | if (boot_cpu_data.x86_phys_bits < |
daa07cbc | 491 | 52 - shadow_nonpresent_or_rsvd_mask_len) { |
28a1f3ac JS |
492 | shadow_nonpresent_or_rsvd_mask = |
493 | rsvd_bits(boot_cpu_data.x86_phys_bits - | |
494 | shadow_nonpresent_or_rsvd_mask_len, | |
495 | boot_cpu_data.x86_phys_bits - 1); | |
daa07cbc SC |
496 | low_phys_bits -= shadow_nonpresent_or_rsvd_mask_len; |
497 | } | |
498 | shadow_nonpresent_or_rsvd_lower_gfn_mask = | |
499 | GENMASK_ULL(low_phys_bits - 1, PAGE_SHIFT); | |
f160c7b7 JS |
500 | } |
501 | ||
6aa8b732 AK |
502 | static int is_cpuid_PSE36(void) |
503 | { | |
504 | return 1; | |
505 | } | |
506 | ||
73b1087e AK |
507 | static int is_nx(struct kvm_vcpu *vcpu) |
508 | { | |
f6801dff | 509 | return vcpu->arch.efer & EFER_NX; |
73b1087e AK |
510 | } |
511 | ||
c7addb90 AK |
512 | static int is_shadow_present_pte(u64 pte) |
513 | { | |
f160c7b7 | 514 | return (pte != 0) && !is_mmio_spte(pte); |
c7addb90 AK |
515 | } |
516 | ||
05da4558 MT |
517 | static int is_large_pte(u64 pte) |
518 | { | |
519 | return pte & PT_PAGE_SIZE_MASK; | |
520 | } | |
521 | ||
776e6633 MT |
522 | static int is_last_spte(u64 pte, int level) |
523 | { | |
524 | if (level == PT_PAGE_TABLE_LEVEL) | |
525 | return 1; | |
852e3c19 | 526 | if (is_large_pte(pte)) |
776e6633 MT |
527 | return 1; |
528 | return 0; | |
529 | } | |
530 | ||
d3e328f2 JS |
531 | static bool is_executable_pte(u64 spte) |
532 | { | |
533 | return (spte & (shadow_x_mask | shadow_nx_mask)) == shadow_x_mask; | |
534 | } | |
535 | ||
ba049e93 | 536 | static kvm_pfn_t spte_to_pfn(u64 pte) |
0b49ea86 | 537 | { |
35149e21 | 538 | return (pte & PT64_BASE_ADDR_MASK) >> PAGE_SHIFT; |
0b49ea86 AK |
539 | } |
540 | ||
da928521 AK |
541 | static gfn_t pse36_gfn_delta(u32 gpte) |
542 | { | |
543 | int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT; | |
544 | ||
545 | return (gpte & PT32_DIR_PSE36_MASK) << shift; | |
546 | } | |
547 | ||
603e0651 | 548 | #ifdef CONFIG_X86_64 |
d555c333 | 549 | static void __set_spte(u64 *sptep, u64 spte) |
e663ee64 | 550 | { |
b19ee2ff | 551 | WRITE_ONCE(*sptep, spte); |
e663ee64 AK |
552 | } |
553 | ||
603e0651 | 554 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
a9221dd5 | 555 | { |
b19ee2ff | 556 | WRITE_ONCE(*sptep, spte); |
603e0651 XG |
557 | } |
558 | ||
559 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
560 | { | |
561 | return xchg(sptep, spte); | |
562 | } | |
c2a2ac2b XG |
563 | |
564 | static u64 __get_spte_lockless(u64 *sptep) | |
565 | { | |
6aa7de05 | 566 | return READ_ONCE(*sptep); |
c2a2ac2b | 567 | } |
a9221dd5 | 568 | #else |
603e0651 XG |
569 | union split_spte { |
570 | struct { | |
571 | u32 spte_low; | |
572 | u32 spte_high; | |
573 | }; | |
574 | u64 spte; | |
575 | }; | |
a9221dd5 | 576 | |
c2a2ac2b XG |
577 | static void count_spte_clear(u64 *sptep, u64 spte) |
578 | { | |
579 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
580 | ||
581 | if (is_shadow_present_pte(spte)) | |
582 | return; | |
583 | ||
584 | /* Ensure the spte is completely set before we increase the count */ | |
585 | smp_wmb(); | |
586 | sp->clear_spte_count++; | |
587 | } | |
588 | ||
603e0651 XG |
589 | static void __set_spte(u64 *sptep, u64 spte) |
590 | { | |
591 | union split_spte *ssptep, sspte; | |
a9221dd5 | 592 | |
603e0651 XG |
593 | ssptep = (union split_spte *)sptep; |
594 | sspte = (union split_spte)spte; | |
595 | ||
596 | ssptep->spte_high = sspte.spte_high; | |
597 | ||
598 | /* | |
599 | * If we map the spte from nonpresent to present, We should store | |
600 | * the high bits firstly, then set present bit, so cpu can not | |
601 | * fetch this spte while we are setting the spte. | |
602 | */ | |
603 | smp_wmb(); | |
604 | ||
b19ee2ff | 605 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
a9221dd5 AK |
606 | } |
607 | ||
603e0651 XG |
608 | static void __update_clear_spte_fast(u64 *sptep, u64 spte) |
609 | { | |
610 | union split_spte *ssptep, sspte; | |
611 | ||
612 | ssptep = (union split_spte *)sptep; | |
613 | sspte = (union split_spte)spte; | |
614 | ||
b19ee2ff | 615 | WRITE_ONCE(ssptep->spte_low, sspte.spte_low); |
603e0651 XG |
616 | |
617 | /* | |
618 | * If we map the spte from present to nonpresent, we should clear | |
619 | * present bit firstly to avoid vcpu fetch the old high bits. | |
620 | */ | |
621 | smp_wmb(); | |
622 | ||
623 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 624 | count_spte_clear(sptep, spte); |
603e0651 XG |
625 | } |
626 | ||
627 | static u64 __update_clear_spte_slow(u64 *sptep, u64 spte) | |
628 | { | |
629 | union split_spte *ssptep, sspte, orig; | |
630 | ||
631 | ssptep = (union split_spte *)sptep; | |
632 | sspte = (union split_spte)spte; | |
633 | ||
634 | /* xchg acts as a barrier before the setting of the high bits */ | |
635 | orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low); | |
41bc3186 ZJ |
636 | orig.spte_high = ssptep->spte_high; |
637 | ssptep->spte_high = sspte.spte_high; | |
c2a2ac2b | 638 | count_spte_clear(sptep, spte); |
603e0651 XG |
639 | |
640 | return orig.spte; | |
641 | } | |
c2a2ac2b XG |
642 | |
643 | /* | |
644 | * The idea using the light way get the spte on x86_32 guest is from | |
645 | * gup_get_pte(arch/x86/mm/gup.c). | |
accaefe0 XG |
646 | * |
647 | * An spte tlb flush may be pending, because kvm_set_pte_rmapp | |
648 | * coalesces them and we are running out of the MMU lock. Therefore | |
649 | * we need to protect against in-progress updates of the spte. | |
650 | * | |
651 | * Reading the spte while an update is in progress may get the old value | |
652 | * for the high part of the spte. The race is fine for a present->non-present | |
653 | * change (because the high part of the spte is ignored for non-present spte), | |
654 | * but for a present->present change we must reread the spte. | |
655 | * | |
656 | * All such changes are done in two steps (present->non-present and | |
657 | * non-present->present), hence it is enough to count the number of | |
658 | * present->non-present updates: if it changed while reading the spte, | |
659 | * we might have hit the race. This is done using clear_spte_count. | |
c2a2ac2b XG |
660 | */ |
661 | static u64 __get_spte_lockless(u64 *sptep) | |
662 | { | |
663 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
664 | union split_spte spte, *orig = (union split_spte *)sptep; | |
665 | int count; | |
666 | ||
667 | retry: | |
668 | count = sp->clear_spte_count; | |
669 | smp_rmb(); | |
670 | ||
671 | spte.spte_low = orig->spte_low; | |
672 | smp_rmb(); | |
673 | ||
674 | spte.spte_high = orig->spte_high; | |
675 | smp_rmb(); | |
676 | ||
677 | if (unlikely(spte.spte_low != orig->spte_low || | |
678 | count != sp->clear_spte_count)) | |
679 | goto retry; | |
680 | ||
681 | return spte.spte; | |
682 | } | |
603e0651 XG |
683 | #endif |
684 | ||
ea4114bc | 685 | static bool spte_can_locklessly_be_made_writable(u64 spte) |
c7ba5b48 | 686 | { |
feb3eb70 GN |
687 | return (spte & (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE)) == |
688 | (SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE); | |
c7ba5b48 XG |
689 | } |
690 | ||
8672b721 XG |
691 | static bool spte_has_volatile_bits(u64 spte) |
692 | { | |
f160c7b7 JS |
693 | if (!is_shadow_present_pte(spte)) |
694 | return false; | |
695 | ||
c7ba5b48 | 696 | /* |
6a6256f9 | 697 | * Always atomically update spte if it can be updated |
c7ba5b48 XG |
698 | * out of mmu-lock, it can ensure dirty bit is not lost, |
699 | * also, it can help us to get a stable is_writable_pte() | |
700 | * to ensure tlb flush is not missed. | |
701 | */ | |
f160c7b7 JS |
702 | if (spte_can_locklessly_be_made_writable(spte) || |
703 | is_access_track_spte(spte)) | |
c7ba5b48 XG |
704 | return true; |
705 | ||
ac8d57e5 | 706 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
707 | if ((spte & shadow_accessed_mask) == 0 || |
708 | (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0)) | |
709 | return true; | |
710 | } | |
8672b721 | 711 | |
f160c7b7 | 712 | return false; |
8672b721 XG |
713 | } |
714 | ||
83ef6c81 | 715 | static bool is_accessed_spte(u64 spte) |
4132779b | 716 | { |
ac8d57e5 PF |
717 | u64 accessed_mask = spte_shadow_accessed_mask(spte); |
718 | ||
719 | return accessed_mask ? spte & accessed_mask | |
720 | : !is_access_track_spte(spte); | |
4132779b XG |
721 | } |
722 | ||
83ef6c81 | 723 | static bool is_dirty_spte(u64 spte) |
7e71a59b | 724 | { |
ac8d57e5 PF |
725 | u64 dirty_mask = spte_shadow_dirty_mask(spte); |
726 | ||
727 | return dirty_mask ? spte & dirty_mask : spte & PT_WRITABLE_MASK; | |
7e71a59b KH |
728 | } |
729 | ||
1df9f2dc XG |
730 | /* Rules for using mmu_spte_set: |
731 | * Set the sptep from nonpresent to present. | |
732 | * Note: the sptep being assigned *must* be either not present | |
733 | * or in a state where the hardware will not attempt to update | |
734 | * the spte. | |
735 | */ | |
736 | static void mmu_spte_set(u64 *sptep, u64 new_spte) | |
737 | { | |
738 | WARN_ON(is_shadow_present_pte(*sptep)); | |
739 | __set_spte(sptep, new_spte); | |
740 | } | |
741 | ||
f39a058d JS |
742 | /* |
743 | * Update the SPTE (excluding the PFN), but do not track changes in its | |
744 | * accessed/dirty status. | |
1df9f2dc | 745 | */ |
f39a058d | 746 | static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte) |
b79b93f9 | 747 | { |
c7ba5b48 | 748 | u64 old_spte = *sptep; |
4132779b | 749 | |
afd28fe1 | 750 | WARN_ON(!is_shadow_present_pte(new_spte)); |
b79b93f9 | 751 | |
6e7d0354 XG |
752 | if (!is_shadow_present_pte(old_spte)) { |
753 | mmu_spte_set(sptep, new_spte); | |
f39a058d | 754 | return old_spte; |
6e7d0354 | 755 | } |
4132779b | 756 | |
c7ba5b48 | 757 | if (!spte_has_volatile_bits(old_spte)) |
603e0651 | 758 | __update_clear_spte_fast(sptep, new_spte); |
4132779b | 759 | else |
603e0651 | 760 | old_spte = __update_clear_spte_slow(sptep, new_spte); |
4132779b | 761 | |
83ef6c81 JS |
762 | WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte)); |
763 | ||
f39a058d JS |
764 | return old_spte; |
765 | } | |
766 | ||
767 | /* Rules for using mmu_spte_update: | |
768 | * Update the state bits, it means the mapped pfn is not changed. | |
769 | * | |
770 | * Whenever we overwrite a writable spte with a read-only one we | |
771 | * should flush remote TLBs. Otherwise rmap_write_protect | |
772 | * will find a read-only spte, even though the writable spte | |
773 | * might be cached on a CPU's TLB, the return value indicates this | |
774 | * case. | |
775 | * | |
776 | * Returns true if the TLB needs to be flushed | |
777 | */ | |
778 | static bool mmu_spte_update(u64 *sptep, u64 new_spte) | |
779 | { | |
780 | bool flush = false; | |
781 | u64 old_spte = mmu_spte_update_no_track(sptep, new_spte); | |
782 | ||
783 | if (!is_shadow_present_pte(old_spte)) | |
784 | return false; | |
785 | ||
c7ba5b48 XG |
786 | /* |
787 | * For the spte updated out of mmu-lock is safe, since | |
6a6256f9 | 788 | * we always atomically update it, see the comments in |
c7ba5b48 XG |
789 | * spte_has_volatile_bits(). |
790 | */ | |
ea4114bc | 791 | if (spte_can_locklessly_be_made_writable(old_spte) && |
7f31c959 | 792 | !is_writable_pte(new_spte)) |
83ef6c81 | 793 | flush = true; |
4132779b | 794 | |
7e71a59b | 795 | /* |
83ef6c81 | 796 | * Flush TLB when accessed/dirty states are changed in the page tables, |
7e71a59b KH |
797 | * to guarantee consistency between TLB and page tables. |
798 | */ | |
7e71a59b | 799 | |
83ef6c81 JS |
800 | if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) { |
801 | flush = true; | |
4132779b | 802 | kvm_set_pfn_accessed(spte_to_pfn(old_spte)); |
83ef6c81 JS |
803 | } |
804 | ||
805 | if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) { | |
806 | flush = true; | |
4132779b | 807 | kvm_set_pfn_dirty(spte_to_pfn(old_spte)); |
83ef6c81 | 808 | } |
6e7d0354 | 809 | |
83ef6c81 | 810 | return flush; |
b79b93f9 AK |
811 | } |
812 | ||
1df9f2dc XG |
813 | /* |
814 | * Rules for using mmu_spte_clear_track_bits: | |
815 | * It sets the sptep from present to nonpresent, and track the | |
816 | * state bits, it is used to clear the last level sptep. | |
83ef6c81 | 817 | * Returns non-zero if the PTE was previously valid. |
1df9f2dc XG |
818 | */ |
819 | static int mmu_spte_clear_track_bits(u64 *sptep) | |
820 | { | |
ba049e93 | 821 | kvm_pfn_t pfn; |
1df9f2dc XG |
822 | u64 old_spte = *sptep; |
823 | ||
824 | if (!spte_has_volatile_bits(old_spte)) | |
603e0651 | 825 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc | 826 | else |
603e0651 | 827 | old_spte = __update_clear_spte_slow(sptep, 0ull); |
1df9f2dc | 828 | |
afd28fe1 | 829 | if (!is_shadow_present_pte(old_spte)) |
1df9f2dc XG |
830 | return 0; |
831 | ||
832 | pfn = spte_to_pfn(old_spte); | |
86fde74c XG |
833 | |
834 | /* | |
835 | * KVM does not hold the refcount of the page used by | |
836 | * kvm mmu, before reclaiming the page, we should | |
837 | * unmap it from mmu first. | |
838 | */ | |
bf4bea8e | 839 | WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn))); |
86fde74c | 840 | |
83ef6c81 | 841 | if (is_accessed_spte(old_spte)) |
1df9f2dc | 842 | kvm_set_pfn_accessed(pfn); |
83ef6c81 JS |
843 | |
844 | if (is_dirty_spte(old_spte)) | |
1df9f2dc | 845 | kvm_set_pfn_dirty(pfn); |
83ef6c81 | 846 | |
1df9f2dc XG |
847 | return 1; |
848 | } | |
849 | ||
850 | /* | |
851 | * Rules for using mmu_spte_clear_no_track: | |
852 | * Directly clear spte without caring the state bits of sptep, | |
853 | * it is used to set the upper level spte. | |
854 | */ | |
855 | static void mmu_spte_clear_no_track(u64 *sptep) | |
856 | { | |
603e0651 | 857 | __update_clear_spte_fast(sptep, 0ull); |
1df9f2dc XG |
858 | } |
859 | ||
c2a2ac2b XG |
860 | static u64 mmu_spte_get_lockless(u64 *sptep) |
861 | { | |
862 | return __get_spte_lockless(sptep); | |
863 | } | |
864 | ||
f160c7b7 JS |
865 | static u64 mark_spte_for_access_track(u64 spte) |
866 | { | |
ac8d57e5 | 867 | if (spte_ad_enabled(spte)) |
f160c7b7 JS |
868 | return spte & ~shadow_accessed_mask; |
869 | ||
ac8d57e5 | 870 | if (is_access_track_spte(spte)) |
f160c7b7 JS |
871 | return spte; |
872 | ||
873 | /* | |
20d65236 JS |
874 | * Making an Access Tracking PTE will result in removal of write access |
875 | * from the PTE. So, verify that we will be able to restore the write | |
876 | * access in the fast page fault path later on. | |
f160c7b7 JS |
877 | */ |
878 | WARN_ONCE((spte & PT_WRITABLE_MASK) && | |
879 | !spte_can_locklessly_be_made_writable(spte), | |
880 | "kvm: Writable SPTE is not locklessly dirty-trackable\n"); | |
881 | ||
882 | WARN_ONCE(spte & (shadow_acc_track_saved_bits_mask << | |
883 | shadow_acc_track_saved_bits_shift), | |
884 | "kvm: Access Tracking saved bit locations are not zero\n"); | |
885 | ||
886 | spte |= (spte & shadow_acc_track_saved_bits_mask) << | |
887 | shadow_acc_track_saved_bits_shift; | |
888 | spte &= ~shadow_acc_track_mask; | |
f160c7b7 JS |
889 | |
890 | return spte; | |
891 | } | |
892 | ||
d3e328f2 JS |
893 | /* Restore an acc-track PTE back to a regular PTE */ |
894 | static u64 restore_acc_track_spte(u64 spte) | |
895 | { | |
896 | u64 new_spte = spte; | |
897 | u64 saved_bits = (spte >> shadow_acc_track_saved_bits_shift) | |
898 | & shadow_acc_track_saved_bits_mask; | |
899 | ||
ac8d57e5 | 900 | WARN_ON_ONCE(spte_ad_enabled(spte)); |
d3e328f2 JS |
901 | WARN_ON_ONCE(!is_access_track_spte(spte)); |
902 | ||
903 | new_spte &= ~shadow_acc_track_mask; | |
904 | new_spte &= ~(shadow_acc_track_saved_bits_mask << | |
905 | shadow_acc_track_saved_bits_shift); | |
906 | new_spte |= saved_bits; | |
907 | ||
908 | return new_spte; | |
909 | } | |
910 | ||
f160c7b7 JS |
911 | /* Returns the Accessed status of the PTE and resets it at the same time. */ |
912 | static bool mmu_spte_age(u64 *sptep) | |
913 | { | |
914 | u64 spte = mmu_spte_get_lockless(sptep); | |
915 | ||
916 | if (!is_accessed_spte(spte)) | |
917 | return false; | |
918 | ||
ac8d57e5 | 919 | if (spte_ad_enabled(spte)) { |
f160c7b7 JS |
920 | clear_bit((ffs(shadow_accessed_mask) - 1), |
921 | (unsigned long *)sptep); | |
922 | } else { | |
923 | /* | |
924 | * Capture the dirty status of the page, so that it doesn't get | |
925 | * lost when the SPTE is marked for access tracking. | |
926 | */ | |
927 | if (is_writable_pte(spte)) | |
928 | kvm_set_pfn_dirty(spte_to_pfn(spte)); | |
929 | ||
930 | spte = mark_spte_for_access_track(spte); | |
931 | mmu_spte_update_no_track(sptep, spte); | |
932 | } | |
933 | ||
934 | return true; | |
935 | } | |
936 | ||
c2a2ac2b XG |
937 | static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu) |
938 | { | |
c142786c AK |
939 | /* |
940 | * Prevent page table teardown by making any free-er wait during | |
941 | * kvm_flush_remote_tlbs() IPI to all active vcpus. | |
942 | */ | |
943 | local_irq_disable(); | |
36ca7e0a | 944 | |
c142786c AK |
945 | /* |
946 | * Make sure a following spte read is not reordered ahead of the write | |
947 | * to vcpu->mode. | |
948 | */ | |
36ca7e0a | 949 | smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES); |
c2a2ac2b XG |
950 | } |
951 | ||
952 | static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu) | |
953 | { | |
c142786c AK |
954 | /* |
955 | * Make sure the write to vcpu->mode is not reordered in front of | |
9a984586 | 956 | * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us |
c142786c AK |
957 | * OUTSIDE_GUEST_MODE and proceed to free the shadow page table. |
958 | */ | |
36ca7e0a | 959 | smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE); |
c142786c | 960 | local_irq_enable(); |
c2a2ac2b XG |
961 | } |
962 | ||
e2dec939 | 963 | static int mmu_topup_memory_cache(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 964 | struct kmem_cache *base_cache, int min) |
714b93da AK |
965 | { |
966 | void *obj; | |
967 | ||
968 | if (cache->nobjs >= min) | |
e2dec939 | 969 | return 0; |
714b93da | 970 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { |
254272ce | 971 | obj = kmem_cache_zalloc(base_cache, GFP_KERNEL_ACCOUNT); |
714b93da | 972 | if (!obj) |
daefb794 | 973 | return cache->nobjs >= min ? 0 : -ENOMEM; |
714b93da AK |
974 | cache->objects[cache->nobjs++] = obj; |
975 | } | |
e2dec939 | 976 | return 0; |
714b93da AK |
977 | } |
978 | ||
f759e2b4 XG |
979 | static int mmu_memory_cache_free_objects(struct kvm_mmu_memory_cache *cache) |
980 | { | |
981 | return cache->nobjs; | |
982 | } | |
983 | ||
e8ad9a70 XG |
984 | static void mmu_free_memory_cache(struct kvm_mmu_memory_cache *mc, |
985 | struct kmem_cache *cache) | |
714b93da AK |
986 | { |
987 | while (mc->nobjs) | |
e8ad9a70 | 988 | kmem_cache_free(cache, mc->objects[--mc->nobjs]); |
714b93da AK |
989 | } |
990 | ||
c1158e63 | 991 | static int mmu_topup_memory_cache_page(struct kvm_mmu_memory_cache *cache, |
2e3e5882 | 992 | int min) |
c1158e63 | 993 | { |
842f22ed | 994 | void *page; |
c1158e63 AK |
995 | |
996 | if (cache->nobjs >= min) | |
997 | return 0; | |
998 | while (cache->nobjs < ARRAY_SIZE(cache->objects)) { | |
d97e5e61 | 999 | page = (void *)__get_free_page(GFP_KERNEL_ACCOUNT); |
c1158e63 | 1000 | if (!page) |
daefb794 | 1001 | return cache->nobjs >= min ? 0 : -ENOMEM; |
842f22ed | 1002 | cache->objects[cache->nobjs++] = page; |
c1158e63 AK |
1003 | } |
1004 | return 0; | |
1005 | } | |
1006 | ||
1007 | static void mmu_free_memory_cache_page(struct kvm_mmu_memory_cache *mc) | |
1008 | { | |
1009 | while (mc->nobjs) | |
c4d198d5 | 1010 | free_page((unsigned long)mc->objects[--mc->nobjs]); |
c1158e63 AK |
1011 | } |
1012 | ||
2e3e5882 | 1013 | static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu) |
714b93da | 1014 | { |
e2dec939 AK |
1015 | int r; |
1016 | ||
53c07b18 | 1017 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
67052b35 | 1018 | pte_list_desc_cache, 8 + PTE_PREFETCH_NUM); |
d3d25b04 AK |
1019 | if (r) |
1020 | goto out; | |
ad312c7c | 1021 | r = mmu_topup_memory_cache_page(&vcpu->arch.mmu_page_cache, 8); |
d3d25b04 AK |
1022 | if (r) |
1023 | goto out; | |
ad312c7c | 1024 | r = mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache, |
2e3e5882 | 1025 | mmu_page_header_cache, 4); |
e2dec939 AK |
1026 | out: |
1027 | return r; | |
714b93da AK |
1028 | } |
1029 | ||
1030 | static void mmu_free_memory_caches(struct kvm_vcpu *vcpu) | |
1031 | { | |
53c07b18 XG |
1032 | mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache, |
1033 | pte_list_desc_cache); | |
ad312c7c | 1034 | mmu_free_memory_cache_page(&vcpu->arch.mmu_page_cache); |
e8ad9a70 XG |
1035 | mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache, |
1036 | mmu_page_header_cache); | |
714b93da AK |
1037 | } |
1038 | ||
80feb89a | 1039 | static void *mmu_memory_cache_alloc(struct kvm_mmu_memory_cache *mc) |
714b93da AK |
1040 | { |
1041 | void *p; | |
1042 | ||
1043 | BUG_ON(!mc->nobjs); | |
1044 | p = mc->objects[--mc->nobjs]; | |
714b93da AK |
1045 | return p; |
1046 | } | |
1047 | ||
53c07b18 | 1048 | static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu) |
714b93da | 1049 | { |
80feb89a | 1050 | return mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache); |
714b93da AK |
1051 | } |
1052 | ||
53c07b18 | 1053 | static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc) |
714b93da | 1054 | { |
53c07b18 | 1055 | kmem_cache_free(pte_list_desc_cache, pte_list_desc); |
714b93da AK |
1056 | } |
1057 | ||
2032a93d LJ |
1058 | static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index) |
1059 | { | |
1060 | if (!sp->role.direct) | |
1061 | return sp->gfns[index]; | |
1062 | ||
1063 | return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS)); | |
1064 | } | |
1065 | ||
1066 | static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn) | |
1067 | { | |
1068 | if (sp->role.direct) | |
1069 | BUG_ON(gfn != kvm_mmu_page_get_gfn(sp, index)); | |
1070 | else | |
1071 | sp->gfns[index] = gfn; | |
1072 | } | |
1073 | ||
05da4558 | 1074 | /* |
d4dbf470 TY |
1075 | * Return the pointer to the large page information for a given gfn, |
1076 | * handling slots that are not large page aligned. | |
05da4558 | 1077 | */ |
d4dbf470 TY |
1078 | static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn, |
1079 | struct kvm_memory_slot *slot, | |
1080 | int level) | |
05da4558 MT |
1081 | { |
1082 | unsigned long idx; | |
1083 | ||
fb03cb6f | 1084 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
db3fe4eb | 1085 | return &slot->arch.lpage_info[level - 2][idx]; |
05da4558 MT |
1086 | } |
1087 | ||
547ffaed XG |
1088 | static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot, |
1089 | gfn_t gfn, int count) | |
1090 | { | |
1091 | struct kvm_lpage_info *linfo; | |
1092 | int i; | |
1093 | ||
1094 | for (i = PT_DIRECTORY_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { | |
1095 | linfo = lpage_info_slot(gfn, slot, i); | |
1096 | linfo->disallow_lpage += count; | |
1097 | WARN_ON(linfo->disallow_lpage < 0); | |
1098 | } | |
1099 | } | |
1100 | ||
1101 | void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
1102 | { | |
1103 | update_gfn_disallow_lpage_count(slot, gfn, 1); | |
1104 | } | |
1105 | ||
1106 | void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn) | |
1107 | { | |
1108 | update_gfn_disallow_lpage_count(slot, gfn, -1); | |
1109 | } | |
1110 | ||
3ed1a478 | 1111 | static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 1112 | { |
699023e2 | 1113 | struct kvm_memslots *slots; |
d25797b2 | 1114 | struct kvm_memory_slot *slot; |
3ed1a478 | 1115 | gfn_t gfn; |
05da4558 | 1116 | |
56ca57f9 | 1117 | kvm->arch.indirect_shadow_pages++; |
3ed1a478 | 1118 | gfn = sp->gfn; |
699023e2 PB |
1119 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1120 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
1121 | |
1122 | /* the non-leaf shadow pages are keeping readonly. */ | |
1123 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) | |
1124 | return kvm_slot_page_track_add_page(kvm, slot, gfn, | |
1125 | KVM_PAGE_TRACK_WRITE); | |
1126 | ||
547ffaed | 1127 | kvm_mmu_gfn_disallow_lpage(slot, gfn); |
05da4558 MT |
1128 | } |
1129 | ||
3ed1a478 | 1130 | static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp) |
05da4558 | 1131 | { |
699023e2 | 1132 | struct kvm_memslots *slots; |
d25797b2 | 1133 | struct kvm_memory_slot *slot; |
3ed1a478 | 1134 | gfn_t gfn; |
05da4558 | 1135 | |
56ca57f9 | 1136 | kvm->arch.indirect_shadow_pages--; |
3ed1a478 | 1137 | gfn = sp->gfn; |
699023e2 PB |
1138 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1139 | slot = __gfn_to_memslot(slots, gfn); | |
56ca57f9 XG |
1140 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
1141 | return kvm_slot_page_track_remove_page(kvm, slot, gfn, | |
1142 | KVM_PAGE_TRACK_WRITE); | |
1143 | ||
547ffaed | 1144 | kvm_mmu_gfn_allow_lpage(slot, gfn); |
05da4558 MT |
1145 | } |
1146 | ||
92f94f1e XG |
1147 | static bool __mmu_gfn_lpage_is_disallowed(gfn_t gfn, int level, |
1148 | struct kvm_memory_slot *slot) | |
05da4558 | 1149 | { |
d4dbf470 | 1150 | struct kvm_lpage_info *linfo; |
05da4558 MT |
1151 | |
1152 | if (slot) { | |
d4dbf470 | 1153 | linfo = lpage_info_slot(gfn, slot, level); |
92f94f1e | 1154 | return !!linfo->disallow_lpage; |
05da4558 MT |
1155 | } |
1156 | ||
92f94f1e | 1157 | return true; |
05da4558 MT |
1158 | } |
1159 | ||
92f94f1e XG |
1160 | static bool mmu_gfn_lpage_is_disallowed(struct kvm_vcpu *vcpu, gfn_t gfn, |
1161 | int level) | |
5225fdf8 TY |
1162 | { |
1163 | struct kvm_memory_slot *slot; | |
1164 | ||
1165 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
92f94f1e | 1166 | return __mmu_gfn_lpage_is_disallowed(gfn, level, slot); |
5225fdf8 TY |
1167 | } |
1168 | ||
d25797b2 | 1169 | static int host_mapping_level(struct kvm *kvm, gfn_t gfn) |
05da4558 | 1170 | { |
8f0b1ab6 | 1171 | unsigned long page_size; |
d25797b2 | 1172 | int i, ret = 0; |
05da4558 | 1173 | |
8f0b1ab6 | 1174 | page_size = kvm_host_page_size(kvm, gfn); |
05da4558 | 1175 | |
8a3d08f1 | 1176 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
d25797b2 JR |
1177 | if (page_size >= KVM_HPAGE_SIZE(i)) |
1178 | ret = i; | |
1179 | else | |
1180 | break; | |
1181 | } | |
1182 | ||
4c2155ce | 1183 | return ret; |
05da4558 MT |
1184 | } |
1185 | ||
d8aacf5d TY |
1186 | static inline bool memslot_valid_for_gpte(struct kvm_memory_slot *slot, |
1187 | bool no_dirty_log) | |
1188 | { | |
1189 | if (!slot || slot->flags & KVM_MEMSLOT_INVALID) | |
1190 | return false; | |
1191 | if (no_dirty_log && slot->dirty_bitmap) | |
1192 | return false; | |
1193 | ||
1194 | return true; | |
1195 | } | |
1196 | ||
5d163b1c XG |
1197 | static struct kvm_memory_slot * |
1198 | gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn, | |
1199 | bool no_dirty_log) | |
05da4558 MT |
1200 | { |
1201 | struct kvm_memory_slot *slot; | |
5d163b1c | 1202 | |
54bf36aa | 1203 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
d8aacf5d | 1204 | if (!memslot_valid_for_gpte(slot, no_dirty_log)) |
5d163b1c XG |
1205 | slot = NULL; |
1206 | ||
1207 | return slot; | |
1208 | } | |
1209 | ||
fd136902 TY |
1210 | static int mapping_level(struct kvm_vcpu *vcpu, gfn_t large_gfn, |
1211 | bool *force_pt_level) | |
936a5fe6 AA |
1212 | { |
1213 | int host_level, level, max_level; | |
d8aacf5d TY |
1214 | struct kvm_memory_slot *slot; |
1215 | ||
8c85ac1c TY |
1216 | if (unlikely(*force_pt_level)) |
1217 | return PT_PAGE_TABLE_LEVEL; | |
05da4558 | 1218 | |
8c85ac1c TY |
1219 | slot = kvm_vcpu_gfn_to_memslot(vcpu, large_gfn); |
1220 | *force_pt_level = !memslot_valid_for_gpte(slot, true); | |
fd136902 TY |
1221 | if (unlikely(*force_pt_level)) |
1222 | return PT_PAGE_TABLE_LEVEL; | |
1223 | ||
d25797b2 JR |
1224 | host_level = host_mapping_level(vcpu->kvm, large_gfn); |
1225 | ||
1226 | if (host_level == PT_PAGE_TABLE_LEVEL) | |
1227 | return host_level; | |
1228 | ||
55dd98c3 | 1229 | max_level = min(kvm_x86_ops->get_lpage_level(), host_level); |
878403b7 SY |
1230 | |
1231 | for (level = PT_DIRECTORY_LEVEL; level <= max_level; ++level) | |
92f94f1e | 1232 | if (__mmu_gfn_lpage_is_disallowed(large_gfn, level, slot)) |
d25797b2 | 1233 | break; |
d25797b2 JR |
1234 | |
1235 | return level - 1; | |
05da4558 MT |
1236 | } |
1237 | ||
290fc38d | 1238 | /* |
018aabb5 | 1239 | * About rmap_head encoding: |
cd4a4e53 | 1240 | * |
018aabb5 TY |
1241 | * If the bit zero of rmap_head->val is clear, then it points to the only spte |
1242 | * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct | |
53c07b18 | 1243 | * pte_list_desc containing more mappings. |
018aabb5 TY |
1244 | */ |
1245 | ||
1246 | /* | |
1247 | * Returns the number of pointers in the rmap chain, not counting the new one. | |
cd4a4e53 | 1248 | */ |
53c07b18 | 1249 | static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte, |
018aabb5 | 1250 | struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1251 | { |
53c07b18 | 1252 | struct pte_list_desc *desc; |
53a27b39 | 1253 | int i, count = 0; |
cd4a4e53 | 1254 | |
018aabb5 | 1255 | if (!rmap_head->val) { |
53c07b18 | 1256 | rmap_printk("pte_list_add: %p %llx 0->1\n", spte, *spte); |
018aabb5 TY |
1257 | rmap_head->val = (unsigned long)spte; |
1258 | } else if (!(rmap_head->val & 1)) { | |
53c07b18 XG |
1259 | rmap_printk("pte_list_add: %p %llx 1->many\n", spte, *spte); |
1260 | desc = mmu_alloc_pte_list_desc(vcpu); | |
018aabb5 | 1261 | desc->sptes[0] = (u64 *)rmap_head->val; |
d555c333 | 1262 | desc->sptes[1] = spte; |
018aabb5 | 1263 | rmap_head->val = (unsigned long)desc | 1; |
cb16a7b3 | 1264 | ++count; |
cd4a4e53 | 1265 | } else { |
53c07b18 | 1266 | rmap_printk("pte_list_add: %p %llx many->many\n", spte, *spte); |
018aabb5 | 1267 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
53c07b18 | 1268 | while (desc->sptes[PTE_LIST_EXT-1] && desc->more) { |
cd4a4e53 | 1269 | desc = desc->more; |
53c07b18 | 1270 | count += PTE_LIST_EXT; |
53a27b39 | 1271 | } |
53c07b18 XG |
1272 | if (desc->sptes[PTE_LIST_EXT-1]) { |
1273 | desc->more = mmu_alloc_pte_list_desc(vcpu); | |
cd4a4e53 AK |
1274 | desc = desc->more; |
1275 | } | |
d555c333 | 1276 | for (i = 0; desc->sptes[i]; ++i) |
cb16a7b3 | 1277 | ++count; |
d555c333 | 1278 | desc->sptes[i] = spte; |
cd4a4e53 | 1279 | } |
53a27b39 | 1280 | return count; |
cd4a4e53 AK |
1281 | } |
1282 | ||
53c07b18 | 1283 | static void |
018aabb5 TY |
1284 | pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head, |
1285 | struct pte_list_desc *desc, int i, | |
1286 | struct pte_list_desc *prev_desc) | |
cd4a4e53 AK |
1287 | { |
1288 | int j; | |
1289 | ||
53c07b18 | 1290 | for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j) |
cd4a4e53 | 1291 | ; |
d555c333 AK |
1292 | desc->sptes[i] = desc->sptes[j]; |
1293 | desc->sptes[j] = NULL; | |
cd4a4e53 AK |
1294 | if (j != 0) |
1295 | return; | |
1296 | if (!prev_desc && !desc->more) | |
018aabb5 | 1297 | rmap_head->val = (unsigned long)desc->sptes[0]; |
cd4a4e53 AK |
1298 | else |
1299 | if (prev_desc) | |
1300 | prev_desc->more = desc->more; | |
1301 | else | |
018aabb5 | 1302 | rmap_head->val = (unsigned long)desc->more | 1; |
53c07b18 | 1303 | mmu_free_pte_list_desc(desc); |
cd4a4e53 AK |
1304 | } |
1305 | ||
8daf3462 | 1306 | static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head) |
cd4a4e53 | 1307 | { |
53c07b18 XG |
1308 | struct pte_list_desc *desc; |
1309 | struct pte_list_desc *prev_desc; | |
cd4a4e53 AK |
1310 | int i; |
1311 | ||
018aabb5 | 1312 | if (!rmap_head->val) { |
8daf3462 | 1313 | pr_err("%s: %p 0->BUG\n", __func__, spte); |
cd4a4e53 | 1314 | BUG(); |
018aabb5 | 1315 | } else if (!(rmap_head->val & 1)) { |
8daf3462 | 1316 | rmap_printk("%s: %p 1->0\n", __func__, spte); |
018aabb5 | 1317 | if ((u64 *)rmap_head->val != spte) { |
8daf3462 | 1318 | pr_err("%s: %p 1->BUG\n", __func__, spte); |
cd4a4e53 AK |
1319 | BUG(); |
1320 | } | |
018aabb5 | 1321 | rmap_head->val = 0; |
cd4a4e53 | 1322 | } else { |
8daf3462 | 1323 | rmap_printk("%s: %p many->many\n", __func__, spte); |
018aabb5 | 1324 | desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
cd4a4e53 AK |
1325 | prev_desc = NULL; |
1326 | while (desc) { | |
018aabb5 | 1327 | for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) { |
d555c333 | 1328 | if (desc->sptes[i] == spte) { |
018aabb5 TY |
1329 | pte_list_desc_remove_entry(rmap_head, |
1330 | desc, i, prev_desc); | |
cd4a4e53 AK |
1331 | return; |
1332 | } | |
018aabb5 | 1333 | } |
cd4a4e53 AK |
1334 | prev_desc = desc; |
1335 | desc = desc->more; | |
1336 | } | |
8daf3462 | 1337 | pr_err("%s: %p many->many\n", __func__, spte); |
cd4a4e53 AK |
1338 | BUG(); |
1339 | } | |
1340 | } | |
1341 | ||
e7912386 WY |
1342 | static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep) |
1343 | { | |
1344 | mmu_spte_clear_track_bits(sptep); | |
1345 | __pte_list_remove(sptep, rmap_head); | |
1346 | } | |
1347 | ||
018aabb5 TY |
1348 | static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level, |
1349 | struct kvm_memory_slot *slot) | |
53c07b18 | 1350 | { |
77d11309 | 1351 | unsigned long idx; |
53c07b18 | 1352 | |
77d11309 | 1353 | idx = gfn_to_index(gfn, slot->base_gfn, level); |
d89cc617 | 1354 | return &slot->arch.rmap[level - PT_PAGE_TABLE_LEVEL][idx]; |
53c07b18 XG |
1355 | } |
1356 | ||
018aabb5 TY |
1357 | static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn, |
1358 | struct kvm_mmu_page *sp) | |
9b9b1492 | 1359 | { |
699023e2 | 1360 | struct kvm_memslots *slots; |
9b9b1492 TY |
1361 | struct kvm_memory_slot *slot; |
1362 | ||
699023e2 PB |
1363 | slots = kvm_memslots_for_spte_role(kvm, sp->role); |
1364 | slot = __gfn_to_memslot(slots, gfn); | |
e4cd1da9 | 1365 | return __gfn_to_rmap(gfn, sp->role.level, slot); |
9b9b1492 TY |
1366 | } |
1367 | ||
f759e2b4 XG |
1368 | static bool rmap_can_add(struct kvm_vcpu *vcpu) |
1369 | { | |
1370 | struct kvm_mmu_memory_cache *cache; | |
1371 | ||
1372 | cache = &vcpu->arch.mmu_pte_list_desc_cache; | |
1373 | return mmu_memory_cache_free_objects(cache); | |
1374 | } | |
1375 | ||
53c07b18 XG |
1376 | static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
1377 | { | |
1378 | struct kvm_mmu_page *sp; | |
018aabb5 | 1379 | struct kvm_rmap_head *rmap_head; |
53c07b18 | 1380 | |
53c07b18 XG |
1381 | sp = page_header(__pa(spte)); |
1382 | kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn); | |
018aabb5 TY |
1383 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
1384 | return pte_list_add(vcpu, spte, rmap_head); | |
53c07b18 XG |
1385 | } |
1386 | ||
53c07b18 XG |
1387 | static void rmap_remove(struct kvm *kvm, u64 *spte) |
1388 | { | |
1389 | struct kvm_mmu_page *sp; | |
1390 | gfn_t gfn; | |
018aabb5 | 1391 | struct kvm_rmap_head *rmap_head; |
53c07b18 XG |
1392 | |
1393 | sp = page_header(__pa(spte)); | |
1394 | gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt); | |
018aabb5 | 1395 | rmap_head = gfn_to_rmap(kvm, gfn, sp); |
8daf3462 | 1396 | __pte_list_remove(spte, rmap_head); |
53c07b18 XG |
1397 | } |
1398 | ||
1e3f42f0 TY |
1399 | /* |
1400 | * Used by the following functions to iterate through the sptes linked by a | |
1401 | * rmap. All fields are private and not assumed to be used outside. | |
1402 | */ | |
1403 | struct rmap_iterator { | |
1404 | /* private fields */ | |
1405 | struct pte_list_desc *desc; /* holds the sptep if not NULL */ | |
1406 | int pos; /* index of the sptep */ | |
1407 | }; | |
1408 | ||
1409 | /* | |
1410 | * Iteration must be started by this function. This should also be used after | |
1411 | * removing/dropping sptes from the rmap link because in such cases the | |
1412 | * information in the itererator may not be valid. | |
1413 | * | |
1414 | * Returns sptep if found, NULL otherwise. | |
1415 | */ | |
018aabb5 TY |
1416 | static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head, |
1417 | struct rmap_iterator *iter) | |
1e3f42f0 | 1418 | { |
77fbbbd2 TY |
1419 | u64 *sptep; |
1420 | ||
018aabb5 | 1421 | if (!rmap_head->val) |
1e3f42f0 TY |
1422 | return NULL; |
1423 | ||
018aabb5 | 1424 | if (!(rmap_head->val & 1)) { |
1e3f42f0 | 1425 | iter->desc = NULL; |
77fbbbd2 TY |
1426 | sptep = (u64 *)rmap_head->val; |
1427 | goto out; | |
1e3f42f0 TY |
1428 | } |
1429 | ||
018aabb5 | 1430 | iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul); |
1e3f42f0 | 1431 | iter->pos = 0; |
77fbbbd2 TY |
1432 | sptep = iter->desc->sptes[iter->pos]; |
1433 | out: | |
1434 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1435 | return sptep; | |
1e3f42f0 TY |
1436 | } |
1437 | ||
1438 | /* | |
1439 | * Must be used with a valid iterator: e.g. after rmap_get_first(). | |
1440 | * | |
1441 | * Returns sptep if found, NULL otherwise. | |
1442 | */ | |
1443 | static u64 *rmap_get_next(struct rmap_iterator *iter) | |
1444 | { | |
77fbbbd2 TY |
1445 | u64 *sptep; |
1446 | ||
1e3f42f0 TY |
1447 | if (iter->desc) { |
1448 | if (iter->pos < PTE_LIST_EXT - 1) { | |
1e3f42f0 TY |
1449 | ++iter->pos; |
1450 | sptep = iter->desc->sptes[iter->pos]; | |
1451 | if (sptep) | |
77fbbbd2 | 1452 | goto out; |
1e3f42f0 TY |
1453 | } |
1454 | ||
1455 | iter->desc = iter->desc->more; | |
1456 | ||
1457 | if (iter->desc) { | |
1458 | iter->pos = 0; | |
1459 | /* desc->sptes[0] cannot be NULL */ | |
77fbbbd2 TY |
1460 | sptep = iter->desc->sptes[iter->pos]; |
1461 | goto out; | |
1e3f42f0 TY |
1462 | } |
1463 | } | |
1464 | ||
1465 | return NULL; | |
77fbbbd2 TY |
1466 | out: |
1467 | BUG_ON(!is_shadow_present_pte(*sptep)); | |
1468 | return sptep; | |
1e3f42f0 TY |
1469 | } |
1470 | ||
018aabb5 TY |
1471 | #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \ |
1472 | for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \ | |
77fbbbd2 | 1473 | _spte_; _spte_ = rmap_get_next(_iter_)) |
0d536790 | 1474 | |
c3707958 | 1475 | static void drop_spte(struct kvm *kvm, u64 *sptep) |
e4b502ea | 1476 | { |
1df9f2dc | 1477 | if (mmu_spte_clear_track_bits(sptep)) |
eb45fda4 | 1478 | rmap_remove(kvm, sptep); |
be38d276 AK |
1479 | } |
1480 | ||
8e22f955 XG |
1481 | |
1482 | static bool __drop_large_spte(struct kvm *kvm, u64 *sptep) | |
1483 | { | |
1484 | if (is_large_pte(*sptep)) { | |
1485 | WARN_ON(page_header(__pa(sptep))->role.level == | |
1486 | PT_PAGE_TABLE_LEVEL); | |
1487 | drop_spte(kvm, sptep); | |
1488 | --kvm->stat.lpages; | |
1489 | return true; | |
1490 | } | |
1491 | ||
1492 | return false; | |
1493 | } | |
1494 | ||
1495 | static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep) | |
1496 | { | |
c3134ce2 LT |
1497 | if (__drop_large_spte(vcpu->kvm, sptep)) { |
1498 | struct kvm_mmu_page *sp = page_header(__pa(sptep)); | |
1499 | ||
1500 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, | |
1501 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
1502 | } | |
8e22f955 XG |
1503 | } |
1504 | ||
1505 | /* | |
49fde340 | 1506 | * Write-protect on the specified @sptep, @pt_protect indicates whether |
c126d94f | 1507 | * spte write-protection is caused by protecting shadow page table. |
49fde340 | 1508 | * |
b4619660 | 1509 | * Note: write protection is difference between dirty logging and spte |
49fde340 XG |
1510 | * protection: |
1511 | * - for dirty logging, the spte can be set to writable at anytime if | |
1512 | * its dirty bitmap is properly set. | |
1513 | * - for spte protection, the spte can be writable only after unsync-ing | |
1514 | * shadow page. | |
8e22f955 | 1515 | * |
c126d94f | 1516 | * Return true if tlb need be flushed. |
8e22f955 | 1517 | */ |
c4f138b4 | 1518 | static bool spte_write_protect(u64 *sptep, bool pt_protect) |
d13bc5b5 XG |
1519 | { |
1520 | u64 spte = *sptep; | |
1521 | ||
49fde340 | 1522 | if (!is_writable_pte(spte) && |
ea4114bc | 1523 | !(pt_protect && spte_can_locklessly_be_made_writable(spte))) |
d13bc5b5 XG |
1524 | return false; |
1525 | ||
1526 | rmap_printk("rmap_write_protect: spte %p %llx\n", sptep, *sptep); | |
1527 | ||
49fde340 XG |
1528 | if (pt_protect) |
1529 | spte &= ~SPTE_MMU_WRITEABLE; | |
d13bc5b5 | 1530 | spte = spte & ~PT_WRITABLE_MASK; |
49fde340 | 1531 | |
c126d94f | 1532 | return mmu_spte_update(sptep, spte); |
d13bc5b5 XG |
1533 | } |
1534 | ||
018aabb5 TY |
1535 | static bool __rmap_write_protect(struct kvm *kvm, |
1536 | struct kvm_rmap_head *rmap_head, | |
245c3912 | 1537 | bool pt_protect) |
98348e95 | 1538 | { |
1e3f42f0 TY |
1539 | u64 *sptep; |
1540 | struct rmap_iterator iter; | |
d13bc5b5 | 1541 | bool flush = false; |
374cbac0 | 1542 | |
018aabb5 | 1543 | for_each_rmap_spte(rmap_head, &iter, sptep) |
c4f138b4 | 1544 | flush |= spte_write_protect(sptep, pt_protect); |
855149aa | 1545 | |
d13bc5b5 | 1546 | return flush; |
a0ed4607 TY |
1547 | } |
1548 | ||
c4f138b4 | 1549 | static bool spte_clear_dirty(u64 *sptep) |
f4b4b180 KH |
1550 | { |
1551 | u64 spte = *sptep; | |
1552 | ||
1553 | rmap_printk("rmap_clear_dirty: spte %p %llx\n", sptep, *sptep); | |
1554 | ||
1555 | spte &= ~shadow_dirty_mask; | |
1556 | ||
1557 | return mmu_spte_update(sptep, spte); | |
1558 | } | |
1559 | ||
ac8d57e5 PF |
1560 | static bool wrprot_ad_disabled_spte(u64 *sptep) |
1561 | { | |
1562 | bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT, | |
1563 | (unsigned long *)sptep); | |
1564 | if (was_writable) | |
1565 | kvm_set_pfn_dirty(spte_to_pfn(*sptep)); | |
1566 | ||
1567 | return was_writable; | |
1568 | } | |
1569 | ||
1570 | /* | |
1571 | * Gets the GFN ready for another round of dirty logging by clearing the | |
1572 | * - D bit on ad-enabled SPTEs, and | |
1573 | * - W bit on ad-disabled SPTEs. | |
1574 | * Returns true iff any D or W bits were cleared. | |
1575 | */ | |
018aabb5 | 1576 | static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1577 | { |
1578 | u64 *sptep; | |
1579 | struct rmap_iterator iter; | |
1580 | bool flush = false; | |
1581 | ||
018aabb5 | 1582 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1583 | if (spte_ad_enabled(*sptep)) |
1584 | flush |= spte_clear_dirty(sptep); | |
1585 | else | |
1586 | flush |= wrprot_ad_disabled_spte(sptep); | |
f4b4b180 KH |
1587 | |
1588 | return flush; | |
1589 | } | |
1590 | ||
c4f138b4 | 1591 | static bool spte_set_dirty(u64 *sptep) |
f4b4b180 KH |
1592 | { |
1593 | u64 spte = *sptep; | |
1594 | ||
1595 | rmap_printk("rmap_set_dirty: spte %p %llx\n", sptep, *sptep); | |
1596 | ||
1597 | spte |= shadow_dirty_mask; | |
1598 | ||
1599 | return mmu_spte_update(sptep, spte); | |
1600 | } | |
1601 | ||
018aabb5 | 1602 | static bool __rmap_set_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
f4b4b180 KH |
1603 | { |
1604 | u64 *sptep; | |
1605 | struct rmap_iterator iter; | |
1606 | bool flush = false; | |
1607 | ||
018aabb5 | 1608 | for_each_rmap_spte(rmap_head, &iter, sptep) |
ac8d57e5 PF |
1609 | if (spte_ad_enabled(*sptep)) |
1610 | flush |= spte_set_dirty(sptep); | |
f4b4b180 KH |
1611 | |
1612 | return flush; | |
1613 | } | |
1614 | ||
5dc99b23 | 1615 | /** |
3b0f1d01 | 1616 | * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages |
5dc99b23 TY |
1617 | * @kvm: kvm instance |
1618 | * @slot: slot to protect | |
1619 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1620 | * @mask: indicates which pages we should protect | |
1621 | * | |
1622 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1623 | * logging we do not have any such mappings. | |
1624 | */ | |
3b0f1d01 | 1625 | static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm, |
5dc99b23 TY |
1626 | struct kvm_memory_slot *slot, |
1627 | gfn_t gfn_offset, unsigned long mask) | |
a0ed4607 | 1628 | { |
018aabb5 | 1629 | struct kvm_rmap_head *rmap_head; |
a0ed4607 | 1630 | |
5dc99b23 | 1631 | while (mask) { |
018aabb5 TY |
1632 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1633 | PT_PAGE_TABLE_LEVEL, slot); | |
1634 | __rmap_write_protect(kvm, rmap_head, false); | |
05da4558 | 1635 | |
5dc99b23 TY |
1636 | /* clear the first set bit */ |
1637 | mask &= mask - 1; | |
1638 | } | |
374cbac0 AK |
1639 | } |
1640 | ||
f4b4b180 | 1641 | /** |
ac8d57e5 PF |
1642 | * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write |
1643 | * protect the page if the D-bit isn't supported. | |
f4b4b180 KH |
1644 | * @kvm: kvm instance |
1645 | * @slot: slot to clear D-bit | |
1646 | * @gfn_offset: start of the BITS_PER_LONG pages we care about | |
1647 | * @mask: indicates which pages we should clear D-bit | |
1648 | * | |
1649 | * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap. | |
1650 | */ | |
1651 | void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm, | |
1652 | struct kvm_memory_slot *slot, | |
1653 | gfn_t gfn_offset, unsigned long mask) | |
1654 | { | |
018aabb5 | 1655 | struct kvm_rmap_head *rmap_head; |
f4b4b180 KH |
1656 | |
1657 | while (mask) { | |
018aabb5 TY |
1658 | rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask), |
1659 | PT_PAGE_TABLE_LEVEL, slot); | |
1660 | __rmap_clear_dirty(kvm, rmap_head); | |
f4b4b180 KH |
1661 | |
1662 | /* clear the first set bit */ | |
1663 | mask &= mask - 1; | |
1664 | } | |
1665 | } | |
1666 | EXPORT_SYMBOL_GPL(kvm_mmu_clear_dirty_pt_masked); | |
1667 | ||
3b0f1d01 KH |
1668 | /** |
1669 | * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected | |
1670 | * PT level pages. | |
1671 | * | |
1672 | * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to | |
1673 | * enable dirty logging for them. | |
1674 | * | |
1675 | * Used when we do not need to care about huge page mappings: e.g. during dirty | |
1676 | * logging we do not have any such mappings. | |
1677 | */ | |
1678 | void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm, | |
1679 | struct kvm_memory_slot *slot, | |
1680 | gfn_t gfn_offset, unsigned long mask) | |
1681 | { | |
88178fd4 KH |
1682 | if (kvm_x86_ops->enable_log_dirty_pt_masked) |
1683 | kvm_x86_ops->enable_log_dirty_pt_masked(kvm, slot, gfn_offset, | |
1684 | mask); | |
1685 | else | |
1686 | kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask); | |
3b0f1d01 KH |
1687 | } |
1688 | ||
bab4165e BD |
1689 | /** |
1690 | * kvm_arch_write_log_dirty - emulate dirty page logging | |
1691 | * @vcpu: Guest mode vcpu | |
1692 | * | |
1693 | * Emulate arch specific page modification logging for the | |
1694 | * nested hypervisor | |
1695 | */ | |
1696 | int kvm_arch_write_log_dirty(struct kvm_vcpu *vcpu) | |
1697 | { | |
1698 | if (kvm_x86_ops->write_log_dirty) | |
1699 | return kvm_x86_ops->write_log_dirty(vcpu); | |
1700 | ||
1701 | return 0; | |
1702 | } | |
1703 | ||
aeecee2e XG |
1704 | bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm, |
1705 | struct kvm_memory_slot *slot, u64 gfn) | |
95d4c16c | 1706 | { |
018aabb5 | 1707 | struct kvm_rmap_head *rmap_head; |
5dc99b23 | 1708 | int i; |
2f84569f | 1709 | bool write_protected = false; |
95d4c16c | 1710 | |
8a3d08f1 | 1711 | for (i = PT_PAGE_TABLE_LEVEL; i <= PT_MAX_HUGEPAGE_LEVEL; ++i) { |
018aabb5 | 1712 | rmap_head = __gfn_to_rmap(gfn, i, slot); |
aeecee2e | 1713 | write_protected |= __rmap_write_protect(kvm, rmap_head, true); |
5dc99b23 TY |
1714 | } |
1715 | ||
1716 | return write_protected; | |
95d4c16c TY |
1717 | } |
1718 | ||
aeecee2e XG |
1719 | static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn) |
1720 | { | |
1721 | struct kvm_memory_slot *slot; | |
1722 | ||
1723 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); | |
1724 | return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn); | |
1725 | } | |
1726 | ||
018aabb5 | 1727 | static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head) |
e930bffe | 1728 | { |
1e3f42f0 TY |
1729 | u64 *sptep; |
1730 | struct rmap_iterator iter; | |
6a49f85c | 1731 | bool flush = false; |
e930bffe | 1732 | |
018aabb5 | 1733 | while ((sptep = rmap_get_first(rmap_head, &iter))) { |
6a49f85c | 1734 | rmap_printk("%s: spte %p %llx.\n", __func__, sptep, *sptep); |
1e3f42f0 | 1735 | |
e7912386 | 1736 | pte_list_remove(rmap_head, sptep); |
6a49f85c | 1737 | flush = true; |
e930bffe | 1738 | } |
1e3f42f0 | 1739 | |
6a49f85c XG |
1740 | return flush; |
1741 | } | |
1742 | ||
018aabb5 | 1743 | static int kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
6a49f85c XG |
1744 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1745 | unsigned long data) | |
1746 | { | |
018aabb5 | 1747 | return kvm_zap_rmapp(kvm, rmap_head); |
e930bffe AA |
1748 | } |
1749 | ||
018aabb5 | 1750 | static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1751 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1752 | unsigned long data) | |
3da0dd43 | 1753 | { |
1e3f42f0 TY |
1754 | u64 *sptep; |
1755 | struct rmap_iterator iter; | |
3da0dd43 | 1756 | int need_flush = 0; |
1e3f42f0 | 1757 | u64 new_spte; |
3da0dd43 | 1758 | pte_t *ptep = (pte_t *)data; |
ba049e93 | 1759 | kvm_pfn_t new_pfn; |
3da0dd43 IE |
1760 | |
1761 | WARN_ON(pte_huge(*ptep)); | |
1762 | new_pfn = pte_pfn(*ptep); | |
1e3f42f0 | 1763 | |
0d536790 | 1764 | restart: |
018aabb5 | 1765 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
8a9522d2 | 1766 | rmap_printk("kvm_set_pte_rmapp: spte %p %llx gfn %llx (%d)\n", |
f160c7b7 | 1767 | sptep, *sptep, gfn, level); |
1e3f42f0 | 1768 | |
3da0dd43 | 1769 | need_flush = 1; |
1e3f42f0 | 1770 | |
3da0dd43 | 1771 | if (pte_write(*ptep)) { |
e7912386 | 1772 | pte_list_remove(rmap_head, sptep); |
0d536790 | 1773 | goto restart; |
3da0dd43 | 1774 | } else { |
1e3f42f0 | 1775 | new_spte = *sptep & ~PT64_BASE_ADDR_MASK; |
3da0dd43 IE |
1776 | new_spte |= (u64)new_pfn << PAGE_SHIFT; |
1777 | ||
1778 | new_spte &= ~PT_WRITABLE_MASK; | |
1779 | new_spte &= ~SPTE_HOST_WRITEABLE; | |
f160c7b7 JS |
1780 | |
1781 | new_spte = mark_spte_for_access_track(new_spte); | |
1e3f42f0 TY |
1782 | |
1783 | mmu_spte_clear_track_bits(sptep); | |
1784 | mmu_spte_set(sptep, new_spte); | |
3da0dd43 IE |
1785 | } |
1786 | } | |
1e3f42f0 | 1787 | |
3cc5ea94 LT |
1788 | if (need_flush && kvm_available_flush_tlb_with_range()) { |
1789 | kvm_flush_remote_tlbs_with_address(kvm, gfn, 1); | |
1790 | return 0; | |
1791 | } | |
1792 | ||
0cf853c5 | 1793 | return need_flush; |
3da0dd43 IE |
1794 | } |
1795 | ||
6ce1f4e2 XG |
1796 | struct slot_rmap_walk_iterator { |
1797 | /* input fields. */ | |
1798 | struct kvm_memory_slot *slot; | |
1799 | gfn_t start_gfn; | |
1800 | gfn_t end_gfn; | |
1801 | int start_level; | |
1802 | int end_level; | |
1803 | ||
1804 | /* output fields. */ | |
1805 | gfn_t gfn; | |
018aabb5 | 1806 | struct kvm_rmap_head *rmap; |
6ce1f4e2 XG |
1807 | int level; |
1808 | ||
1809 | /* private field. */ | |
018aabb5 | 1810 | struct kvm_rmap_head *end_rmap; |
6ce1f4e2 XG |
1811 | }; |
1812 | ||
1813 | static void | |
1814 | rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level) | |
1815 | { | |
1816 | iterator->level = level; | |
1817 | iterator->gfn = iterator->start_gfn; | |
1818 | iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot); | |
1819 | iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level, | |
1820 | iterator->slot); | |
1821 | } | |
1822 | ||
1823 | static void | |
1824 | slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator, | |
1825 | struct kvm_memory_slot *slot, int start_level, | |
1826 | int end_level, gfn_t start_gfn, gfn_t end_gfn) | |
1827 | { | |
1828 | iterator->slot = slot; | |
1829 | iterator->start_level = start_level; | |
1830 | iterator->end_level = end_level; | |
1831 | iterator->start_gfn = start_gfn; | |
1832 | iterator->end_gfn = end_gfn; | |
1833 | ||
1834 | rmap_walk_init_level(iterator, iterator->start_level); | |
1835 | } | |
1836 | ||
1837 | static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator) | |
1838 | { | |
1839 | return !!iterator->rmap; | |
1840 | } | |
1841 | ||
1842 | static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator) | |
1843 | { | |
1844 | if (++iterator->rmap <= iterator->end_rmap) { | |
1845 | iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level)); | |
1846 | return; | |
1847 | } | |
1848 | ||
1849 | if (++iterator->level > iterator->end_level) { | |
1850 | iterator->rmap = NULL; | |
1851 | return; | |
1852 | } | |
1853 | ||
1854 | rmap_walk_init_level(iterator, iterator->level); | |
1855 | } | |
1856 | ||
1857 | #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \ | |
1858 | _start_gfn, _end_gfn, _iter_) \ | |
1859 | for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \ | |
1860 | _end_level_, _start_gfn, _end_gfn); \ | |
1861 | slot_rmap_walk_okay(_iter_); \ | |
1862 | slot_rmap_walk_next(_iter_)) | |
1863 | ||
84504ef3 TY |
1864 | static int kvm_handle_hva_range(struct kvm *kvm, |
1865 | unsigned long start, | |
1866 | unsigned long end, | |
1867 | unsigned long data, | |
1868 | int (*handler)(struct kvm *kvm, | |
018aabb5 | 1869 | struct kvm_rmap_head *rmap_head, |
048212d0 | 1870 | struct kvm_memory_slot *slot, |
8a9522d2 ALC |
1871 | gfn_t gfn, |
1872 | int level, | |
84504ef3 | 1873 | unsigned long data)) |
e930bffe | 1874 | { |
bc6678a3 | 1875 | struct kvm_memslots *slots; |
be6ba0f0 | 1876 | struct kvm_memory_slot *memslot; |
6ce1f4e2 XG |
1877 | struct slot_rmap_walk_iterator iterator; |
1878 | int ret = 0; | |
9da0e4d5 | 1879 | int i; |
bc6678a3 | 1880 | |
9da0e4d5 PB |
1881 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
1882 | slots = __kvm_memslots(kvm, i); | |
1883 | kvm_for_each_memslot(memslot, slots) { | |
1884 | unsigned long hva_start, hva_end; | |
1885 | gfn_t gfn_start, gfn_end; | |
e930bffe | 1886 | |
9da0e4d5 PB |
1887 | hva_start = max(start, memslot->userspace_addr); |
1888 | hva_end = min(end, memslot->userspace_addr + | |
1889 | (memslot->npages << PAGE_SHIFT)); | |
1890 | if (hva_start >= hva_end) | |
1891 | continue; | |
1892 | /* | |
1893 | * {gfn(page) | page intersects with [hva_start, hva_end)} = | |
1894 | * {gfn_start, gfn_start+1, ..., gfn_end-1}. | |
1895 | */ | |
1896 | gfn_start = hva_to_gfn_memslot(hva_start, memslot); | |
1897 | gfn_end = hva_to_gfn_memslot(hva_end + PAGE_SIZE - 1, memslot); | |
1898 | ||
1899 | for_each_slot_rmap_range(memslot, PT_PAGE_TABLE_LEVEL, | |
1900 | PT_MAX_HUGEPAGE_LEVEL, | |
1901 | gfn_start, gfn_end - 1, | |
1902 | &iterator) | |
1903 | ret |= handler(kvm, iterator.rmap, memslot, | |
1904 | iterator.gfn, iterator.level, data); | |
1905 | } | |
e930bffe AA |
1906 | } |
1907 | ||
f395302e | 1908 | return ret; |
e930bffe AA |
1909 | } |
1910 | ||
84504ef3 TY |
1911 | static int kvm_handle_hva(struct kvm *kvm, unsigned long hva, |
1912 | unsigned long data, | |
018aabb5 TY |
1913 | int (*handler)(struct kvm *kvm, |
1914 | struct kvm_rmap_head *rmap_head, | |
048212d0 | 1915 | struct kvm_memory_slot *slot, |
8a9522d2 | 1916 | gfn_t gfn, int level, |
84504ef3 TY |
1917 | unsigned long data)) |
1918 | { | |
1919 | return kvm_handle_hva_range(kvm, hva, hva + 1, data, handler); | |
e930bffe AA |
1920 | } |
1921 | ||
b3ae2096 TY |
1922 | int kvm_unmap_hva_range(struct kvm *kvm, unsigned long start, unsigned long end) |
1923 | { | |
1924 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_unmap_rmapp); | |
1925 | } | |
1926 | ||
748c0e31 | 1927 | int kvm_set_spte_hva(struct kvm *kvm, unsigned long hva, pte_t pte) |
3da0dd43 | 1928 | { |
0cf853c5 | 1929 | return kvm_handle_hva(kvm, hva, (unsigned long)&pte, kvm_set_pte_rmapp); |
e930bffe AA |
1930 | } |
1931 | ||
018aabb5 | 1932 | static int kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1933 | struct kvm_memory_slot *slot, gfn_t gfn, int level, |
1934 | unsigned long data) | |
e930bffe | 1935 | { |
1e3f42f0 | 1936 | u64 *sptep; |
79f702a6 | 1937 | struct rmap_iterator uninitialized_var(iter); |
e930bffe AA |
1938 | int young = 0; |
1939 | ||
f160c7b7 JS |
1940 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1941 | young |= mmu_spte_age(sptep); | |
0d536790 | 1942 | |
8a9522d2 | 1943 | trace_kvm_age_page(gfn, level, slot, young); |
e930bffe AA |
1944 | return young; |
1945 | } | |
1946 | ||
018aabb5 | 1947 | static int kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, |
8a9522d2 ALC |
1948 | struct kvm_memory_slot *slot, gfn_t gfn, |
1949 | int level, unsigned long data) | |
8ee53820 | 1950 | { |
1e3f42f0 TY |
1951 | u64 *sptep; |
1952 | struct rmap_iterator iter; | |
8ee53820 | 1953 | |
83ef6c81 JS |
1954 | for_each_rmap_spte(rmap_head, &iter, sptep) |
1955 | if (is_accessed_spte(*sptep)) | |
1956 | return 1; | |
83ef6c81 | 1957 | return 0; |
8ee53820 AA |
1958 | } |
1959 | ||
53a27b39 MT |
1960 | #define RMAP_RECYCLE_THRESHOLD 1000 |
1961 | ||
852e3c19 | 1962 | static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn) |
53a27b39 | 1963 | { |
018aabb5 | 1964 | struct kvm_rmap_head *rmap_head; |
852e3c19 JR |
1965 | struct kvm_mmu_page *sp; |
1966 | ||
1967 | sp = page_header(__pa(spte)); | |
53a27b39 | 1968 | |
018aabb5 | 1969 | rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp); |
53a27b39 | 1970 | |
018aabb5 | 1971 | kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, 0); |
c3134ce2 LT |
1972 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn, |
1973 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
53a27b39 MT |
1974 | } |
1975 | ||
57128468 | 1976 | int kvm_age_hva(struct kvm *kvm, unsigned long start, unsigned long end) |
e930bffe | 1977 | { |
57128468 | 1978 | return kvm_handle_hva_range(kvm, start, end, 0, kvm_age_rmapp); |
e930bffe AA |
1979 | } |
1980 | ||
8ee53820 AA |
1981 | int kvm_test_age_hva(struct kvm *kvm, unsigned long hva) |
1982 | { | |
1983 | return kvm_handle_hva(kvm, hva, 0, kvm_test_age_rmapp); | |
1984 | } | |
1985 | ||
d6c69ee9 | 1986 | #ifdef MMU_DEBUG |
47ad8e68 | 1987 | static int is_empty_shadow_page(u64 *spt) |
6aa8b732 | 1988 | { |
139bdb2d AK |
1989 | u64 *pos; |
1990 | u64 *end; | |
1991 | ||
47ad8e68 | 1992 | for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++) |
3c915510 | 1993 | if (is_shadow_present_pte(*pos)) { |
b8688d51 | 1994 | printk(KERN_ERR "%s: %p %llx\n", __func__, |
139bdb2d | 1995 | pos, *pos); |
6aa8b732 | 1996 | return 0; |
139bdb2d | 1997 | } |
6aa8b732 AK |
1998 | return 1; |
1999 | } | |
d6c69ee9 | 2000 | #endif |
6aa8b732 | 2001 | |
45221ab6 DH |
2002 | /* |
2003 | * This value is the sum of all of the kvm instances's | |
2004 | * kvm->arch.n_used_mmu_pages values. We need a global, | |
2005 | * aggregate version in order to make the slab shrinker | |
2006 | * faster | |
2007 | */ | |
2008 | static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, int nr) | |
2009 | { | |
2010 | kvm->arch.n_used_mmu_pages += nr; | |
2011 | percpu_counter_add(&kvm_total_used_mmu_pages, nr); | |
2012 | } | |
2013 | ||
834be0d8 | 2014 | static void kvm_mmu_free_page(struct kvm_mmu_page *sp) |
260746c0 | 2015 | { |
fa4a2c08 | 2016 | MMU_WARN_ON(!is_empty_shadow_page(sp->spt)); |
7775834a | 2017 | hlist_del(&sp->hash_link); |
bd4c86ea XG |
2018 | list_del(&sp->link); |
2019 | free_page((unsigned long)sp->spt); | |
834be0d8 GN |
2020 | if (!sp->role.direct) |
2021 | free_page((unsigned long)sp->gfns); | |
e8ad9a70 | 2022 | kmem_cache_free(mmu_page_header_cache, sp); |
260746c0 AK |
2023 | } |
2024 | ||
cea0f0e7 AK |
2025 | static unsigned kvm_page_table_hashfn(gfn_t gfn) |
2026 | { | |
114df303 | 2027 | return hash_64(gfn, KVM_MMU_HASH_SHIFT); |
cea0f0e7 AK |
2028 | } |
2029 | ||
714b93da | 2030 | static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu, |
4db35314 | 2031 | struct kvm_mmu_page *sp, u64 *parent_pte) |
cea0f0e7 | 2032 | { |
cea0f0e7 AK |
2033 | if (!parent_pte) |
2034 | return; | |
cea0f0e7 | 2035 | |
67052b35 | 2036 | pte_list_add(vcpu, parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
2037 | } |
2038 | ||
4db35314 | 2039 | static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp, |
cea0f0e7 AK |
2040 | u64 *parent_pte) |
2041 | { | |
8daf3462 | 2042 | __pte_list_remove(parent_pte, &sp->parent_ptes); |
cea0f0e7 AK |
2043 | } |
2044 | ||
bcdd9a93 XG |
2045 | static void drop_parent_pte(struct kvm_mmu_page *sp, |
2046 | u64 *parent_pte) | |
2047 | { | |
2048 | mmu_page_remove_parent_pte(sp, parent_pte); | |
1df9f2dc | 2049 | mmu_spte_clear_no_track(parent_pte); |
bcdd9a93 XG |
2050 | } |
2051 | ||
47005792 | 2052 | static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct) |
ad8cfbe3 | 2053 | { |
67052b35 | 2054 | struct kvm_mmu_page *sp; |
7ddca7e4 | 2055 | |
80feb89a TY |
2056 | sp = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache); |
2057 | sp->spt = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); | |
67052b35 | 2058 | if (!direct) |
80feb89a | 2059 | sp->gfns = mmu_memory_cache_alloc(&vcpu->arch.mmu_page_cache); |
67052b35 | 2060 | set_page_private(virt_to_page(sp->spt), (unsigned long)sp); |
5304b8d3 XG |
2061 | |
2062 | /* | |
2063 | * The active_mmu_pages list is the FIFO list, do not move the | |
2064 | * page until it is zapped. kvm_zap_obsolete_pages depends on | |
2065 | * this feature. See the comments in kvm_zap_obsolete_pages(). | |
2066 | */ | |
67052b35 | 2067 | list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages); |
67052b35 XG |
2068 | kvm_mod_used_mmu_pages(vcpu->kvm, +1); |
2069 | return sp; | |
ad8cfbe3 MT |
2070 | } |
2071 | ||
67052b35 | 2072 | static void mark_unsync(u64 *spte); |
1047df1f | 2073 | static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp) |
0074ff63 | 2074 | { |
74c4e63a TY |
2075 | u64 *sptep; |
2076 | struct rmap_iterator iter; | |
2077 | ||
2078 | for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) { | |
2079 | mark_unsync(sptep); | |
2080 | } | |
0074ff63 MT |
2081 | } |
2082 | ||
67052b35 | 2083 | static void mark_unsync(u64 *spte) |
0074ff63 | 2084 | { |
67052b35 | 2085 | struct kvm_mmu_page *sp; |
1047df1f | 2086 | unsigned int index; |
0074ff63 | 2087 | |
67052b35 | 2088 | sp = page_header(__pa(spte)); |
1047df1f XG |
2089 | index = spte - sp->spt; |
2090 | if (__test_and_set_bit(index, sp->unsync_child_bitmap)) | |
0074ff63 | 2091 | return; |
1047df1f | 2092 | if (sp->unsync_children++) |
0074ff63 | 2093 | return; |
1047df1f | 2094 | kvm_mmu_mark_parents_unsync(sp); |
0074ff63 MT |
2095 | } |
2096 | ||
e8bc217a | 2097 | static int nonpaging_sync_page(struct kvm_vcpu *vcpu, |
a4a8e6f7 | 2098 | struct kvm_mmu_page *sp) |
e8bc217a | 2099 | { |
1f50f1b3 | 2100 | return 0; |
e8bc217a MT |
2101 | } |
2102 | ||
7eb77e9f | 2103 | static void nonpaging_invlpg(struct kvm_vcpu *vcpu, gva_t gva, hpa_t root) |
a7052897 MT |
2104 | { |
2105 | } | |
2106 | ||
0f53b5b1 XG |
2107 | static void nonpaging_update_pte(struct kvm_vcpu *vcpu, |
2108 | struct kvm_mmu_page *sp, u64 *spte, | |
7c562522 | 2109 | const void *pte) |
0f53b5b1 XG |
2110 | { |
2111 | WARN_ON(1); | |
2112 | } | |
2113 | ||
60c8aec6 MT |
2114 | #define KVM_PAGE_ARRAY_NR 16 |
2115 | ||
2116 | struct kvm_mmu_pages { | |
2117 | struct mmu_page_and_offset { | |
2118 | struct kvm_mmu_page *sp; | |
2119 | unsigned int idx; | |
2120 | } page[KVM_PAGE_ARRAY_NR]; | |
2121 | unsigned int nr; | |
2122 | }; | |
2123 | ||
cded19f3 HE |
2124 | static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp, |
2125 | int idx) | |
4731d4c7 | 2126 | { |
60c8aec6 | 2127 | int i; |
4731d4c7 | 2128 | |
60c8aec6 MT |
2129 | if (sp->unsync) |
2130 | for (i=0; i < pvec->nr; i++) | |
2131 | if (pvec->page[i].sp == sp) | |
2132 | return 0; | |
2133 | ||
2134 | pvec->page[pvec->nr].sp = sp; | |
2135 | pvec->page[pvec->nr].idx = idx; | |
2136 | pvec->nr++; | |
2137 | return (pvec->nr == KVM_PAGE_ARRAY_NR); | |
2138 | } | |
2139 | ||
fd951457 TY |
2140 | static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx) |
2141 | { | |
2142 | --sp->unsync_children; | |
2143 | WARN_ON((int)sp->unsync_children < 0); | |
2144 | __clear_bit(idx, sp->unsync_child_bitmap); | |
2145 | } | |
2146 | ||
60c8aec6 MT |
2147 | static int __mmu_unsync_walk(struct kvm_mmu_page *sp, |
2148 | struct kvm_mmu_pages *pvec) | |
2149 | { | |
2150 | int i, ret, nr_unsync_leaf = 0; | |
4731d4c7 | 2151 | |
37178b8b | 2152 | for_each_set_bit(i, sp->unsync_child_bitmap, 512) { |
7a8f1a74 | 2153 | struct kvm_mmu_page *child; |
4731d4c7 MT |
2154 | u64 ent = sp->spt[i]; |
2155 | ||
fd951457 TY |
2156 | if (!is_shadow_present_pte(ent) || is_large_pte(ent)) { |
2157 | clear_unsync_child_bit(sp, i); | |
2158 | continue; | |
2159 | } | |
7a8f1a74 XG |
2160 | |
2161 | child = page_header(ent & PT64_BASE_ADDR_MASK); | |
2162 | ||
2163 | if (child->unsync_children) { | |
2164 | if (mmu_pages_add(pvec, child, i)) | |
2165 | return -ENOSPC; | |
2166 | ||
2167 | ret = __mmu_unsync_walk(child, pvec); | |
fd951457 TY |
2168 | if (!ret) { |
2169 | clear_unsync_child_bit(sp, i); | |
2170 | continue; | |
2171 | } else if (ret > 0) { | |
7a8f1a74 | 2172 | nr_unsync_leaf += ret; |
fd951457 | 2173 | } else |
7a8f1a74 XG |
2174 | return ret; |
2175 | } else if (child->unsync) { | |
2176 | nr_unsync_leaf++; | |
2177 | if (mmu_pages_add(pvec, child, i)) | |
2178 | return -ENOSPC; | |
2179 | } else | |
fd951457 | 2180 | clear_unsync_child_bit(sp, i); |
4731d4c7 MT |
2181 | } |
2182 | ||
60c8aec6 MT |
2183 | return nr_unsync_leaf; |
2184 | } | |
2185 | ||
e23d3fef XG |
2186 | #define INVALID_INDEX (-1) |
2187 | ||
60c8aec6 MT |
2188 | static int mmu_unsync_walk(struct kvm_mmu_page *sp, |
2189 | struct kvm_mmu_pages *pvec) | |
2190 | { | |
0a47cd85 | 2191 | pvec->nr = 0; |
60c8aec6 MT |
2192 | if (!sp->unsync_children) |
2193 | return 0; | |
2194 | ||
e23d3fef | 2195 | mmu_pages_add(pvec, sp, INVALID_INDEX); |
60c8aec6 | 2196 | return __mmu_unsync_walk(sp, pvec); |
4731d4c7 MT |
2197 | } |
2198 | ||
4731d4c7 MT |
2199 | static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp) |
2200 | { | |
2201 | WARN_ON(!sp->unsync); | |
5e1b3ddb | 2202 | trace_kvm_mmu_sync_page(sp); |
4731d4c7 MT |
2203 | sp->unsync = 0; |
2204 | --kvm->stat.mmu_unsync; | |
2205 | } | |
2206 | ||
7775834a XG |
2207 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2208 | struct list_head *invalid_list); | |
2209 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, | |
2210 | struct list_head *invalid_list); | |
4731d4c7 | 2211 | |
f34d251d XG |
2212 | /* |
2213 | * NOTE: we should pay more attention on the zapped-obsolete page | |
2214 | * (is_obsolete_sp(sp) && sp->role.invalid) when you do hash list walk | |
2215 | * since it has been deleted from active_mmu_pages but still can be found | |
2216 | * at hast list. | |
2217 | * | |
f3414bc7 | 2218 | * for_each_valid_sp() has skipped that kind of pages. |
f34d251d | 2219 | */ |
f3414bc7 | 2220 | #define for_each_valid_sp(_kvm, _sp, _gfn) \ |
1044b030 TY |
2221 | hlist_for_each_entry(_sp, \ |
2222 | &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)], hash_link) \ | |
f3414bc7 DM |
2223 | if (is_obsolete_sp((_kvm), (_sp)) || (_sp)->role.invalid) { \ |
2224 | } else | |
1044b030 TY |
2225 | |
2226 | #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \ | |
f3414bc7 DM |
2227 | for_each_valid_sp(_kvm, _sp, _gfn) \ |
2228 | if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else | |
7ae680eb | 2229 | |
f918b443 | 2230 | /* @sp->gfn should be write-protected at the call site */ |
1f50f1b3 PB |
2231 | static bool __kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
2232 | struct list_head *invalid_list) | |
4731d4c7 | 2233 | { |
450917b6 | 2234 | if (sp->role.cr4_pae != !!is_pae(vcpu) |
44dd3ffa | 2235 | || vcpu->arch.mmu->sync_page(vcpu, sp) == 0) { |
d98ba053 | 2236 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list); |
1f50f1b3 | 2237 | return false; |
4731d4c7 MT |
2238 | } |
2239 | ||
1f50f1b3 | 2240 | return true; |
4731d4c7 MT |
2241 | } |
2242 | ||
35a70510 PB |
2243 | static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu, |
2244 | struct list_head *invalid_list, | |
2245 | bool remote_flush, bool local_flush) | |
1d9dc7e0 | 2246 | { |
35a70510 PB |
2247 | if (!list_empty(invalid_list)) { |
2248 | kvm_mmu_commit_zap_page(vcpu->kvm, invalid_list); | |
2249 | return; | |
2250 | } | |
d98ba053 | 2251 | |
35a70510 PB |
2252 | if (remote_flush) |
2253 | kvm_flush_remote_tlbs(vcpu->kvm); | |
2254 | else if (local_flush) | |
2255 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
1d9dc7e0 XG |
2256 | } |
2257 | ||
e37fa785 XG |
2258 | #ifdef CONFIG_KVM_MMU_AUDIT |
2259 | #include "mmu_audit.c" | |
2260 | #else | |
2261 | static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { } | |
2262 | static void mmu_audit_disable(void) { } | |
2263 | #endif | |
2264 | ||
46971a2f XG |
2265 | static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp) |
2266 | { | |
2267 | return unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen); | |
2268 | } | |
2269 | ||
1f50f1b3 | 2270 | static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d98ba053 | 2271 | struct list_head *invalid_list) |
1d9dc7e0 | 2272 | { |
9a43c5d9 PB |
2273 | kvm_unlink_unsync_page(vcpu->kvm, sp); |
2274 | return __kvm_sync_page(vcpu, sp, invalid_list); | |
1d9dc7e0 XG |
2275 | } |
2276 | ||
9f1a122f | 2277 | /* @gfn should be write-protected at the call site */ |
2a74003a PB |
2278 | static bool kvm_sync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, |
2279 | struct list_head *invalid_list) | |
9f1a122f | 2280 | { |
9f1a122f | 2281 | struct kvm_mmu_page *s; |
2a74003a | 2282 | bool ret = false; |
9f1a122f | 2283 | |
b67bfe0d | 2284 | for_each_gfn_indirect_valid_sp(vcpu->kvm, s, gfn) { |
7ae680eb | 2285 | if (!s->unsync) |
9f1a122f XG |
2286 | continue; |
2287 | ||
2288 | WARN_ON(s->role.level != PT_PAGE_TABLE_LEVEL); | |
2a74003a | 2289 | ret |= kvm_sync_page(vcpu, s, invalid_list); |
9f1a122f XG |
2290 | } |
2291 | ||
2a74003a | 2292 | return ret; |
9f1a122f XG |
2293 | } |
2294 | ||
60c8aec6 | 2295 | struct mmu_page_path { |
2a7266a8 YZ |
2296 | struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL]; |
2297 | unsigned int idx[PT64_ROOT_MAX_LEVEL]; | |
4731d4c7 MT |
2298 | }; |
2299 | ||
60c8aec6 | 2300 | #define for_each_sp(pvec, sp, parents, i) \ |
0a47cd85 | 2301 | for (i = mmu_pages_first(&pvec, &parents); \ |
60c8aec6 MT |
2302 | i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \ |
2303 | i = mmu_pages_next(&pvec, &parents, i)) | |
2304 | ||
cded19f3 HE |
2305 | static int mmu_pages_next(struct kvm_mmu_pages *pvec, |
2306 | struct mmu_page_path *parents, | |
2307 | int i) | |
60c8aec6 MT |
2308 | { |
2309 | int n; | |
2310 | ||
2311 | for (n = i+1; n < pvec->nr; n++) { | |
2312 | struct kvm_mmu_page *sp = pvec->page[n].sp; | |
0a47cd85 PB |
2313 | unsigned idx = pvec->page[n].idx; |
2314 | int level = sp->role.level; | |
60c8aec6 | 2315 | |
0a47cd85 PB |
2316 | parents->idx[level-1] = idx; |
2317 | if (level == PT_PAGE_TABLE_LEVEL) | |
2318 | break; | |
60c8aec6 | 2319 | |
0a47cd85 | 2320 | parents->parent[level-2] = sp; |
60c8aec6 MT |
2321 | } |
2322 | ||
2323 | return n; | |
2324 | } | |
2325 | ||
0a47cd85 PB |
2326 | static int mmu_pages_first(struct kvm_mmu_pages *pvec, |
2327 | struct mmu_page_path *parents) | |
2328 | { | |
2329 | struct kvm_mmu_page *sp; | |
2330 | int level; | |
2331 | ||
2332 | if (pvec->nr == 0) | |
2333 | return 0; | |
2334 | ||
e23d3fef XG |
2335 | WARN_ON(pvec->page[0].idx != INVALID_INDEX); |
2336 | ||
0a47cd85 PB |
2337 | sp = pvec->page[0].sp; |
2338 | level = sp->role.level; | |
2339 | WARN_ON(level == PT_PAGE_TABLE_LEVEL); | |
2340 | ||
2341 | parents->parent[level-2] = sp; | |
2342 | ||
2343 | /* Also set up a sentinel. Further entries in pvec are all | |
2344 | * children of sp, so this element is never overwritten. | |
2345 | */ | |
2346 | parents->parent[level-1] = NULL; | |
2347 | return mmu_pages_next(pvec, parents, 0); | |
2348 | } | |
2349 | ||
cded19f3 | 2350 | static void mmu_pages_clear_parents(struct mmu_page_path *parents) |
4731d4c7 | 2351 | { |
60c8aec6 MT |
2352 | struct kvm_mmu_page *sp; |
2353 | unsigned int level = 0; | |
2354 | ||
2355 | do { | |
2356 | unsigned int idx = parents->idx[level]; | |
60c8aec6 MT |
2357 | sp = parents->parent[level]; |
2358 | if (!sp) | |
2359 | return; | |
2360 | ||
e23d3fef | 2361 | WARN_ON(idx == INVALID_INDEX); |
fd951457 | 2362 | clear_unsync_child_bit(sp, idx); |
60c8aec6 | 2363 | level++; |
0a47cd85 | 2364 | } while (!sp->unsync_children); |
60c8aec6 | 2365 | } |
4731d4c7 | 2366 | |
60c8aec6 MT |
2367 | static void mmu_sync_children(struct kvm_vcpu *vcpu, |
2368 | struct kvm_mmu_page *parent) | |
2369 | { | |
2370 | int i; | |
2371 | struct kvm_mmu_page *sp; | |
2372 | struct mmu_page_path parents; | |
2373 | struct kvm_mmu_pages pages; | |
d98ba053 | 2374 | LIST_HEAD(invalid_list); |
50c9e6f3 | 2375 | bool flush = false; |
60c8aec6 | 2376 | |
60c8aec6 | 2377 | while (mmu_unsync_walk(parent, &pages)) { |
2f84569f | 2378 | bool protected = false; |
b1a36821 MT |
2379 | |
2380 | for_each_sp(pages, sp, parents, i) | |
54bf36aa | 2381 | protected |= rmap_write_protect(vcpu, sp->gfn); |
b1a36821 | 2382 | |
50c9e6f3 | 2383 | if (protected) { |
b1a36821 | 2384 | kvm_flush_remote_tlbs(vcpu->kvm); |
50c9e6f3 PB |
2385 | flush = false; |
2386 | } | |
b1a36821 | 2387 | |
60c8aec6 | 2388 | for_each_sp(pages, sp, parents, i) { |
1f50f1b3 | 2389 | flush |= kvm_sync_page(vcpu, sp, &invalid_list); |
60c8aec6 MT |
2390 | mmu_pages_clear_parents(&parents); |
2391 | } | |
50c9e6f3 PB |
2392 | if (need_resched() || spin_needbreak(&vcpu->kvm->mmu_lock)) { |
2393 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
2394 | cond_resched_lock(&vcpu->kvm->mmu_lock); | |
2395 | flush = false; | |
2396 | } | |
60c8aec6 | 2397 | } |
50c9e6f3 PB |
2398 | |
2399 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
4731d4c7 MT |
2400 | } |
2401 | ||
a30f47cb XG |
2402 | static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp) |
2403 | { | |
e5691a81 | 2404 | atomic_set(&sp->write_flooding_count, 0); |
a30f47cb XG |
2405 | } |
2406 | ||
2407 | static void clear_sp_write_flooding_count(u64 *spte) | |
2408 | { | |
2409 | struct kvm_mmu_page *sp = page_header(__pa(spte)); | |
2410 | ||
2411 | __clear_sp_write_flooding_count(sp); | |
2412 | } | |
2413 | ||
cea0f0e7 AK |
2414 | static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu, |
2415 | gfn_t gfn, | |
2416 | gva_t gaddr, | |
2417 | unsigned level, | |
f6e2c02b | 2418 | int direct, |
bb11c6c9 | 2419 | unsigned access) |
cea0f0e7 AK |
2420 | { |
2421 | union kvm_mmu_page_role role; | |
cea0f0e7 | 2422 | unsigned quadrant; |
9f1a122f | 2423 | struct kvm_mmu_page *sp; |
9f1a122f | 2424 | bool need_sync = false; |
2a74003a | 2425 | bool flush = false; |
f3414bc7 | 2426 | int collisions = 0; |
2a74003a | 2427 | LIST_HEAD(invalid_list); |
cea0f0e7 | 2428 | |
36d9594d | 2429 | role = vcpu->arch.mmu->mmu_role.base; |
cea0f0e7 | 2430 | role.level = level; |
f6e2c02b | 2431 | role.direct = direct; |
84b0c8c6 | 2432 | if (role.direct) |
5b7e0102 | 2433 | role.cr4_pae = 0; |
41074d07 | 2434 | role.access = access; |
44dd3ffa VK |
2435 | if (!vcpu->arch.mmu->direct_map |
2436 | && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) { | |
cea0f0e7 AK |
2437 | quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level)); |
2438 | quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1; | |
2439 | role.quadrant = quadrant; | |
2440 | } | |
f3414bc7 DM |
2441 | for_each_valid_sp(vcpu->kvm, sp, gfn) { |
2442 | if (sp->gfn != gfn) { | |
2443 | collisions++; | |
2444 | continue; | |
2445 | } | |
2446 | ||
7ae680eb XG |
2447 | if (!need_sync && sp->unsync) |
2448 | need_sync = true; | |
4731d4c7 | 2449 | |
7ae680eb XG |
2450 | if (sp->role.word != role.word) |
2451 | continue; | |
4731d4c7 | 2452 | |
2a74003a PB |
2453 | if (sp->unsync) { |
2454 | /* The page is good, but __kvm_sync_page might still end | |
2455 | * up zapping it. If so, break in order to rebuild it. | |
2456 | */ | |
2457 | if (!__kvm_sync_page(vcpu, sp, &invalid_list)) | |
2458 | break; | |
2459 | ||
2460 | WARN_ON(!list_empty(&invalid_list)); | |
2461 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); | |
2462 | } | |
e02aa901 | 2463 | |
98bba238 | 2464 | if (sp->unsync_children) |
a8eeb04a | 2465 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); |
e02aa901 | 2466 | |
a30f47cb | 2467 | __clear_sp_write_flooding_count(sp); |
7ae680eb | 2468 | trace_kvm_mmu_get_page(sp, false); |
f3414bc7 | 2469 | goto out; |
7ae680eb | 2470 | } |
47005792 | 2471 | |
dfc5aa00 | 2472 | ++vcpu->kvm->stat.mmu_cache_miss; |
47005792 TY |
2473 | |
2474 | sp = kvm_mmu_alloc_page(vcpu, direct); | |
2475 | ||
4db35314 AK |
2476 | sp->gfn = gfn; |
2477 | sp->role = role; | |
7ae680eb XG |
2478 | hlist_add_head(&sp->hash_link, |
2479 | &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)]); | |
f6e2c02b | 2480 | if (!direct) { |
56ca57f9 XG |
2481 | /* |
2482 | * we should do write protection before syncing pages | |
2483 | * otherwise the content of the synced shadow page may | |
2484 | * be inconsistent with guest page table. | |
2485 | */ | |
2486 | account_shadowed(vcpu->kvm, sp); | |
2487 | if (level == PT_PAGE_TABLE_LEVEL && | |
2488 | rmap_write_protect(vcpu, gfn)) | |
c3134ce2 | 2489 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1); |
9f1a122f | 2490 | |
9f1a122f | 2491 | if (level > PT_PAGE_TABLE_LEVEL && need_sync) |
2a74003a | 2492 | flush |= kvm_sync_pages(vcpu, gfn, &invalid_list); |
4731d4c7 | 2493 | } |
5304b8d3 | 2494 | sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen; |
77492664 | 2495 | clear_page(sp->spt); |
f691fe1d | 2496 | trace_kvm_mmu_get_page(sp, true); |
2a74003a PB |
2497 | |
2498 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush); | |
f3414bc7 DM |
2499 | out: |
2500 | if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions) | |
2501 | vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions; | |
4db35314 | 2502 | return sp; |
cea0f0e7 AK |
2503 | } |
2504 | ||
7eb77e9f JS |
2505 | static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator, |
2506 | struct kvm_vcpu *vcpu, hpa_t root, | |
2507 | u64 addr) | |
2d11123a AK |
2508 | { |
2509 | iterator->addr = addr; | |
7eb77e9f | 2510 | iterator->shadow_addr = root; |
44dd3ffa | 2511 | iterator->level = vcpu->arch.mmu->shadow_root_level; |
81407ca5 | 2512 | |
2a7266a8 | 2513 | if (iterator->level == PT64_ROOT_4LEVEL && |
44dd3ffa VK |
2514 | vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL && |
2515 | !vcpu->arch.mmu->direct_map) | |
81407ca5 JR |
2516 | --iterator->level; |
2517 | ||
2d11123a | 2518 | if (iterator->level == PT32E_ROOT_LEVEL) { |
7eb77e9f JS |
2519 | /* |
2520 | * prev_root is currently only used for 64-bit hosts. So only | |
2521 | * the active root_hpa is valid here. | |
2522 | */ | |
44dd3ffa | 2523 | BUG_ON(root != vcpu->arch.mmu->root_hpa); |
7eb77e9f | 2524 | |
2d11123a | 2525 | iterator->shadow_addr |
44dd3ffa | 2526 | = vcpu->arch.mmu->pae_root[(addr >> 30) & 3]; |
2d11123a AK |
2527 | iterator->shadow_addr &= PT64_BASE_ADDR_MASK; |
2528 | --iterator->level; | |
2529 | if (!iterator->shadow_addr) | |
2530 | iterator->level = 0; | |
2531 | } | |
2532 | } | |
2533 | ||
7eb77e9f JS |
2534 | static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator, |
2535 | struct kvm_vcpu *vcpu, u64 addr) | |
2536 | { | |
44dd3ffa | 2537 | shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa, |
7eb77e9f JS |
2538 | addr); |
2539 | } | |
2540 | ||
2d11123a AK |
2541 | static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator) |
2542 | { | |
2543 | if (iterator->level < PT_PAGE_TABLE_LEVEL) | |
2544 | return false; | |
4d88954d | 2545 | |
2d11123a AK |
2546 | iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level); |
2547 | iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index; | |
2548 | return true; | |
2549 | } | |
2550 | ||
c2a2ac2b XG |
2551 | static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator, |
2552 | u64 spte) | |
2d11123a | 2553 | { |
c2a2ac2b | 2554 | if (is_last_spte(spte, iterator->level)) { |
052331be XG |
2555 | iterator->level = 0; |
2556 | return; | |
2557 | } | |
2558 | ||
c2a2ac2b | 2559 | iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK; |
2d11123a AK |
2560 | --iterator->level; |
2561 | } | |
2562 | ||
c2a2ac2b XG |
2563 | static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator) |
2564 | { | |
bb606a9b | 2565 | __shadow_walk_next(iterator, *iterator->sptep); |
c2a2ac2b XG |
2566 | } |
2567 | ||
98bba238 TY |
2568 | static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep, |
2569 | struct kvm_mmu_page *sp) | |
32ef26a3 AK |
2570 | { |
2571 | u64 spte; | |
2572 | ||
ffb128c8 | 2573 | BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK); |
7a1638ce | 2574 | |
ffb128c8 | 2575 | spte = __pa(sp->spt) | shadow_present_mask | PT_WRITABLE_MASK | |
d0ec49d4 | 2576 | shadow_user_mask | shadow_x_mask | shadow_me_mask; |
ac8d57e5 PF |
2577 | |
2578 | if (sp_ad_disabled(sp)) | |
2579 | spte |= shadow_acc_track_value; | |
2580 | else | |
2581 | spte |= shadow_accessed_mask; | |
24db2734 | 2582 | |
1df9f2dc | 2583 | mmu_spte_set(sptep, spte); |
98bba238 TY |
2584 | |
2585 | mmu_page_add_parent_pte(vcpu, sp, sptep); | |
2586 | ||
2587 | if (sp->unsync_children || sp->unsync) | |
2588 | mark_unsync(sptep); | |
32ef26a3 AK |
2589 | } |
2590 | ||
a357bd22 AK |
2591 | static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
2592 | unsigned direct_access) | |
2593 | { | |
2594 | if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) { | |
2595 | struct kvm_mmu_page *child; | |
2596 | ||
2597 | /* | |
2598 | * For the direct sp, if the guest pte's dirty bit | |
2599 | * changed form clean to dirty, it will corrupt the | |
2600 | * sp's access: allow writable in the read-only sp, | |
2601 | * so we should update the spte at this point to get | |
2602 | * a new sp with the correct access. | |
2603 | */ | |
2604 | child = page_header(*sptep & PT64_BASE_ADDR_MASK); | |
2605 | if (child->role.access == direct_access) | |
2606 | return; | |
2607 | ||
bcdd9a93 | 2608 | drop_parent_pte(child, sptep); |
c3134ce2 | 2609 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1); |
a357bd22 AK |
2610 | } |
2611 | } | |
2612 | ||
505aef8f | 2613 | static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, |
38e3b2b2 XG |
2614 | u64 *spte) |
2615 | { | |
2616 | u64 pte; | |
2617 | struct kvm_mmu_page *child; | |
2618 | ||
2619 | pte = *spte; | |
2620 | if (is_shadow_present_pte(pte)) { | |
505aef8f | 2621 | if (is_last_spte(pte, sp->role.level)) { |
c3707958 | 2622 | drop_spte(kvm, spte); |
505aef8f XG |
2623 | if (is_large_pte(pte)) |
2624 | --kvm->stat.lpages; | |
2625 | } else { | |
38e3b2b2 | 2626 | child = page_header(pte & PT64_BASE_ADDR_MASK); |
bcdd9a93 | 2627 | drop_parent_pte(child, spte); |
38e3b2b2 | 2628 | } |
505aef8f XG |
2629 | return true; |
2630 | } | |
2631 | ||
2632 | if (is_mmio_spte(pte)) | |
ce88decf | 2633 | mmu_spte_clear_no_track(spte); |
c3707958 | 2634 | |
505aef8f | 2635 | return false; |
38e3b2b2 XG |
2636 | } |
2637 | ||
90cb0529 | 2638 | static void kvm_mmu_page_unlink_children(struct kvm *kvm, |
4db35314 | 2639 | struct kvm_mmu_page *sp) |
a436036b | 2640 | { |
697fe2e2 | 2641 | unsigned i; |
697fe2e2 | 2642 | |
38e3b2b2 XG |
2643 | for (i = 0; i < PT64_ENT_PER_PAGE; ++i) |
2644 | mmu_page_zap_pte(kvm, sp, sp->spt + i); | |
a436036b AK |
2645 | } |
2646 | ||
31aa2b44 | 2647 | static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp) |
a436036b | 2648 | { |
1e3f42f0 TY |
2649 | u64 *sptep; |
2650 | struct rmap_iterator iter; | |
a436036b | 2651 | |
018aabb5 | 2652 | while ((sptep = rmap_get_first(&sp->parent_ptes, &iter))) |
1e3f42f0 | 2653 | drop_parent_pte(sp, sptep); |
31aa2b44 AK |
2654 | } |
2655 | ||
60c8aec6 | 2656 | static int mmu_zap_unsync_children(struct kvm *kvm, |
7775834a XG |
2657 | struct kvm_mmu_page *parent, |
2658 | struct list_head *invalid_list) | |
4731d4c7 | 2659 | { |
60c8aec6 MT |
2660 | int i, zapped = 0; |
2661 | struct mmu_page_path parents; | |
2662 | struct kvm_mmu_pages pages; | |
4731d4c7 | 2663 | |
60c8aec6 | 2664 | if (parent->role.level == PT_PAGE_TABLE_LEVEL) |
4731d4c7 | 2665 | return 0; |
60c8aec6 | 2666 | |
60c8aec6 MT |
2667 | while (mmu_unsync_walk(parent, &pages)) { |
2668 | struct kvm_mmu_page *sp; | |
2669 | ||
2670 | for_each_sp(pages, sp, parents, i) { | |
7775834a | 2671 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
60c8aec6 | 2672 | mmu_pages_clear_parents(&parents); |
77662e00 | 2673 | zapped++; |
60c8aec6 | 2674 | } |
60c8aec6 MT |
2675 | } |
2676 | ||
2677 | return zapped; | |
4731d4c7 MT |
2678 | } |
2679 | ||
7775834a XG |
2680 | static int kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp, |
2681 | struct list_head *invalid_list) | |
31aa2b44 | 2682 | { |
4731d4c7 | 2683 | int ret; |
f691fe1d | 2684 | |
7775834a | 2685 | trace_kvm_mmu_prepare_zap_page(sp); |
31aa2b44 | 2686 | ++kvm->stat.mmu_shadow_zapped; |
7775834a | 2687 | ret = mmu_zap_unsync_children(kvm, sp, invalid_list); |
4db35314 | 2688 | kvm_mmu_page_unlink_children(kvm, sp); |
31aa2b44 | 2689 | kvm_mmu_unlink_parents(kvm, sp); |
5304b8d3 | 2690 | |
f6e2c02b | 2691 | if (!sp->role.invalid && !sp->role.direct) |
3ed1a478 | 2692 | unaccount_shadowed(kvm, sp); |
5304b8d3 | 2693 | |
4731d4c7 MT |
2694 | if (sp->unsync) |
2695 | kvm_unlink_unsync_page(kvm, sp); | |
4db35314 | 2696 | if (!sp->root_count) { |
54a4f023 GJ |
2697 | /* Count self */ |
2698 | ret++; | |
7775834a | 2699 | list_move(&sp->link, invalid_list); |
aa6bd187 | 2700 | kvm_mod_used_mmu_pages(kvm, -1); |
2e53d63a | 2701 | } else { |
5b5c6a5a | 2702 | list_move(&sp->link, &kvm->arch.active_mmu_pages); |
05988d72 GN |
2703 | |
2704 | /* | |
2705 | * The obsolete pages can not be used on any vcpus. | |
2706 | * See the comments in kvm_mmu_invalidate_zap_all_pages(). | |
2707 | */ | |
2708 | if (!sp->role.invalid && !is_obsolete_sp(kvm, sp)) | |
2709 | kvm_reload_remote_mmus(kvm); | |
2e53d63a | 2710 | } |
7775834a XG |
2711 | |
2712 | sp->role.invalid = 1; | |
4731d4c7 | 2713 | return ret; |
a436036b AK |
2714 | } |
2715 | ||
7775834a XG |
2716 | static void kvm_mmu_commit_zap_page(struct kvm *kvm, |
2717 | struct list_head *invalid_list) | |
2718 | { | |
945315b9 | 2719 | struct kvm_mmu_page *sp, *nsp; |
7775834a XG |
2720 | |
2721 | if (list_empty(invalid_list)) | |
2722 | return; | |
2723 | ||
c142786c | 2724 | /* |
9753f529 LT |
2725 | * We need to make sure everyone sees our modifications to |
2726 | * the page tables and see changes to vcpu->mode here. The barrier | |
2727 | * in the kvm_flush_remote_tlbs() achieves this. This pairs | |
2728 | * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end. | |
2729 | * | |
2730 | * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit | |
2731 | * guest mode and/or lockless shadow page table walks. | |
c142786c AK |
2732 | */ |
2733 | kvm_flush_remote_tlbs(kvm); | |
c2a2ac2b | 2734 | |
945315b9 | 2735 | list_for_each_entry_safe(sp, nsp, invalid_list, link) { |
7775834a | 2736 | WARN_ON(!sp->role.invalid || sp->root_count); |
aa6bd187 | 2737 | kvm_mmu_free_page(sp); |
945315b9 | 2738 | } |
7775834a XG |
2739 | } |
2740 | ||
5da59607 TY |
2741 | static bool prepare_zap_oldest_mmu_page(struct kvm *kvm, |
2742 | struct list_head *invalid_list) | |
2743 | { | |
2744 | struct kvm_mmu_page *sp; | |
2745 | ||
2746 | if (list_empty(&kvm->arch.active_mmu_pages)) | |
2747 | return false; | |
2748 | ||
d74c0e6b GT |
2749 | sp = list_last_entry(&kvm->arch.active_mmu_pages, |
2750 | struct kvm_mmu_page, link); | |
42bcbebf | 2751 | return kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); |
5da59607 TY |
2752 | } |
2753 | ||
82ce2c96 IE |
2754 | /* |
2755 | * Changing the number of mmu pages allocated to the vm | |
49d5ca26 | 2756 | * Note: if goal_nr_mmu_pages is too small, you will get dead lock |
82ce2c96 | 2757 | */ |
49d5ca26 | 2758 | void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned int goal_nr_mmu_pages) |
82ce2c96 | 2759 | { |
d98ba053 | 2760 | LIST_HEAD(invalid_list); |
82ce2c96 | 2761 | |
b34cb590 TY |
2762 | spin_lock(&kvm->mmu_lock); |
2763 | ||
49d5ca26 | 2764 | if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) { |
5da59607 TY |
2765 | /* Need to free some mmu pages to achieve the goal. */ |
2766 | while (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) | |
2767 | if (!prepare_zap_oldest_mmu_page(kvm, &invalid_list)) | |
2768 | break; | |
82ce2c96 | 2769 | |
aa6bd187 | 2770 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
49d5ca26 | 2771 | goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages; |
82ce2c96 | 2772 | } |
82ce2c96 | 2773 | |
49d5ca26 | 2774 | kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages; |
b34cb590 TY |
2775 | |
2776 | spin_unlock(&kvm->mmu_lock); | |
82ce2c96 IE |
2777 | } |
2778 | ||
1cb3f3ae | 2779 | int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn) |
a436036b | 2780 | { |
4db35314 | 2781 | struct kvm_mmu_page *sp; |
d98ba053 | 2782 | LIST_HEAD(invalid_list); |
a436036b AK |
2783 | int r; |
2784 | ||
9ad17b10 | 2785 | pgprintk("%s: looking for gfn %llx\n", __func__, gfn); |
a436036b | 2786 | r = 0; |
1cb3f3ae | 2787 | spin_lock(&kvm->mmu_lock); |
b67bfe0d | 2788 | for_each_gfn_indirect_valid_sp(kvm, sp, gfn) { |
9ad17b10 | 2789 | pgprintk("%s: gfn %llx role %x\n", __func__, gfn, |
7ae680eb XG |
2790 | sp->role.word); |
2791 | r = 1; | |
f41d335a | 2792 | kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list); |
7ae680eb | 2793 | } |
d98ba053 | 2794 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
1cb3f3ae XG |
2795 | spin_unlock(&kvm->mmu_lock); |
2796 | ||
a436036b | 2797 | return r; |
cea0f0e7 | 2798 | } |
1cb3f3ae | 2799 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page); |
cea0f0e7 | 2800 | |
5c520e90 | 2801 | static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp) |
9cf5cf5a XG |
2802 | { |
2803 | trace_kvm_mmu_unsync_page(sp); | |
2804 | ++vcpu->kvm->stat.mmu_unsync; | |
2805 | sp->unsync = 1; | |
2806 | ||
2807 | kvm_mmu_mark_parents_unsync(sp); | |
9cf5cf5a XG |
2808 | } |
2809 | ||
3d0c27ad XG |
2810 | static bool mmu_need_write_protect(struct kvm_vcpu *vcpu, gfn_t gfn, |
2811 | bool can_unsync) | |
4731d4c7 | 2812 | { |
5c520e90 | 2813 | struct kvm_mmu_page *sp; |
4731d4c7 | 2814 | |
3d0c27ad XG |
2815 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) |
2816 | return true; | |
9cf5cf5a | 2817 | |
5c520e90 | 2818 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
36a2e677 | 2819 | if (!can_unsync) |
3d0c27ad | 2820 | return true; |
36a2e677 | 2821 | |
5c520e90 XG |
2822 | if (sp->unsync) |
2823 | continue; | |
9cf5cf5a | 2824 | |
5c520e90 XG |
2825 | WARN_ON(sp->role.level != PT_PAGE_TABLE_LEVEL); |
2826 | kvm_unsync_page(vcpu, sp); | |
4731d4c7 | 2827 | } |
3d0c27ad | 2828 | |
578e1c4d JS |
2829 | /* |
2830 | * We need to ensure that the marking of unsync pages is visible | |
2831 | * before the SPTE is updated to allow writes because | |
2832 | * kvm_mmu_sync_roots() checks the unsync flags without holding | |
2833 | * the MMU lock and so can race with this. If the SPTE was updated | |
2834 | * before the page had been marked as unsync-ed, something like the | |
2835 | * following could happen: | |
2836 | * | |
2837 | * CPU 1 CPU 2 | |
2838 | * --------------------------------------------------------------------- | |
2839 | * 1.2 Host updates SPTE | |
2840 | * to be writable | |
2841 | * 2.1 Guest writes a GPTE for GVA X. | |
2842 | * (GPTE being in the guest page table shadowed | |
2843 | * by the SP from CPU 1.) | |
2844 | * This reads SPTE during the page table walk. | |
2845 | * Since SPTE.W is read as 1, there is no | |
2846 | * fault. | |
2847 | * | |
2848 | * 2.2 Guest issues TLB flush. | |
2849 | * That causes a VM Exit. | |
2850 | * | |
2851 | * 2.3 kvm_mmu_sync_pages() reads sp->unsync. | |
2852 | * Since it is false, so it just returns. | |
2853 | * | |
2854 | * 2.4 Guest accesses GVA X. | |
2855 | * Since the mapping in the SP was not updated, | |
2856 | * so the old mapping for GVA X incorrectly | |
2857 | * gets used. | |
2858 | * 1.1 Host marks SP | |
2859 | * as unsync | |
2860 | * (sp->unsync = true) | |
2861 | * | |
2862 | * The write barrier below ensures that 1.1 happens before 1.2 and thus | |
2863 | * the situation in 2.4 does not arise. The implicit barrier in 2.2 | |
2864 | * pairs with this write barrier. | |
2865 | */ | |
2866 | smp_wmb(); | |
2867 | ||
3d0c27ad | 2868 | return false; |
4731d4c7 MT |
2869 | } |
2870 | ||
ba049e93 | 2871 | static bool kvm_is_mmio_pfn(kvm_pfn_t pfn) |
d1fe9219 PB |
2872 | { |
2873 | if (pfn_valid(pfn)) | |
aa2e063a HZ |
2874 | return !is_zero_pfn(pfn) && PageReserved(pfn_to_page(pfn)) && |
2875 | /* | |
2876 | * Some reserved pages, such as those from NVDIMM | |
2877 | * DAX devices, are not for MMIO, and can be mapped | |
2878 | * with cached memory type for better performance. | |
2879 | * However, the above check misconceives those pages | |
2880 | * as MMIO, and results in KVM mapping them with UC | |
2881 | * memory type, which would hurt the performance. | |
2882 | * Therefore, we check the host memory type in addition | |
2883 | * and only treat UC/UC-/WC pages as MMIO. | |
2884 | */ | |
2885 | (!pat_enabled() || pat_pfn_immune_to_uc_mtrr(pfn)); | |
d1fe9219 PB |
2886 | |
2887 | return true; | |
2888 | } | |
2889 | ||
5ce4786f JS |
2890 | /* Bits which may be returned by set_spte() */ |
2891 | #define SET_SPTE_WRITE_PROTECTED_PT BIT(0) | |
2892 | #define SET_SPTE_NEED_REMOTE_TLB_FLUSH BIT(1) | |
2893 | ||
d555c333 | 2894 | static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep, |
c2288505 | 2895 | unsigned pte_access, int level, |
ba049e93 | 2896 | gfn_t gfn, kvm_pfn_t pfn, bool speculative, |
9bdbba13 | 2897 | bool can_unsync, bool host_writable) |
1c4f1fd6 | 2898 | { |
ffb128c8 | 2899 | u64 spte = 0; |
1e73f9dd | 2900 | int ret = 0; |
ac8d57e5 | 2901 | struct kvm_mmu_page *sp; |
64d4d521 | 2902 | |
54bf36aa | 2903 | if (set_mmio_spte(vcpu, sptep, gfn, pfn, pte_access)) |
ce88decf XG |
2904 | return 0; |
2905 | ||
ac8d57e5 PF |
2906 | sp = page_header(__pa(sptep)); |
2907 | if (sp_ad_disabled(sp)) | |
2908 | spte |= shadow_acc_track_value; | |
2909 | ||
d95c5568 BD |
2910 | /* |
2911 | * For the EPT case, shadow_present_mask is 0 if hardware | |
2912 | * supports exec-only page table entries. In that case, | |
2913 | * ACC_USER_MASK and shadow_user_mask are used to represent | |
2914 | * read access. See FNAME(gpte_access) in paging_tmpl.h. | |
2915 | */ | |
ffb128c8 | 2916 | spte |= shadow_present_mask; |
947da538 | 2917 | if (!speculative) |
ac8d57e5 | 2918 | spte |= spte_shadow_accessed_mask(spte); |
640d9b0d | 2919 | |
7b52345e SY |
2920 | if (pte_access & ACC_EXEC_MASK) |
2921 | spte |= shadow_x_mask; | |
2922 | else | |
2923 | spte |= shadow_nx_mask; | |
49fde340 | 2924 | |
1c4f1fd6 | 2925 | if (pte_access & ACC_USER_MASK) |
7b52345e | 2926 | spte |= shadow_user_mask; |
49fde340 | 2927 | |
852e3c19 | 2928 | if (level > PT_PAGE_TABLE_LEVEL) |
05da4558 | 2929 | spte |= PT_PAGE_SIZE_MASK; |
b0bc3ee2 | 2930 | if (tdp_enabled) |
4b12f0de | 2931 | spte |= kvm_x86_ops->get_mt_mask(vcpu, gfn, |
d1fe9219 | 2932 | kvm_is_mmio_pfn(pfn)); |
1c4f1fd6 | 2933 | |
9bdbba13 | 2934 | if (host_writable) |
1403283a | 2935 | spte |= SPTE_HOST_WRITEABLE; |
f8e453b0 XG |
2936 | else |
2937 | pte_access &= ~ACC_WRITE_MASK; | |
1403283a | 2938 | |
daaf216c TL |
2939 | if (!kvm_is_mmio_pfn(pfn)) |
2940 | spte |= shadow_me_mask; | |
2941 | ||
35149e21 | 2942 | spte |= (u64)pfn << PAGE_SHIFT; |
1c4f1fd6 | 2943 | |
c2288505 | 2944 | if (pte_access & ACC_WRITE_MASK) { |
1c4f1fd6 | 2945 | |
c2193463 | 2946 | /* |
7751babd XG |
2947 | * Other vcpu creates new sp in the window between |
2948 | * mapping_level() and acquiring mmu-lock. We can | |
2949 | * allow guest to retry the access, the mapping can | |
2950 | * be fixed if guest refault. | |
c2193463 | 2951 | */ |
852e3c19 | 2952 | if (level > PT_PAGE_TABLE_LEVEL && |
92f94f1e | 2953 | mmu_gfn_lpage_is_disallowed(vcpu, gfn, level)) |
be38d276 | 2954 | goto done; |
38187c83 | 2955 | |
49fde340 | 2956 | spte |= PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE; |
1c4f1fd6 | 2957 | |
ecc5589f MT |
2958 | /* |
2959 | * Optimization: for pte sync, if spte was writable the hash | |
2960 | * lookup is unnecessary (and expensive). Write protection | |
2961 | * is responsibility of mmu_get_page / kvm_sync_page. | |
2962 | * Same reasoning can be applied to dirty page accounting. | |
2963 | */ | |
8dae4445 | 2964 | if (!can_unsync && is_writable_pte(*sptep)) |
ecc5589f MT |
2965 | goto set_pte; |
2966 | ||
4731d4c7 | 2967 | if (mmu_need_write_protect(vcpu, gfn, can_unsync)) { |
9ad17b10 | 2968 | pgprintk("%s: found shadow page for %llx, marking ro\n", |
b8688d51 | 2969 | __func__, gfn); |
5ce4786f | 2970 | ret |= SET_SPTE_WRITE_PROTECTED_PT; |
1c4f1fd6 | 2971 | pte_access &= ~ACC_WRITE_MASK; |
49fde340 | 2972 | spte &= ~(PT_WRITABLE_MASK | SPTE_MMU_WRITEABLE); |
1c4f1fd6 AK |
2973 | } |
2974 | } | |
2975 | ||
9b51a630 | 2976 | if (pte_access & ACC_WRITE_MASK) { |
54bf36aa | 2977 | kvm_vcpu_mark_page_dirty(vcpu, gfn); |
ac8d57e5 | 2978 | spte |= spte_shadow_dirty_mask(spte); |
9b51a630 | 2979 | } |
1c4f1fd6 | 2980 | |
f160c7b7 JS |
2981 | if (speculative) |
2982 | spte = mark_spte_for_access_track(spte); | |
2983 | ||
38187c83 | 2984 | set_pte: |
6e7d0354 | 2985 | if (mmu_spte_update(sptep, spte)) |
5ce4786f | 2986 | ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH; |
be38d276 | 2987 | done: |
1e73f9dd MT |
2988 | return ret; |
2989 | } | |
2990 | ||
9b8ebbdb PB |
2991 | static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep, unsigned pte_access, |
2992 | int write_fault, int level, gfn_t gfn, kvm_pfn_t pfn, | |
2993 | bool speculative, bool host_writable) | |
1e73f9dd MT |
2994 | { |
2995 | int was_rmapped = 0; | |
53a27b39 | 2996 | int rmap_count; |
5ce4786f | 2997 | int set_spte_ret; |
9b8ebbdb | 2998 | int ret = RET_PF_RETRY; |
c2a4eadf | 2999 | bool flush = false; |
1e73f9dd | 3000 | |
f7616203 XG |
3001 | pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__, |
3002 | *sptep, write_fault, gfn); | |
1e73f9dd | 3003 | |
afd28fe1 | 3004 | if (is_shadow_present_pte(*sptep)) { |
1e73f9dd MT |
3005 | /* |
3006 | * If we overwrite a PTE page pointer with a 2MB PMD, unlink | |
3007 | * the parent of the now unreachable PTE. | |
3008 | */ | |
852e3c19 JR |
3009 | if (level > PT_PAGE_TABLE_LEVEL && |
3010 | !is_large_pte(*sptep)) { | |
1e73f9dd | 3011 | struct kvm_mmu_page *child; |
d555c333 | 3012 | u64 pte = *sptep; |
1e73f9dd MT |
3013 | |
3014 | child = page_header(pte & PT64_BASE_ADDR_MASK); | |
bcdd9a93 | 3015 | drop_parent_pte(child, sptep); |
c2a4eadf | 3016 | flush = true; |
d555c333 | 3017 | } else if (pfn != spte_to_pfn(*sptep)) { |
9ad17b10 | 3018 | pgprintk("hfn old %llx new %llx\n", |
d555c333 | 3019 | spte_to_pfn(*sptep), pfn); |
c3707958 | 3020 | drop_spte(vcpu->kvm, sptep); |
c2a4eadf | 3021 | flush = true; |
6bed6b9e JR |
3022 | } else |
3023 | was_rmapped = 1; | |
1e73f9dd | 3024 | } |
852e3c19 | 3025 | |
5ce4786f JS |
3026 | set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn, |
3027 | speculative, true, host_writable); | |
3028 | if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) { | |
1e73f9dd | 3029 | if (write_fault) |
9b8ebbdb | 3030 | ret = RET_PF_EMULATE; |
77c3913b | 3031 | kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu); |
a378b4e6 | 3032 | } |
c3134ce2 | 3033 | |
c2a4eadf | 3034 | if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush) |
c3134ce2 LT |
3035 | kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, |
3036 | KVM_PAGES_PER_HPAGE(level)); | |
1e73f9dd | 3037 | |
029499b4 | 3038 | if (unlikely(is_mmio_spte(*sptep))) |
9b8ebbdb | 3039 | ret = RET_PF_EMULATE; |
ce88decf | 3040 | |
d555c333 | 3041 | pgprintk("%s: setting spte %llx\n", __func__, *sptep); |
9ad17b10 | 3042 | pgprintk("instantiating %s PTE (%s) at %llx (%llx) addr %p\n", |
d555c333 | 3043 | is_large_pte(*sptep)? "2MB" : "4kB", |
f160c7b7 | 3044 | *sptep & PT_WRITABLE_MASK ? "RW" : "R", gfn, |
a205bc19 | 3045 | *sptep, sptep); |
d555c333 | 3046 | if (!was_rmapped && is_large_pte(*sptep)) |
05da4558 MT |
3047 | ++vcpu->kvm->stat.lpages; |
3048 | ||
ffb61bb3 | 3049 | if (is_shadow_present_pte(*sptep)) { |
ffb61bb3 XG |
3050 | if (!was_rmapped) { |
3051 | rmap_count = rmap_add(vcpu, sptep, gfn); | |
3052 | if (rmap_count > RMAP_RECYCLE_THRESHOLD) | |
3053 | rmap_recycle(vcpu, sptep, gfn); | |
3054 | } | |
1c4f1fd6 | 3055 | } |
cb9aaa30 | 3056 | |
f3ac1a4b | 3057 | kvm_release_pfn_clean(pfn); |
029499b4 | 3058 | |
9b8ebbdb | 3059 | return ret; |
1c4f1fd6 AK |
3060 | } |
3061 | ||
ba049e93 | 3062 | static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn, |
957ed9ef XG |
3063 | bool no_dirty_log) |
3064 | { | |
3065 | struct kvm_memory_slot *slot; | |
957ed9ef | 3066 | |
5d163b1c | 3067 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log); |
903816fa | 3068 | if (!slot) |
6c8ee57b | 3069 | return KVM_PFN_ERR_FAULT; |
957ed9ef | 3070 | |
037d92dc | 3071 | return gfn_to_pfn_memslot_atomic(slot, gfn); |
957ed9ef XG |
3072 | } |
3073 | ||
3074 | static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu, | |
3075 | struct kvm_mmu_page *sp, | |
3076 | u64 *start, u64 *end) | |
3077 | { | |
3078 | struct page *pages[PTE_PREFETCH_NUM]; | |
d9ef13c2 | 3079 | struct kvm_memory_slot *slot; |
957ed9ef XG |
3080 | unsigned access = sp->role.access; |
3081 | int i, ret; | |
3082 | gfn_t gfn; | |
3083 | ||
3084 | gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt); | |
d9ef13c2 PB |
3085 | slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK); |
3086 | if (!slot) | |
957ed9ef XG |
3087 | return -1; |
3088 | ||
d9ef13c2 | 3089 | ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start); |
957ed9ef XG |
3090 | if (ret <= 0) |
3091 | return -1; | |
3092 | ||
3093 | for (i = 0; i < ret; i++, gfn++, start++) | |
029499b4 TY |
3094 | mmu_set_spte(vcpu, start, access, 0, sp->role.level, gfn, |
3095 | page_to_pfn(pages[i]), true, true); | |
957ed9ef XG |
3096 | |
3097 | return 0; | |
3098 | } | |
3099 | ||
3100 | static void __direct_pte_prefetch(struct kvm_vcpu *vcpu, | |
3101 | struct kvm_mmu_page *sp, u64 *sptep) | |
3102 | { | |
3103 | u64 *spte, *start = NULL; | |
3104 | int i; | |
3105 | ||
3106 | WARN_ON(!sp->role.direct); | |
3107 | ||
3108 | i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1); | |
3109 | spte = sp->spt + i; | |
3110 | ||
3111 | for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) { | |
c3707958 | 3112 | if (is_shadow_present_pte(*spte) || spte == sptep) { |
957ed9ef XG |
3113 | if (!start) |
3114 | continue; | |
3115 | if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0) | |
3116 | break; | |
3117 | start = NULL; | |
3118 | } else if (!start) | |
3119 | start = spte; | |
3120 | } | |
3121 | } | |
3122 | ||
3123 | static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep) | |
3124 | { | |
3125 | struct kvm_mmu_page *sp; | |
3126 | ||
ac8d57e5 PF |
3127 | sp = page_header(__pa(sptep)); |
3128 | ||
957ed9ef | 3129 | /* |
ac8d57e5 PF |
3130 | * Without accessed bits, there's no way to distinguish between |
3131 | * actually accessed translations and prefetched, so disable pte | |
3132 | * prefetch if accessed bits aren't available. | |
957ed9ef | 3133 | */ |
ac8d57e5 | 3134 | if (sp_ad_disabled(sp)) |
957ed9ef XG |
3135 | return; |
3136 | ||
957ed9ef XG |
3137 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
3138 | return; | |
3139 | ||
3140 | __direct_pte_prefetch(vcpu, sp, sptep); | |
3141 | } | |
3142 | ||
7ee0e5b2 | 3143 | static int __direct_map(struct kvm_vcpu *vcpu, int write, int map_writable, |
ba049e93 | 3144 | int level, gfn_t gfn, kvm_pfn_t pfn, bool prefault) |
140754bc | 3145 | { |
9f652d21 | 3146 | struct kvm_shadow_walk_iterator iterator; |
140754bc | 3147 | struct kvm_mmu_page *sp; |
b90a0e6c | 3148 | int emulate = 0; |
140754bc | 3149 | gfn_t pseudo_gfn; |
6aa8b732 | 3150 | |
44dd3ffa | 3151 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
989c6b34 MT |
3152 | return 0; |
3153 | ||
9f652d21 | 3154 | for_each_shadow_entry(vcpu, (u64)gfn << PAGE_SHIFT, iterator) { |
852e3c19 | 3155 | if (iterator.level == level) { |
029499b4 TY |
3156 | emulate = mmu_set_spte(vcpu, iterator.sptep, ACC_ALL, |
3157 | write, level, gfn, pfn, prefault, | |
3158 | map_writable); | |
957ed9ef | 3159 | direct_pte_prefetch(vcpu, iterator.sptep); |
9f652d21 AK |
3160 | ++vcpu->stat.pf_fixed; |
3161 | break; | |
6aa8b732 AK |
3162 | } |
3163 | ||
404381c5 | 3164 | drop_large_spte(vcpu, iterator.sptep); |
c3707958 | 3165 | if (!is_shadow_present_pte(*iterator.sptep)) { |
c9fa0b3b LJ |
3166 | u64 base_addr = iterator.addr; |
3167 | ||
3168 | base_addr &= PT64_LVL_ADDR_MASK(iterator.level); | |
3169 | pseudo_gfn = base_addr >> PAGE_SHIFT; | |
9f652d21 | 3170 | sp = kvm_mmu_get_page(vcpu, pseudo_gfn, iterator.addr, |
bb11c6c9 | 3171 | iterator.level - 1, 1, ACC_ALL); |
140754bc | 3172 | |
98bba238 | 3173 | link_shadow_page(vcpu, iterator.sptep, sp); |
9f652d21 AK |
3174 | } |
3175 | } | |
b90a0e6c | 3176 | return emulate; |
6aa8b732 AK |
3177 | } |
3178 | ||
77db5cbd | 3179 | static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk) |
bf998156 | 3180 | { |
585a8b9b | 3181 | send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk); |
bf998156 HY |
3182 | } |
3183 | ||
ba049e93 | 3184 | static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn) |
bf998156 | 3185 | { |
4d8b81ab XG |
3186 | /* |
3187 | * Do not cache the mmio info caused by writing the readonly gfn | |
3188 | * into the spte otherwise read access on readonly gfn also can | |
3189 | * caused mmio page fault and treat it as mmio access. | |
4d8b81ab XG |
3190 | */ |
3191 | if (pfn == KVM_PFN_ERR_RO_FAULT) | |
9b8ebbdb | 3192 | return RET_PF_EMULATE; |
4d8b81ab | 3193 | |
e6c1502b | 3194 | if (pfn == KVM_PFN_ERR_HWPOISON) { |
54bf36aa | 3195 | kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current); |
9b8ebbdb | 3196 | return RET_PF_RETRY; |
d7c55201 | 3197 | } |
edba23e5 | 3198 | |
2c151b25 | 3199 | return -EFAULT; |
bf998156 HY |
3200 | } |
3201 | ||
936a5fe6 | 3202 | static void transparent_hugepage_adjust(struct kvm_vcpu *vcpu, |
ba049e93 DW |
3203 | gfn_t *gfnp, kvm_pfn_t *pfnp, |
3204 | int *levelp) | |
936a5fe6 | 3205 | { |
ba049e93 | 3206 | kvm_pfn_t pfn = *pfnp; |
936a5fe6 AA |
3207 | gfn_t gfn = *gfnp; |
3208 | int level = *levelp; | |
3209 | ||
3210 | /* | |
3211 | * Check if it's a transparent hugepage. If this would be an | |
3212 | * hugetlbfs page, level wouldn't be set to | |
3213 | * PT_PAGE_TABLE_LEVEL and there would be no adjustment done | |
3214 | * here. | |
3215 | */ | |
bf4bea8e | 3216 | if (!is_error_noslot_pfn(pfn) && !kvm_is_reserved_pfn(pfn) && |
936a5fe6 | 3217 | level == PT_PAGE_TABLE_LEVEL && |
127393fb | 3218 | PageTransCompoundMap(pfn_to_page(pfn)) && |
92f94f1e | 3219 | !mmu_gfn_lpage_is_disallowed(vcpu, gfn, PT_DIRECTORY_LEVEL)) { |
936a5fe6 AA |
3220 | unsigned long mask; |
3221 | /* | |
3222 | * mmu_notifier_retry was successful and we hold the | |
3223 | * mmu_lock here, so the pmd can't become splitting | |
3224 | * from under us, and in turn | |
3225 | * __split_huge_page_refcount() can't run from under | |
3226 | * us and we can safely transfer the refcount from | |
3227 | * PG_tail to PG_head as we switch the pfn to tail to | |
3228 | * head. | |
3229 | */ | |
3230 | *levelp = level = PT_DIRECTORY_LEVEL; | |
3231 | mask = KVM_PAGES_PER_HPAGE(level) - 1; | |
3232 | VM_BUG_ON((gfn & mask) != (pfn & mask)); | |
3233 | if (pfn & mask) { | |
3234 | gfn &= ~mask; | |
3235 | *gfnp = gfn; | |
3236 | kvm_release_pfn_clean(pfn); | |
3237 | pfn &= ~mask; | |
c3586667 | 3238 | kvm_get_pfn(pfn); |
936a5fe6 AA |
3239 | *pfnp = pfn; |
3240 | } | |
3241 | } | |
3242 | } | |
3243 | ||
d7c55201 | 3244 | static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn, |
ba049e93 | 3245 | kvm_pfn_t pfn, unsigned access, int *ret_val) |
d7c55201 | 3246 | { |
d7c55201 | 3247 | /* The pfn is invalid, report the error! */ |
81c52c56 | 3248 | if (unlikely(is_error_pfn(pfn))) { |
d7c55201 | 3249 | *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn); |
798e88b3 | 3250 | return true; |
d7c55201 XG |
3251 | } |
3252 | ||
ce88decf | 3253 | if (unlikely(is_noslot_pfn(pfn))) |
d7c55201 | 3254 | vcpu_cache_mmio_info(vcpu, gva, gfn, access); |
d7c55201 | 3255 | |
798e88b3 | 3256 | return false; |
d7c55201 XG |
3257 | } |
3258 | ||
e5552fd2 | 3259 | static bool page_fault_can_be_fast(u32 error_code) |
c7ba5b48 | 3260 | { |
1c118b82 XG |
3261 | /* |
3262 | * Do not fix the mmio spte with invalid generation number which | |
3263 | * need to be updated by slow page fault path. | |
3264 | */ | |
3265 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3266 | return false; | |
3267 | ||
f160c7b7 JS |
3268 | /* See if the page fault is due to an NX violation */ |
3269 | if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)) | |
3270 | == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK)))) | |
3271 | return false; | |
3272 | ||
c7ba5b48 | 3273 | /* |
f160c7b7 JS |
3274 | * #PF can be fast if: |
3275 | * 1. The shadow page table entry is not present, which could mean that | |
3276 | * the fault is potentially caused by access tracking (if enabled). | |
3277 | * 2. The shadow page table entry is present and the fault | |
3278 | * is caused by write-protect, that means we just need change the W | |
3279 | * bit of the spte which can be done out of mmu-lock. | |
3280 | * | |
3281 | * However, if access tracking is disabled we know that a non-present | |
3282 | * page must be a genuine page fault where we have to create a new SPTE. | |
3283 | * So, if access tracking is disabled, we return true only for write | |
3284 | * accesses to a present page. | |
c7ba5b48 | 3285 | */ |
c7ba5b48 | 3286 | |
f160c7b7 JS |
3287 | return shadow_acc_track_mask != 0 || |
3288 | ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)) | |
3289 | == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK)); | |
c7ba5b48 XG |
3290 | } |
3291 | ||
97dceba2 JS |
3292 | /* |
3293 | * Returns true if the SPTE was fixed successfully. Otherwise, | |
3294 | * someone else modified the SPTE from its original value. | |
3295 | */ | |
c7ba5b48 | 3296 | static bool |
92a476cb | 3297 | fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp, |
d3e328f2 | 3298 | u64 *sptep, u64 old_spte, u64 new_spte) |
c7ba5b48 | 3299 | { |
c7ba5b48 XG |
3300 | gfn_t gfn; |
3301 | ||
3302 | WARN_ON(!sp->role.direct); | |
3303 | ||
9b51a630 KH |
3304 | /* |
3305 | * Theoretically we could also set dirty bit (and flush TLB) here in | |
3306 | * order to eliminate unnecessary PML logging. See comments in | |
3307 | * set_spte. But fast_page_fault is very unlikely to happen with PML | |
3308 | * enabled, so we do not do this. This might result in the same GPA | |
3309 | * to be logged in PML buffer again when the write really happens, and | |
3310 | * eventually to be called by mark_page_dirty twice. But it's also no | |
3311 | * harm. This also avoids the TLB flush needed after setting dirty bit | |
3312 | * so non-PML cases won't be impacted. | |
3313 | * | |
3314 | * Compare with set_spte where instead shadow_dirty_mask is set. | |
3315 | */ | |
f160c7b7 | 3316 | if (cmpxchg64(sptep, old_spte, new_spte) != old_spte) |
97dceba2 JS |
3317 | return false; |
3318 | ||
d3e328f2 | 3319 | if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) { |
f160c7b7 JS |
3320 | /* |
3321 | * The gfn of direct spte is stable since it is | |
3322 | * calculated by sp->gfn. | |
3323 | */ | |
3324 | gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt); | |
3325 | kvm_vcpu_mark_page_dirty(vcpu, gfn); | |
3326 | } | |
c7ba5b48 XG |
3327 | |
3328 | return true; | |
3329 | } | |
3330 | ||
d3e328f2 JS |
3331 | static bool is_access_allowed(u32 fault_err_code, u64 spte) |
3332 | { | |
3333 | if (fault_err_code & PFERR_FETCH_MASK) | |
3334 | return is_executable_pte(spte); | |
3335 | ||
3336 | if (fault_err_code & PFERR_WRITE_MASK) | |
3337 | return is_writable_pte(spte); | |
3338 | ||
3339 | /* Fault was on Read access */ | |
3340 | return spte & PT_PRESENT_MASK; | |
3341 | } | |
3342 | ||
c7ba5b48 XG |
3343 | /* |
3344 | * Return value: | |
3345 | * - true: let the vcpu to access on the same address again. | |
3346 | * - false: let the real page fault path to fix it. | |
3347 | */ | |
3348 | static bool fast_page_fault(struct kvm_vcpu *vcpu, gva_t gva, int level, | |
3349 | u32 error_code) | |
3350 | { | |
3351 | struct kvm_shadow_walk_iterator iterator; | |
92a476cb | 3352 | struct kvm_mmu_page *sp; |
97dceba2 | 3353 | bool fault_handled = false; |
c7ba5b48 | 3354 | u64 spte = 0ull; |
97dceba2 | 3355 | uint retry_count = 0; |
c7ba5b48 | 3356 | |
44dd3ffa | 3357 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
37f6a4e2 MT |
3358 | return false; |
3359 | ||
e5552fd2 | 3360 | if (!page_fault_can_be_fast(error_code)) |
c7ba5b48 XG |
3361 | return false; |
3362 | ||
3363 | walk_shadow_page_lockless_begin(vcpu); | |
c7ba5b48 | 3364 | |
97dceba2 | 3365 | do { |
d3e328f2 | 3366 | u64 new_spte; |
c7ba5b48 | 3367 | |
d162f30a JS |
3368 | for_each_shadow_entry_lockless(vcpu, gva, iterator, spte) |
3369 | if (!is_shadow_present_pte(spte) || | |
3370 | iterator.level < level) | |
3371 | break; | |
3372 | ||
97dceba2 JS |
3373 | sp = page_header(__pa(iterator.sptep)); |
3374 | if (!is_last_spte(spte, sp->role.level)) | |
3375 | break; | |
c7ba5b48 | 3376 | |
97dceba2 | 3377 | /* |
f160c7b7 JS |
3378 | * Check whether the memory access that caused the fault would |
3379 | * still cause it if it were to be performed right now. If not, | |
3380 | * then this is a spurious fault caused by TLB lazily flushed, | |
3381 | * or some other CPU has already fixed the PTE after the | |
3382 | * current CPU took the fault. | |
97dceba2 JS |
3383 | * |
3384 | * Need not check the access of upper level table entries since | |
3385 | * they are always ACC_ALL. | |
3386 | */ | |
d3e328f2 JS |
3387 | if (is_access_allowed(error_code, spte)) { |
3388 | fault_handled = true; | |
3389 | break; | |
3390 | } | |
f160c7b7 | 3391 | |
d3e328f2 JS |
3392 | new_spte = spte; |
3393 | ||
3394 | if (is_access_track_spte(spte)) | |
3395 | new_spte = restore_acc_track_spte(new_spte); | |
3396 | ||
3397 | /* | |
3398 | * Currently, to simplify the code, write-protection can | |
3399 | * be removed in the fast path only if the SPTE was | |
3400 | * write-protected for dirty-logging or access tracking. | |
3401 | */ | |
3402 | if ((error_code & PFERR_WRITE_MASK) && | |
3403 | spte_can_locklessly_be_made_writable(spte)) | |
3404 | { | |
3405 | new_spte |= PT_WRITABLE_MASK; | |
f160c7b7 JS |
3406 | |
3407 | /* | |
d3e328f2 JS |
3408 | * Do not fix write-permission on the large spte. Since |
3409 | * we only dirty the first page into the dirty-bitmap in | |
3410 | * fast_pf_fix_direct_spte(), other pages are missed | |
3411 | * if its slot has dirty logging enabled. | |
3412 | * | |
3413 | * Instead, we let the slow page fault path create a | |
3414 | * normal spte to fix the access. | |
3415 | * | |
3416 | * See the comments in kvm_arch_commit_memory_region(). | |
f160c7b7 | 3417 | */ |
d3e328f2 | 3418 | if (sp->role.level > PT_PAGE_TABLE_LEVEL) |
f160c7b7 | 3419 | break; |
97dceba2 | 3420 | } |
c7ba5b48 | 3421 | |
f160c7b7 | 3422 | /* Verify that the fault can be handled in the fast path */ |
d3e328f2 JS |
3423 | if (new_spte == spte || |
3424 | !is_access_allowed(error_code, new_spte)) | |
97dceba2 JS |
3425 | break; |
3426 | ||
3427 | /* | |
3428 | * Currently, fast page fault only works for direct mapping | |
3429 | * since the gfn is not stable for indirect shadow page. See | |
3430 | * Documentation/virtual/kvm/locking.txt to get more detail. | |
3431 | */ | |
3432 | fault_handled = fast_pf_fix_direct_spte(vcpu, sp, | |
f160c7b7 | 3433 | iterator.sptep, spte, |
d3e328f2 | 3434 | new_spte); |
97dceba2 JS |
3435 | if (fault_handled) |
3436 | break; | |
3437 | ||
3438 | if (++retry_count > 4) { | |
3439 | printk_once(KERN_WARNING | |
3440 | "kvm: Fast #PF retrying more than 4 times.\n"); | |
3441 | break; | |
3442 | } | |
3443 | ||
97dceba2 | 3444 | } while (true); |
c126d94f | 3445 | |
a72faf25 | 3446 | trace_fast_page_fault(vcpu, gva, error_code, iterator.sptep, |
97dceba2 | 3447 | spte, fault_handled); |
c7ba5b48 XG |
3448 | walk_shadow_page_lockless_end(vcpu); |
3449 | ||
97dceba2 | 3450 | return fault_handled; |
c7ba5b48 XG |
3451 | } |
3452 | ||
78b2c54a | 3453 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 3454 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable); |
26eeb53c | 3455 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu); |
060c2abe | 3456 | |
c7ba5b48 XG |
3457 | static int nonpaging_map(struct kvm_vcpu *vcpu, gva_t v, u32 error_code, |
3458 | gfn_t gfn, bool prefault) | |
10589a46 MT |
3459 | { |
3460 | int r; | |
852e3c19 | 3461 | int level; |
fd136902 | 3462 | bool force_pt_level = false; |
ba049e93 | 3463 | kvm_pfn_t pfn; |
e930bffe | 3464 | unsigned long mmu_seq; |
c7ba5b48 | 3465 | bool map_writable, write = error_code & PFERR_WRITE_MASK; |
aaee2c94 | 3466 | |
fd136902 | 3467 | level = mapping_level(vcpu, gfn, &force_pt_level); |
936a5fe6 | 3468 | if (likely(!force_pt_level)) { |
936a5fe6 AA |
3469 | /* |
3470 | * This path builds a PAE pagetable - so we can map | |
3471 | * 2mb pages at maximum. Therefore check if the level | |
3472 | * is larger than that. | |
3473 | */ | |
3474 | if (level > PT_DIRECTORY_LEVEL) | |
3475 | level = PT_DIRECTORY_LEVEL; | |
852e3c19 | 3476 | |
936a5fe6 | 3477 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 3478 | } |
05da4558 | 3479 | |
c7ba5b48 | 3480 | if (fast_page_fault(vcpu, v, level, error_code)) |
9b8ebbdb | 3481 | return RET_PF_RETRY; |
c7ba5b48 | 3482 | |
e930bffe | 3483 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 3484 | smp_rmb(); |
060c2abe | 3485 | |
78b2c54a | 3486 | if (try_async_pf(vcpu, prefault, gfn, v, &pfn, write, &map_writable)) |
9b8ebbdb | 3487 | return RET_PF_RETRY; |
aaee2c94 | 3488 | |
d7c55201 XG |
3489 | if (handle_abnormal_pfn(vcpu, v, gfn, pfn, ACC_ALL, &r)) |
3490 | return r; | |
d196e343 | 3491 | |
aaee2c94 | 3492 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 3493 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 3494 | goto out_unlock; |
26eeb53c WL |
3495 | if (make_mmu_pages_available(vcpu) < 0) |
3496 | goto out_unlock; | |
936a5fe6 AA |
3497 | if (likely(!force_pt_level)) |
3498 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 3499 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
aaee2c94 MT |
3500 | spin_unlock(&vcpu->kvm->mmu_lock); |
3501 | ||
10589a46 | 3502 | return r; |
e930bffe AA |
3503 | |
3504 | out_unlock: | |
3505 | spin_unlock(&vcpu->kvm->mmu_lock); | |
3506 | kvm_release_pfn_clean(pfn); | |
9b8ebbdb | 3507 | return RET_PF_RETRY; |
10589a46 MT |
3508 | } |
3509 | ||
74b566e6 JS |
3510 | static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa, |
3511 | struct list_head *invalid_list) | |
17ac10ad | 3512 | { |
4db35314 | 3513 | struct kvm_mmu_page *sp; |
17ac10ad | 3514 | |
74b566e6 | 3515 | if (!VALID_PAGE(*root_hpa)) |
7b53aa56 | 3516 | return; |
35af577a | 3517 | |
74b566e6 JS |
3518 | sp = page_header(*root_hpa & PT64_BASE_ADDR_MASK); |
3519 | --sp->root_count; | |
3520 | if (!sp->root_count && sp->role.invalid) | |
3521 | kvm_mmu_prepare_zap_page(kvm, sp, invalid_list); | |
17ac10ad | 3522 | |
74b566e6 JS |
3523 | *root_hpa = INVALID_PAGE; |
3524 | } | |
3525 | ||
08fb59d8 | 3526 | /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */ |
6a82cd1c VK |
3527 | void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, |
3528 | ulong roots_to_free) | |
74b566e6 JS |
3529 | { |
3530 | int i; | |
3531 | LIST_HEAD(invalid_list); | |
08fb59d8 | 3532 | bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT; |
74b566e6 | 3533 | |
b94742c9 | 3534 | BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG); |
74b566e6 | 3535 | |
08fb59d8 | 3536 | /* Before acquiring the MMU lock, see if we need to do any real work. */ |
b94742c9 JS |
3537 | if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) { |
3538 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
3539 | if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) && | |
3540 | VALID_PAGE(mmu->prev_roots[i].hpa)) | |
3541 | break; | |
3542 | ||
3543 | if (i == KVM_MMU_NUM_PREV_ROOTS) | |
3544 | return; | |
3545 | } | |
35af577a GN |
3546 | |
3547 | spin_lock(&vcpu->kvm->mmu_lock); | |
17ac10ad | 3548 | |
b94742c9 JS |
3549 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
3550 | if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) | |
3551 | mmu_free_root_page(vcpu->kvm, &mmu->prev_roots[i].hpa, | |
3552 | &invalid_list); | |
7c390d35 | 3553 | |
08fb59d8 JS |
3554 | if (free_active_root) { |
3555 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
3556 | (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) { | |
3557 | mmu_free_root_page(vcpu->kvm, &mmu->root_hpa, | |
3558 | &invalid_list); | |
3559 | } else { | |
3560 | for (i = 0; i < 4; ++i) | |
3561 | if (mmu->pae_root[i] != 0) | |
3562 | mmu_free_root_page(vcpu->kvm, | |
3563 | &mmu->pae_root[i], | |
3564 | &invalid_list); | |
3565 | mmu->root_hpa = INVALID_PAGE; | |
3566 | } | |
17ac10ad | 3567 | } |
74b566e6 | 3568 | |
d98ba053 | 3569 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
aaee2c94 | 3570 | spin_unlock(&vcpu->kvm->mmu_lock); |
17ac10ad | 3571 | } |
74b566e6 | 3572 | EXPORT_SYMBOL_GPL(kvm_mmu_free_roots); |
17ac10ad | 3573 | |
8986ecc0 MT |
3574 | static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn) |
3575 | { | |
3576 | int ret = 0; | |
3577 | ||
3578 | if (!kvm_is_visible_gfn(vcpu->kvm, root_gfn)) { | |
a8eeb04a | 3579 | kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu); |
8986ecc0 MT |
3580 | ret = 1; |
3581 | } | |
3582 | ||
3583 | return ret; | |
3584 | } | |
3585 | ||
651dd37a JR |
3586 | static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu) |
3587 | { | |
3588 | struct kvm_mmu_page *sp; | |
7ebaf15e | 3589 | unsigned i; |
651dd37a | 3590 | |
44dd3ffa | 3591 | if (vcpu->arch.mmu->shadow_root_level >= PT64_ROOT_4LEVEL) { |
651dd37a | 3592 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3593 | if(make_mmu_pages_available(vcpu) < 0) { |
3594 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3595 | return -ENOSPC; |
26eeb53c | 3596 | } |
855feb67 | 3597 | sp = kvm_mmu_get_page(vcpu, 0, 0, |
44dd3ffa | 3598 | vcpu->arch.mmu->shadow_root_level, 1, ACC_ALL); |
651dd37a JR |
3599 | ++sp->root_count; |
3600 | spin_unlock(&vcpu->kvm->mmu_lock); | |
44dd3ffa VK |
3601 | vcpu->arch.mmu->root_hpa = __pa(sp->spt); |
3602 | } else if (vcpu->arch.mmu->shadow_root_level == PT32E_ROOT_LEVEL) { | |
651dd37a | 3603 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3604 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
651dd37a | 3605 | |
fa4a2c08 | 3606 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3607 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3608 | if (make_mmu_pages_available(vcpu) < 0) { |
3609 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3610 | return -ENOSPC; |
26eeb53c | 3611 | } |
649497d1 | 3612 | sp = kvm_mmu_get_page(vcpu, i << (30 - PAGE_SHIFT), |
bb11c6c9 | 3613 | i << 30, PT32_ROOT_LEVEL, 1, ACC_ALL); |
651dd37a JR |
3614 | root = __pa(sp->spt); |
3615 | ++sp->root_count; | |
3616 | spin_unlock(&vcpu->kvm->mmu_lock); | |
44dd3ffa | 3617 | vcpu->arch.mmu->pae_root[i] = root | PT_PRESENT_MASK; |
651dd37a | 3618 | } |
44dd3ffa | 3619 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root); |
651dd37a JR |
3620 | } else |
3621 | BUG(); | |
3622 | ||
3623 | return 0; | |
3624 | } | |
3625 | ||
3626 | static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu) | |
17ac10ad | 3627 | { |
4db35314 | 3628 | struct kvm_mmu_page *sp; |
81407ca5 JR |
3629 | u64 pdptr, pm_mask; |
3630 | gfn_t root_gfn; | |
3631 | int i; | |
3bb65a22 | 3632 | |
44dd3ffa | 3633 | root_gfn = vcpu->arch.mmu->get_cr3(vcpu) >> PAGE_SHIFT; |
17ac10ad | 3634 | |
651dd37a JR |
3635 | if (mmu_check_root(vcpu, root_gfn)) |
3636 | return 1; | |
3637 | ||
3638 | /* | |
3639 | * Do we shadow a long mode page table? If so we need to | |
3640 | * write-protect the guests page table root. | |
3641 | */ | |
44dd3ffa VK |
3642 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
3643 | hpa_t root = vcpu->arch.mmu->root_hpa; | |
17ac10ad | 3644 | |
fa4a2c08 | 3645 | MMU_WARN_ON(VALID_PAGE(root)); |
651dd37a | 3646 | |
8facbbff | 3647 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3648 | if (make_mmu_pages_available(vcpu) < 0) { |
3649 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3650 | return -ENOSPC; |
26eeb53c | 3651 | } |
855feb67 | 3652 | sp = kvm_mmu_get_page(vcpu, root_gfn, 0, |
44dd3ffa | 3653 | vcpu->arch.mmu->shadow_root_level, 0, ACC_ALL); |
4db35314 AK |
3654 | root = __pa(sp->spt); |
3655 | ++sp->root_count; | |
8facbbff | 3656 | spin_unlock(&vcpu->kvm->mmu_lock); |
44dd3ffa | 3657 | vcpu->arch.mmu->root_hpa = root; |
8986ecc0 | 3658 | return 0; |
17ac10ad | 3659 | } |
f87f9288 | 3660 | |
651dd37a JR |
3661 | /* |
3662 | * We shadow a 32 bit page table. This may be a legacy 2-level | |
81407ca5 JR |
3663 | * or a PAE 3-level page table. In either case we need to be aware that |
3664 | * the shadow page table may be a PAE or a long mode page table. | |
651dd37a | 3665 | */ |
81407ca5 | 3666 | pm_mask = PT_PRESENT_MASK; |
44dd3ffa | 3667 | if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) |
81407ca5 JR |
3668 | pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK; |
3669 | ||
17ac10ad | 3670 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3671 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
17ac10ad | 3672 | |
fa4a2c08 | 3673 | MMU_WARN_ON(VALID_PAGE(root)); |
44dd3ffa VK |
3674 | if (vcpu->arch.mmu->root_level == PT32E_ROOT_LEVEL) { |
3675 | pdptr = vcpu->arch.mmu->get_pdptr(vcpu, i); | |
812f30b2 | 3676 | if (!(pdptr & PT_PRESENT_MASK)) { |
44dd3ffa | 3677 | vcpu->arch.mmu->pae_root[i] = 0; |
417726a3 AK |
3678 | continue; |
3679 | } | |
6de4f3ad | 3680 | root_gfn = pdptr >> PAGE_SHIFT; |
f87f9288 JR |
3681 | if (mmu_check_root(vcpu, root_gfn)) |
3682 | return 1; | |
5a7388c2 | 3683 | } |
8facbbff | 3684 | spin_lock(&vcpu->kvm->mmu_lock); |
26eeb53c WL |
3685 | if (make_mmu_pages_available(vcpu) < 0) { |
3686 | spin_unlock(&vcpu->kvm->mmu_lock); | |
ed52870f | 3687 | return -ENOSPC; |
26eeb53c | 3688 | } |
bb11c6c9 TY |
3689 | sp = kvm_mmu_get_page(vcpu, root_gfn, i << 30, PT32_ROOT_LEVEL, |
3690 | 0, ACC_ALL); | |
4db35314 AK |
3691 | root = __pa(sp->spt); |
3692 | ++sp->root_count; | |
8facbbff AK |
3693 | spin_unlock(&vcpu->kvm->mmu_lock); |
3694 | ||
44dd3ffa | 3695 | vcpu->arch.mmu->pae_root[i] = root | pm_mask; |
17ac10ad | 3696 | } |
44dd3ffa | 3697 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->pae_root); |
81407ca5 JR |
3698 | |
3699 | /* | |
3700 | * If we shadow a 32 bit page table with a long mode page | |
3701 | * table we enter this path. | |
3702 | */ | |
44dd3ffa VK |
3703 | if (vcpu->arch.mmu->shadow_root_level == PT64_ROOT_4LEVEL) { |
3704 | if (vcpu->arch.mmu->lm_root == NULL) { | |
81407ca5 JR |
3705 | /* |
3706 | * The additional page necessary for this is only | |
3707 | * allocated on demand. | |
3708 | */ | |
3709 | ||
3710 | u64 *lm_root; | |
3711 | ||
254272ce | 3712 | lm_root = (void*)get_zeroed_page(GFP_KERNEL_ACCOUNT); |
81407ca5 JR |
3713 | if (lm_root == NULL) |
3714 | return 1; | |
3715 | ||
44dd3ffa | 3716 | lm_root[0] = __pa(vcpu->arch.mmu->pae_root) | pm_mask; |
81407ca5 | 3717 | |
44dd3ffa | 3718 | vcpu->arch.mmu->lm_root = lm_root; |
81407ca5 JR |
3719 | } |
3720 | ||
44dd3ffa | 3721 | vcpu->arch.mmu->root_hpa = __pa(vcpu->arch.mmu->lm_root); |
81407ca5 JR |
3722 | } |
3723 | ||
8986ecc0 | 3724 | return 0; |
17ac10ad AK |
3725 | } |
3726 | ||
651dd37a JR |
3727 | static int mmu_alloc_roots(struct kvm_vcpu *vcpu) |
3728 | { | |
44dd3ffa | 3729 | if (vcpu->arch.mmu->direct_map) |
651dd37a JR |
3730 | return mmu_alloc_direct_roots(vcpu); |
3731 | else | |
3732 | return mmu_alloc_shadow_roots(vcpu); | |
3733 | } | |
3734 | ||
578e1c4d | 3735 | void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu) |
0ba73cda MT |
3736 | { |
3737 | int i; | |
3738 | struct kvm_mmu_page *sp; | |
3739 | ||
44dd3ffa | 3740 | if (vcpu->arch.mmu->direct_map) |
81407ca5 JR |
3741 | return; |
3742 | ||
44dd3ffa | 3743 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
0ba73cda | 3744 | return; |
6903074c | 3745 | |
56f17dd3 | 3746 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); |
578e1c4d | 3747 | |
44dd3ffa VK |
3748 | if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) { |
3749 | hpa_t root = vcpu->arch.mmu->root_hpa; | |
0ba73cda | 3750 | sp = page_header(root); |
578e1c4d JS |
3751 | |
3752 | /* | |
3753 | * Even if another CPU was marking the SP as unsync-ed | |
3754 | * simultaneously, any guest page table changes are not | |
3755 | * guaranteed to be visible anyway until this VCPU issues a TLB | |
3756 | * flush strictly after those changes are made. We only need to | |
3757 | * ensure that the other CPU sets these flags before any actual | |
3758 | * changes to the page tables are made. The comments in | |
3759 | * mmu_need_write_protect() describe what could go wrong if this | |
3760 | * requirement isn't satisfied. | |
3761 | */ | |
3762 | if (!smp_load_acquire(&sp->unsync) && | |
3763 | !smp_load_acquire(&sp->unsync_children)) | |
3764 | return; | |
3765 | ||
3766 | spin_lock(&vcpu->kvm->mmu_lock); | |
3767 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
3768 | ||
0ba73cda | 3769 | mmu_sync_children(vcpu, sp); |
578e1c4d | 3770 | |
0375f7fa | 3771 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
578e1c4d | 3772 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda MT |
3773 | return; |
3774 | } | |
578e1c4d JS |
3775 | |
3776 | spin_lock(&vcpu->kvm->mmu_lock); | |
3777 | kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC); | |
3778 | ||
0ba73cda | 3779 | for (i = 0; i < 4; ++i) { |
44dd3ffa | 3780 | hpa_t root = vcpu->arch.mmu->pae_root[i]; |
0ba73cda | 3781 | |
8986ecc0 | 3782 | if (root && VALID_PAGE(root)) { |
0ba73cda MT |
3783 | root &= PT64_BASE_ADDR_MASK; |
3784 | sp = page_header(root); | |
3785 | mmu_sync_children(vcpu, sp); | |
3786 | } | |
3787 | } | |
0ba73cda | 3788 | |
578e1c4d | 3789 | kvm_mmu_audit(vcpu, AUDIT_POST_SYNC); |
6cffe8ca | 3790 | spin_unlock(&vcpu->kvm->mmu_lock); |
0ba73cda | 3791 | } |
bfd0a56b | 3792 | EXPORT_SYMBOL_GPL(kvm_mmu_sync_roots); |
0ba73cda | 3793 | |
1871c602 | 3794 | static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 | 3795 | u32 access, struct x86_exception *exception) |
6aa8b732 | 3796 | { |
ab9ae313 AK |
3797 | if (exception) |
3798 | exception->error_code = 0; | |
6aa8b732 AK |
3799 | return vaddr; |
3800 | } | |
3801 | ||
6539e738 | 3802 | static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gva_t vaddr, |
ab9ae313 AK |
3803 | u32 access, |
3804 | struct x86_exception *exception) | |
6539e738 | 3805 | { |
ab9ae313 AK |
3806 | if (exception) |
3807 | exception->error_code = 0; | |
54987b7a | 3808 | return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception); |
6539e738 JR |
3809 | } |
3810 | ||
d625b155 XG |
3811 | static bool |
3812 | __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level) | |
3813 | { | |
3814 | int bit7 = (pte >> 7) & 1, low6 = pte & 0x3f; | |
3815 | ||
3816 | return (pte & rsvd_check->rsvd_bits_mask[bit7][level-1]) | | |
3817 | ((rsvd_check->bad_mt_xwr & (1ull << low6)) != 0); | |
3818 | } | |
3819 | ||
3820 | static bool is_rsvd_bits_set(struct kvm_mmu *mmu, u64 gpte, int level) | |
3821 | { | |
3822 | return __is_rsvd_bits_set(&mmu->guest_rsvd_check, gpte, level); | |
3823 | } | |
3824 | ||
3825 | static bool is_shadow_zero_bits_set(struct kvm_mmu *mmu, u64 spte, int level) | |
3826 | { | |
3827 | return __is_rsvd_bits_set(&mmu->shadow_zero_check, spte, level); | |
3828 | } | |
3829 | ||
ded58749 | 3830 | static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf | 3831 | { |
9034e6e8 PB |
3832 | /* |
3833 | * A nested guest cannot use the MMIO cache if it is using nested | |
3834 | * page tables, because cr2 is a nGPA while the cache stores GPAs. | |
3835 | */ | |
3836 | if (mmu_is_nested(vcpu)) | |
3837 | return false; | |
3838 | ||
ce88decf XG |
3839 | if (direct) |
3840 | return vcpu_match_mmio_gpa(vcpu, addr); | |
3841 | ||
3842 | return vcpu_match_mmio_gva(vcpu, addr); | |
3843 | } | |
3844 | ||
47ab8751 XG |
3845 | /* return true if reserved bit is detected on spte. */ |
3846 | static bool | |
3847 | walk_shadow_page_get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep) | |
ce88decf XG |
3848 | { |
3849 | struct kvm_shadow_walk_iterator iterator; | |
2a7266a8 | 3850 | u64 sptes[PT64_ROOT_MAX_LEVEL], spte = 0ull; |
47ab8751 XG |
3851 | int root, leaf; |
3852 | bool reserved = false; | |
ce88decf | 3853 | |
44dd3ffa | 3854 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
47ab8751 | 3855 | goto exit; |
37f6a4e2 | 3856 | |
ce88decf | 3857 | walk_shadow_page_lockless_begin(vcpu); |
47ab8751 | 3858 | |
29ecd660 PB |
3859 | for (shadow_walk_init(&iterator, vcpu, addr), |
3860 | leaf = root = iterator.level; | |
47ab8751 XG |
3861 | shadow_walk_okay(&iterator); |
3862 | __shadow_walk_next(&iterator, spte)) { | |
47ab8751 XG |
3863 | spte = mmu_spte_get_lockless(iterator.sptep); |
3864 | ||
3865 | sptes[leaf - 1] = spte; | |
29ecd660 | 3866 | leaf--; |
47ab8751 | 3867 | |
ce88decf XG |
3868 | if (!is_shadow_present_pte(spte)) |
3869 | break; | |
47ab8751 | 3870 | |
44dd3ffa | 3871 | reserved |= is_shadow_zero_bits_set(vcpu->arch.mmu, spte, |
58c95070 | 3872 | iterator.level); |
47ab8751 XG |
3873 | } |
3874 | ||
ce88decf XG |
3875 | walk_shadow_page_lockless_end(vcpu); |
3876 | ||
47ab8751 XG |
3877 | if (reserved) { |
3878 | pr_err("%s: detect reserved bits on spte, addr 0x%llx, dump hierarchy:\n", | |
3879 | __func__, addr); | |
29ecd660 | 3880 | while (root > leaf) { |
47ab8751 XG |
3881 | pr_err("------ spte 0x%llx level %d.\n", |
3882 | sptes[root - 1], root); | |
3883 | root--; | |
3884 | } | |
3885 | } | |
3886 | exit: | |
3887 | *sptep = spte; | |
3888 | return reserved; | |
ce88decf XG |
3889 | } |
3890 | ||
e08d26f0 | 3891 | static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct) |
ce88decf XG |
3892 | { |
3893 | u64 spte; | |
47ab8751 | 3894 | bool reserved; |
ce88decf | 3895 | |
ded58749 | 3896 | if (mmio_info_in_cache(vcpu, addr, direct)) |
9b8ebbdb | 3897 | return RET_PF_EMULATE; |
ce88decf | 3898 | |
47ab8751 | 3899 | reserved = walk_shadow_page_get_mmio_spte(vcpu, addr, &spte); |
450869d6 | 3900 | if (WARN_ON(reserved)) |
9b8ebbdb | 3901 | return -EINVAL; |
ce88decf XG |
3902 | |
3903 | if (is_mmio_spte(spte)) { | |
3904 | gfn_t gfn = get_mmio_spte_gfn(spte); | |
3905 | unsigned access = get_mmio_spte_access(spte); | |
3906 | ||
54bf36aa | 3907 | if (!check_mmio_spte(vcpu, spte)) |
9b8ebbdb | 3908 | return RET_PF_INVALID; |
f8f55942 | 3909 | |
ce88decf XG |
3910 | if (direct) |
3911 | addr = 0; | |
4f022648 XG |
3912 | |
3913 | trace_handle_mmio_page_fault(addr, gfn, access); | |
ce88decf | 3914 | vcpu_cache_mmio_info(vcpu, addr, gfn, access); |
9b8ebbdb | 3915 | return RET_PF_EMULATE; |
ce88decf XG |
3916 | } |
3917 | ||
ce88decf XG |
3918 | /* |
3919 | * If the page table is zapped by other cpus, let CPU fault again on | |
3920 | * the address. | |
3921 | */ | |
9b8ebbdb | 3922 | return RET_PF_RETRY; |
ce88decf | 3923 | } |
ce88decf | 3924 | |
3d0c27ad XG |
3925 | static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu, |
3926 | u32 error_code, gfn_t gfn) | |
3927 | { | |
3928 | if (unlikely(error_code & PFERR_RSVD_MASK)) | |
3929 | return false; | |
3930 | ||
3931 | if (!(error_code & PFERR_PRESENT_MASK) || | |
3932 | !(error_code & PFERR_WRITE_MASK)) | |
3933 | return false; | |
3934 | ||
3935 | /* | |
3936 | * guest is writing the page which is write tracked which can | |
3937 | * not be fixed by page fault handler. | |
3938 | */ | |
3939 | if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE)) | |
3940 | return true; | |
3941 | ||
3942 | return false; | |
3943 | } | |
3944 | ||
e5691a81 XG |
3945 | static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr) |
3946 | { | |
3947 | struct kvm_shadow_walk_iterator iterator; | |
3948 | u64 spte; | |
3949 | ||
44dd3ffa | 3950 | if (!VALID_PAGE(vcpu->arch.mmu->root_hpa)) |
e5691a81 XG |
3951 | return; |
3952 | ||
3953 | walk_shadow_page_lockless_begin(vcpu); | |
3954 | for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) { | |
3955 | clear_sp_write_flooding_count(iterator.sptep); | |
3956 | if (!is_shadow_present_pte(spte)) | |
3957 | break; | |
3958 | } | |
3959 | walk_shadow_page_lockless_end(vcpu); | |
3960 | } | |
3961 | ||
6aa8b732 | 3962 | static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gva_t gva, |
78b2c54a | 3963 | u32 error_code, bool prefault) |
6aa8b732 | 3964 | { |
3d0c27ad | 3965 | gfn_t gfn = gva >> PAGE_SHIFT; |
e2dec939 | 3966 | int r; |
6aa8b732 | 3967 | |
b8688d51 | 3968 | pgprintk("%s: gva %lx error %x\n", __func__, gva, error_code); |
ce88decf | 3969 | |
3d0c27ad | 3970 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 3971 | return RET_PF_EMULATE; |
ce88decf | 3972 | |
e2dec939 AK |
3973 | r = mmu_topup_memory_caches(vcpu); |
3974 | if (r) | |
3975 | return r; | |
714b93da | 3976 | |
44dd3ffa | 3977 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)); |
6aa8b732 | 3978 | |
6aa8b732 | 3979 | |
e833240f | 3980 | return nonpaging_map(vcpu, gva & PAGE_MASK, |
c7ba5b48 | 3981 | error_code, gfn, prefault); |
6aa8b732 AK |
3982 | } |
3983 | ||
7e1fbeac | 3984 | static int kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn) |
af585b92 GN |
3985 | { |
3986 | struct kvm_arch_async_pf arch; | |
fb67e14f | 3987 | |
7c90705b | 3988 | arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id; |
af585b92 | 3989 | arch.gfn = gfn; |
44dd3ffa VK |
3990 | arch.direct_map = vcpu->arch.mmu->direct_map; |
3991 | arch.cr3 = vcpu->arch.mmu->get_cr3(vcpu); | |
af585b92 | 3992 | |
54bf36aa | 3993 | return kvm_setup_async_pf(vcpu, gva, kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch); |
af585b92 GN |
3994 | } |
3995 | ||
9bc1f09f | 3996 | bool kvm_can_do_async_pf(struct kvm_vcpu *vcpu) |
af585b92 | 3997 | { |
35754c98 | 3998 | if (unlikely(!lapic_in_kernel(vcpu) || |
2a266f23 HZ |
3999 | kvm_event_needs_reinjection(vcpu) || |
4000 | vcpu->arch.exception.pending)) | |
af585b92 GN |
4001 | return false; |
4002 | ||
52a5c155 | 4003 | if (!vcpu->arch.apf.delivery_as_pf_vmexit && is_guest_mode(vcpu)) |
9bc1f09f WL |
4004 | return false; |
4005 | ||
af585b92 GN |
4006 | return kvm_x86_ops->interrupt_allowed(vcpu); |
4007 | } | |
4008 | ||
78b2c54a | 4009 | static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn, |
ba049e93 | 4010 | gva_t gva, kvm_pfn_t *pfn, bool write, bool *writable) |
af585b92 | 4011 | { |
3520469d | 4012 | struct kvm_memory_slot *slot; |
af585b92 GN |
4013 | bool async; |
4014 | ||
3a2936de JM |
4015 | /* |
4016 | * Don't expose private memslots to L2. | |
4017 | */ | |
4018 | if (is_guest_mode(vcpu) && !kvm_is_visible_gfn(vcpu->kvm, gfn)) { | |
4019 | *pfn = KVM_PFN_NOSLOT; | |
4020 | return false; | |
4021 | } | |
4022 | ||
54bf36aa | 4023 | slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn); |
3520469d PB |
4024 | async = false; |
4025 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async, write, writable); | |
af585b92 GN |
4026 | if (!async) |
4027 | return false; /* *pfn has correct page already */ | |
4028 | ||
9bc1f09f | 4029 | if (!prefault && kvm_can_do_async_pf(vcpu)) { |
c9b263d2 | 4030 | trace_kvm_try_async_get_page(gva, gfn); |
af585b92 GN |
4031 | if (kvm_find_async_pf_gfn(vcpu, gfn)) { |
4032 | trace_kvm_async_pf_doublefault(gva, gfn); | |
4033 | kvm_make_request(KVM_REQ_APF_HALT, vcpu); | |
4034 | return true; | |
4035 | } else if (kvm_arch_setup_async_pf(vcpu, gva, gfn)) | |
4036 | return true; | |
4037 | } | |
4038 | ||
3520469d | 4039 | *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL, write, writable); |
af585b92 GN |
4040 | return false; |
4041 | } | |
4042 | ||
1261bfa3 | 4043 | int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code, |
d0006530 | 4044 | u64 fault_address, char *insn, int insn_len) |
1261bfa3 WL |
4045 | { |
4046 | int r = 1; | |
4047 | ||
c595ceee | 4048 | vcpu->arch.l1tf_flush_l1d = true; |
1261bfa3 WL |
4049 | switch (vcpu->arch.apf.host_apf_reason) { |
4050 | default: | |
4051 | trace_kvm_page_fault(fault_address, error_code); | |
4052 | ||
d0006530 | 4053 | if (kvm_event_needs_reinjection(vcpu)) |
1261bfa3 WL |
4054 | kvm_mmu_unprotect_page_virt(vcpu, fault_address); |
4055 | r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn, | |
4056 | insn_len); | |
4057 | break; | |
4058 | case KVM_PV_REASON_PAGE_NOT_PRESENT: | |
4059 | vcpu->arch.apf.host_apf_reason = 0; | |
4060 | local_irq_disable(); | |
a2b7861b | 4061 | kvm_async_pf_task_wait(fault_address, 0); |
1261bfa3 WL |
4062 | local_irq_enable(); |
4063 | break; | |
4064 | case KVM_PV_REASON_PAGE_READY: | |
4065 | vcpu->arch.apf.host_apf_reason = 0; | |
4066 | local_irq_disable(); | |
4067 | kvm_async_pf_task_wake(fault_address); | |
4068 | local_irq_enable(); | |
4069 | break; | |
4070 | } | |
4071 | return r; | |
4072 | } | |
4073 | EXPORT_SYMBOL_GPL(kvm_handle_page_fault); | |
4074 | ||
6a39bbc5 XG |
4075 | static bool |
4076 | check_hugepage_cache_consistency(struct kvm_vcpu *vcpu, gfn_t gfn, int level) | |
4077 | { | |
4078 | int page_num = KVM_PAGES_PER_HPAGE(level); | |
4079 | ||
4080 | gfn &= ~(page_num - 1); | |
4081 | ||
4082 | return kvm_mtrr_check_gfn_range_consistency(vcpu, gfn, page_num); | |
4083 | } | |
4084 | ||
56028d08 | 4085 | static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code, |
78b2c54a | 4086 | bool prefault) |
fb72d167 | 4087 | { |
ba049e93 | 4088 | kvm_pfn_t pfn; |
fb72d167 | 4089 | int r; |
852e3c19 | 4090 | int level; |
cd1872f0 | 4091 | bool force_pt_level; |
05da4558 | 4092 | gfn_t gfn = gpa >> PAGE_SHIFT; |
e930bffe | 4093 | unsigned long mmu_seq; |
612819c3 MT |
4094 | int write = error_code & PFERR_WRITE_MASK; |
4095 | bool map_writable; | |
fb72d167 | 4096 | |
44dd3ffa | 4097 | MMU_WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)); |
fb72d167 | 4098 | |
3d0c27ad | 4099 | if (page_fault_handle_page_track(vcpu, error_code, gfn)) |
9b8ebbdb | 4100 | return RET_PF_EMULATE; |
ce88decf | 4101 | |
fb72d167 JR |
4102 | r = mmu_topup_memory_caches(vcpu); |
4103 | if (r) | |
4104 | return r; | |
4105 | ||
fd136902 TY |
4106 | force_pt_level = !check_hugepage_cache_consistency(vcpu, gfn, |
4107 | PT_DIRECTORY_LEVEL); | |
4108 | level = mapping_level(vcpu, gfn, &force_pt_level); | |
936a5fe6 | 4109 | if (likely(!force_pt_level)) { |
6a39bbc5 XG |
4110 | if (level > PT_DIRECTORY_LEVEL && |
4111 | !check_hugepage_cache_consistency(vcpu, gfn, level)) | |
4112 | level = PT_DIRECTORY_LEVEL; | |
936a5fe6 | 4113 | gfn &= ~(KVM_PAGES_PER_HPAGE(level) - 1); |
fd136902 | 4114 | } |
852e3c19 | 4115 | |
c7ba5b48 | 4116 | if (fast_page_fault(vcpu, gpa, level, error_code)) |
9b8ebbdb | 4117 | return RET_PF_RETRY; |
c7ba5b48 | 4118 | |
e930bffe | 4119 | mmu_seq = vcpu->kvm->mmu_notifier_seq; |
4c2155ce | 4120 | smp_rmb(); |
af585b92 | 4121 | |
78b2c54a | 4122 | if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, write, &map_writable)) |
9b8ebbdb | 4123 | return RET_PF_RETRY; |
af585b92 | 4124 | |
d7c55201 XG |
4125 | if (handle_abnormal_pfn(vcpu, 0, gfn, pfn, ACC_ALL, &r)) |
4126 | return r; | |
4127 | ||
fb72d167 | 4128 | spin_lock(&vcpu->kvm->mmu_lock); |
8ca40a70 | 4129 | if (mmu_notifier_retry(vcpu->kvm, mmu_seq)) |
e930bffe | 4130 | goto out_unlock; |
26eeb53c WL |
4131 | if (make_mmu_pages_available(vcpu) < 0) |
4132 | goto out_unlock; | |
936a5fe6 AA |
4133 | if (likely(!force_pt_level)) |
4134 | transparent_hugepage_adjust(vcpu, &gfn, &pfn, &level); | |
7ee0e5b2 | 4135 | r = __direct_map(vcpu, write, map_writable, level, gfn, pfn, prefault); |
fb72d167 | 4136 | spin_unlock(&vcpu->kvm->mmu_lock); |
fb72d167 JR |
4137 | |
4138 | return r; | |
e930bffe AA |
4139 | |
4140 | out_unlock: | |
4141 | spin_unlock(&vcpu->kvm->mmu_lock); | |
4142 | kvm_release_pfn_clean(pfn); | |
9b8ebbdb | 4143 | return RET_PF_RETRY; |
fb72d167 JR |
4144 | } |
4145 | ||
8a3c1a33 PB |
4146 | static void nonpaging_init_context(struct kvm_vcpu *vcpu, |
4147 | struct kvm_mmu *context) | |
6aa8b732 | 4148 | { |
6aa8b732 | 4149 | context->page_fault = nonpaging_page_fault; |
6aa8b732 | 4150 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
e8bc217a | 4151 | context->sync_page = nonpaging_sync_page; |
a7052897 | 4152 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 4153 | context->update_pte = nonpaging_update_pte; |
cea0f0e7 | 4154 | context->root_level = 0; |
6aa8b732 | 4155 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 4156 | context->direct_map = true; |
2d48a985 | 4157 | context->nx = false; |
6aa8b732 AK |
4158 | } |
4159 | ||
b94742c9 JS |
4160 | /* |
4161 | * Find out if a previously cached root matching the new CR3/role is available. | |
4162 | * The current root is also inserted into the cache. | |
4163 | * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is | |
4164 | * returned. | |
4165 | * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and | |
4166 | * false is returned. This root should now be freed by the caller. | |
4167 | */ | |
4168 | static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_cr3, | |
4169 | union kvm_mmu_page_role new_role) | |
4170 | { | |
4171 | uint i; | |
4172 | struct kvm_mmu_root_info root; | |
44dd3ffa | 4173 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
b94742c9 JS |
4174 | |
4175 | root.cr3 = mmu->get_cr3(vcpu); | |
4176 | root.hpa = mmu->root_hpa; | |
4177 | ||
4178 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { | |
4179 | swap(root, mmu->prev_roots[i]); | |
4180 | ||
4181 | if (new_cr3 == root.cr3 && VALID_PAGE(root.hpa) && | |
4182 | page_header(root.hpa) != NULL && | |
4183 | new_role.word == page_header(root.hpa)->role.word) | |
4184 | break; | |
4185 | } | |
4186 | ||
4187 | mmu->root_hpa = root.hpa; | |
4188 | ||
4189 | return i < KVM_MMU_NUM_PREV_ROOTS; | |
4190 | } | |
4191 | ||
0aab33e4 | 4192 | static bool fast_cr3_switch(struct kvm_vcpu *vcpu, gpa_t new_cr3, |
ade61e28 JS |
4193 | union kvm_mmu_page_role new_role, |
4194 | bool skip_tlb_flush) | |
6aa8b732 | 4195 | { |
44dd3ffa | 4196 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
7c390d35 JS |
4197 | |
4198 | /* | |
4199 | * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid | |
4200 | * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs | |
4201 | * later if necessary. | |
4202 | */ | |
4203 | if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL && | |
4204 | mmu->root_level >= PT64_ROOT_4LEVEL) { | |
7c390d35 JS |
4205 | if (mmu_check_root(vcpu, new_cr3 >> PAGE_SHIFT)) |
4206 | return false; | |
4207 | ||
b94742c9 | 4208 | if (cached_root_available(vcpu, new_cr3, new_role)) { |
7c390d35 JS |
4209 | /* |
4210 | * It is possible that the cached previous root page is | |
4211 | * obsolete because of a change in the MMU | |
4212 | * generation number. However, that is accompanied by | |
4213 | * KVM_REQ_MMU_RELOAD, which will free the root that we | |
4214 | * have set here and allocate a new one. | |
4215 | */ | |
4216 | ||
0aab33e4 | 4217 | kvm_make_request(KVM_REQ_LOAD_CR3, vcpu); |
956bf353 JS |
4218 | if (!skip_tlb_flush) { |
4219 | kvm_make_request(KVM_REQ_MMU_SYNC, vcpu); | |
ade61e28 | 4220 | kvm_x86_ops->tlb_flush(vcpu, true); |
956bf353 JS |
4221 | } |
4222 | ||
4223 | /* | |
4224 | * The last MMIO access's GVA and GPA are cached in the | |
4225 | * VCPU. When switching to a new CR3, that GVA->GPA | |
4226 | * mapping may no longer be valid. So clear any cached | |
4227 | * MMIO info even when we don't need to sync the shadow | |
4228 | * page tables. | |
4229 | */ | |
4230 | vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY); | |
ade61e28 | 4231 | |
7c390d35 JS |
4232 | __clear_sp_write_flooding_count( |
4233 | page_header(mmu->root_hpa)); | |
4234 | ||
7c390d35 JS |
4235 | return true; |
4236 | } | |
4237 | } | |
4238 | ||
4239 | return false; | |
6aa8b732 AK |
4240 | } |
4241 | ||
0aab33e4 | 4242 | static void __kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, |
ade61e28 JS |
4243 | union kvm_mmu_page_role new_role, |
4244 | bool skip_tlb_flush) | |
6aa8b732 | 4245 | { |
ade61e28 | 4246 | if (!fast_cr3_switch(vcpu, new_cr3, new_role, skip_tlb_flush)) |
6a82cd1c VK |
4247 | kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, |
4248 | KVM_MMU_ROOT_CURRENT); | |
6aa8b732 AK |
4249 | } |
4250 | ||
ade61e28 | 4251 | void kvm_mmu_new_cr3(struct kvm_vcpu *vcpu, gpa_t new_cr3, bool skip_tlb_flush) |
0aab33e4 | 4252 | { |
ade61e28 JS |
4253 | __kvm_mmu_new_cr3(vcpu, new_cr3, kvm_mmu_calc_root_page_role(vcpu), |
4254 | skip_tlb_flush); | |
0aab33e4 | 4255 | } |
50c28f21 | 4256 | EXPORT_SYMBOL_GPL(kvm_mmu_new_cr3); |
0aab33e4 | 4257 | |
5777ed34 JR |
4258 | static unsigned long get_cr3(struct kvm_vcpu *vcpu) |
4259 | { | |
9f8fe504 | 4260 | return kvm_read_cr3(vcpu); |
5777ed34 JR |
4261 | } |
4262 | ||
6389ee94 AK |
4263 | static void inject_page_fault(struct kvm_vcpu *vcpu, |
4264 | struct x86_exception *fault) | |
6aa8b732 | 4265 | { |
44dd3ffa | 4266 | vcpu->arch.mmu->inject_page_fault(vcpu, fault); |
6aa8b732 AK |
4267 | } |
4268 | ||
54bf36aa | 4269 | static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn, |
f2fd125d | 4270 | unsigned access, int *nr_present) |
ce88decf XG |
4271 | { |
4272 | if (unlikely(is_mmio_spte(*sptep))) { | |
4273 | if (gfn != get_mmio_spte_gfn(*sptep)) { | |
4274 | mmu_spte_clear_no_track(sptep); | |
4275 | return true; | |
4276 | } | |
4277 | ||
4278 | (*nr_present)++; | |
54bf36aa | 4279 | mark_mmio_spte(vcpu, sptep, gfn, access); |
ce88decf XG |
4280 | return true; |
4281 | } | |
4282 | ||
4283 | return false; | |
4284 | } | |
4285 | ||
6bb69c9b PB |
4286 | static inline bool is_last_gpte(struct kvm_mmu *mmu, |
4287 | unsigned level, unsigned gpte) | |
6fd01b71 | 4288 | { |
6bb69c9b PB |
4289 | /* |
4290 | * The RHS has bit 7 set iff level < mmu->last_nonleaf_level. | |
4291 | * If it is clear, there are no large pages at this level, so clear | |
4292 | * PT_PAGE_SIZE_MASK in gpte if that is the case. | |
4293 | */ | |
4294 | gpte &= level - mmu->last_nonleaf_level; | |
4295 | ||
829ee279 LP |
4296 | /* |
4297 | * PT_PAGE_TABLE_LEVEL always terminates. The RHS has bit 7 set | |
4298 | * iff level <= PT_PAGE_TABLE_LEVEL, which for our purpose means | |
4299 | * level == PT_PAGE_TABLE_LEVEL; set PT_PAGE_SIZE_MASK in gpte then. | |
4300 | */ | |
4301 | gpte |= level - PT_PAGE_TABLE_LEVEL - 1; | |
4302 | ||
6bb69c9b | 4303 | return gpte & PT_PAGE_SIZE_MASK; |
6fd01b71 AK |
4304 | } |
4305 | ||
37406aaa NHE |
4306 | #define PTTYPE_EPT 18 /* arbitrary */ |
4307 | #define PTTYPE PTTYPE_EPT | |
4308 | #include "paging_tmpl.h" | |
4309 | #undef PTTYPE | |
4310 | ||
6aa8b732 AK |
4311 | #define PTTYPE 64 |
4312 | #include "paging_tmpl.h" | |
4313 | #undef PTTYPE | |
4314 | ||
4315 | #define PTTYPE 32 | |
4316 | #include "paging_tmpl.h" | |
4317 | #undef PTTYPE | |
4318 | ||
6dc98b86 XG |
4319 | static void |
4320 | __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, | |
4321 | struct rsvd_bits_validate *rsvd_check, | |
4322 | int maxphyaddr, int level, bool nx, bool gbpages, | |
6fec2144 | 4323 | bool pse, bool amd) |
82725b20 | 4324 | { |
82725b20 | 4325 | u64 exb_bit_rsvd = 0; |
5f7dde7b | 4326 | u64 gbpages_bit_rsvd = 0; |
a0c0feb5 | 4327 | u64 nonleaf_bit8_rsvd = 0; |
82725b20 | 4328 | |
a0a64f50 | 4329 | rsvd_check->bad_mt_xwr = 0; |
25d92081 | 4330 | |
6dc98b86 | 4331 | if (!nx) |
82725b20 | 4332 | exb_bit_rsvd = rsvd_bits(63, 63); |
6dc98b86 | 4333 | if (!gbpages) |
5f7dde7b | 4334 | gbpages_bit_rsvd = rsvd_bits(7, 7); |
a0c0feb5 PB |
4335 | |
4336 | /* | |
4337 | * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for | |
4338 | * leaf entries) on AMD CPUs only. | |
4339 | */ | |
6fec2144 | 4340 | if (amd) |
a0c0feb5 PB |
4341 | nonleaf_bit8_rsvd = rsvd_bits(8, 8); |
4342 | ||
6dc98b86 | 4343 | switch (level) { |
82725b20 DE |
4344 | case PT32_ROOT_LEVEL: |
4345 | /* no rsvd bits for 2 level 4K page table entries */ | |
a0a64f50 XG |
4346 | rsvd_check->rsvd_bits_mask[0][1] = 0; |
4347 | rsvd_check->rsvd_bits_mask[0][0] = 0; | |
4348 | rsvd_check->rsvd_bits_mask[1][0] = | |
4349 | rsvd_check->rsvd_bits_mask[0][0]; | |
f815bce8 | 4350 | |
6dc98b86 | 4351 | if (!pse) { |
a0a64f50 | 4352 | rsvd_check->rsvd_bits_mask[1][1] = 0; |
f815bce8 XG |
4353 | break; |
4354 | } | |
4355 | ||
82725b20 DE |
4356 | if (is_cpuid_PSE36()) |
4357 | /* 36bits PSE 4MB page */ | |
a0a64f50 | 4358 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21); |
82725b20 DE |
4359 | else |
4360 | /* 32 bits PSE 4MB page */ | |
a0a64f50 | 4361 | rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21); |
82725b20 DE |
4362 | break; |
4363 | case PT32E_ROOT_LEVEL: | |
a0a64f50 | 4364 | rsvd_check->rsvd_bits_mask[0][2] = |
20c466b5 | 4365 | rsvd_bits(maxphyaddr, 63) | |
cd9ae5fe | 4366 | rsvd_bits(5, 8) | rsvd_bits(1, 2); /* PDPTE */ |
a0a64f50 | 4367 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4c26b4cd | 4368 | rsvd_bits(maxphyaddr, 62); /* PDE */ |
a0a64f50 | 4369 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | |
82725b20 | 4370 | rsvd_bits(maxphyaddr, 62); /* PTE */ |
a0a64f50 | 4371 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
82725b20 DE |
4372 | rsvd_bits(maxphyaddr, 62) | |
4373 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4374 | rsvd_check->rsvd_bits_mask[1][0] = |
4375 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 | 4376 | break; |
855feb67 YZ |
4377 | case PT64_ROOT_5LEVEL: |
4378 | rsvd_check->rsvd_bits_mask[0][4] = exb_bit_rsvd | | |
4379 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4380 | rsvd_bits(maxphyaddr, 51); | |
4381 | rsvd_check->rsvd_bits_mask[1][4] = | |
4382 | rsvd_check->rsvd_bits_mask[0][4]; | |
b2869f28 | 4383 | /* fall through */ |
2a7266a8 | 4384 | case PT64_ROOT_4LEVEL: |
a0a64f50 XG |
4385 | rsvd_check->rsvd_bits_mask[0][3] = exb_bit_rsvd | |
4386 | nonleaf_bit8_rsvd | rsvd_bits(7, 7) | | |
4c26b4cd | 4387 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
4388 | rsvd_check->rsvd_bits_mask[0][2] = exb_bit_rsvd | |
4389 | nonleaf_bit8_rsvd | gbpages_bit_rsvd | | |
82725b20 | 4390 | rsvd_bits(maxphyaddr, 51); |
a0a64f50 XG |
4391 | rsvd_check->rsvd_bits_mask[0][1] = exb_bit_rsvd | |
4392 | rsvd_bits(maxphyaddr, 51); | |
4393 | rsvd_check->rsvd_bits_mask[0][0] = exb_bit_rsvd | | |
4394 | rsvd_bits(maxphyaddr, 51); | |
4395 | rsvd_check->rsvd_bits_mask[1][3] = | |
4396 | rsvd_check->rsvd_bits_mask[0][3]; | |
4397 | rsvd_check->rsvd_bits_mask[1][2] = exb_bit_rsvd | | |
5f7dde7b | 4398 | gbpages_bit_rsvd | rsvd_bits(maxphyaddr, 51) | |
e04da980 | 4399 | rsvd_bits(13, 29); |
a0a64f50 | 4400 | rsvd_check->rsvd_bits_mask[1][1] = exb_bit_rsvd | |
4c26b4cd SY |
4401 | rsvd_bits(maxphyaddr, 51) | |
4402 | rsvd_bits(13, 20); /* large page */ | |
a0a64f50 XG |
4403 | rsvd_check->rsvd_bits_mask[1][0] = |
4404 | rsvd_check->rsvd_bits_mask[0][0]; | |
82725b20 DE |
4405 | break; |
4406 | } | |
4407 | } | |
4408 | ||
6dc98b86 XG |
4409 | static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu, |
4410 | struct kvm_mmu *context) | |
4411 | { | |
4412 | __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check, | |
4413 | cpuid_maxphyaddr(vcpu), context->root_level, | |
d6321d49 RK |
4414 | context->nx, |
4415 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), | |
6fec2144 | 4416 | is_pse(vcpu), guest_cpuid_is_amd(vcpu)); |
6dc98b86 XG |
4417 | } |
4418 | ||
81b8eebb XG |
4419 | static void |
4420 | __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check, | |
4421 | int maxphyaddr, bool execonly) | |
25d92081 | 4422 | { |
951f9fd7 | 4423 | u64 bad_mt_xwr; |
25d92081 | 4424 | |
855feb67 YZ |
4425 | rsvd_check->rsvd_bits_mask[0][4] = |
4426 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); | |
a0a64f50 | 4427 | rsvd_check->rsvd_bits_mask[0][3] = |
25d92081 | 4428 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 7); |
a0a64f50 | 4429 | rsvd_check->rsvd_bits_mask[0][2] = |
25d92081 | 4430 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4431 | rsvd_check->rsvd_bits_mask[0][1] = |
25d92081 | 4432 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(3, 6); |
a0a64f50 | 4433 | rsvd_check->rsvd_bits_mask[0][0] = rsvd_bits(maxphyaddr, 51); |
25d92081 YZ |
4434 | |
4435 | /* large page */ | |
855feb67 | 4436 | rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4]; |
a0a64f50 XG |
4437 | rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3]; |
4438 | rsvd_check->rsvd_bits_mask[1][2] = | |
25d92081 | 4439 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 29); |
a0a64f50 | 4440 | rsvd_check->rsvd_bits_mask[1][1] = |
25d92081 | 4441 | rsvd_bits(maxphyaddr, 51) | rsvd_bits(12, 20); |
a0a64f50 | 4442 | rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0]; |
25d92081 | 4443 | |
951f9fd7 PB |
4444 | bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */ |
4445 | bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */ | |
4446 | bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */ | |
4447 | bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */ | |
4448 | bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */ | |
4449 | if (!execonly) { | |
4450 | /* bits 0..2 must not be 100 unless VMX capabilities allow it */ | |
4451 | bad_mt_xwr |= REPEAT_BYTE(1ull << 4); | |
25d92081 | 4452 | } |
951f9fd7 | 4453 | rsvd_check->bad_mt_xwr = bad_mt_xwr; |
25d92081 YZ |
4454 | } |
4455 | ||
81b8eebb XG |
4456 | static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu, |
4457 | struct kvm_mmu *context, bool execonly) | |
4458 | { | |
4459 | __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check, | |
4460 | cpuid_maxphyaddr(vcpu), execonly); | |
4461 | } | |
4462 | ||
c258b62b XG |
4463 | /* |
4464 | * the page table on host is the shadow page table for the page | |
4465 | * table in guest or amd nested guest, its mmu features completely | |
4466 | * follow the features in guest. | |
4467 | */ | |
4468 | void | |
4469 | reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, struct kvm_mmu *context) | |
4470 | { | |
36d9594d VK |
4471 | bool uses_nx = context->nx || |
4472 | context->mmu_role.base.smep_andnot_wp; | |
ea2800dd BS |
4473 | struct rsvd_bits_validate *shadow_zero_check; |
4474 | int i; | |
5f0b8199 | 4475 | |
6fec2144 PB |
4476 | /* |
4477 | * Passing "true" to the last argument is okay; it adds a check | |
4478 | * on bit 8 of the SPTEs which KVM doesn't use anyway. | |
4479 | */ | |
ea2800dd BS |
4480 | shadow_zero_check = &context->shadow_zero_check; |
4481 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, | |
c258b62b | 4482 | boot_cpu_data.x86_phys_bits, |
5f0b8199 | 4483 | context->shadow_root_level, uses_nx, |
d6321d49 RK |
4484 | guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES), |
4485 | is_pse(vcpu), true); | |
ea2800dd BS |
4486 | |
4487 | if (!shadow_me_mask) | |
4488 | return; | |
4489 | ||
4490 | for (i = context->shadow_root_level; --i >= 0;) { | |
4491 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4492 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4493 | } | |
4494 | ||
c258b62b XG |
4495 | } |
4496 | EXPORT_SYMBOL_GPL(reset_shadow_zero_bits_mask); | |
4497 | ||
6fec2144 PB |
4498 | static inline bool boot_cpu_is_amd(void) |
4499 | { | |
4500 | WARN_ON_ONCE(!tdp_enabled); | |
4501 | return shadow_x_mask == 0; | |
4502 | } | |
4503 | ||
c258b62b XG |
4504 | /* |
4505 | * the direct page table on host, use as much mmu features as | |
4506 | * possible, however, kvm currently does not do execution-protection. | |
4507 | */ | |
4508 | static void | |
4509 | reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4510 | struct kvm_mmu *context) | |
4511 | { | |
ea2800dd BS |
4512 | struct rsvd_bits_validate *shadow_zero_check; |
4513 | int i; | |
4514 | ||
4515 | shadow_zero_check = &context->shadow_zero_check; | |
4516 | ||
6fec2144 | 4517 | if (boot_cpu_is_amd()) |
ea2800dd | 4518 | __reset_rsvds_bits_mask(vcpu, shadow_zero_check, |
c258b62b XG |
4519 | boot_cpu_data.x86_phys_bits, |
4520 | context->shadow_root_level, false, | |
b8291adc BP |
4521 | boot_cpu_has(X86_FEATURE_GBPAGES), |
4522 | true, true); | |
c258b62b | 4523 | else |
ea2800dd | 4524 | __reset_rsvds_bits_mask_ept(shadow_zero_check, |
c258b62b XG |
4525 | boot_cpu_data.x86_phys_bits, |
4526 | false); | |
4527 | ||
ea2800dd BS |
4528 | if (!shadow_me_mask) |
4529 | return; | |
4530 | ||
4531 | for (i = context->shadow_root_level; --i >= 0;) { | |
4532 | shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask; | |
4533 | shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask; | |
4534 | } | |
c258b62b XG |
4535 | } |
4536 | ||
4537 | /* | |
4538 | * as the comments in reset_shadow_zero_bits_mask() except it | |
4539 | * is the shadow page table for intel nested guest. | |
4540 | */ | |
4541 | static void | |
4542 | reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu, | |
4543 | struct kvm_mmu *context, bool execonly) | |
4544 | { | |
4545 | __reset_rsvds_bits_mask_ept(&context->shadow_zero_check, | |
4546 | boot_cpu_data.x86_phys_bits, execonly); | |
4547 | } | |
4548 | ||
09f037aa PB |
4549 | #define BYTE_MASK(access) \ |
4550 | ((1 & (access) ? 2 : 0) | \ | |
4551 | (2 & (access) ? 4 : 0) | \ | |
4552 | (3 & (access) ? 8 : 0) | \ | |
4553 | (4 & (access) ? 16 : 0) | \ | |
4554 | (5 & (access) ? 32 : 0) | \ | |
4555 | (6 & (access) ? 64 : 0) | \ | |
4556 | (7 & (access) ? 128 : 0)) | |
4557 | ||
4558 | ||
edc90b7d XG |
4559 | static void update_permission_bitmask(struct kvm_vcpu *vcpu, |
4560 | struct kvm_mmu *mmu, bool ept) | |
97d64b78 | 4561 | { |
09f037aa PB |
4562 | unsigned byte; |
4563 | ||
4564 | const u8 x = BYTE_MASK(ACC_EXEC_MASK); | |
4565 | const u8 w = BYTE_MASK(ACC_WRITE_MASK); | |
4566 | const u8 u = BYTE_MASK(ACC_USER_MASK); | |
4567 | ||
4568 | bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0; | |
4569 | bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0; | |
4570 | bool cr0_wp = is_write_protection(vcpu); | |
97d64b78 | 4571 | |
97d64b78 | 4572 | for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) { |
09f037aa PB |
4573 | unsigned pfec = byte << 1; |
4574 | ||
97ec8c06 | 4575 | /* |
09f037aa PB |
4576 | * Each "*f" variable has a 1 bit for each UWX value |
4577 | * that causes a fault with the given PFEC. | |
97ec8c06 | 4578 | */ |
97d64b78 | 4579 | |
09f037aa PB |
4580 | /* Faults from writes to non-writable pages */ |
4581 | u8 wf = (pfec & PFERR_WRITE_MASK) ? ~w : 0; | |
4582 | /* Faults from user mode accesses to supervisor pages */ | |
4583 | u8 uf = (pfec & PFERR_USER_MASK) ? ~u : 0; | |
4584 | /* Faults from fetches of non-executable pages*/ | |
4585 | u8 ff = (pfec & PFERR_FETCH_MASK) ? ~x : 0; | |
4586 | /* Faults from kernel mode fetches of user pages */ | |
4587 | u8 smepf = 0; | |
4588 | /* Faults from kernel mode accesses of user pages */ | |
4589 | u8 smapf = 0; | |
4590 | ||
4591 | if (!ept) { | |
4592 | /* Faults from kernel mode accesses to user pages */ | |
4593 | u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u; | |
4594 | ||
4595 | /* Not really needed: !nx will cause pte.nx to fault */ | |
4596 | if (!mmu->nx) | |
4597 | ff = 0; | |
4598 | ||
4599 | /* Allow supervisor writes if !cr0.wp */ | |
4600 | if (!cr0_wp) | |
4601 | wf = (pfec & PFERR_USER_MASK) ? wf : 0; | |
4602 | ||
4603 | /* Disallow supervisor fetches of user code if cr4.smep */ | |
4604 | if (cr4_smep) | |
4605 | smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0; | |
4606 | ||
4607 | /* | |
4608 | * SMAP:kernel-mode data accesses from user-mode | |
4609 | * mappings should fault. A fault is considered | |
4610 | * as a SMAP violation if all of the following | |
39337ad1 | 4611 | * conditions are true: |
09f037aa PB |
4612 | * - X86_CR4_SMAP is set in CR4 |
4613 | * - A user page is accessed | |
4614 | * - The access is not a fetch | |
4615 | * - Page fault in kernel mode | |
4616 | * - if CPL = 3 or X86_EFLAGS_AC is clear | |
4617 | * | |
4618 | * Here, we cover the first three conditions. | |
4619 | * The fourth is computed dynamically in permission_fault(); | |
4620 | * PFERR_RSVD_MASK bit will be set in PFEC if the access is | |
4621 | * *not* subject to SMAP restrictions. | |
4622 | */ | |
4623 | if (cr4_smap) | |
4624 | smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf; | |
97d64b78 | 4625 | } |
09f037aa PB |
4626 | |
4627 | mmu->permissions[byte] = ff | uf | wf | smepf | smapf; | |
97d64b78 AK |
4628 | } |
4629 | } | |
4630 | ||
2d344105 HH |
4631 | /* |
4632 | * PKU is an additional mechanism by which the paging controls access to | |
4633 | * user-mode addresses based on the value in the PKRU register. Protection | |
4634 | * key violations are reported through a bit in the page fault error code. | |
4635 | * Unlike other bits of the error code, the PK bit is not known at the | |
4636 | * call site of e.g. gva_to_gpa; it must be computed directly in | |
4637 | * permission_fault based on two bits of PKRU, on some machine state (CR4, | |
4638 | * CR0, EFER, CPL), and on other bits of the error code and the page tables. | |
4639 | * | |
4640 | * In particular the following conditions come from the error code, the | |
4641 | * page tables and the machine state: | |
4642 | * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1 | |
4643 | * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch) | |
4644 | * - PK is always zero if U=0 in the page tables | |
4645 | * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access. | |
4646 | * | |
4647 | * The PKRU bitmask caches the result of these four conditions. The error | |
4648 | * code (minus the P bit) and the page table's U bit form an index into the | |
4649 | * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed | |
4650 | * with the two bits of the PKRU register corresponding to the protection key. | |
4651 | * For the first three conditions above the bits will be 00, thus masking | |
4652 | * away both AD and WD. For all reads or if the last condition holds, WD | |
4653 | * only will be masked away. | |
4654 | */ | |
4655 | static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu, | |
4656 | bool ept) | |
4657 | { | |
4658 | unsigned bit; | |
4659 | bool wp; | |
4660 | ||
4661 | if (ept) { | |
4662 | mmu->pkru_mask = 0; | |
4663 | return; | |
4664 | } | |
4665 | ||
4666 | /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */ | |
4667 | if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) { | |
4668 | mmu->pkru_mask = 0; | |
4669 | return; | |
4670 | } | |
4671 | ||
4672 | wp = is_write_protection(vcpu); | |
4673 | ||
4674 | for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) { | |
4675 | unsigned pfec, pkey_bits; | |
4676 | bool check_pkey, check_write, ff, uf, wf, pte_user; | |
4677 | ||
4678 | pfec = bit << 1; | |
4679 | ff = pfec & PFERR_FETCH_MASK; | |
4680 | uf = pfec & PFERR_USER_MASK; | |
4681 | wf = pfec & PFERR_WRITE_MASK; | |
4682 | ||
4683 | /* PFEC.RSVD is replaced by ACC_USER_MASK. */ | |
4684 | pte_user = pfec & PFERR_RSVD_MASK; | |
4685 | ||
4686 | /* | |
4687 | * Only need to check the access which is not an | |
4688 | * instruction fetch and is to a user page. | |
4689 | */ | |
4690 | check_pkey = (!ff && pte_user); | |
4691 | /* | |
4692 | * write access is controlled by PKRU if it is a | |
4693 | * user access or CR0.WP = 1. | |
4694 | */ | |
4695 | check_write = check_pkey && wf && (uf || wp); | |
4696 | ||
4697 | /* PKRU.AD stops both read and write access. */ | |
4698 | pkey_bits = !!check_pkey; | |
4699 | /* PKRU.WD stops write access. */ | |
4700 | pkey_bits |= (!!check_write) << 1; | |
4701 | ||
4702 | mmu->pkru_mask |= (pkey_bits & 3) << pfec; | |
4703 | } | |
4704 | } | |
4705 | ||
6bb69c9b | 4706 | static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu) |
6fd01b71 | 4707 | { |
6bb69c9b PB |
4708 | unsigned root_level = mmu->root_level; |
4709 | ||
4710 | mmu->last_nonleaf_level = root_level; | |
4711 | if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu)) | |
4712 | mmu->last_nonleaf_level++; | |
6fd01b71 AK |
4713 | } |
4714 | ||
8a3c1a33 PB |
4715 | static void paging64_init_context_common(struct kvm_vcpu *vcpu, |
4716 | struct kvm_mmu *context, | |
4717 | int level) | |
6aa8b732 | 4718 | { |
2d48a985 | 4719 | context->nx = is_nx(vcpu); |
4d6931c3 | 4720 | context->root_level = level; |
2d48a985 | 4721 | |
4d6931c3 | 4722 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4723 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4724 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4725 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4726 | |
fa4a2c08 | 4727 | MMU_WARN_ON(!is_pae(vcpu)); |
6aa8b732 | 4728 | context->page_fault = paging64_page_fault; |
6aa8b732 | 4729 | context->gva_to_gpa = paging64_gva_to_gpa; |
e8bc217a | 4730 | context->sync_page = paging64_sync_page; |
a7052897 | 4731 | context->invlpg = paging64_invlpg; |
0f53b5b1 | 4732 | context->update_pte = paging64_update_pte; |
17ac10ad | 4733 | context->shadow_root_level = level; |
c5a78f2b | 4734 | context->direct_map = false; |
6aa8b732 AK |
4735 | } |
4736 | ||
8a3c1a33 PB |
4737 | static void paging64_init_context(struct kvm_vcpu *vcpu, |
4738 | struct kvm_mmu *context) | |
17ac10ad | 4739 | { |
855feb67 YZ |
4740 | int root_level = is_la57_mode(vcpu) ? |
4741 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4742 | ||
4743 | paging64_init_context_common(vcpu, context, root_level); | |
17ac10ad AK |
4744 | } |
4745 | ||
8a3c1a33 PB |
4746 | static void paging32_init_context(struct kvm_vcpu *vcpu, |
4747 | struct kvm_mmu *context) | |
6aa8b732 | 4748 | { |
2d48a985 | 4749 | context->nx = false; |
4d6931c3 | 4750 | context->root_level = PT32_ROOT_LEVEL; |
2d48a985 | 4751 | |
4d6931c3 | 4752 | reset_rsvds_bits_mask(vcpu, context); |
25d92081 | 4753 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4754 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4755 | update_last_nonleaf_level(vcpu, context); |
6aa8b732 | 4756 | |
6aa8b732 | 4757 | context->page_fault = paging32_page_fault; |
6aa8b732 | 4758 | context->gva_to_gpa = paging32_gva_to_gpa; |
e8bc217a | 4759 | context->sync_page = paging32_sync_page; |
a7052897 | 4760 | context->invlpg = paging32_invlpg; |
0f53b5b1 | 4761 | context->update_pte = paging32_update_pte; |
6aa8b732 | 4762 | context->shadow_root_level = PT32E_ROOT_LEVEL; |
c5a78f2b | 4763 | context->direct_map = false; |
6aa8b732 AK |
4764 | } |
4765 | ||
8a3c1a33 PB |
4766 | static void paging32E_init_context(struct kvm_vcpu *vcpu, |
4767 | struct kvm_mmu *context) | |
6aa8b732 | 4768 | { |
8a3c1a33 | 4769 | paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL); |
6aa8b732 AK |
4770 | } |
4771 | ||
a336282d VK |
4772 | static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu) |
4773 | { | |
4774 | union kvm_mmu_extended_role ext = {0}; | |
4775 | ||
7dcd5755 | 4776 | ext.cr0_pg = !!is_paging(vcpu); |
a336282d VK |
4777 | ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP); |
4778 | ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP); | |
4779 | ext.cr4_pse = !!is_pse(vcpu); | |
4780 | ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE); | |
7dcd5755 | 4781 | ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57); |
a336282d VK |
4782 | |
4783 | ext.valid = 1; | |
4784 | ||
4785 | return ext; | |
4786 | } | |
4787 | ||
7dcd5755 VK |
4788 | static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu, |
4789 | bool base_only) | |
4790 | { | |
4791 | union kvm_mmu_role role = {0}; | |
4792 | ||
4793 | role.base.access = ACC_ALL; | |
4794 | role.base.nxe = !!is_nx(vcpu); | |
4795 | role.base.cr4_pae = !!is_pae(vcpu); | |
4796 | role.base.cr0_wp = is_write_protection(vcpu); | |
4797 | role.base.smm = is_smm(vcpu); | |
4798 | role.base.guest_mode = is_guest_mode(vcpu); | |
4799 | ||
4800 | if (base_only) | |
4801 | return role; | |
4802 | ||
4803 | role.ext = kvm_calc_mmu_role_ext(vcpu); | |
4804 | ||
4805 | return role; | |
4806 | } | |
4807 | ||
4808 | static union kvm_mmu_role | |
4809 | kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
9fa72119 | 4810 | { |
7dcd5755 | 4811 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); |
9fa72119 | 4812 | |
7dcd5755 VK |
4813 | role.base.ad_disabled = (shadow_accessed_mask == 0); |
4814 | role.base.level = kvm_x86_ops->get_tdp_level(vcpu); | |
4815 | role.base.direct = true; | |
9fa72119 JS |
4816 | |
4817 | return role; | |
4818 | } | |
4819 | ||
8a3c1a33 | 4820 | static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu) |
fb72d167 | 4821 | { |
44dd3ffa | 4822 | struct kvm_mmu *context = vcpu->arch.mmu; |
7dcd5755 VK |
4823 | union kvm_mmu_role new_role = |
4824 | kvm_calc_tdp_mmu_root_page_role(vcpu, false); | |
fb72d167 | 4825 | |
7dcd5755 VK |
4826 | new_role.base.word &= mmu_base_role_mask.word; |
4827 | if (new_role.as_u64 == context->mmu_role.as_u64) | |
4828 | return; | |
4829 | ||
4830 | context->mmu_role.as_u64 = new_role.as_u64; | |
fb72d167 | 4831 | context->page_fault = tdp_page_fault; |
e8bc217a | 4832 | context->sync_page = nonpaging_sync_page; |
a7052897 | 4833 | context->invlpg = nonpaging_invlpg; |
0f53b5b1 | 4834 | context->update_pte = nonpaging_update_pte; |
855feb67 | 4835 | context->shadow_root_level = kvm_x86_ops->get_tdp_level(vcpu); |
c5a78f2b | 4836 | context->direct_map = true; |
1c97f0a0 | 4837 | context->set_cr3 = kvm_x86_ops->set_tdp_cr3; |
5777ed34 | 4838 | context->get_cr3 = get_cr3; |
e4e517b4 | 4839 | context->get_pdptr = kvm_pdptr_read; |
cb659db8 | 4840 | context->inject_page_fault = kvm_inject_page_fault; |
fb72d167 JR |
4841 | |
4842 | if (!is_paging(vcpu)) { | |
2d48a985 | 4843 | context->nx = false; |
fb72d167 JR |
4844 | context->gva_to_gpa = nonpaging_gva_to_gpa; |
4845 | context->root_level = 0; | |
4846 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 4847 | context->nx = is_nx(vcpu); |
855feb67 YZ |
4848 | context->root_level = is_la57_mode(vcpu) ? |
4849 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 DB |
4850 | reset_rsvds_bits_mask(vcpu, context); |
4851 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4852 | } else if (is_pae(vcpu)) { |
2d48a985 | 4853 | context->nx = is_nx(vcpu); |
fb72d167 | 4854 | context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 DB |
4855 | reset_rsvds_bits_mask(vcpu, context); |
4856 | context->gva_to_gpa = paging64_gva_to_gpa; | |
fb72d167 | 4857 | } else { |
2d48a985 | 4858 | context->nx = false; |
fb72d167 | 4859 | context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 DB |
4860 | reset_rsvds_bits_mask(vcpu, context); |
4861 | context->gva_to_gpa = paging32_gva_to_gpa; | |
fb72d167 JR |
4862 | } |
4863 | ||
25d92081 | 4864 | update_permission_bitmask(vcpu, context, false); |
2d344105 | 4865 | update_pkru_bitmask(vcpu, context, false); |
6bb69c9b | 4866 | update_last_nonleaf_level(vcpu, context); |
c258b62b | 4867 | reset_tdp_shadow_zero_bits_mask(vcpu, context); |
fb72d167 JR |
4868 | } |
4869 | ||
7dcd5755 VK |
4870 | static union kvm_mmu_role |
4871 | kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only) | |
4872 | { | |
4873 | union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only); | |
4874 | ||
4875 | role.base.smep_andnot_wp = role.ext.cr4_smep && | |
4876 | !is_write_protection(vcpu); | |
4877 | role.base.smap_andnot_wp = role.ext.cr4_smap && | |
4878 | !is_write_protection(vcpu); | |
4879 | role.base.direct = !is_paging(vcpu); | |
9fa72119 JS |
4880 | |
4881 | if (!is_long_mode(vcpu)) | |
7dcd5755 | 4882 | role.base.level = PT32E_ROOT_LEVEL; |
9fa72119 | 4883 | else if (is_la57_mode(vcpu)) |
7dcd5755 | 4884 | role.base.level = PT64_ROOT_5LEVEL; |
9fa72119 | 4885 | else |
7dcd5755 | 4886 | role.base.level = PT64_ROOT_4LEVEL; |
9fa72119 JS |
4887 | |
4888 | return role; | |
4889 | } | |
4890 | ||
4891 | void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu) | |
4892 | { | |
44dd3ffa | 4893 | struct kvm_mmu *context = vcpu->arch.mmu; |
7dcd5755 VK |
4894 | union kvm_mmu_role new_role = |
4895 | kvm_calc_shadow_mmu_root_page_role(vcpu, false); | |
4896 | ||
4897 | new_role.base.word &= mmu_base_role_mask.word; | |
4898 | if (new_role.as_u64 == context->mmu_role.as_u64) | |
4899 | return; | |
6aa8b732 AK |
4900 | |
4901 | if (!is_paging(vcpu)) | |
8a3c1a33 | 4902 | nonpaging_init_context(vcpu, context); |
a9058ecd | 4903 | else if (is_long_mode(vcpu)) |
8a3c1a33 | 4904 | paging64_init_context(vcpu, context); |
6aa8b732 | 4905 | else if (is_pae(vcpu)) |
8a3c1a33 | 4906 | paging32E_init_context(vcpu, context); |
6aa8b732 | 4907 | else |
8a3c1a33 | 4908 | paging32_init_context(vcpu, context); |
a770f6f2 | 4909 | |
7dcd5755 | 4910 | context->mmu_role.as_u64 = new_role.as_u64; |
c258b62b | 4911 | reset_shadow_zero_bits_mask(vcpu, context); |
52fde8df JR |
4912 | } |
4913 | EXPORT_SYMBOL_GPL(kvm_init_shadow_mmu); | |
4914 | ||
a336282d VK |
4915 | static union kvm_mmu_role |
4916 | kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty, | |
4917 | bool execonly) | |
9fa72119 | 4918 | { |
a336282d | 4919 | union kvm_mmu_role role; |
14c07ad8 | 4920 | |
a336282d VK |
4921 | /* Base role is inherited from root_mmu */ |
4922 | role.base.word = vcpu->arch.root_mmu.mmu_role.base.word; | |
4923 | role.ext = kvm_calc_mmu_role_ext(vcpu); | |
9fa72119 | 4924 | |
a336282d VK |
4925 | role.base.level = PT64_ROOT_4LEVEL; |
4926 | role.base.direct = false; | |
4927 | role.base.ad_disabled = !accessed_dirty; | |
4928 | role.base.guest_mode = true; | |
4929 | role.base.access = ACC_ALL; | |
9fa72119 | 4930 | |
a336282d | 4931 | role.ext.execonly = execonly; |
9fa72119 JS |
4932 | |
4933 | return role; | |
4934 | } | |
4935 | ||
ae1e2d10 | 4936 | void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly, |
50c28f21 | 4937 | bool accessed_dirty, gpa_t new_eptp) |
155a97a3 | 4938 | { |
44dd3ffa | 4939 | struct kvm_mmu *context = vcpu->arch.mmu; |
a336282d VK |
4940 | union kvm_mmu_role new_role = |
4941 | kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty, | |
4942 | execonly); | |
4943 | ||
4944 | __kvm_mmu_new_cr3(vcpu, new_eptp, new_role.base, false); | |
4945 | ||
4946 | new_role.base.word &= mmu_base_role_mask.word; | |
4947 | if (new_role.as_u64 == context->mmu_role.as_u64) | |
4948 | return; | |
ad896af0 | 4949 | |
855feb67 | 4950 | context->shadow_root_level = PT64_ROOT_4LEVEL; |
155a97a3 NHE |
4951 | |
4952 | context->nx = true; | |
ae1e2d10 | 4953 | context->ept_ad = accessed_dirty; |
155a97a3 NHE |
4954 | context->page_fault = ept_page_fault; |
4955 | context->gva_to_gpa = ept_gva_to_gpa; | |
4956 | context->sync_page = ept_sync_page; | |
4957 | context->invlpg = ept_invlpg; | |
4958 | context->update_pte = ept_update_pte; | |
855feb67 | 4959 | context->root_level = PT64_ROOT_4LEVEL; |
155a97a3 | 4960 | context->direct_map = false; |
a336282d | 4961 | context->mmu_role.as_u64 = new_role.as_u64; |
3dc773e7 | 4962 | |
155a97a3 | 4963 | update_permission_bitmask(vcpu, context, true); |
2d344105 | 4964 | update_pkru_bitmask(vcpu, context, true); |
fd19d3b4 | 4965 | update_last_nonleaf_level(vcpu, context); |
155a97a3 | 4966 | reset_rsvds_bits_mask_ept(vcpu, context, execonly); |
c258b62b | 4967 | reset_ept_shadow_zero_bits_mask(vcpu, context, execonly); |
155a97a3 NHE |
4968 | } |
4969 | EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu); | |
4970 | ||
8a3c1a33 | 4971 | static void init_kvm_softmmu(struct kvm_vcpu *vcpu) |
52fde8df | 4972 | { |
44dd3ffa | 4973 | struct kvm_mmu *context = vcpu->arch.mmu; |
ad896af0 PB |
4974 | |
4975 | kvm_init_shadow_mmu(vcpu); | |
4976 | context->set_cr3 = kvm_x86_ops->set_cr3; | |
4977 | context->get_cr3 = get_cr3; | |
4978 | context->get_pdptr = kvm_pdptr_read; | |
4979 | context->inject_page_fault = kvm_inject_page_fault; | |
6aa8b732 AK |
4980 | } |
4981 | ||
8a3c1a33 | 4982 | static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu) |
02f59dc9 | 4983 | { |
bf627a92 | 4984 | union kvm_mmu_role new_role = kvm_calc_mmu_role_common(vcpu, false); |
02f59dc9 JR |
4985 | struct kvm_mmu *g_context = &vcpu->arch.nested_mmu; |
4986 | ||
bf627a92 VK |
4987 | new_role.base.word &= mmu_base_role_mask.word; |
4988 | if (new_role.as_u64 == g_context->mmu_role.as_u64) | |
4989 | return; | |
4990 | ||
4991 | g_context->mmu_role.as_u64 = new_role.as_u64; | |
02f59dc9 | 4992 | g_context->get_cr3 = get_cr3; |
e4e517b4 | 4993 | g_context->get_pdptr = kvm_pdptr_read; |
02f59dc9 JR |
4994 | g_context->inject_page_fault = kvm_inject_page_fault; |
4995 | ||
4996 | /* | |
44dd3ffa | 4997 | * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using |
0af2593b DM |
4998 | * L1's nested page tables (e.g. EPT12). The nested translation |
4999 | * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using | |
5000 | * L2's page tables as the first level of translation and L1's | |
5001 | * nested page tables as the second level of translation. Basically | |
5002 | * the gva_to_gpa functions between mmu and nested_mmu are swapped. | |
02f59dc9 JR |
5003 | */ |
5004 | if (!is_paging(vcpu)) { | |
2d48a985 | 5005 | g_context->nx = false; |
02f59dc9 JR |
5006 | g_context->root_level = 0; |
5007 | g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested; | |
5008 | } else if (is_long_mode(vcpu)) { | |
2d48a985 | 5009 | g_context->nx = is_nx(vcpu); |
855feb67 YZ |
5010 | g_context->root_level = is_la57_mode(vcpu) ? |
5011 | PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL; | |
4d6931c3 | 5012 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
5013 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
5014 | } else if (is_pae(vcpu)) { | |
2d48a985 | 5015 | g_context->nx = is_nx(vcpu); |
02f59dc9 | 5016 | g_context->root_level = PT32E_ROOT_LEVEL; |
4d6931c3 | 5017 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
5018 | g_context->gva_to_gpa = paging64_gva_to_gpa_nested; |
5019 | } else { | |
2d48a985 | 5020 | g_context->nx = false; |
02f59dc9 | 5021 | g_context->root_level = PT32_ROOT_LEVEL; |
4d6931c3 | 5022 | reset_rsvds_bits_mask(vcpu, g_context); |
02f59dc9 JR |
5023 | g_context->gva_to_gpa = paging32_gva_to_gpa_nested; |
5024 | } | |
5025 | ||
25d92081 | 5026 | update_permission_bitmask(vcpu, g_context, false); |
2d344105 | 5027 | update_pkru_bitmask(vcpu, g_context, false); |
6bb69c9b | 5028 | update_last_nonleaf_level(vcpu, g_context); |
02f59dc9 JR |
5029 | } |
5030 | ||
1c53da3f | 5031 | void kvm_init_mmu(struct kvm_vcpu *vcpu, bool reset_roots) |
fb72d167 | 5032 | { |
1c53da3f | 5033 | if (reset_roots) { |
b94742c9 JS |
5034 | uint i; |
5035 | ||
44dd3ffa | 5036 | vcpu->arch.mmu->root_hpa = INVALID_PAGE; |
b94742c9 JS |
5037 | |
5038 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
44dd3ffa | 5039 | vcpu->arch.mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; |
1c53da3f JS |
5040 | } |
5041 | ||
02f59dc9 | 5042 | if (mmu_is_nested(vcpu)) |
e0c6db3e | 5043 | init_kvm_nested_mmu(vcpu); |
02f59dc9 | 5044 | else if (tdp_enabled) |
e0c6db3e | 5045 | init_kvm_tdp_mmu(vcpu); |
fb72d167 | 5046 | else |
e0c6db3e | 5047 | init_kvm_softmmu(vcpu); |
fb72d167 | 5048 | } |
1c53da3f | 5049 | EXPORT_SYMBOL_GPL(kvm_init_mmu); |
fb72d167 | 5050 | |
9fa72119 JS |
5051 | static union kvm_mmu_page_role |
5052 | kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu) | |
5053 | { | |
7dcd5755 VK |
5054 | union kvm_mmu_role role; |
5055 | ||
9fa72119 | 5056 | if (tdp_enabled) |
7dcd5755 | 5057 | role = kvm_calc_tdp_mmu_root_page_role(vcpu, true); |
9fa72119 | 5058 | else |
7dcd5755 VK |
5059 | role = kvm_calc_shadow_mmu_root_page_role(vcpu, true); |
5060 | ||
5061 | return role.base; | |
9fa72119 | 5062 | } |
fb72d167 | 5063 | |
8a3c1a33 | 5064 | void kvm_mmu_reset_context(struct kvm_vcpu *vcpu) |
6aa8b732 | 5065 | { |
95f93af4 | 5066 | kvm_mmu_unload(vcpu); |
1c53da3f | 5067 | kvm_init_mmu(vcpu, true); |
17c3ba9d | 5068 | } |
8668a3c4 | 5069 | EXPORT_SYMBOL_GPL(kvm_mmu_reset_context); |
17c3ba9d AK |
5070 | |
5071 | int kvm_mmu_load(struct kvm_vcpu *vcpu) | |
6aa8b732 | 5072 | { |
714b93da AK |
5073 | int r; |
5074 | ||
e2dec939 | 5075 | r = mmu_topup_memory_caches(vcpu); |
17c3ba9d AK |
5076 | if (r) |
5077 | goto out; | |
8986ecc0 | 5078 | r = mmu_alloc_roots(vcpu); |
e2858b4a | 5079 | kvm_mmu_sync_roots(vcpu); |
8986ecc0 MT |
5080 | if (r) |
5081 | goto out; | |
6e42782f | 5082 | kvm_mmu_load_cr3(vcpu); |
afe828d1 | 5083 | kvm_x86_ops->tlb_flush(vcpu, true); |
714b93da AK |
5084 | out: |
5085 | return r; | |
6aa8b732 | 5086 | } |
17c3ba9d AK |
5087 | EXPORT_SYMBOL_GPL(kvm_mmu_load); |
5088 | ||
5089 | void kvm_mmu_unload(struct kvm_vcpu *vcpu) | |
5090 | { | |
14c07ad8 VK |
5091 | kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL); |
5092 | WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa)); | |
5093 | kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL); | |
5094 | WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa)); | |
17c3ba9d | 5095 | } |
4b16184c | 5096 | EXPORT_SYMBOL_GPL(kvm_mmu_unload); |
6aa8b732 | 5097 | |
0028425f | 5098 | static void mmu_pte_write_new_pte(struct kvm_vcpu *vcpu, |
7c562522 XG |
5099 | struct kvm_mmu_page *sp, u64 *spte, |
5100 | const void *new) | |
0028425f | 5101 | { |
30945387 | 5102 | if (sp->role.level != PT_PAGE_TABLE_LEVEL) { |
7e4e4056 JR |
5103 | ++vcpu->kvm->stat.mmu_pde_zapped; |
5104 | return; | |
30945387 | 5105 | } |
0028425f | 5106 | |
4cee5764 | 5107 | ++vcpu->kvm->stat.mmu_pte_updated; |
44dd3ffa | 5108 | vcpu->arch.mmu->update_pte(vcpu, sp, spte, new); |
0028425f AK |
5109 | } |
5110 | ||
79539cec AK |
5111 | static bool need_remote_flush(u64 old, u64 new) |
5112 | { | |
5113 | if (!is_shadow_present_pte(old)) | |
5114 | return false; | |
5115 | if (!is_shadow_present_pte(new)) | |
5116 | return true; | |
5117 | if ((old ^ new) & PT64_BASE_ADDR_MASK) | |
5118 | return true; | |
53166229 GN |
5119 | old ^= shadow_nx_mask; |
5120 | new ^= shadow_nx_mask; | |
79539cec AK |
5121 | return (old & ~new & PT64_PERM_MASK) != 0; |
5122 | } | |
5123 | ||
889e5cbc | 5124 | static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa, |
0e0fee5c | 5125 | int *bytes) |
da4a00f0 | 5126 | { |
0e0fee5c | 5127 | u64 gentry = 0; |
889e5cbc | 5128 | int r; |
72016f3a | 5129 | |
72016f3a AK |
5130 | /* |
5131 | * Assume that the pte write on a page table of the same type | |
49b26e26 XG |
5132 | * as the current vcpu paging mode since we update the sptes only |
5133 | * when they have the same mode. | |
72016f3a | 5134 | */ |
889e5cbc | 5135 | if (is_pae(vcpu) && *bytes == 4) { |
72016f3a | 5136 | /* Handle a 32-bit guest writing two halves of a 64-bit gpte */ |
889e5cbc XG |
5137 | *gpa &= ~(gpa_t)7; |
5138 | *bytes = 8; | |
08e850c6 AK |
5139 | } |
5140 | ||
0e0fee5c JS |
5141 | if (*bytes == 4 || *bytes == 8) { |
5142 | r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes); | |
5143 | if (r) | |
5144 | gentry = 0; | |
72016f3a AK |
5145 | } |
5146 | ||
889e5cbc XG |
5147 | return gentry; |
5148 | } | |
5149 | ||
5150 | /* | |
5151 | * If we're seeing too many writes to a page, it may no longer be a page table, | |
5152 | * or we may be forking, in which case it is better to unmap the page. | |
5153 | */ | |
a138fe75 | 5154 | static bool detect_write_flooding(struct kvm_mmu_page *sp) |
889e5cbc | 5155 | { |
a30f47cb XG |
5156 | /* |
5157 | * Skip write-flooding detected for the sp whose level is 1, because | |
5158 | * it can become unsync, then the guest page is not write-protected. | |
5159 | */ | |
f71fa31f | 5160 | if (sp->role.level == PT_PAGE_TABLE_LEVEL) |
a30f47cb | 5161 | return false; |
3246af0e | 5162 | |
e5691a81 XG |
5163 | atomic_inc(&sp->write_flooding_count); |
5164 | return atomic_read(&sp->write_flooding_count) >= 3; | |
889e5cbc XG |
5165 | } |
5166 | ||
5167 | /* | |
5168 | * Misaligned accesses are too much trouble to fix up; also, they usually | |
5169 | * indicate a page is not used as a page table. | |
5170 | */ | |
5171 | static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa, | |
5172 | int bytes) | |
5173 | { | |
5174 | unsigned offset, pte_size, misaligned; | |
5175 | ||
5176 | pgprintk("misaligned: gpa %llx bytes %d role %x\n", | |
5177 | gpa, bytes, sp->role.word); | |
5178 | ||
5179 | offset = offset_in_page(gpa); | |
5180 | pte_size = sp->role.cr4_pae ? 8 : 4; | |
5d9ca30e XG |
5181 | |
5182 | /* | |
5183 | * Sometimes, the OS only writes the last one bytes to update status | |
5184 | * bits, for example, in linux, andb instruction is used in clear_bit(). | |
5185 | */ | |
5186 | if (!(offset & (pte_size - 1)) && bytes == 1) | |
5187 | return false; | |
5188 | ||
889e5cbc XG |
5189 | misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1); |
5190 | misaligned |= bytes < 4; | |
5191 | ||
5192 | return misaligned; | |
5193 | } | |
5194 | ||
5195 | static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte) | |
5196 | { | |
5197 | unsigned page_offset, quadrant; | |
5198 | u64 *spte; | |
5199 | int level; | |
5200 | ||
5201 | page_offset = offset_in_page(gpa); | |
5202 | level = sp->role.level; | |
5203 | *nspte = 1; | |
5204 | if (!sp->role.cr4_pae) { | |
5205 | page_offset <<= 1; /* 32->64 */ | |
5206 | /* | |
5207 | * A 32-bit pde maps 4MB while the shadow pdes map | |
5208 | * only 2MB. So we need to double the offset again | |
5209 | * and zap two pdes instead of one. | |
5210 | */ | |
5211 | if (level == PT32_ROOT_LEVEL) { | |
5212 | page_offset &= ~7; /* kill rounding error */ | |
5213 | page_offset <<= 1; | |
5214 | *nspte = 2; | |
5215 | } | |
5216 | quadrant = page_offset >> PAGE_SHIFT; | |
5217 | page_offset &= ~PAGE_MASK; | |
5218 | if (quadrant != sp->role.quadrant) | |
5219 | return NULL; | |
5220 | } | |
5221 | ||
5222 | spte = &sp->spt[page_offset / sizeof(*spte)]; | |
5223 | return spte; | |
5224 | } | |
5225 | ||
13d268ca | 5226 | static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa, |
d126363d JS |
5227 | const u8 *new, int bytes, |
5228 | struct kvm_page_track_notifier_node *node) | |
889e5cbc XG |
5229 | { |
5230 | gfn_t gfn = gpa >> PAGE_SHIFT; | |
889e5cbc | 5231 | struct kvm_mmu_page *sp; |
889e5cbc XG |
5232 | LIST_HEAD(invalid_list); |
5233 | u64 entry, gentry, *spte; | |
5234 | int npte; | |
b8c67b7a | 5235 | bool remote_flush, local_flush; |
889e5cbc XG |
5236 | |
5237 | /* | |
5238 | * If we don't have indirect shadow pages, it means no page is | |
5239 | * write-protected, so we can exit simply. | |
5240 | */ | |
6aa7de05 | 5241 | if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages)) |
889e5cbc XG |
5242 | return; |
5243 | ||
b8c67b7a | 5244 | remote_flush = local_flush = false; |
889e5cbc XG |
5245 | |
5246 | pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes); | |
5247 | ||
889e5cbc XG |
5248 | /* |
5249 | * No need to care whether allocation memory is successful | |
5250 | * or not since pte prefetch is skiped if it does not have | |
5251 | * enough objects in the cache. | |
5252 | */ | |
5253 | mmu_topup_memory_caches(vcpu); | |
5254 | ||
5255 | spin_lock(&vcpu->kvm->mmu_lock); | |
0e0fee5c JS |
5256 | |
5257 | gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes); | |
5258 | ||
889e5cbc | 5259 | ++vcpu->kvm->stat.mmu_pte_write; |
0375f7fa | 5260 | kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE); |
889e5cbc | 5261 | |
b67bfe0d | 5262 | for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) { |
a30f47cb | 5263 | if (detect_write_misaligned(sp, gpa, bytes) || |
a138fe75 | 5264 | detect_write_flooding(sp)) { |
b8c67b7a | 5265 | kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list); |
4cee5764 | 5266 | ++vcpu->kvm->stat.mmu_flooded; |
0e7bc4b9 AK |
5267 | continue; |
5268 | } | |
889e5cbc XG |
5269 | |
5270 | spte = get_written_sptes(sp, gpa, &npte); | |
5271 | if (!spte) | |
5272 | continue; | |
5273 | ||
0671a8e7 | 5274 | local_flush = true; |
ac1b714e | 5275 | while (npte--) { |
36d9594d VK |
5276 | u32 base_role = vcpu->arch.mmu->mmu_role.base.word; |
5277 | ||
79539cec | 5278 | entry = *spte; |
38e3b2b2 | 5279 | mmu_page_zap_pte(vcpu->kvm, sp, spte); |
fa1de2bf | 5280 | if (gentry && |
36d9594d | 5281 | !((sp->role.word ^ base_role) |
9fa72119 | 5282 | & mmu_base_role_mask.word) && rmap_can_add(vcpu)) |
7c562522 | 5283 | mmu_pte_write_new_pte(vcpu, sp, spte, &gentry); |
9bb4f6b1 | 5284 | if (need_remote_flush(entry, *spte)) |
0671a8e7 | 5285 | remote_flush = true; |
ac1b714e | 5286 | ++spte; |
9b7a0325 | 5287 | } |
9b7a0325 | 5288 | } |
b8c67b7a | 5289 | kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush); |
0375f7fa | 5290 | kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE); |
aaee2c94 | 5291 | spin_unlock(&vcpu->kvm->mmu_lock); |
da4a00f0 AK |
5292 | } |
5293 | ||
a436036b AK |
5294 | int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva) |
5295 | { | |
10589a46 MT |
5296 | gpa_t gpa; |
5297 | int r; | |
a436036b | 5298 | |
44dd3ffa | 5299 | if (vcpu->arch.mmu->direct_map) |
60f24784 AK |
5300 | return 0; |
5301 | ||
1871c602 | 5302 | gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL); |
10589a46 | 5303 | |
10589a46 | 5304 | r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT); |
1cb3f3ae | 5305 | |
10589a46 | 5306 | return r; |
a436036b | 5307 | } |
577bdc49 | 5308 | EXPORT_SYMBOL_GPL(kvm_mmu_unprotect_page_virt); |
a436036b | 5309 | |
26eeb53c | 5310 | static int make_mmu_pages_available(struct kvm_vcpu *vcpu) |
ebeace86 | 5311 | { |
d98ba053 | 5312 | LIST_HEAD(invalid_list); |
103ad25a | 5313 | |
81f4f76b | 5314 | if (likely(kvm_mmu_available_pages(vcpu->kvm) >= KVM_MIN_FREE_MMU_PAGES)) |
26eeb53c | 5315 | return 0; |
81f4f76b | 5316 | |
5da59607 TY |
5317 | while (kvm_mmu_available_pages(vcpu->kvm) < KVM_REFILL_PAGES) { |
5318 | if (!prepare_zap_oldest_mmu_page(vcpu->kvm, &invalid_list)) | |
5319 | break; | |
ebeace86 | 5320 | |
4cee5764 | 5321 | ++vcpu->kvm->stat.mmu_recycled; |
ebeace86 | 5322 | } |
aa6bd187 | 5323 | kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list); |
26eeb53c WL |
5324 | |
5325 | if (!kvm_mmu_available_pages(vcpu->kvm)) | |
5326 | return -ENOSPC; | |
5327 | return 0; | |
ebeace86 | 5328 | } |
ebeace86 | 5329 | |
14727754 | 5330 | int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t cr2, u64 error_code, |
dc25e89e | 5331 | void *insn, int insn_len) |
3067714c | 5332 | { |
472faffa | 5333 | int r, emulation_type = 0; |
3067714c | 5334 | enum emulation_result er; |
44dd3ffa | 5335 | bool direct = vcpu->arch.mmu->direct_map; |
3067714c | 5336 | |
618232e2 | 5337 | /* With shadow page tables, fault_address contains a GVA or nGPA. */ |
44dd3ffa | 5338 | if (vcpu->arch.mmu->direct_map) { |
618232e2 BS |
5339 | vcpu->arch.gpa_available = true; |
5340 | vcpu->arch.gpa_val = cr2; | |
5341 | } | |
3067714c | 5342 | |
9b8ebbdb | 5343 | r = RET_PF_INVALID; |
e9ee956e TY |
5344 | if (unlikely(error_code & PFERR_RSVD_MASK)) { |
5345 | r = handle_mmio_page_fault(vcpu, cr2, direct); | |
472faffa | 5346 | if (r == RET_PF_EMULATE) |
e9ee956e | 5347 | goto emulate; |
e9ee956e | 5348 | } |
3067714c | 5349 | |
9b8ebbdb | 5350 | if (r == RET_PF_INVALID) { |
44dd3ffa VK |
5351 | r = vcpu->arch.mmu->page_fault(vcpu, cr2, |
5352 | lower_32_bits(error_code), | |
5353 | false); | |
9b8ebbdb PB |
5354 | WARN_ON(r == RET_PF_INVALID); |
5355 | } | |
5356 | ||
5357 | if (r == RET_PF_RETRY) | |
5358 | return 1; | |
3067714c | 5359 | if (r < 0) |
e9ee956e | 5360 | return r; |
3067714c | 5361 | |
14727754 TL |
5362 | /* |
5363 | * Before emulating the instruction, check if the error code | |
5364 | * was due to a RO violation while translating the guest page. | |
5365 | * This can occur when using nested virtualization with nested | |
5366 | * paging in both guests. If true, we simply unprotect the page | |
5367 | * and resume the guest. | |
14727754 | 5368 | */ |
44dd3ffa | 5369 | if (vcpu->arch.mmu->direct_map && |
eebed243 | 5370 | (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) { |
14727754 TL |
5371 | kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2)); |
5372 | return 1; | |
5373 | } | |
5374 | ||
472faffa SC |
5375 | /* |
5376 | * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still | |
5377 | * optimistically try to just unprotect the page and let the processor | |
5378 | * re-execute the instruction that caused the page fault. Do not allow | |
5379 | * retrying MMIO emulation, as it's not only pointless but could also | |
5380 | * cause us to enter an infinite loop because the processor will keep | |
6c3dfeb6 SC |
5381 | * faulting on the non-existent MMIO address. Retrying an instruction |
5382 | * from a nested guest is also pointless and dangerous as we are only | |
5383 | * explicitly shadowing L1's page tables, i.e. unprotecting something | |
5384 | * for L1 isn't going to magically fix whatever issue cause L2 to fail. | |
472faffa | 5385 | */ |
6c3dfeb6 | 5386 | if (!mmio_info_in_cache(vcpu, cr2, direct) && !is_guest_mode(vcpu)) |
472faffa | 5387 | emulation_type = EMULTYPE_ALLOW_RETRY; |
e9ee956e | 5388 | emulate: |
00b10fe1 BS |
5389 | /* |
5390 | * On AMD platforms, under certain conditions insn_len may be zero on #NPF. | |
5391 | * This can happen if a guest gets a page-fault on data access but the HW | |
5392 | * table walker is not able to read the instruction page (e.g instruction | |
5393 | * page is not present in memory). In those cases we simply restart the | |
5394 | * guest. | |
5395 | */ | |
5396 | if (unlikely(insn && !insn_len)) | |
5397 | return 1; | |
5398 | ||
1cb3f3ae | 5399 | er = x86_emulate_instruction(vcpu, cr2, emulation_type, insn, insn_len); |
3067714c AK |
5400 | |
5401 | switch (er) { | |
5402 | case EMULATE_DONE: | |
5403 | return 1; | |
ac0a48c3 | 5404 | case EMULATE_USER_EXIT: |
3067714c | 5405 | ++vcpu->stat.mmio_exits; |
6d77dbfc | 5406 | /* fall through */ |
3067714c | 5407 | case EMULATE_FAIL: |
3f5d18a9 | 5408 | return 0; |
3067714c AK |
5409 | default: |
5410 | BUG(); | |
5411 | } | |
3067714c AK |
5412 | } |
5413 | EXPORT_SYMBOL_GPL(kvm_mmu_page_fault); | |
5414 | ||
a7052897 MT |
5415 | void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva) |
5416 | { | |
44dd3ffa | 5417 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
b94742c9 | 5418 | int i; |
7eb77e9f | 5419 | |
faff8758 JS |
5420 | /* INVLPG on a * non-canonical address is a NOP according to the SDM. */ |
5421 | if (is_noncanonical_address(gva, vcpu)) | |
5422 | return; | |
5423 | ||
7eb77e9f | 5424 | mmu->invlpg(vcpu, gva, mmu->root_hpa); |
956bf353 JS |
5425 | |
5426 | /* | |
5427 | * INVLPG is required to invalidate any global mappings for the VA, | |
5428 | * irrespective of PCID. Since it would take us roughly similar amount | |
b94742c9 JS |
5429 | * of work to determine whether any of the prev_root mappings of the VA |
5430 | * is marked global, or to just sync it blindly, so we might as well | |
5431 | * just always sync it. | |
956bf353 | 5432 | * |
b94742c9 JS |
5433 | * Mappings not reachable via the current cr3 or the prev_roots will be |
5434 | * synced when switching to that cr3, so nothing needs to be done here | |
5435 | * for them. | |
956bf353 | 5436 | */ |
b94742c9 JS |
5437 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
5438 | if (VALID_PAGE(mmu->prev_roots[i].hpa)) | |
5439 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); | |
956bf353 | 5440 | |
faff8758 | 5441 | kvm_x86_ops->tlb_flush_gva(vcpu, gva); |
a7052897 MT |
5442 | ++vcpu->stat.invlpg; |
5443 | } | |
5444 | EXPORT_SYMBOL_GPL(kvm_mmu_invlpg); | |
5445 | ||
eb4b248e JS |
5446 | void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid) |
5447 | { | |
44dd3ffa | 5448 | struct kvm_mmu *mmu = vcpu->arch.mmu; |
faff8758 | 5449 | bool tlb_flush = false; |
b94742c9 | 5450 | uint i; |
eb4b248e JS |
5451 | |
5452 | if (pcid == kvm_get_active_pcid(vcpu)) { | |
7eb77e9f | 5453 | mmu->invlpg(vcpu, gva, mmu->root_hpa); |
faff8758 | 5454 | tlb_flush = true; |
eb4b248e JS |
5455 | } |
5456 | ||
b94742c9 JS |
5457 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) { |
5458 | if (VALID_PAGE(mmu->prev_roots[i].hpa) && | |
5459 | pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].cr3)) { | |
5460 | mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa); | |
5461 | tlb_flush = true; | |
5462 | } | |
956bf353 | 5463 | } |
ade61e28 | 5464 | |
faff8758 JS |
5465 | if (tlb_flush) |
5466 | kvm_x86_ops->tlb_flush_gva(vcpu, gva); | |
5467 | ||
eb4b248e JS |
5468 | ++vcpu->stat.invlpg; |
5469 | ||
5470 | /* | |
b94742c9 JS |
5471 | * Mappings not reachable via the current cr3 or the prev_roots will be |
5472 | * synced when switching to that cr3, so nothing needs to be done here | |
5473 | * for them. | |
eb4b248e JS |
5474 | */ |
5475 | } | |
5476 | EXPORT_SYMBOL_GPL(kvm_mmu_invpcid_gva); | |
5477 | ||
18552672 JR |
5478 | void kvm_enable_tdp(void) |
5479 | { | |
5480 | tdp_enabled = true; | |
5481 | } | |
5482 | EXPORT_SYMBOL_GPL(kvm_enable_tdp); | |
5483 | ||
5f4cb662 JR |
5484 | void kvm_disable_tdp(void) |
5485 | { | |
5486 | tdp_enabled = false; | |
5487 | } | |
5488 | EXPORT_SYMBOL_GPL(kvm_disable_tdp); | |
5489 | ||
6aa8b732 AK |
5490 | static void free_mmu_pages(struct kvm_vcpu *vcpu) |
5491 | { | |
44dd3ffa VK |
5492 | free_page((unsigned long)vcpu->arch.mmu->pae_root); |
5493 | free_page((unsigned long)vcpu->arch.mmu->lm_root); | |
6aa8b732 AK |
5494 | } |
5495 | ||
5496 | static int alloc_mmu_pages(struct kvm_vcpu *vcpu) | |
5497 | { | |
17ac10ad | 5498 | struct page *page; |
6aa8b732 AK |
5499 | int i; |
5500 | ||
ee6268ba LC |
5501 | if (tdp_enabled) |
5502 | return 0; | |
5503 | ||
17ac10ad AK |
5504 | /* |
5505 | * When emulating 32-bit mode, cr3 is only 32 bits even on x86_64. | |
5506 | * Therefore we need to allocate shadow page tables in the first | |
5507 | * 4GB of memory, which happens to fit the DMA32 zone. | |
5508 | */ | |
254272ce | 5509 | page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32); |
17ac10ad | 5510 | if (!page) |
d7fa6ab2 WY |
5511 | return -ENOMEM; |
5512 | ||
44dd3ffa | 5513 | vcpu->arch.mmu->pae_root = page_address(page); |
17ac10ad | 5514 | for (i = 0; i < 4; ++i) |
44dd3ffa | 5515 | vcpu->arch.mmu->pae_root[i] = INVALID_PAGE; |
17ac10ad | 5516 | |
6aa8b732 | 5517 | return 0; |
6aa8b732 AK |
5518 | } |
5519 | ||
8018c27b | 5520 | int kvm_mmu_create(struct kvm_vcpu *vcpu) |
6aa8b732 | 5521 | { |
b94742c9 JS |
5522 | uint i; |
5523 | ||
44dd3ffa VK |
5524 | vcpu->arch.mmu = &vcpu->arch.root_mmu; |
5525 | vcpu->arch.walk_mmu = &vcpu->arch.root_mmu; | |
6aa8b732 | 5526 | |
44dd3ffa VK |
5527 | vcpu->arch.root_mmu.root_hpa = INVALID_PAGE; |
5528 | vcpu->arch.root_mmu.translate_gpa = translate_gpa; | |
b94742c9 | 5529 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) |
44dd3ffa | 5530 | vcpu->arch.root_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; |
6aa8b732 | 5531 | |
14c07ad8 VK |
5532 | vcpu->arch.guest_mmu.root_hpa = INVALID_PAGE; |
5533 | vcpu->arch.guest_mmu.translate_gpa = translate_gpa; | |
5534 | for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) | |
5535 | vcpu->arch.guest_mmu.prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID; | |
2c264957 | 5536 | |
14c07ad8 | 5537 | vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa; |
8018c27b | 5538 | return alloc_mmu_pages(vcpu); |
6aa8b732 AK |
5539 | } |
5540 | ||
b5f5fdca | 5541 | static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm, |
d126363d JS |
5542 | struct kvm_memory_slot *slot, |
5543 | struct kvm_page_track_notifier_node *node) | |
b5f5fdca XC |
5544 | { |
5545 | kvm_mmu_invalidate_zap_all_pages(kvm); | |
5546 | } | |
5547 | ||
13d268ca XG |
5548 | void kvm_mmu_init_vm(struct kvm *kvm) |
5549 | { | |
5550 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
5551 | ||
5552 | node->track_write = kvm_mmu_pte_write; | |
b5f5fdca | 5553 | node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot; |
13d268ca XG |
5554 | kvm_page_track_register_notifier(kvm, node); |
5555 | } | |
5556 | ||
5557 | void kvm_mmu_uninit_vm(struct kvm *kvm) | |
5558 | { | |
5559 | struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker; | |
5560 | ||
5561 | kvm_page_track_unregister_notifier(kvm, node); | |
5562 | } | |
5563 | ||
1bad2b2a | 5564 | /* The return value indicates if tlb flush on all vcpus is needed. */ |
018aabb5 | 5565 | typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head); |
1bad2b2a XG |
5566 | |
5567 | /* The caller should hold mmu-lock before calling this function. */ | |
928a4c39 | 5568 | static __always_inline bool |
1bad2b2a XG |
5569 | slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot, |
5570 | slot_level_handler fn, int start_level, int end_level, | |
5571 | gfn_t start_gfn, gfn_t end_gfn, bool lock_flush_tlb) | |
5572 | { | |
5573 | struct slot_rmap_walk_iterator iterator; | |
5574 | bool flush = false; | |
5575 | ||
5576 | for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn, | |
5577 | end_gfn, &iterator) { | |
5578 | if (iterator.rmap) | |
5579 | flush |= fn(kvm, iterator.rmap); | |
5580 | ||
5581 | if (need_resched() || spin_needbreak(&kvm->mmu_lock)) { | |
5582 | if (flush && lock_flush_tlb) { | |
5583 | kvm_flush_remote_tlbs(kvm); | |
5584 | flush = false; | |
5585 | } | |
5586 | cond_resched_lock(&kvm->mmu_lock); | |
5587 | } | |
5588 | } | |
5589 | ||
5590 | if (flush && lock_flush_tlb) { | |
5591 | kvm_flush_remote_tlbs(kvm); | |
5592 | flush = false; | |
5593 | } | |
5594 | ||
5595 | return flush; | |
5596 | } | |
5597 | ||
928a4c39 | 5598 | static __always_inline bool |
1bad2b2a XG |
5599 | slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot, |
5600 | slot_level_handler fn, int start_level, int end_level, | |
5601 | bool lock_flush_tlb) | |
5602 | { | |
5603 | return slot_handle_level_range(kvm, memslot, fn, start_level, | |
5604 | end_level, memslot->base_gfn, | |
5605 | memslot->base_gfn + memslot->npages - 1, | |
5606 | lock_flush_tlb); | |
5607 | } | |
5608 | ||
928a4c39 | 5609 | static __always_inline bool |
1bad2b2a XG |
5610 | slot_handle_all_level(struct kvm *kvm, struct kvm_memory_slot *memslot, |
5611 | slot_level_handler fn, bool lock_flush_tlb) | |
5612 | { | |
5613 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
5614 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
5615 | } | |
5616 | ||
928a4c39 | 5617 | static __always_inline bool |
1bad2b2a XG |
5618 | slot_handle_large_level(struct kvm *kvm, struct kvm_memory_slot *memslot, |
5619 | slot_level_handler fn, bool lock_flush_tlb) | |
5620 | { | |
5621 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL + 1, | |
5622 | PT_MAX_HUGEPAGE_LEVEL, lock_flush_tlb); | |
5623 | } | |
5624 | ||
928a4c39 | 5625 | static __always_inline bool |
1bad2b2a XG |
5626 | slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot, |
5627 | slot_level_handler fn, bool lock_flush_tlb) | |
5628 | { | |
5629 | return slot_handle_level(kvm, memslot, fn, PT_PAGE_TABLE_LEVEL, | |
5630 | PT_PAGE_TABLE_LEVEL, lock_flush_tlb); | |
5631 | } | |
5632 | ||
efdfe536 XG |
5633 | void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end) |
5634 | { | |
5635 | struct kvm_memslots *slots; | |
5636 | struct kvm_memory_slot *memslot; | |
71883a62 LT |
5637 | bool flush_tlb = true; |
5638 | bool flush = false; | |
9da0e4d5 | 5639 | int i; |
efdfe536 | 5640 | |
71883a62 LT |
5641 | if (kvm_available_flush_tlb_with_range()) |
5642 | flush_tlb = false; | |
5643 | ||
efdfe536 | 5644 | spin_lock(&kvm->mmu_lock); |
9da0e4d5 PB |
5645 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
5646 | slots = __kvm_memslots(kvm, i); | |
5647 | kvm_for_each_memslot(memslot, slots) { | |
5648 | gfn_t start, end; | |
5649 | ||
5650 | start = max(gfn_start, memslot->base_gfn); | |
5651 | end = min(gfn_end, memslot->base_gfn + memslot->npages); | |
5652 | if (start >= end) | |
5653 | continue; | |
efdfe536 | 5654 | |
71883a62 LT |
5655 | flush |= slot_handle_level_range(kvm, memslot, |
5656 | kvm_zap_rmapp, PT_PAGE_TABLE_LEVEL, | |
5657 | PT_MAX_HUGEPAGE_LEVEL, start, | |
5658 | end - 1, flush_tlb); | |
9da0e4d5 | 5659 | } |
efdfe536 XG |
5660 | } |
5661 | ||
71883a62 LT |
5662 | if (flush) |
5663 | kvm_flush_remote_tlbs_with_address(kvm, gfn_start, | |
5664 | gfn_end - gfn_start + 1); | |
5665 | ||
efdfe536 XG |
5666 | spin_unlock(&kvm->mmu_lock); |
5667 | } | |
5668 | ||
018aabb5 TY |
5669 | static bool slot_rmap_write_protect(struct kvm *kvm, |
5670 | struct kvm_rmap_head *rmap_head) | |
d77aa73c | 5671 | { |
018aabb5 | 5672 | return __rmap_write_protect(kvm, rmap_head, false); |
d77aa73c XG |
5673 | } |
5674 | ||
1c91cad4 KH |
5675 | void kvm_mmu_slot_remove_write_access(struct kvm *kvm, |
5676 | struct kvm_memory_slot *memslot) | |
6aa8b732 | 5677 | { |
d77aa73c | 5678 | bool flush; |
6aa8b732 | 5679 | |
9d1beefb | 5680 | spin_lock(&kvm->mmu_lock); |
d77aa73c XG |
5681 | flush = slot_handle_all_level(kvm, memslot, slot_rmap_write_protect, |
5682 | false); | |
9d1beefb | 5683 | spin_unlock(&kvm->mmu_lock); |
198c74f4 XG |
5684 | |
5685 | /* | |
5686 | * kvm_mmu_slot_remove_write_access() and kvm_vm_ioctl_get_dirty_log() | |
5687 | * which do tlb flush out of mmu-lock should be serialized by | |
5688 | * kvm->slots_lock otherwise tlb flush would be missed. | |
5689 | */ | |
5690 | lockdep_assert_held(&kvm->slots_lock); | |
5691 | ||
5692 | /* | |
5693 | * We can flush all the TLBs out of the mmu lock without TLB | |
5694 | * corruption since we just change the spte from writable to | |
5695 | * readonly so that we only need to care the case of changing | |
5696 | * spte from present to present (changing the spte from present | |
5697 | * to nonpresent will flush all the TLBs immediately), in other | |
5698 | * words, the only case we care is mmu_spte_update() where we | |
bdd303cb | 5699 | * have checked SPTE_HOST_WRITEABLE | SPTE_MMU_WRITEABLE |
198c74f4 XG |
5700 | * instead of PT_WRITABLE_MASK, that means it does not depend |
5701 | * on PT_WRITABLE_MASK anymore. | |
5702 | */ | |
d91ffee9 | 5703 | if (flush) |
c3134ce2 LT |
5704 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5705 | memslot->npages); | |
6aa8b732 | 5706 | } |
37a7d8b0 | 5707 | |
3ea3b7fa | 5708 | static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm, |
018aabb5 | 5709 | struct kvm_rmap_head *rmap_head) |
3ea3b7fa WL |
5710 | { |
5711 | u64 *sptep; | |
5712 | struct rmap_iterator iter; | |
5713 | int need_tlb_flush = 0; | |
ba049e93 | 5714 | kvm_pfn_t pfn; |
3ea3b7fa WL |
5715 | struct kvm_mmu_page *sp; |
5716 | ||
0d536790 | 5717 | restart: |
018aabb5 | 5718 | for_each_rmap_spte(rmap_head, &iter, sptep) { |
3ea3b7fa WL |
5719 | sp = page_header(__pa(sptep)); |
5720 | pfn = spte_to_pfn(*sptep); | |
5721 | ||
5722 | /* | |
decf6333 XG |
5723 | * We cannot do huge page mapping for indirect shadow pages, |
5724 | * which are found on the last rmap (level = 1) when not using | |
5725 | * tdp; such shadow pages are synced with the page table in | |
5726 | * the guest, and the guest page table is using 4K page size | |
5727 | * mapping if the indirect sp has level = 1. | |
3ea3b7fa WL |
5728 | */ |
5729 | if (sp->role.direct && | |
5730 | !kvm_is_reserved_pfn(pfn) && | |
127393fb | 5731 | PageTransCompoundMap(pfn_to_page(pfn))) { |
e7912386 | 5732 | pte_list_remove(rmap_head, sptep); |
40ef75a7 LT |
5733 | |
5734 | if (kvm_available_flush_tlb_with_range()) | |
5735 | kvm_flush_remote_tlbs_with_address(kvm, sp->gfn, | |
5736 | KVM_PAGES_PER_HPAGE(sp->role.level)); | |
5737 | else | |
5738 | need_tlb_flush = 1; | |
5739 | ||
0d536790 XG |
5740 | goto restart; |
5741 | } | |
3ea3b7fa WL |
5742 | } |
5743 | ||
5744 | return need_tlb_flush; | |
5745 | } | |
5746 | ||
5747 | void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm, | |
f36f3f28 | 5748 | const struct kvm_memory_slot *memslot) |
3ea3b7fa | 5749 | { |
f36f3f28 | 5750 | /* FIXME: const-ify all uses of struct kvm_memory_slot. */ |
3ea3b7fa | 5751 | spin_lock(&kvm->mmu_lock); |
f36f3f28 PB |
5752 | slot_handle_leaf(kvm, (struct kvm_memory_slot *)memslot, |
5753 | kvm_mmu_zap_collapsible_spte, true); | |
3ea3b7fa WL |
5754 | spin_unlock(&kvm->mmu_lock); |
5755 | } | |
5756 | ||
f4b4b180 KH |
5757 | void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm, |
5758 | struct kvm_memory_slot *memslot) | |
5759 | { | |
d77aa73c | 5760 | bool flush; |
f4b4b180 KH |
5761 | |
5762 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5763 | flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty, false); |
f4b4b180 KH |
5764 | spin_unlock(&kvm->mmu_lock); |
5765 | ||
5766 | lockdep_assert_held(&kvm->slots_lock); | |
5767 | ||
5768 | /* | |
5769 | * It's also safe to flush TLBs out of mmu lock here as currently this | |
5770 | * function is only used for dirty logging, in which case flushing TLB | |
5771 | * out of mmu lock also guarantees no dirty pages will be lost in | |
5772 | * dirty_bitmap. | |
5773 | */ | |
5774 | if (flush) | |
c3134ce2 LT |
5775 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5776 | memslot->npages); | |
f4b4b180 KH |
5777 | } |
5778 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_leaf_clear_dirty); | |
5779 | ||
5780 | void kvm_mmu_slot_largepage_remove_write_access(struct kvm *kvm, | |
5781 | struct kvm_memory_slot *memslot) | |
5782 | { | |
d77aa73c | 5783 | bool flush; |
f4b4b180 KH |
5784 | |
5785 | spin_lock(&kvm->mmu_lock); | |
d77aa73c XG |
5786 | flush = slot_handle_large_level(kvm, memslot, slot_rmap_write_protect, |
5787 | false); | |
f4b4b180 KH |
5788 | spin_unlock(&kvm->mmu_lock); |
5789 | ||
5790 | /* see kvm_mmu_slot_remove_write_access */ | |
5791 | lockdep_assert_held(&kvm->slots_lock); | |
5792 | ||
5793 | if (flush) | |
c3134ce2 LT |
5794 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5795 | memslot->npages); | |
f4b4b180 KH |
5796 | } |
5797 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_largepage_remove_write_access); | |
5798 | ||
5799 | void kvm_mmu_slot_set_dirty(struct kvm *kvm, | |
5800 | struct kvm_memory_slot *memslot) | |
5801 | { | |
d77aa73c | 5802 | bool flush; |
f4b4b180 KH |
5803 | |
5804 | spin_lock(&kvm->mmu_lock); | |
d77aa73c | 5805 | flush = slot_handle_all_level(kvm, memslot, __rmap_set_dirty, false); |
f4b4b180 KH |
5806 | spin_unlock(&kvm->mmu_lock); |
5807 | ||
5808 | lockdep_assert_held(&kvm->slots_lock); | |
5809 | ||
5810 | /* see kvm_mmu_slot_leaf_clear_dirty */ | |
5811 | if (flush) | |
c3134ce2 LT |
5812 | kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn, |
5813 | memslot->npages); | |
f4b4b180 KH |
5814 | } |
5815 | EXPORT_SYMBOL_GPL(kvm_mmu_slot_set_dirty); | |
5816 | ||
e7d11c7a | 5817 | #define BATCH_ZAP_PAGES 10 |
5304b8d3 XG |
5818 | static void kvm_zap_obsolete_pages(struct kvm *kvm) |
5819 | { | |
5820 | struct kvm_mmu_page *sp, *node; | |
e7d11c7a | 5821 | int batch = 0; |
5304b8d3 XG |
5822 | |
5823 | restart: | |
5824 | list_for_each_entry_safe_reverse(sp, node, | |
5825 | &kvm->arch.active_mmu_pages, link) { | |
e7d11c7a XG |
5826 | int ret; |
5827 | ||
5304b8d3 XG |
5828 | /* |
5829 | * No obsolete page exists before new created page since | |
5830 | * active_mmu_pages is the FIFO list. | |
5831 | */ | |
5832 | if (!is_obsolete_sp(kvm, sp)) | |
5833 | break; | |
5834 | ||
5835 | /* | |
5304b8d3 XG |
5836 | * Since we are reversely walking the list and the invalid |
5837 | * list will be moved to the head, skip the invalid page | |
5838 | * can help us to avoid the infinity list walking. | |
5839 | */ | |
5840 | if (sp->role.invalid) | |
5841 | continue; | |
5842 | ||
f34d251d XG |
5843 | /* |
5844 | * Need not flush tlb since we only zap the sp with invalid | |
5845 | * generation number. | |
5846 | */ | |
e7d11c7a | 5847 | if (batch >= BATCH_ZAP_PAGES && |
f34d251d | 5848 | cond_resched_lock(&kvm->mmu_lock)) { |
e7d11c7a | 5849 | batch = 0; |
5304b8d3 XG |
5850 | goto restart; |
5851 | } | |
5852 | ||
365c8868 XG |
5853 | ret = kvm_mmu_prepare_zap_page(kvm, sp, |
5854 | &kvm->arch.zapped_obsolete_pages); | |
e7d11c7a XG |
5855 | batch += ret; |
5856 | ||
5857 | if (ret) | |
5304b8d3 XG |
5858 | goto restart; |
5859 | } | |
5860 | ||
f34d251d XG |
5861 | /* |
5862 | * Should flush tlb before free page tables since lockless-walking | |
5863 | * may use the pages. | |
5864 | */ | |
365c8868 | 5865 | kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages); |
5304b8d3 XG |
5866 | } |
5867 | ||
5868 | /* | |
5869 | * Fast invalidate all shadow pages and use lock-break technique | |
5870 | * to zap obsolete pages. | |
5871 | * | |
5872 | * It's required when memslot is being deleted or VM is being | |
5873 | * destroyed, in these cases, we should ensure that KVM MMU does | |
5874 | * not use any resource of the being-deleted slot or all slots | |
5875 | * after calling the function. | |
5876 | */ | |
5877 | void kvm_mmu_invalidate_zap_all_pages(struct kvm *kvm) | |
5878 | { | |
5879 | spin_lock(&kvm->mmu_lock); | |
35006126 | 5880 | trace_kvm_mmu_invalidate_zap_all_pages(kvm); |
5304b8d3 XG |
5881 | kvm->arch.mmu_valid_gen++; |
5882 | ||
f34d251d XG |
5883 | /* |
5884 | * Notify all vcpus to reload its shadow page table | |
5885 | * and flush TLB. Then all vcpus will switch to new | |
5886 | * shadow page table with the new mmu_valid_gen. | |
5887 | * | |
5888 | * Note: we should do this under the protection of | |
5889 | * mmu-lock, otherwise, vcpu would purge shadow page | |
5890 | * but miss tlb flush. | |
5891 | */ | |
5892 | kvm_reload_remote_mmus(kvm); | |
5893 | ||
5304b8d3 XG |
5894 | kvm_zap_obsolete_pages(kvm); |
5895 | spin_unlock(&kvm->mmu_lock); | |
5896 | } | |
5897 | ||
365c8868 XG |
5898 | static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm) |
5899 | { | |
5900 | return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages)); | |
5901 | } | |
5902 | ||
15248258 | 5903 | void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen) |
f8f55942 | 5904 | { |
164bf7e5 | 5905 | WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS); |
e1359e2b | 5906 | |
164bf7e5 | 5907 | gen &= MMIO_SPTE_GEN_MASK; |
e1359e2b SC |
5908 | |
5909 | /* | |
5910 | * Generation numbers are incremented in multiples of the number of | |
5911 | * address spaces in order to provide unique generations across all | |
5912 | * address spaces. Strip what is effectively the address space | |
5913 | * modifier prior to checking for a wrap of the MMIO generation so | |
5914 | * that a wrap in any address space is detected. | |
5915 | */ | |
5916 | gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1); | |
5917 | ||
f8f55942 | 5918 | /* |
e1359e2b | 5919 | * The very rare case: if the MMIO generation number has wrapped, |
f8f55942 | 5920 | * zap all shadow pages. |
f8f55942 | 5921 | */ |
e1359e2b | 5922 | if (unlikely(gen == 0)) { |
ae0f5499 | 5923 | kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n"); |
a8eca9dc | 5924 | kvm_mmu_invalidate_zap_all_pages(kvm); |
7a2e8aaf | 5925 | } |
f8f55942 XG |
5926 | } |
5927 | ||
70534a73 DC |
5928 | static unsigned long |
5929 | mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc) | |
3ee16c81 IE |
5930 | { |
5931 | struct kvm *kvm; | |
1495f230 | 5932 | int nr_to_scan = sc->nr_to_scan; |
70534a73 | 5933 | unsigned long freed = 0; |
3ee16c81 | 5934 | |
2f303b74 | 5935 | spin_lock(&kvm_lock); |
3ee16c81 IE |
5936 | |
5937 | list_for_each_entry(kvm, &vm_list, vm_list) { | |
3d56cbdf | 5938 | int idx; |
d98ba053 | 5939 | LIST_HEAD(invalid_list); |
3ee16c81 | 5940 | |
35f2d16b TY |
5941 | /* |
5942 | * Never scan more than sc->nr_to_scan VM instances. | |
5943 | * Will not hit this condition practically since we do not try | |
5944 | * to shrink more than one VM and it is very unlikely to see | |
5945 | * !n_used_mmu_pages so many times. | |
5946 | */ | |
5947 | if (!nr_to_scan--) | |
5948 | break; | |
19526396 GN |
5949 | /* |
5950 | * n_used_mmu_pages is accessed without holding kvm->mmu_lock | |
5951 | * here. We may skip a VM instance errorneosly, but we do not | |
5952 | * want to shrink a VM that only started to populate its MMU | |
5953 | * anyway. | |
5954 | */ | |
365c8868 XG |
5955 | if (!kvm->arch.n_used_mmu_pages && |
5956 | !kvm_has_zapped_obsolete_pages(kvm)) | |
19526396 | 5957 | continue; |
19526396 | 5958 | |
f656ce01 | 5959 | idx = srcu_read_lock(&kvm->srcu); |
3ee16c81 | 5960 | spin_lock(&kvm->mmu_lock); |
3ee16c81 | 5961 | |
365c8868 XG |
5962 | if (kvm_has_zapped_obsolete_pages(kvm)) { |
5963 | kvm_mmu_commit_zap_page(kvm, | |
5964 | &kvm->arch.zapped_obsolete_pages); | |
5965 | goto unlock; | |
5966 | } | |
5967 | ||
70534a73 DC |
5968 | if (prepare_zap_oldest_mmu_page(kvm, &invalid_list)) |
5969 | freed++; | |
d98ba053 | 5970 | kvm_mmu_commit_zap_page(kvm, &invalid_list); |
19526396 | 5971 | |
365c8868 | 5972 | unlock: |
3ee16c81 | 5973 | spin_unlock(&kvm->mmu_lock); |
f656ce01 | 5974 | srcu_read_unlock(&kvm->srcu, idx); |
19526396 | 5975 | |
70534a73 DC |
5976 | /* |
5977 | * unfair on small ones | |
5978 | * per-vm shrinkers cry out | |
5979 | * sadness comes quickly | |
5980 | */ | |
19526396 GN |
5981 | list_move_tail(&kvm->vm_list, &vm_list); |
5982 | break; | |
3ee16c81 | 5983 | } |
3ee16c81 | 5984 | |
2f303b74 | 5985 | spin_unlock(&kvm_lock); |
70534a73 | 5986 | return freed; |
70534a73 DC |
5987 | } |
5988 | ||
5989 | static unsigned long | |
5990 | mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc) | |
5991 | { | |
45221ab6 | 5992 | return percpu_counter_read_positive(&kvm_total_used_mmu_pages); |
3ee16c81 IE |
5993 | } |
5994 | ||
5995 | static struct shrinker mmu_shrinker = { | |
70534a73 DC |
5996 | .count_objects = mmu_shrink_count, |
5997 | .scan_objects = mmu_shrink_scan, | |
3ee16c81 IE |
5998 | .seeks = DEFAULT_SEEKS * 10, |
5999 | }; | |
6000 | ||
2ddfd20e | 6001 | static void mmu_destroy_caches(void) |
b5a33a75 | 6002 | { |
c1bd743e TH |
6003 | kmem_cache_destroy(pte_list_desc_cache); |
6004 | kmem_cache_destroy(mmu_page_header_cache); | |
b5a33a75 AK |
6005 | } |
6006 | ||
6007 | int kvm_mmu_module_init(void) | |
6008 | { | |
ab271bd4 AB |
6009 | int ret = -ENOMEM; |
6010 | ||
36d9594d VK |
6011 | /* |
6012 | * MMU roles use union aliasing which is, generally speaking, an | |
6013 | * undefined behavior. However, we supposedly know how compilers behave | |
6014 | * and the current status quo is unlikely to change. Guardians below are | |
6015 | * supposed to let us know if the assumption becomes false. | |
6016 | */ | |
6017 | BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32)); | |
6018 | BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32)); | |
6019 | BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64)); | |
6020 | ||
28a1f3ac | 6021 | kvm_mmu_reset_all_pte_masks(); |
f160c7b7 | 6022 | |
53c07b18 XG |
6023 | pte_list_desc_cache = kmem_cache_create("pte_list_desc", |
6024 | sizeof(struct pte_list_desc), | |
46bea48a | 6025 | 0, SLAB_ACCOUNT, NULL); |
53c07b18 | 6026 | if (!pte_list_desc_cache) |
ab271bd4 | 6027 | goto out; |
b5a33a75 | 6028 | |
d3d25b04 AK |
6029 | mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header", |
6030 | sizeof(struct kvm_mmu_page), | |
46bea48a | 6031 | 0, SLAB_ACCOUNT, NULL); |
d3d25b04 | 6032 | if (!mmu_page_header_cache) |
ab271bd4 | 6033 | goto out; |
d3d25b04 | 6034 | |
908c7f19 | 6035 | if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL)) |
ab271bd4 | 6036 | goto out; |
45bf21a8 | 6037 | |
ab271bd4 AB |
6038 | ret = register_shrinker(&mmu_shrinker); |
6039 | if (ret) | |
6040 | goto out; | |
3ee16c81 | 6041 | |
b5a33a75 AK |
6042 | return 0; |
6043 | ||
ab271bd4 | 6044 | out: |
3ee16c81 | 6045 | mmu_destroy_caches(); |
ab271bd4 | 6046 | return ret; |
b5a33a75 AK |
6047 | } |
6048 | ||
3ad82a7e | 6049 | /* |
39337ad1 | 6050 | * Calculate mmu pages needed for kvm. |
3ad82a7e ZX |
6051 | */ |
6052 | unsigned int kvm_mmu_calculate_mmu_pages(struct kvm *kvm) | |
6053 | { | |
3ad82a7e ZX |
6054 | unsigned int nr_mmu_pages; |
6055 | unsigned int nr_pages = 0; | |
bc6678a3 | 6056 | struct kvm_memslots *slots; |
be6ba0f0 | 6057 | struct kvm_memory_slot *memslot; |
9da0e4d5 | 6058 | int i; |
3ad82a7e | 6059 | |
9da0e4d5 PB |
6060 | for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) { |
6061 | slots = __kvm_memslots(kvm, i); | |
90d83dc3 | 6062 | |
9da0e4d5 PB |
6063 | kvm_for_each_memslot(memslot, slots) |
6064 | nr_pages += memslot->npages; | |
6065 | } | |
3ad82a7e ZX |
6066 | |
6067 | nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000; | |
6068 | nr_mmu_pages = max(nr_mmu_pages, | |
9da0e4d5 | 6069 | (unsigned int) KVM_MIN_ALLOC_MMU_PAGES); |
3ad82a7e ZX |
6070 | |
6071 | return nr_mmu_pages; | |
6072 | } | |
6073 | ||
c42fffe3 XG |
6074 | void kvm_mmu_destroy(struct kvm_vcpu *vcpu) |
6075 | { | |
95f93af4 | 6076 | kvm_mmu_unload(vcpu); |
c42fffe3 XG |
6077 | free_mmu_pages(vcpu); |
6078 | mmu_free_memory_caches(vcpu); | |
b034cf01 XG |
6079 | } |
6080 | ||
b034cf01 XG |
6081 | void kvm_mmu_module_exit(void) |
6082 | { | |
6083 | mmu_destroy_caches(); | |
6084 | percpu_counter_destroy(&kvm_total_used_mmu_pages); | |
6085 | unregister_shrinker(&mmu_shrinker); | |
c42fffe3 XG |
6086 | mmu_audit_disable(); |
6087 | } |