[people/ms/linux.git] / arch / x86 / kvm / paging_tmpl.h

/*
 * Kernel-based Virtual Machine driver for Linux
 *
 * This module enables machines with Intel VT-x extensions to run virtual
 * machines without emulation or binary translation.
 *
 * MMU support
 *
 * Copyright (C) 2006 Qumranet, Inc.
 *
 * Authors:
 *   Yaniv Kamay  <yaniv@qumranet.com>
 *   Avi Kivity   <avi@qumranet.com>
 *
 * This work is licensed under the terms of the GNU GPL, version 2.  See
 * the COPYING file in the top-level directory.
 *
 */

/*
 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
 * so the code in this file is compiled twice, once per pte size.
 */

#if PTTYPE == 64
	#define pt_element_t u64
	#define guest_walker guest_walker64
	#define shadow_walker shadow_walker64
	#define FNAME(name) paging##64_##name
	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT64_LEVEL_BITS
	#ifdef CONFIG_X86_64
	#define PT_MAX_FULL_LEVELS 4
	#define CMPXCHG cmpxchg
	#else
	#define CMPXCHG cmpxchg64
	#define PT_MAX_FULL_LEVELS 2
	#endif
#elif PTTYPE == 32
	#define pt_element_t u32
	#define guest_walker guest_walker32
	#define shadow_walker shadow_walker32
	#define FNAME(name) paging##32_##name
	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
	#define PT_LEVEL_BITS PT32_LEVEL_BITS
	#define PT_MAX_FULL_LEVELS 2
	#define CMPXCHG cmpxchg
#else
	#error Invalid PTTYPE value
#endif

#define gpte_to_gfn FNAME(gpte_to_gfn)
#define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)

/*
 * The guest_walker structure emulates the behavior of the hardware page
 * table walker.
 */
struct guest_walker {
	int level;
	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
	pt_element_t ptes[PT_MAX_FULL_LEVELS];
	gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
	unsigned pt_access;
	unsigned pte_access;
	gfn_t gfn;
	u32 error_code;
};

struct shadow_walker {
	struct kvm_shadow_walk walker;
	struct guest_walker *guest_walker;
	int user_fault;
	int write_fault;
	int largepage;
	int *ptwrite;
	pfn_t pfn;
	u64 *sptep;
};

static gfn_t gpte_to_gfn(pt_element_t gpte)
{
	return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
}

static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
{
	return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
}

static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
			 gfn_t table_gfn, unsigned index,
			 pt_element_t orig_pte, pt_element_t new_pte)
{
	pt_element_t ret;
	pt_element_t *table;
	struct page *page;

	page = gfn_to_page(kvm, table_gfn);

	table = kmap_atomic(page, KM_USER0);
	ret = CMPXCHG(&table[index], orig_pte, new_pte);
	kunmap_atomic(table, KM_USER0);

	kvm_release_page_dirty(page);

	return (ret != orig_pte);
}

static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
{
	unsigned access;

	access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
#if PTTYPE == 64
	if (is_nx(vcpu))
		access &= ~(gpte >> PT64_NX_SHIFT);
#endif
	return access;
}

/*
 * Fetch a guest pte for a guest virtual address
 */
static int FNAME(walk_addr)(struct guest_walker *walker,
			    struct kvm_vcpu *vcpu, gva_t addr,
			    int write_fault, int user_fault, int fetch_fault)
{
	pt_element_t pte;
	gfn_t table_gfn;
	unsigned index, pt_access, pte_access;
	gpa_t pte_gpa;

	pgprintk("%s: addr %lx\n", __func__, addr);
walk:
	walker->level = vcpu->arch.mmu.root_level;
	pte = vcpu->arch.cr3;
#if PTTYPE == 64
	if (!is_long_mode(vcpu)) {
		pte = vcpu->arch.pdptrs[(addr >> 30) & 3];
		if (!is_present_pte(pte))
			goto not_present;
		--walker->level;
	}
#endif
	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
	       (vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);

	pt_access = ACC_ALL;

	for (;;) {
		index = PT_INDEX(addr, walker->level);

		table_gfn = gpte_to_gfn(pte);
		pte_gpa = gfn_to_gpa(table_gfn);
		pte_gpa += index * sizeof(pt_element_t);
		walker->table_gfn[walker->level - 1] = table_gfn;
		walker->pte_gpa[walker->level - 1] = pte_gpa;
		pgprintk("%s: table_gfn[%d] %lx\n", __func__,
			 walker->level - 1, table_gfn);

		kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));

		if (!is_present_pte(pte))
			goto not_present;

		if (write_fault && !is_writeble_pte(pte))
			if (user_fault || is_write_protection(vcpu))
				goto access_error;

		if (user_fault && !(pte & PT_USER_MASK))
			goto access_error;

#if PTTYPE == 64
		if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
			goto access_error;
#endif

		if (!(pte & PT_ACCESSED_MASK)) {
			mark_page_dirty(vcpu->kvm, table_gfn);
			if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
			    index, pte, pte|PT_ACCESSED_MASK))
				goto walk;
			pte |= PT_ACCESSED_MASK;
		}

		pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);

		walker->ptes[walker->level - 1] = pte;

		if (walker->level == PT_PAGE_TABLE_LEVEL) {
			walker->gfn = gpte_to_gfn(pte);
			break;
		}

		if (walker->level == PT_DIRECTORY_LEVEL
		    && (pte & PT_PAGE_SIZE_MASK)
		    && (PTTYPE == 64 || is_pse(vcpu))) {
			walker->gfn = gpte_to_gfn_pde(pte);
			walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
			if (PTTYPE == 32 && is_cpuid_PSE36())
				walker->gfn += pse36_gfn_delta(pte);
			break;
		}

		pt_access = pte_access;
		--walker->level;
	}

	if (write_fault && !is_dirty_pte(pte)) {
		bool ret;

		mark_page_dirty(vcpu->kvm, table_gfn);
		ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
			    pte|PT_DIRTY_MASK);
		if (ret)
			goto walk;
		pte |= PT_DIRTY_MASK;
		kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
		walker->ptes[walker->level - 1] = pte;
	}

	walker->pt_access = pt_access;
	walker->pte_access = pte_access;
	pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
		 __func__, (u64)pte, pt_access, pte_access);
	return 1;

not_present:
	walker->error_code = 0;
	goto err;

access_error:
	walker->error_code = PFERR_PRESENT_MASK;

err:
	if (write_fault)
		walker->error_code |= PFERR_WRITE_MASK;
	if (user_fault)
		walker->error_code |= PFERR_USER_MASK;
	if (fetch_fault)
		walker->error_code |= PFERR_FETCH_MASK;
	return 0;
}

static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *page,
			      u64 *spte, const void *pte)
{
	pt_element_t gpte;
	unsigned pte_access;
	pfn_t pfn;
	int largepage = vcpu->arch.update_pte.largepage;

	gpte = *(const pt_element_t *)pte;
	if (~gpte & (PT_PRESENT_MASK | PT_ACCESSED_MASK)) {
		if (!is_present_pte(gpte))
			set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
		return;
	}
	pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
	pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
	if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
		return;
	pfn = vcpu->arch.update_pte.pfn;
	if (is_error_pfn(pfn))
		return;
	if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
		return;
	kvm_get_pfn(pfn);
	mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
		     gpte & PT_DIRTY_MASK, NULL, largepage, gpte_to_gfn(gpte),
		     pfn, true);
}

/*
 * Fetch a shadow pte for a specific level in the paging hierarchy.
 */
static int FNAME(shadow_walk_entry)(struct kvm_shadow_walk *_sw,
				    struct kvm_vcpu *vcpu, u64 addr,
				    u64 *sptep, int level)
{
	struct shadow_walker *sw =
		container_of(_sw, struct shadow_walker, walker);
	struct guest_walker *gw = sw->guest_walker;
	unsigned access = gw->pt_access;
	struct kvm_mmu_page *shadow_page;
	u64 spte;
	int metaphysical;
	gfn_t table_gfn;
	int r;
	pt_element_t curr_pte;

	if (level == PT_PAGE_TABLE_LEVEL
	    || (sw->largepage && level == PT_DIRECTORY_LEVEL)) {
		mmu_set_spte(vcpu, sptep, access, gw->pte_access & access,
			     sw->user_fault, sw->write_fault,
			     gw->ptes[gw->level-1] & PT_DIRTY_MASK,
			     sw->ptwrite, sw->largepage, gw->gfn, sw->pfn,
			     false);
		sw->sptep = sptep;
		return 1;
	}

	if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep))
		return 0;

	if (is_large_pte(*sptep)) {
		set_shadow_pte(sptep, shadow_trap_nonpresent_pte);
		kvm_flush_remote_tlbs(vcpu->kvm);
		rmap_remove(vcpu->kvm, sptep);
	}

	if (level == PT_DIRECTORY_LEVEL && gw->level == PT_DIRECTORY_LEVEL) {
		metaphysical = 1;
		if (!is_dirty_pte(gw->ptes[level - 1]))
			access &= ~ACC_WRITE_MASK;
		table_gfn = gpte_to_gfn(gw->ptes[level - 1]);
	} else {
		metaphysical = 0;
		table_gfn = gw->table_gfn[level - 2];
	}
	shadow_page = kvm_mmu_get_page(vcpu, table_gfn, (gva_t)addr, level-1,
				       metaphysical, access, sptep);
	if (!metaphysical) {
		r = kvm_read_guest_atomic(vcpu->kvm, gw->pte_gpa[level - 2],
					  &curr_pte, sizeof(curr_pte));
		if (r || curr_pte != gw->ptes[level - 2]) {
			kvm_release_pfn_clean(sw->pfn);
			sw->sptep = NULL;
			return 1;
		}
	}

	spte = __pa(shadow_page->spt) | PT_PRESENT_MASK | PT_ACCESSED_MASK
		| PT_WRITABLE_MASK | PT_USER_MASK;
	*sptep = spte;
	return 0;
}

static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
			 struct guest_walker *guest_walker,
			 int user_fault, int write_fault, int largepage,
			 int *ptwrite, pfn_t pfn)
{
	struct shadow_walker walker = {
		.walker = { .entry = FNAME(shadow_walk_entry), },
		.guest_walker = guest_walker,
		.user_fault = user_fault,
		.write_fault = write_fault,
		.largepage = largepage,
		.ptwrite = ptwrite,
		.pfn = pfn,
	};

	if (!is_present_pte(guest_walker->ptes[guest_walker->level - 1]))
		return NULL;

	walk_shadow(&walker.walker, vcpu, addr);

	return walker.sptep;
}

/*
 * Page fault handler.  There are several causes for a page fault:
 *   - there is no shadow pte for the guest pte
 *   - write access through a shadow pte marked read only so that we can set
 *     the dirty bit
 *   - write access to a shadow pte marked read only so we can update the page
 *     dirty bitmap, when userspace requests it
 *   - mmio access; in this case we will never install a present shadow pte
 *   - normal guest page fault due to the guest pte marked not present, not
 *     writable, or not executable
 *
 *  Returns: 1 if we need to emulate the instruction, 0 otherwise, or
 *           a negative value on error.
 */
static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
			       u32 error_code)
{
	int write_fault = error_code & PFERR_WRITE_MASK;
	int user_fault = error_code & PFERR_USER_MASK;
	int fetch_fault = error_code & PFERR_FETCH_MASK;
	struct guest_walker walker;
	u64 *shadow_pte;
	int write_pt = 0;
	int r;
	pfn_t pfn;
	int largepage = 0;
	unsigned long mmu_seq;

	pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
	kvm_mmu_audit(vcpu, "pre page fault");

	r = mmu_topup_memory_caches(vcpu);
	if (r)
		return r;

	/*
	 * Look up the shadow pte for the faulting address.
	 */
	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
			     fetch_fault);

	/*
	 * The page is not mapped by the guest.  Let the guest handle it.
	 */
	if (!r) {
		pgprintk("%s: guest page fault\n", __func__);
		inject_page_fault(vcpu, addr, walker.error_code);
		vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
		return 0;
	}

	if (walker.level == PT_DIRECTORY_LEVEL) {
		gfn_t large_gfn;
		large_gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE-1);
		if (is_largepage_backed(vcpu, large_gfn)) {
			walker.gfn = large_gfn;
			largepage = 1;
		}
	}
	mmu_seq = vcpu->kvm->mmu_notifier_seq;
	smp_rmb();
	pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);

	/* mmio */
	if (is_error_pfn(pfn)) {
		pgprintk("gfn %lx is mmio\n", walker.gfn);
		kvm_release_pfn_clean(pfn);
		return 1;
	}

	spin_lock(&vcpu->kvm->mmu_lock);
	if (mmu_notifier_retry(vcpu, mmu_seq))
		goto out_unlock;
	kvm_mmu_free_some_pages(vcpu);
	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
				  largepage, &write_pt, pfn);

	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
		 shadow_pte, *shadow_pte, write_pt);

	if (!write_pt)
		vcpu->arch.last_pt_write_count = 0; /* reset fork detector */

	++vcpu->stat.pf_fixed;
	kvm_mmu_audit(vcpu, "post page fault (fixed)");
	spin_unlock(&vcpu->kvm->mmu_lock);

	return write_pt;

out_unlock:
	spin_unlock(&vcpu->kvm->mmu_lock);
	kvm_release_pfn_clean(pfn);
	return 0;
}

static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
{
	struct guest_walker walker;
	gpa_t gpa = UNMAPPED_GVA;
	int r;

	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);

	if (r) {
		gpa = gfn_to_gpa(walker.gfn);
		gpa |= vaddr & ~PAGE_MASK;
	}

	return gpa;
}

static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
				 struct kvm_mmu_page *sp)
{
	int i, j, offset, r;
	pt_element_t pt[256 / sizeof(pt_element_t)];
	gpa_t pte_gpa;

	if (sp->role.metaphysical
	    || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
		nonpaging_prefetch_page(vcpu, sp);
		return;
	}

	pte_gpa = gfn_to_gpa(sp->gfn);
	if (PTTYPE == 32) {
		offset = sp->role.quadrant << PT64_LEVEL_BITS;
		pte_gpa += offset * sizeof(pt_element_t);
	}

	for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
		r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
		pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
		for (j = 0; j < ARRAY_SIZE(pt); ++j)
			if (r || is_present_pte(pt[j]))
				sp->spt[i+j] = shadow_trap_nonpresent_pte;
			else
				sp->spt[i+j] = shadow_notrap_nonpresent_pte;
	}
}

/*
 * Using the cached information from sp->gfns is safe because:
 * - The spte has a reference to the struct page, so the pfn for a given gfn
 *   can't change unless all sptes pointing to it are nuked first.
 * - Alias changes zap the entire shadow cache.
 */
static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
{
	int i, offset, nr_present;

	offset = nr_present = 0;

	if (PTTYPE == 32)
		offset = sp->role.quadrant << PT64_LEVEL_BITS;

	for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
		unsigned pte_access;
		pt_element_t gpte;
		gpa_t pte_gpa;
		gfn_t gfn = sp->gfns[i];

		if (!is_shadow_present_pte(sp->spt[i]))
			continue;

		pte_gpa = gfn_to_gpa(sp->gfn);
		pte_gpa += (i+offset) * sizeof(pt_element_t);

		if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
					  sizeof(pt_element_t)))
			return -EINVAL;

		if (gpte_to_gfn(gpte) != gfn || !is_present_pte(gpte) ||
		    !(gpte & PT_ACCESSED_MASK)) {
			u64 nonpresent;

			rmap_remove(vcpu->kvm, &sp->spt[i]);
			if (is_present_pte(gpte))
				nonpresent = shadow_trap_nonpresent_pte;
			else
				nonpresent = shadow_notrap_nonpresent_pte;
			set_shadow_pte(&sp->spt[i], nonpresent);
			continue;
		}

		nr_present++;
		pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
		set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
			 is_dirty_pte(gpte), 0, gfn,
			 spte_to_pfn(sp->spt[i]), true);
	}

	return !nr_present;
}

#undef pt_element_t
#undef guest_walker
#undef shadow_walker
#undef FNAME
#undef PT_BASE_ADDR_MASK
#undef PT_INDEX
#undef PT_LEVEL_MASK
#undef PT_DIR_BASE_ADDR_MASK
#undef PT_LEVEL_BITS
#undef PT_MAX_FULL_LEVELS
#undef gpte_to_gfn
#undef gpte_to_gfn_pde
#undef CMPXCHG
Commit	Line	Data
6aa8b732 AK	1	/*
	2	* Kernel-based Virtual Machine driver for Linux
	3	*
	4	* This module enables machines with Intel VT-x extensions to run virtual
	5	* machines without emulation or binary translation.
	6	*
	7	* MMU support
	8	*
	9	* Copyright (C) 2006 Qumranet, Inc.
	10	*
	11	* Authors:
	12	* Yaniv Kamay <yaniv@qumranet.com>
	13	* Avi Kivity <avi@qumranet.com>
	14	*
	15	* This work is licensed under the terms of the GNU GPL, version 2. See
	16	* the COPYING file in the top-level directory.
	17	*
	18	*/
	19
	20	/*
	21	* We need the mmu code to access both 32-bit and 64-bit guest ptes,
	22	* so the code in this file is compiled twice, once per pte size.
	23	*/
	24
	25	#if PTTYPE == 64
	26	#define pt_element_t u64
	27	#define guest_walker guest_walker64
abb9e0b8	28	#define shadow_walker shadow_walker64
6aa8b732 AK	29	#define FNAME(name) paging##64_##name
	30	#define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
	31	#define PT_DIR_BASE_ADDR_MASK PT64_DIR_BASE_ADDR_MASK
	32	#define PT_INDEX(addr, level) PT64_INDEX(addr, level)
6aa8b732	33	#define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
c7addb90	34	#define PT_LEVEL_BITS PT64_LEVEL_BITS
cea0f0e7 AK	35	#ifdef CONFIG_X86_64
cea0f0e7 AK	36	#define PT_MAX_FULL_LEVELS 4
b3e4e63f	37	#define CMPXCHG cmpxchg
cea0f0e7	38	#else
b3e4e63f	39	#define CMPXCHG cmpxchg64
cea0f0e7 AK	40	#define PT_MAX_FULL_LEVELS 2
cea0f0e7 AK	41	#endif
6aa8b732 AK	42	#elif PTTYPE == 32
	43	#define pt_element_t u32
	44	#define guest_walker guest_walker32
abb9e0b8	45	#define shadow_walker shadow_walker32
6aa8b732 AK	46	#define FNAME(name) paging##32_##name
	47	#define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
	48	#define PT_DIR_BASE_ADDR_MASK PT32_DIR_BASE_ADDR_MASK
	49	#define PT_INDEX(addr, level) PT32_INDEX(addr, level)
6aa8b732	50	#define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
c7addb90	51	#define PT_LEVEL_BITS PT32_LEVEL_BITS
cea0f0e7	52	#define PT_MAX_FULL_LEVELS 2
b3e4e63f	53	#define CMPXCHG cmpxchg
6aa8b732 AK	54	#else
	55	#error Invalid PTTYPE value
	56	#endif
	57
5fb07ddb AK	58	#define gpte_to_gfn FNAME(gpte_to_gfn)
	59	#define gpte_to_gfn_pde FNAME(gpte_to_gfn_pde)
	60
6aa8b732 AK	61	/*
	62	* The guest_walker structure emulates the behavior of the hardware page
	63	* table walker.
	64	*/
	65	struct guest_walker {
	66	int level;
cea0f0e7	67	gfn_t table_gfn[PT_MAX_FULL_LEVELS];
7819026e MT	68	pt_element_t ptes[PT_MAX_FULL_LEVELS];
7819026e MT	69	gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
fe135d2c AK	70	unsigned pt_access;
fe135d2c AK	71	unsigned pte_access;
815af8d4	72	gfn_t gfn;
7993ba43	73	u32 error_code;
6aa8b732 AK	74	};
6aa8b732 AK	75
abb9e0b8 AK	76	struct shadow_walker {
	77	struct kvm_shadow_walk walker;
	78	struct guest_walker *guest_walker;
	79	int user_fault;
	80	int write_fault;
	81	int largepage;
	82	int *ptwrite;
	83	pfn_t pfn;
	84	u64 *sptep;
	85	};
	86
5fb07ddb AK	87	static gfn_t gpte_to_gfn(pt_element_t gpte)
	88	{
	89	return (gpte & PT_BASE_ADDR_MASK) >> PAGE_SHIFT;
	90	}
	91
	92	static gfn_t gpte_to_gfn_pde(pt_element_t gpte)
	93	{
	94	return (gpte & PT_DIR_BASE_ADDR_MASK) >> PAGE_SHIFT;
	95	}
	96
b3e4e63f MT	97	static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
	98	gfn_t table_gfn, unsigned index,
	99	pt_element_t orig_pte, pt_element_t new_pte)
	100	{
	101	pt_element_t ret;
	102	pt_element_t *table;
	103	struct page *page;
	104
	105	page = gfn_to_page(kvm, table_gfn);
72dc67a6	106
b3e4e63f	107	table = kmap_atomic(page, KM_USER0);
b3e4e63f	108	ret = CMPXCHG(&table[index], orig_pte, new_pte);
b3e4e63f MT	109	kunmap_atomic(table, KM_USER0);
	110
	111	kvm_release_page_dirty(page);
	112
	113	return (ret != orig_pte);
	114	}
	115
bedbe4ee AK	116	static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
	117	{
	118	unsigned access;
	119
	120	access = (gpte & (PT_WRITABLE_MASK \| PT_USER_MASK)) \| ACC_EXEC_MASK;
	121	#if PTTYPE == 64
	122	if (is_nx(vcpu))
	123	access &= ~(gpte >> PT64_NX_SHIFT);
	124	#endif
	125	return access;
	126	}
	127
ac79c978 AK	128	/*
	129	* Fetch a guest pte for a guest virtual address
	130	*/
7993ba43 AK	131	static int FNAME(walk_addr)(struct guest_walker *walker,
7993ba43 AK	132	struct kvm_vcpu *vcpu, gva_t addr,
73b1087e	133	int write_fault, int user_fault, int fetch_fault)
6aa8b732	134	{
42bf3f0a	135	pt_element_t pte;
cea0f0e7	136	gfn_t table_gfn;
fe135d2c	137	unsigned index, pt_access, pte_access;
42bf3f0a	138	gpa_t pte_gpa;
6aa8b732	139
b8688d51	140	pgprintk("%s: addr %lx\n", __func__, addr);
b3e4e63f	141	walk:
ad312c7c ZX	142	walker->level = vcpu->arch.mmu.root_level;
ad312c7c ZX	143	pte = vcpu->arch.cr3;
1b0973bd AK	144	#if PTTYPE == 64
1b0973bd AK	145	if (!is_long_mode(vcpu)) {
ad312c7c	146	pte = vcpu->arch.pdptrs[(addr >> 30) & 3];
42bf3f0a	147	if (!is_present_pte(pte))
7993ba43	148	goto not_present;
1b0973bd AK	149	--walker->level;
	150	}
	151	#endif
a9058ecd	152	ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) \|\|
24993d53	153	(vcpu->arch.cr3 & CR3_NONPAE_RESERVED_BITS) == 0);
6aa8b732	154
fe135d2c	155	pt_access = ACC_ALL;
ac79c978 AK	156
ac79c978 AK	157	for (;;) {
42bf3f0a	158	index = PT_INDEX(addr, walker->level);
ac79c978	159
5fb07ddb	160	table_gfn = gpte_to_gfn(pte);
1755fbcc	161	pte_gpa = gfn_to_gpa(table_gfn);
ec8d4eae	162	pte_gpa += index * sizeof(pt_element_t);
42bf3f0a	163	walker->table_gfn[walker->level - 1] = table_gfn;
7819026e	164	walker->pte_gpa[walker->level - 1] = pte_gpa;
b8688d51	165	pgprintk("%s: table_gfn[%d] %lx\n", __func__,
42bf3f0a AK	166	walker->level - 1, table_gfn);
42bf3f0a AK	167
ec8d4eae	168	kvm_read_guest(vcpu->kvm, pte_gpa, &pte, sizeof(pte));
42bf3f0a AK	169
42bf3f0a AK	170	if (!is_present_pte(pte))
7993ba43 AK	171	goto not_present;
7993ba43 AK	172
42bf3f0a	173	if (write_fault && !is_writeble_pte(pte))
7993ba43 AK	174	if (user_fault \|\| is_write_protection(vcpu))
	175	goto access_error;
	176
42bf3f0a	177	if (user_fault && !(pte & PT_USER_MASK))
7993ba43 AK	178	goto access_error;
7993ba43 AK	179
73b1087e	180	#if PTTYPE == 64
42bf3f0a	181	if (fetch_fault && is_nx(vcpu) && (pte & PT64_NX_MASK))
73b1087e AK	182	goto access_error;
	183	#endif
	184
42bf3f0a	185	if (!(pte & PT_ACCESSED_MASK)) {
bf3f8e86	186	mark_page_dirty(vcpu->kvm, table_gfn);
b3e4e63f MT	187	if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
	188	index, pte, pte\|PT_ACCESSED_MASK))
	189	goto walk;
42bf3f0a	190	pte \|= PT_ACCESSED_MASK;
bf3f8e86	191	}
815af8d4	192
bedbe4ee	193	pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
fe135d2c	194
7819026e MT	195	walker->ptes[walker->level - 1] = pte;
7819026e MT	196
815af8d4	197	if (walker->level == PT_PAGE_TABLE_LEVEL) {
5fb07ddb	198	walker->gfn = gpte_to_gfn(pte);
815af8d4 AK	199	break;
	200	}
	201
	202	if (walker->level == PT_DIRECTORY_LEVEL
42bf3f0a	203	&& (pte & PT_PAGE_SIZE_MASK)
815af8d4	204	&& (PTTYPE == 64 \|\| is_pse(vcpu))) {
5fb07ddb	205	walker->gfn = gpte_to_gfn_pde(pte);
815af8d4	206	walker->gfn += PT_INDEX(addr, PT_PAGE_TABLE_LEVEL);
da928521 AK	207	if (PTTYPE == 32 && is_cpuid_PSE36())
da928521 AK	208	walker->gfn += pse36_gfn_delta(pte);
ac79c978	209	break;
815af8d4	210	}
ac79c978	211
fe135d2c	212	pt_access = pte_access;
ac79c978 AK	213	--walker->level;
ac79c978 AK	214	}
42bf3f0a AK	215
42bf3f0a AK	216	if (write_fault && !is_dirty_pte(pte)) {
b3e4e63f MT	217	bool ret;
b3e4e63f MT	218
42bf3f0a	219	mark_page_dirty(vcpu->kvm, table_gfn);
b3e4e63f MT	220	ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
	221	pte\|PT_DIRTY_MASK);
	222	if (ret)
	223	goto walk;
42bf3f0a	224	pte \|= PT_DIRTY_MASK;
42bf3f0a	225	kvm_mmu_pte_write(vcpu, pte_gpa, (u8 *)&pte, sizeof(pte));
7819026e	226	walker->ptes[walker->level - 1] = pte;
42bf3f0a AK	227	}
42bf3f0a AK	228
fe135d2c AK	229	walker->pt_access = pt_access;
	230	walker->pte_access = pte_access;
	231	pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
b8688d51	232	__func__, (u64)pte, pt_access, pte_access);
7993ba43 AK	233	return 1;
	234
	235	not_present:
	236	walker->error_code = 0;
	237	goto err;
	238
	239	access_error:
	240	walker->error_code = PFERR_PRESENT_MASK;
	241
	242	err:
	243	if (write_fault)
	244	walker->error_code \|= PFERR_WRITE_MASK;
	245	if (user_fault)
	246	walker->error_code \|= PFERR_USER_MASK;
73b1087e AK	247	if (fetch_fault)
73b1087e AK	248	walker->error_code \|= PFERR_FETCH_MASK;
fe551881	249	return 0;
6aa8b732 AK	250	}
6aa8b732 AK	251
0028425f	252	static void FNAME(update_pte)(struct kvm_vcpu vcpu, struct kvm_mmu_page page,
489f1d65	253	u64 spte, const void pte)
0028425f AK	254	{
0028425f AK	255	pt_element_t gpte;
41074d07	256	unsigned pte_access;
35149e21	257	pfn_t pfn;
05da4558	258	int largepage = vcpu->arch.update_pte.largepage;
0028425f	259
0028425f	260	gpte = (const pt_element_t )pte;
c7addb90	261	if (~gpte & (PT_PRESENT_MASK \| PT_ACCESSED_MASK)) {
489f1d65	262	if (!is_present_pte(gpte))
c7addb90 AK	263	set_shadow_pte(spte, shadow_notrap_nonpresent_pte);
	264	return;
	265	}
b8688d51	266	pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
41074d07	267	pte_access = page->role.access & FNAME(gpte_access)(vcpu, gpte);
d7824fff AK	268	if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
d7824fff AK	269	return;
35149e21 AL	270	pfn = vcpu->arch.update_pte.pfn;
35149e21 AL	271	if (is_error_pfn(pfn))
d7824fff	272	return;
e930bffe AA	273	if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
e930bffe AA	274	return;
35149e21	275	kvm_get_pfn(pfn);
1c4f1fd6	276	mmu_set_spte(vcpu, spte, page->role.access, pte_access, 0, 0,
05da4558	277	gpte & PT_DIRTY_MASK, NULL, largepage, gpte_to_gfn(gpte),
35149e21	278	pfn, true);
0028425f AK	279	}
0028425f AK	280
6aa8b732 AK	281	/*
	282	* Fetch a shadow pte for a specific level in the paging hierarchy.
	283	*/
abb9e0b8	284	static int FNAME(shadow_walk_entry)(struct kvm_shadow_walk *_sw,
d40a1ee4	285	struct kvm_vcpu *vcpu, u64 addr,
abb9e0b8	286	u64 *sptep, int level)
6aa8b732	287	{
abb9e0b8 AK	288	struct shadow_walker *sw =
	289	container_of(_sw, struct shadow_walker, walker);
	290	struct guest_walker *gw = sw->guest_walker;
	291	unsigned access = gw->pt_access;
	292	struct kvm_mmu_page *shadow_page;
	293	u64 spte;
	294	int metaphysical;
	295	gfn_t table_gfn;
	296	int r;
	297	pt_element_t curr_pte;
	298
	299	if (level == PT_PAGE_TABLE_LEVEL
	300	\|\| (sw->largepage && level == PT_DIRECTORY_LEVEL)) {
	301	mmu_set_spte(vcpu, sptep, access, gw->pte_access & access,
	302	sw->user_fault, sw->write_fault,
	303	gw->ptes[gw->level-1] & PT_DIRTY_MASK,
	304	sw->ptwrite, sw->largepage, gw->gfn, sw->pfn,
	305	false);
	306	sw->sptep = sptep;
	307	return 1;
aef3d3fe	308	}
6aa8b732	309
abb9e0b8 AK	310	if (is_shadow_present_pte(sptep) && !is_large_pte(sptep))
abb9e0b8 AK	311	return 0;
6aa8b732	312
93a423e7 MT	313	if (is_large_pte(*sptep)) {
	314	set_shadow_pte(sptep, shadow_trap_nonpresent_pte);
	315	kvm_flush_remote_tlbs(vcpu->kvm);
abb9e0b8	316	rmap_remove(vcpu->kvm, sptep);
93a423e7	317	}
abb9e0b8 AK	318
	319	if (level == PT_DIRECTORY_LEVEL && gw->level == PT_DIRECTORY_LEVEL) {
	320	metaphysical = 1;
	321	if (!is_dirty_pte(gw->ptes[level - 1]))
	322	access &= ~ACC_WRITE_MASK;
	323	table_gfn = gpte_to_gfn(gw->ptes[level - 1]);
	324	} else {
	325	metaphysical = 0;
	326	table_gfn = gw->table_gfn[level - 2];
	327	}
d40a1ee4	328	shadow_page = kvm_mmu_get_page(vcpu, table_gfn, (gva_t)addr, level-1,
abb9e0b8 AK	329	metaphysical, access, sptep);
	330	if (!metaphysical) {
	331	r = kvm_read_guest_atomic(vcpu->kvm, gw->pte_gpa[level - 2],
	332	&curr_pte, sizeof(curr_pte));
	333	if (r \|\| curr_pte != gw->ptes[level - 2]) {
	334	kvm_release_pfn_clean(sw->pfn);
	335	sw->sptep = NULL;
	336	return 1;
7819026e	337	}
6aa8b732	338	}
ef0197e8	339
abb9e0b8 AK	340	spte = __pa(shadow_page->spt) \| PT_PRESENT_MASK \| PT_ACCESSED_MASK
	341	\| PT_WRITABLE_MASK \| PT_USER_MASK;
	342	*sptep = spte;
	343	return 0;
	344	}
	345
	346	static u64 FNAME(fetch)(struct kvm_vcpu vcpu, gva_t addr,
	347	struct guest_walker *guest_walker,
	348	int user_fault, int write_fault, int largepage,
	349	int *ptwrite, pfn_t pfn)
	350	{
	351	struct shadow_walker walker = {
	352	.walker = { .entry = FNAME(shadow_walk_entry), },
	353	.guest_walker = guest_walker,
	354	.user_fault = user_fault,
	355	.write_fault = write_fault,
	356	.largepage = largepage,
	357	.ptwrite = ptwrite,
	358	.pfn = pfn,
	359	};
	360
	361	if (!is_present_pte(guest_walker->ptes[guest_walker->level - 1]))
	362	return NULL;
	363
	364	walk_shadow(&walker.walker, vcpu, addr);
050e6499	365
abb9e0b8	366	return walker.sptep;
6aa8b732 AK	367	}
6aa8b732 AK	368
6aa8b732 AK	369	/*
	370	* Page fault handler. There are several causes for a page fault:
	371	* - there is no shadow pte for the guest pte
	372	* - write access through a shadow pte marked read only so that we can set
	373	* the dirty bit
	374	* - write access to a shadow pte marked read only so we can update the page
	375	* dirty bitmap, when userspace requests it
	376	* - mmio access; in this case we will never install a present shadow pte
	377	* - normal guest page fault due to the guest pte marked not present, not
	378	* writable, or not executable
	379	*
e2dec939 AK	380	* Returns: 1 if we need to emulate the instruction, 0 otherwise, or
e2dec939 AK	381	* a negative value on error.
6aa8b732 AK	382	*/
	383	static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr,
	384	u32 error_code)
	385	{
	386	int write_fault = error_code & PFERR_WRITE_MASK;
6aa8b732	387	int user_fault = error_code & PFERR_USER_MASK;
73b1087e	388	int fetch_fault = error_code & PFERR_FETCH_MASK;
6aa8b732 AK	389	struct guest_walker walker;
6aa8b732 AK	390	u64 *shadow_pte;
cea0f0e7	391	int write_pt = 0;
e2dec939	392	int r;
35149e21	393	pfn_t pfn;
05da4558	394	int largepage = 0;
e930bffe	395	unsigned long mmu_seq;
6aa8b732	396
b8688d51	397	pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
37a7d8b0	398	kvm_mmu_audit(vcpu, "pre page fault");
714b93da	399
e2dec939 AK	400	r = mmu_topup_memory_caches(vcpu);
	401	if (r)
	402	return r;
714b93da	403
6aa8b732 AK	404	/*
	405	* Look up the shadow pte for the faulting address.
	406	*/
73b1087e AK	407	r = FNAME(walk_addr)(&walker, vcpu, addr, write_fault, user_fault,
73b1087e AK	408	fetch_fault);
6aa8b732 AK	409
	410	/*
	411	* The page is not mapped by the guest. Let the guest handle it.
	412	*/
7993ba43	413	if (!r) {
b8688d51	414	pgprintk("%s: guest page fault\n", __func__);
7993ba43	415	inject_page_fault(vcpu, addr, walker.error_code);
ad312c7c	416	vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
6aa8b732 AK	417	return 0;
	418	}
	419
05da4558 MT	420	if (walker.level == PT_DIRECTORY_LEVEL) {
	421	gfn_t large_gfn;
	422	large_gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE-1);
	423	if (is_largepage_backed(vcpu, large_gfn)) {
	424	walker.gfn = large_gfn;
	425	largepage = 1;
	426	}
	427	}
e930bffe	428	mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce	429	smp_rmb();
35149e21	430	pfn = gfn_to_pfn(vcpu->kvm, walker.gfn);
d7824fff	431
d196e343	432	/* mmio */
35149e21	433	if (is_error_pfn(pfn)) {
ebb0e626	434	pgprintk("gfn %lx is mmio\n", walker.gfn);
35149e21	435	kvm_release_pfn_clean(pfn);
d196e343 AK	436	return 1;
	437	}
	438
aaee2c94	439	spin_lock(&vcpu->kvm->mmu_lock);
e930bffe AA	440	if (mmu_notifier_retry(vcpu, mmu_seq))
e930bffe AA	441	goto out_unlock;
eb787d10	442	kvm_mmu_free_some_pages(vcpu);
97a0a01e	443	shadow_pte = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
35149e21	444	largepage, &write_pt, pfn);
05da4558	445
b8688d51	446	pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
97a0a01e	447	shadow_pte, *shadow_pte, write_pt);
cea0f0e7	448
a25f7e1f	449	if (!write_pt)
ad312c7c	450	vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
a25f7e1f	451
1165f5fe	452	++vcpu->stat.pf_fixed;
37a7d8b0	453	kvm_mmu_audit(vcpu, "post page fault (fixed)");
aaee2c94	454	spin_unlock(&vcpu->kvm->mmu_lock);
6aa8b732	455
cea0f0e7	456	return write_pt;
e930bffe AA	457
	458	out_unlock:
	459	spin_unlock(&vcpu->kvm->mmu_lock);
	460	kvm_release_pfn_clean(pfn);
	461	return 0;
6aa8b732 AK	462	}
	463
	464	static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr)
	465	{
	466	struct guest_walker walker;
e119d117 AK	467	gpa_t gpa = UNMAPPED_GVA;
e119d117 AK	468	int r;
6aa8b732	469
e119d117	470	r = FNAME(walk_addr)(&walker, vcpu, vaddr, 0, 0, 0);
6aa8b732	471
e119d117	472	if (r) {
1755fbcc	473	gpa = gfn_to_gpa(walker.gfn);
e119d117	474	gpa \|= vaddr & ~PAGE_MASK;
6aa8b732 AK	475	}
	476
	477	return gpa;
	478	}
	479
c7addb90 AK	480	static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
	481	struct kvm_mmu_page *sp)
	482	{
eab9f71f AK	483	int i, j, offset, r;
	484	pt_element_t pt[256 / sizeof(pt_element_t)];
	485	gpa_t pte_gpa;
c7addb90	486
e5a4c8ca AK	487	if (sp->role.metaphysical
e5a4c8ca AK	488	\|\| (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
c7addb90 AK	489	nonpaging_prefetch_page(vcpu, sp);
	490	return;
	491	}
	492
eab9f71f AK	493	pte_gpa = gfn_to_gpa(sp->gfn);
eab9f71f AK	494	if (PTTYPE == 32) {
e5a4c8ca	495	offset = sp->role.quadrant << PT64_LEVEL_BITS;
eab9f71f AK	496	pte_gpa += offset * sizeof(pt_element_t);
eab9f71f AK	497	}
7ec54588	498
eab9f71f AK	499	for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
	500	r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
	501	pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
	502	for (j = 0; j < ARRAY_SIZE(pt); ++j)
	503	if (r \|\| is_present_pte(pt[j]))
	504	sp->spt[i+j] = shadow_trap_nonpresent_pte;
	505	else
	506	sp->spt[i+j] = shadow_notrap_nonpresent_pte;
7ec54588	507	}
c7addb90 AK	508	}
c7addb90 AK	509
e8bc217a MT	510	/*
	511	* Using the cached information from sp->gfns is safe because:
	512	* - The spte has a reference to the struct page, so the pfn for a given gfn
	513	* can't change unless all sptes pointing to it are nuked first.
	514	* - Alias changes zap the entire shadow cache.
	515	*/
	516	static int FNAME(sync_page)(struct kvm_vcpu vcpu, struct kvm_mmu_page sp)
	517	{
	518	int i, offset, nr_present;
	519
	520	offset = nr_present = 0;
	521
	522	if (PTTYPE == 32)
	523	offset = sp->role.quadrant << PT64_LEVEL_BITS;
	524
	525	for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
	526	unsigned pte_access;
	527	pt_element_t gpte;
	528	gpa_t pte_gpa;
	529	gfn_t gfn = sp->gfns[i];
	530
	531	if (!is_shadow_present_pte(sp->spt[i]))
	532	continue;
	533
	534	pte_gpa = gfn_to_gpa(sp->gfn);
	535	pte_gpa += (i+offset) * sizeof(pt_element_t);
	536
	537	if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
	538	sizeof(pt_element_t)))
	539	return -EINVAL;
	540
	541	if (gpte_to_gfn(gpte) != gfn \|\| !is_present_pte(gpte) \|\|
	542	!(gpte & PT_ACCESSED_MASK)) {
	543	u64 nonpresent;
	544
	545	rmap_remove(vcpu->kvm, &sp->spt[i]);
	546	if (is_present_pte(gpte))
	547	nonpresent = shadow_trap_nonpresent_pte;
	548	else
	549	nonpresent = shadow_notrap_nonpresent_pte;
	550	set_shadow_pte(&sp->spt[i], nonpresent);
	551	continue;
	552	}
	553
	554	nr_present++;
	555	pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
	556	set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
	557	is_dirty_pte(gpte), 0, gfn,
	558	spte_to_pfn(sp->spt[i]), true);
	559	}
	560
	561	return !nr_present;
	562	}
	563
6aa8b732 AK	564	#undef pt_element_t
6aa8b732 AK	565	#undef guest_walker
abb9e0b8	566	#undef shadow_walker
6aa8b732 AK	567	#undef FNAME
	568	#undef PT_BASE_ADDR_MASK
	569	#undef PT_INDEX
6aa8b732	570	#undef PT_LEVEL_MASK
6aa8b732	571	#undef PT_DIR_BASE_ADDR_MASK
c7addb90	572	#undef PT_LEVEL_BITS
cea0f0e7	573	#undef PT_MAX_FULL_LEVELS
5fb07ddb AK	574	#undef gpte_to_gfn
5fb07ddb AK	575	#undef gpte_to_gfn_pde
b3e4e63f	576	#undef CMPXCHG