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KVM: x86 emulator: simplify exception generation
[people/ms/linux.git] / arch / x86 / kvm / paging_tmpl.h
CommitLineData
6aa8b732
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1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * MMU support
8 *
9 * Copyright (C) 2006 Qumranet, Inc.
9611c187 10 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
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11 *
12 * Authors:
13 * Yaniv Kamay <yaniv@qumranet.com>
14 * Avi Kivity <avi@qumranet.com>
15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
21/*
22 * We need the mmu code to access both 32-bit and 64-bit guest ptes,
23 * so the code in this file is compiled twice, once per pte size.
24 */
25
26#if PTTYPE == 64
27 #define pt_element_t u64
28 #define guest_walker guest_walker64
29 #define FNAME(name) paging##64_##name
30 #define PT_BASE_ADDR_MASK PT64_BASE_ADDR_MASK
e04da980
JR
31 #define PT_LVL_ADDR_MASK(lvl) PT64_LVL_ADDR_MASK(lvl)
32 #define PT_LVL_OFFSET_MASK(lvl) PT64_LVL_OFFSET_MASK(lvl)
6aa8b732 33 #define PT_INDEX(addr, level) PT64_INDEX(addr, level)
6aa8b732 34 #define PT_LEVEL_MASK(level) PT64_LEVEL_MASK(level)
c7addb90 35 #define PT_LEVEL_BITS PT64_LEVEL_BITS
cea0f0e7
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36 #ifdef CONFIG_X86_64
37 #define PT_MAX_FULL_LEVELS 4
b3e4e63f 38 #define CMPXCHG cmpxchg
cea0f0e7 39 #else
b3e4e63f 40 #define CMPXCHG cmpxchg64
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41 #define PT_MAX_FULL_LEVELS 2
42 #endif
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43#elif PTTYPE == 32
44 #define pt_element_t u32
45 #define guest_walker guest_walker32
46 #define FNAME(name) paging##32_##name
47 #define PT_BASE_ADDR_MASK PT32_BASE_ADDR_MASK
e04da980
JR
48 #define PT_LVL_ADDR_MASK(lvl) PT32_LVL_ADDR_MASK(lvl)
49 #define PT_LVL_OFFSET_MASK(lvl) PT32_LVL_OFFSET_MASK(lvl)
6aa8b732 50 #define PT_INDEX(addr, level) PT32_INDEX(addr, level)
6aa8b732 51 #define PT_LEVEL_MASK(level) PT32_LEVEL_MASK(level)
c7addb90 52 #define PT_LEVEL_BITS PT32_LEVEL_BITS
cea0f0e7 53 #define PT_MAX_FULL_LEVELS 2
b3e4e63f 54 #define CMPXCHG cmpxchg
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55#else
56 #error Invalid PTTYPE value
57#endif
58
e04da980
JR
59#define gpte_to_gfn_lvl FNAME(gpte_to_gfn_lvl)
60#define gpte_to_gfn(pte) gpte_to_gfn_lvl((pte), PT_PAGE_TABLE_LEVEL)
5fb07ddb 61
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62/*
63 * The guest_walker structure emulates the behavior of the hardware page
64 * table walker.
65 */
66struct guest_walker {
67 int level;
cea0f0e7 68 gfn_t table_gfn[PT_MAX_FULL_LEVELS];
7819026e 69 pt_element_t ptes[PT_MAX_FULL_LEVELS];
189be38d 70 pt_element_t prefetch_ptes[PTE_PREFETCH_NUM];
7819026e 71 gpa_t pte_gpa[PT_MAX_FULL_LEVELS];
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72 unsigned pt_access;
73 unsigned pte_access;
815af8d4 74 gfn_t gfn;
7993ba43 75 u32 error_code;
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76};
77
e04da980 78static gfn_t gpte_to_gfn_lvl(pt_element_t gpte, int lvl)
5fb07ddb 79{
e04da980 80 return (gpte & PT_LVL_ADDR_MASK(lvl)) >> PAGE_SHIFT;
5fb07ddb
AK
81}
82
b3e4e63f
MT
83static bool FNAME(cmpxchg_gpte)(struct kvm *kvm,
84 gfn_t table_gfn, unsigned index,
85 pt_element_t orig_pte, pt_element_t new_pte)
86{
87 pt_element_t ret;
88 pt_element_t *table;
89 struct page *page;
90
91 page = gfn_to_page(kvm, table_gfn);
72dc67a6 92
b3e4e63f 93 table = kmap_atomic(page, KM_USER0);
b3e4e63f 94 ret = CMPXCHG(&table[index], orig_pte, new_pte);
b3e4e63f
MT
95 kunmap_atomic(table, KM_USER0);
96
97 kvm_release_page_dirty(page);
98
99 return (ret != orig_pte);
100}
101
bedbe4ee
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102static unsigned FNAME(gpte_access)(struct kvm_vcpu *vcpu, pt_element_t gpte)
103{
104 unsigned access;
105
106 access = (gpte & (PT_WRITABLE_MASK | PT_USER_MASK)) | ACC_EXEC_MASK;
107#if PTTYPE == 64
2d48a985 108 if (vcpu->arch.mmu.nx)
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109 access &= ~(gpte >> PT64_NX_SHIFT);
110#endif
111 return access;
112}
113
ac79c978
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114/*
115 * Fetch a guest pte for a guest virtual address
116 */
1e301feb
JR
117static int FNAME(walk_addr_generic)(struct guest_walker *walker,
118 struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
33770780 119 gva_t addr, u32 access)
6aa8b732 120{
42bf3f0a 121 pt_element_t pte;
cea0f0e7 122 gfn_t table_gfn;
f59c1d2d 123 unsigned index, pt_access, uninitialized_var(pte_access);
42bf3f0a 124 gpa_t pte_gpa;
f59c1d2d 125 bool eperm, present, rsvd_fault;
33770780
XG
126 int offset, write_fault, user_fault, fetch_fault;
127
128 write_fault = access & PFERR_WRITE_MASK;
129 user_fault = access & PFERR_USER_MASK;
130 fetch_fault = access & PFERR_FETCH_MASK;
6aa8b732 131
07420171
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132 trace_kvm_mmu_pagetable_walk(addr, write_fault, user_fault,
133 fetch_fault);
b3e4e63f 134walk:
f59c1d2d
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135 present = true;
136 eperm = rsvd_fault = false;
1e301feb
JR
137 walker->level = mmu->root_level;
138 pte = mmu->get_cr3(vcpu);
139
1b0973bd 140#if PTTYPE == 64
1e301feb 141 if (walker->level == PT32E_ROOT_LEVEL) {
d41d1895 142 pte = kvm_pdptr_read_mmu(vcpu, mmu, (addr >> 30) & 3);
07420171 143 trace_kvm_mmu_paging_element(pte, walker->level);
f59c1d2d
AK
144 if (!is_present_gpte(pte)) {
145 present = false;
146 goto error;
147 }
1b0973bd
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148 --walker->level;
149 }
150#endif
a9058ecd 151 ASSERT((!is_long_mode(vcpu) && is_pae(vcpu)) ||
1e301feb 152 (mmu->get_cr3(vcpu) & CR3_NONPAE_RESERVED_BITS) == 0);
6aa8b732 153
fe135d2c 154 pt_access = ACC_ALL;
ac79c978
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155
156 for (;;) {
42bf3f0a 157 index = PT_INDEX(addr, walker->level);
ac79c978 158
5fb07ddb 159 table_gfn = gpte_to_gfn(pte);
2329d46d
JR
160 offset = index * sizeof(pt_element_t);
161 pte_gpa = gfn_to_gpa(table_gfn) + offset;
42bf3f0a 162 walker->table_gfn[walker->level - 1] = table_gfn;
7819026e 163 walker->pte_gpa[walker->level - 1] = pte_gpa;
42bf3f0a 164
2329d46d
JR
165 if (kvm_read_guest_page_mmu(vcpu, mmu, table_gfn, &pte,
166 offset, sizeof(pte),
167 PFERR_USER_MASK|PFERR_WRITE_MASK)) {
f59c1d2d
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168 present = false;
169 break;
170 }
a6085fba 171
07420171 172 trace_kvm_mmu_paging_element(pte, walker->level);
42bf3f0a 173
f59c1d2d
AK
174 if (!is_present_gpte(pte)) {
175 present = false;
176 break;
177 }
7993ba43 178
3241f22d 179 if (is_rsvd_bits_set(&vcpu->arch.mmu, pte, walker->level)) {
f59c1d2d
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180 rsvd_fault = true;
181 break;
182 }
82725b20 183
8dae4445 184 if (write_fault && !is_writable_pte(pte))
7993ba43 185 if (user_fault || is_write_protection(vcpu))
f59c1d2d 186 eperm = true;
7993ba43 187
42bf3f0a 188 if (user_fault && !(pte & PT_USER_MASK))
f59c1d2d 189 eperm = true;
7993ba43 190
73b1087e 191#if PTTYPE == 64
24222c2f 192 if (fetch_fault && (pte & PT64_NX_MASK))
f59c1d2d 193 eperm = true;
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194#endif
195
f59c1d2d 196 if (!eperm && !rsvd_fault && !(pte & PT_ACCESSED_MASK)) {
07420171
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197 trace_kvm_mmu_set_accessed_bit(table_gfn, index,
198 sizeof(pte));
b3e4e63f
MT
199 if (FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn,
200 index, pte, pte|PT_ACCESSED_MASK))
201 goto walk;
f3b8c964 202 mark_page_dirty(vcpu->kvm, table_gfn);
42bf3f0a 203 pte |= PT_ACCESSED_MASK;
bf3f8e86 204 }
815af8d4 205
bedbe4ee 206 pte_access = pt_access & FNAME(gpte_access)(vcpu, pte);
fe135d2c 207
7819026e
MT
208 walker->ptes[walker->level - 1] = pte;
209
e04da980
JR
210 if ((walker->level == PT_PAGE_TABLE_LEVEL) ||
211 ((walker->level == PT_DIRECTORY_LEVEL) &&
814a59d2 212 is_large_pte(pte) &&
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JR
213 (PTTYPE == 64 || is_pse(vcpu))) ||
214 ((walker->level == PT_PDPE_LEVEL) &&
814a59d2 215 is_large_pte(pte) &&
1e301feb 216 mmu->root_level == PT64_ROOT_LEVEL)) {
e04da980 217 int lvl = walker->level;
2329d46d
JR
218 gpa_t real_gpa;
219 gfn_t gfn;
33770780 220 u32 ac;
e04da980 221
2329d46d
JR
222 gfn = gpte_to_gfn_lvl(pte, lvl);
223 gfn += (addr & PT_LVL_OFFSET_MASK(lvl)) >> PAGE_SHIFT;
e04da980
JR
224
225 if (PTTYPE == 32 &&
226 walker->level == PT_DIRECTORY_LEVEL &&
227 is_cpuid_PSE36())
2329d46d
JR
228 gfn += pse36_gfn_delta(pte);
229
33770780 230 ac = write_fault | fetch_fault | user_fault;
2329d46d
JR
231
232 real_gpa = mmu->translate_gpa(vcpu, gfn_to_gpa(gfn),
33770780 233 ac);
2329d46d
JR
234 if (real_gpa == UNMAPPED_GVA)
235 return 0;
236
237 walker->gfn = real_gpa >> PAGE_SHIFT;
e04da980 238
ac79c978 239 break;
815af8d4 240 }
ac79c978 241
fe135d2c 242 pt_access = pte_access;
ac79c978
AK
243 --walker->level;
244 }
42bf3f0a 245
f59c1d2d
AK
246 if (!present || eperm || rsvd_fault)
247 goto error;
248
43a3795a 249 if (write_fault && !is_dirty_gpte(pte)) {
b3e4e63f
MT
250 bool ret;
251
07420171 252 trace_kvm_mmu_set_dirty_bit(table_gfn, index, sizeof(pte));
b3e4e63f
MT
253 ret = FNAME(cmpxchg_gpte)(vcpu->kvm, table_gfn, index, pte,
254 pte|PT_DIRTY_MASK);
255 if (ret)
256 goto walk;
f3b8c964 257 mark_page_dirty(vcpu->kvm, table_gfn);
42bf3f0a 258 pte |= PT_DIRTY_MASK;
7819026e 259 walker->ptes[walker->level - 1] = pte;
42bf3f0a
AK
260 }
261
fe135d2c
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262 walker->pt_access = pt_access;
263 walker->pte_access = pte_access;
264 pgprintk("%s: pte %llx pte_access %x pt_access %x\n",
518c5a05 265 __func__, (u64)pte, pte_access, pt_access);
7993ba43
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266 return 1;
267
f59c1d2d 268error:
7993ba43 269 walker->error_code = 0;
f59c1d2d
AK
270 if (present)
271 walker->error_code |= PFERR_PRESENT_MASK;
20bd40dc
XG
272
273 walker->error_code |= write_fault | user_fault;
274
2d48a985 275 if (fetch_fault && mmu->nx)
73b1087e 276 walker->error_code |= PFERR_FETCH_MASK;
82725b20
DE
277 if (rsvd_fault)
278 walker->error_code |= PFERR_RSVD_MASK;
8df25a32
JR
279
280 vcpu->arch.fault.address = addr;
281 vcpu->arch.fault.error_code = walker->error_code;
282
07420171 283 trace_kvm_mmu_walker_error(walker->error_code);
fe551881 284 return 0;
6aa8b732
AK
285}
286
1e301feb 287static int FNAME(walk_addr)(struct guest_walker *walker,
33770780 288 struct kvm_vcpu *vcpu, gva_t addr, u32 access)
1e301feb
JR
289{
290 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.mmu, addr,
33770780 291 access);
1e301feb
JR
292}
293
6539e738
JR
294static int FNAME(walk_addr_nested)(struct guest_walker *walker,
295 struct kvm_vcpu *vcpu, gva_t addr,
33770780 296 u32 access)
6539e738
JR
297{
298 return FNAME(walk_addr_generic)(walker, vcpu, &vcpu->arch.nested_mmu,
33770780 299 addr, access);
6539e738
JR
300}
301
407c61c6
XG
302static bool FNAME(prefetch_invalid_gpte)(struct kvm_vcpu *vcpu,
303 struct kvm_mmu_page *sp, u64 *spte,
304 pt_element_t gpte)
305{
306 u64 nonpresent = shadow_trap_nonpresent_pte;
307
308 if (is_rsvd_bits_set(&vcpu->arch.mmu, gpte, PT_PAGE_TABLE_LEVEL))
309 goto no_present;
310
311 if (!is_present_gpte(gpte)) {
312 if (!sp->unsync)
313 nonpresent = shadow_notrap_nonpresent_pte;
314 goto no_present;
315 }
316
317 if (!(gpte & PT_ACCESSED_MASK))
318 goto no_present;
319
320 return false;
321
322no_present:
323 drop_spte(vcpu->kvm, spte, nonpresent);
324 return true;
325}
326
ac3cd03c 327static void FNAME(update_pte)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
489f1d65 328 u64 *spte, const void *pte)
0028425f
AK
329{
330 pt_element_t gpte;
41074d07 331 unsigned pte_access;
35149e21 332 pfn_t pfn;
0028425f 333
0028425f 334 gpte = *(const pt_element_t *)pte;
407c61c6 335 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
c7addb90 336 return;
407c61c6 337
b8688d51 338 pgprintk("%s: gpte %llx spte %p\n", __func__, (u64)gpte, spte);
ac3cd03c 339 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
d7824fff
AK
340 if (gpte_to_gfn(gpte) != vcpu->arch.update_pte.gfn)
341 return;
35149e21
AL
342 pfn = vcpu->arch.update_pte.pfn;
343 if (is_error_pfn(pfn))
d7824fff 344 return;
e930bffe
AA
345 if (mmu_notifier_retry(vcpu, vcpu->arch.update_pte.mmu_seq))
346 return;
35149e21 347 kvm_get_pfn(pfn);
1403283a 348 /*
9bdbba13 349 * we call mmu_set_spte() with host_writable = true beacuse that
1403283a
IE
350 * vcpu->arch.update_pte.pfn was fetched from get_user_pages(write = 1).
351 */
ac3cd03c 352 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
cb83cad2 353 is_dirty_gpte(gpte), NULL, PT_PAGE_TABLE_LEVEL,
1403283a 354 gpte_to_gfn(gpte), pfn, true, true);
0028425f
AK
355}
356
39c8c672
AK
357static bool FNAME(gpte_changed)(struct kvm_vcpu *vcpu,
358 struct guest_walker *gw, int level)
359{
39c8c672 360 pt_element_t curr_pte;
189be38d
XG
361 gpa_t base_gpa, pte_gpa = gw->pte_gpa[level - 1];
362 u64 mask;
363 int r, index;
364
365 if (level == PT_PAGE_TABLE_LEVEL) {
366 mask = PTE_PREFETCH_NUM * sizeof(pt_element_t) - 1;
367 base_gpa = pte_gpa & ~mask;
368 index = (pte_gpa - base_gpa) / sizeof(pt_element_t);
369
370 r = kvm_read_guest_atomic(vcpu->kvm, base_gpa,
371 gw->prefetch_ptes, sizeof(gw->prefetch_ptes));
372 curr_pte = gw->prefetch_ptes[index];
373 } else
374 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa,
39c8c672 375 &curr_pte, sizeof(curr_pte));
189be38d 376
39c8c672
AK
377 return r || curr_pte != gw->ptes[level - 1];
378}
379
189be38d
XG
380static void FNAME(pte_prefetch)(struct kvm_vcpu *vcpu, struct guest_walker *gw,
381 u64 *sptep)
957ed9ef
XG
382{
383 struct kvm_mmu_page *sp;
189be38d 384 pt_element_t *gptep = gw->prefetch_ptes;
957ed9ef 385 u64 *spte;
189be38d 386 int i;
957ed9ef
XG
387
388 sp = page_header(__pa(sptep));
389
390 if (sp->role.level > PT_PAGE_TABLE_LEVEL)
391 return;
392
393 if (sp->role.direct)
394 return __direct_pte_prefetch(vcpu, sp, sptep);
395
396 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
957ed9ef
XG
397 spte = sp->spt + i;
398
399 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
400 pt_element_t gpte;
401 unsigned pte_access;
402 gfn_t gfn;
403 pfn_t pfn;
404 bool dirty;
405
406 if (spte == sptep)
407 continue;
408
409 if (*spte != shadow_trap_nonpresent_pte)
410 continue;
411
412 gpte = gptep[i];
413
407c61c6 414 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, spte, gpte))
957ed9ef
XG
415 continue;
416
417 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
418 gfn = gpte_to_gfn(gpte);
419 dirty = is_dirty_gpte(gpte);
420 pfn = pte_prefetch_gfn_to_pfn(vcpu, gfn,
421 (pte_access & ACC_WRITE_MASK) && dirty);
422 if (is_error_pfn(pfn)) {
423 kvm_release_pfn_clean(pfn);
424 break;
425 }
426
427 mmu_set_spte(vcpu, spte, sp->role.access, pte_access, 0, 0,
428 dirty, NULL, PT_PAGE_TABLE_LEVEL, gfn,
429 pfn, true, true);
430 }
431}
432
6aa8b732
AK
433/*
434 * Fetch a shadow pte for a specific level in the paging hierarchy.
435 */
e7a04c99
AK
436static u64 *FNAME(fetch)(struct kvm_vcpu *vcpu, gva_t addr,
437 struct guest_walker *gw,
7e4e4056 438 int user_fault, int write_fault, int hlevel,
612819c3 439 int *ptwrite, pfn_t pfn, bool map_writable)
6aa8b732 440{
abb9e0b8 441 unsigned access = gw->pt_access;
5991b332 442 struct kvm_mmu_page *sp = NULL;
84754cd8 443 bool dirty = is_dirty_gpte(gw->ptes[gw->level - 1]);
5991b332 444 int top_level;
84754cd8 445 unsigned direct_access;
24157aaf 446 struct kvm_shadow_walk_iterator it;
abb9e0b8 447
43a3795a 448 if (!is_present_gpte(gw->ptes[gw->level - 1]))
e7a04c99 449 return NULL;
6aa8b732 450
84754cd8
XG
451 direct_access = gw->pt_access & gw->pte_access;
452 if (!dirty)
453 direct_access &= ~ACC_WRITE_MASK;
454
5991b332
AK
455 top_level = vcpu->arch.mmu.root_level;
456 if (top_level == PT32E_ROOT_LEVEL)
457 top_level = PT32_ROOT_LEVEL;
458 /*
459 * Verify that the top-level gpte is still there. Since the page
460 * is a root page, it is either write protected (and cannot be
461 * changed from now on) or it is invalid (in which case, we don't
462 * really care if it changes underneath us after this point).
463 */
464 if (FNAME(gpte_changed)(vcpu, gw, top_level))
465 goto out_gpte_changed;
466
24157aaf
AK
467 for (shadow_walk_init(&it, vcpu, addr);
468 shadow_walk_okay(&it) && it.level > gw->level;
469 shadow_walk_next(&it)) {
0b3c9333
AK
470 gfn_t table_gfn;
471
24157aaf 472 drop_large_spte(vcpu, it.sptep);
ef0197e8 473
5991b332 474 sp = NULL;
24157aaf
AK
475 if (!is_shadow_present_pte(*it.sptep)) {
476 table_gfn = gw->table_gfn[it.level - 2];
477 sp = kvm_mmu_get_page(vcpu, table_gfn, addr, it.level-1,
478 false, access, it.sptep);
5991b332 479 }
0b3c9333
AK
480
481 /*
482 * Verify that the gpte in the page we've just write
483 * protected is still there.
484 */
24157aaf 485 if (FNAME(gpte_changed)(vcpu, gw, it.level - 1))
0b3c9333 486 goto out_gpte_changed;
abb9e0b8 487
5991b332 488 if (sp)
24157aaf 489 link_shadow_page(it.sptep, sp);
e7a04c99 490 }
050e6499 491
0b3c9333 492 for (;
24157aaf
AK
493 shadow_walk_okay(&it) && it.level > hlevel;
494 shadow_walk_next(&it)) {
0b3c9333
AK
495 gfn_t direct_gfn;
496
24157aaf 497 validate_direct_spte(vcpu, it.sptep, direct_access);
0b3c9333 498
24157aaf 499 drop_large_spte(vcpu, it.sptep);
0b3c9333 500
24157aaf 501 if (is_shadow_present_pte(*it.sptep))
0b3c9333
AK
502 continue;
503
24157aaf 504 direct_gfn = gw->gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
0b3c9333 505
24157aaf
AK
506 sp = kvm_mmu_get_page(vcpu, direct_gfn, addr, it.level-1,
507 true, direct_access, it.sptep);
508 link_shadow_page(it.sptep, sp);
0b3c9333
AK
509 }
510
24157aaf
AK
511 mmu_set_spte(vcpu, it.sptep, access, gw->pte_access & access,
512 user_fault, write_fault, dirty, ptwrite, it.level,
612819c3 513 gw->gfn, pfn, false, map_writable);
189be38d 514 FNAME(pte_prefetch)(vcpu, gw, it.sptep);
0b3c9333 515
24157aaf 516 return it.sptep;
0b3c9333
AK
517
518out_gpte_changed:
5991b332 519 if (sp)
24157aaf 520 kvm_mmu_put_page(sp, it.sptep);
0b3c9333
AK
521 kvm_release_pfn_clean(pfn);
522 return NULL;
6aa8b732
AK
523}
524
6aa8b732
AK
525/*
526 * Page fault handler. There are several causes for a page fault:
527 * - there is no shadow pte for the guest pte
528 * - write access through a shadow pte marked read only so that we can set
529 * the dirty bit
530 * - write access to a shadow pte marked read only so we can update the page
531 * dirty bitmap, when userspace requests it
532 * - mmio access; in this case we will never install a present shadow pte
533 * - normal guest page fault due to the guest pte marked not present, not
534 * writable, or not executable
535 *
e2dec939
AK
536 * Returns: 1 if we need to emulate the instruction, 0 otherwise, or
537 * a negative value on error.
6aa8b732 538 */
56028d08
GN
539static int FNAME(page_fault)(struct kvm_vcpu *vcpu, gva_t addr, u32 error_code,
540 bool no_apf)
6aa8b732
AK
541{
542 int write_fault = error_code & PFERR_WRITE_MASK;
6aa8b732
AK
543 int user_fault = error_code & PFERR_USER_MASK;
544 struct guest_walker walker;
d555c333 545 u64 *sptep;
cea0f0e7 546 int write_pt = 0;
e2dec939 547 int r;
35149e21 548 pfn_t pfn;
7e4e4056 549 int level = PT_PAGE_TABLE_LEVEL;
e930bffe 550 unsigned long mmu_seq;
612819c3 551 bool map_writable;
6aa8b732 552
b8688d51 553 pgprintk("%s: addr %lx err %x\n", __func__, addr, error_code);
714b93da 554
e2dec939
AK
555 r = mmu_topup_memory_caches(vcpu);
556 if (r)
557 return r;
714b93da 558
6aa8b732 559 /*
a8b876b1 560 * Look up the guest pte for the faulting address.
6aa8b732 561 */
33770780 562 r = FNAME(walk_addr)(&walker, vcpu, addr, error_code);
6aa8b732
AK
563
564 /*
565 * The page is not mapped by the guest. Let the guest handle it.
566 */
7993ba43 567 if (!r) {
b8688d51 568 pgprintk("%s: guest page fault\n", __func__);
8df25a32 569 inject_page_fault(vcpu);
ad312c7c 570 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
6aa8b732
AK
571 return 0;
572 }
573
7e4e4056
JR
574 if (walker.level >= PT_DIRECTORY_LEVEL) {
575 level = min(walker.level, mapping_level(vcpu, walker.gfn));
576 walker.gfn = walker.gfn & ~(KVM_PAGES_PER_HPAGE(level) - 1);
05da4558 577 }
7e4e4056 578
e930bffe 579 mmu_seq = vcpu->kvm->mmu_notifier_seq;
4c2155ce 580 smp_rmb();
af585b92 581
612819c3
MT
582 if (try_async_pf(vcpu, no_apf, walker.gfn, addr, &pfn, write_fault,
583 &map_writable))
af585b92 584 return 0;
d7824fff 585
d196e343 586 /* mmio */
bf998156
HY
587 if (is_error_pfn(pfn))
588 return kvm_handle_bad_page(vcpu->kvm, walker.gfn, pfn);
d196e343 589
612819c3
MT
590 if (!map_writable)
591 walker.pte_access &= ~ACC_WRITE_MASK;
592
aaee2c94 593 spin_lock(&vcpu->kvm->mmu_lock);
e930bffe
AA
594 if (mmu_notifier_retry(vcpu, mmu_seq))
595 goto out_unlock;
bc32ce21 596
8b1fe17c 597 trace_kvm_mmu_audit(vcpu, AUDIT_PRE_PAGE_FAULT);
eb787d10 598 kvm_mmu_free_some_pages(vcpu);
d555c333 599 sptep = FNAME(fetch)(vcpu, addr, &walker, user_fault, write_fault,
612819c3 600 level, &write_pt, pfn, map_writable);
a24e8099 601 (void)sptep;
b8688d51 602 pgprintk("%s: shadow pte %p %llx ptwrite %d\n", __func__,
d555c333 603 sptep, *sptep, write_pt);
cea0f0e7 604
a25f7e1f 605 if (!write_pt)
ad312c7c 606 vcpu->arch.last_pt_write_count = 0; /* reset fork detector */
a25f7e1f 607
1165f5fe 608 ++vcpu->stat.pf_fixed;
8b1fe17c 609 trace_kvm_mmu_audit(vcpu, AUDIT_POST_PAGE_FAULT);
aaee2c94 610 spin_unlock(&vcpu->kvm->mmu_lock);
6aa8b732 611
cea0f0e7 612 return write_pt;
e930bffe
AA
613
614out_unlock:
615 spin_unlock(&vcpu->kvm->mmu_lock);
616 kvm_release_pfn_clean(pfn);
617 return 0;
6aa8b732
AK
618}
619
a461930b 620static void FNAME(invlpg)(struct kvm_vcpu *vcpu, gva_t gva)
a7052897 621{
a461930b 622 struct kvm_shadow_walk_iterator iterator;
f78978aa 623 struct kvm_mmu_page *sp;
08e850c6 624 gpa_t pte_gpa = -1;
a461930b
AK
625 int level;
626 u64 *sptep;
4539b358 627 int need_flush = 0;
a461930b
AK
628
629 spin_lock(&vcpu->kvm->mmu_lock);
a7052897 630
a461930b
AK
631 for_each_shadow_entry(vcpu, gva, iterator) {
632 level = iterator.level;
633 sptep = iterator.sptep;
ad218f85 634
f78978aa 635 sp = page_header(__pa(sptep));
884a0ff0 636 if (is_last_spte(*sptep, level)) {
22c9b2d1 637 int offset, shift;
08e850c6 638
f78978aa
XG
639 if (!sp->unsync)
640 break;
641
22c9b2d1
XG
642 shift = PAGE_SHIFT -
643 (PT_LEVEL_BITS - PT64_LEVEL_BITS) * level;
644 offset = sp->role.quadrant << shift;
645
646 pte_gpa = (sp->gfn << PAGE_SHIFT) + offset;
08e850c6 647 pte_gpa += (sptep - sp->spt) * sizeof(pt_element_t);
a461930b
AK
648
649 if (is_shadow_present_pte(*sptep)) {
a461930b
AK
650 if (is_large_pte(*sptep))
651 --vcpu->kvm->stat.lpages;
be38d276
AK
652 drop_spte(vcpu->kvm, sptep,
653 shadow_trap_nonpresent_pte);
4539b358 654 need_flush = 1;
be38d276
AK
655 } else
656 __set_spte(sptep, shadow_trap_nonpresent_pte);
a461930b 657 break;
87917239 658 }
a7052897 659
f78978aa 660 if (!is_shadow_present_pte(*sptep) || !sp->unsync_children)
a461930b
AK
661 break;
662 }
a7052897 663
4539b358
AA
664 if (need_flush)
665 kvm_flush_remote_tlbs(vcpu->kvm);
08e850c6
AK
666
667 atomic_inc(&vcpu->kvm->arch.invlpg_counter);
668
ad218f85 669 spin_unlock(&vcpu->kvm->mmu_lock);
08e850c6
AK
670
671 if (pte_gpa == -1)
672 return;
673
674 if (mmu_topup_memory_caches(vcpu))
675 return;
676 kvm_mmu_pte_write(vcpu, pte_gpa, NULL, sizeof(pt_element_t), 0);
a7052897
MT
677}
678
1871c602
GN
679static gpa_t FNAME(gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t vaddr, u32 access,
680 u32 *error)
6aa8b732
AK
681{
682 struct guest_walker walker;
e119d117
AK
683 gpa_t gpa = UNMAPPED_GVA;
684 int r;
6aa8b732 685
33770780 686 r = FNAME(walk_addr)(&walker, vcpu, vaddr, access);
6aa8b732 687
e119d117 688 if (r) {
1755fbcc 689 gpa = gfn_to_gpa(walker.gfn);
e119d117 690 gpa |= vaddr & ~PAGE_MASK;
1871c602
GN
691 } else if (error)
692 *error = walker.error_code;
6aa8b732
AK
693
694 return gpa;
695}
696
6539e738
JR
697static gpa_t FNAME(gva_to_gpa_nested)(struct kvm_vcpu *vcpu, gva_t vaddr,
698 u32 access, u32 *error)
699{
700 struct guest_walker walker;
701 gpa_t gpa = UNMAPPED_GVA;
702 int r;
703
33770780 704 r = FNAME(walk_addr_nested)(&walker, vcpu, vaddr, access);
6539e738
JR
705
706 if (r) {
707 gpa = gfn_to_gpa(walker.gfn);
708 gpa |= vaddr & ~PAGE_MASK;
709 } else if (error)
710 *error = walker.error_code;
711
712 return gpa;
713}
714
c7addb90
AK
715static void FNAME(prefetch_page)(struct kvm_vcpu *vcpu,
716 struct kvm_mmu_page *sp)
717{
eab9f71f
AK
718 int i, j, offset, r;
719 pt_element_t pt[256 / sizeof(pt_element_t)];
720 gpa_t pte_gpa;
c7addb90 721
f6e2c02b 722 if (sp->role.direct
e5a4c8ca 723 || (PTTYPE == 32 && sp->role.level > PT_PAGE_TABLE_LEVEL)) {
c7addb90
AK
724 nonpaging_prefetch_page(vcpu, sp);
725 return;
726 }
727
eab9f71f
AK
728 pte_gpa = gfn_to_gpa(sp->gfn);
729 if (PTTYPE == 32) {
e5a4c8ca 730 offset = sp->role.quadrant << PT64_LEVEL_BITS;
eab9f71f
AK
731 pte_gpa += offset * sizeof(pt_element_t);
732 }
7ec54588 733
eab9f71f
AK
734 for (i = 0; i < PT64_ENT_PER_PAGE; i += ARRAY_SIZE(pt)) {
735 r = kvm_read_guest_atomic(vcpu->kvm, pte_gpa, pt, sizeof pt);
736 pte_gpa += ARRAY_SIZE(pt) * sizeof(pt_element_t);
737 for (j = 0; j < ARRAY_SIZE(pt); ++j)
43a3795a 738 if (r || is_present_gpte(pt[j]))
eab9f71f
AK
739 sp->spt[i+j] = shadow_trap_nonpresent_pte;
740 else
741 sp->spt[i+j] = shadow_notrap_nonpresent_pte;
7ec54588 742 }
c7addb90
AK
743}
744
e8bc217a
MT
745/*
746 * Using the cached information from sp->gfns is safe because:
747 * - The spte has a reference to the struct page, so the pfn for a given gfn
748 * can't change unless all sptes pointing to it are nuked first.
a4ee1ca4
XG
749 *
750 * Note:
751 * We should flush all tlbs if spte is dropped even though guest is
752 * responsible for it. Since if we don't, kvm_mmu_notifier_invalidate_page
753 * and kvm_mmu_notifier_invalidate_range_start detect the mapping page isn't
754 * used by guest then tlbs are not flushed, so guest is allowed to access the
755 * freed pages.
756 * And we increase kvm->tlbs_dirty to delay tlbs flush in this case.
e8bc217a 757 */
a4a8e6f7 758static int FNAME(sync_page)(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
e8bc217a
MT
759{
760 int i, offset, nr_present;
9bdbba13 761 bool host_writable;
51fb60d8 762 gpa_t first_pte_gpa;
e8bc217a
MT
763
764 offset = nr_present = 0;
765
2032a93d
LJ
766 /* direct kvm_mmu_page can not be unsync. */
767 BUG_ON(sp->role.direct);
768
e8bc217a
MT
769 if (PTTYPE == 32)
770 offset = sp->role.quadrant << PT64_LEVEL_BITS;
771
51fb60d8
GJ
772 first_pte_gpa = gfn_to_gpa(sp->gfn) + offset * sizeof(pt_element_t);
773
e8bc217a
MT
774 for (i = 0; i < PT64_ENT_PER_PAGE; i++) {
775 unsigned pte_access;
776 pt_element_t gpte;
777 gpa_t pte_gpa;
f55c3f41 778 gfn_t gfn;
e8bc217a
MT
779
780 if (!is_shadow_present_pte(sp->spt[i]))
781 continue;
782
51fb60d8 783 pte_gpa = first_pte_gpa + i * sizeof(pt_element_t);
e8bc217a
MT
784
785 if (kvm_read_guest_atomic(vcpu->kvm, pte_gpa, &gpte,
786 sizeof(pt_element_t)))
787 return -EINVAL;
788
f55c3f41 789 gfn = gpte_to_gfn(gpte);
407c61c6
XG
790
791 if (FNAME(prefetch_invalid_gpte)(vcpu, sp, &sp->spt[i], gpte)) {
a4ee1ca4 792 vcpu->kvm->tlbs_dirty++;
407c61c6
XG
793 continue;
794 }
795
796 if (gfn != sp->gfns[i]) {
797 drop_spte(vcpu->kvm, &sp->spt[i],
798 shadow_trap_nonpresent_pte);
a4ee1ca4 799 vcpu->kvm->tlbs_dirty++;
e8bc217a
MT
800 continue;
801 }
802
803 nr_present++;
804 pte_access = sp->role.access & FNAME(gpte_access)(vcpu, gpte);
1403283a
IE
805 if (!(sp->spt[i] & SPTE_HOST_WRITEABLE)) {
806 pte_access &= ~ACC_WRITE_MASK;
9bdbba13 807 host_writable = 0;
1403283a 808 } else {
9bdbba13 809 host_writable = 1;
1403283a 810 }
e8bc217a 811 set_spte(vcpu, &sp->spt[i], pte_access, 0, 0,
7e4e4056 812 is_dirty_gpte(gpte), PT_PAGE_TABLE_LEVEL, gfn,
1403283a 813 spte_to_pfn(sp->spt[i]), true, false,
9bdbba13 814 host_writable);
e8bc217a
MT
815 }
816
817 return !nr_present;
818}
819
6aa8b732
AK
820#undef pt_element_t
821#undef guest_walker
822#undef FNAME
823#undef PT_BASE_ADDR_MASK
824#undef PT_INDEX
6aa8b732 825#undef PT_LEVEL_MASK
e04da980
JR
826#undef PT_LVL_ADDR_MASK
827#undef PT_LVL_OFFSET_MASK
c7addb90 828#undef PT_LEVEL_BITS
cea0f0e7 829#undef PT_MAX_FULL_LEVELS
5fb07ddb 830#undef gpte_to_gfn
e04da980 831#undef gpte_to_gfn_lvl
b3e4e63f 832#undef CMPXCHG