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KVM: VMX: Remove duplicated include from vmx.c
[thirdparty/kernel/stable.git] / arch / x86 / kvm / vmx / vmx.c
CommitLineData
6aa8b732
AK		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * This module enables machines with Intel VT-x extensions to run virtual
5 * machines without emulation or binary translation.
6 *
7 * Copyright (C) 2006 Qumranet, Inc.
9611c187 8 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
6aa8b732
AK		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
13 *
14 * This work is licensed under the terms of the GNU GPL, version 2. See
15 * the COPYING file in the top-level directory.
16 *
17 */
18
199b118a
SC		 19#include <linux/frame.h>
20#include <linux/highmem.h>
21#include <linux/hrtimer.h>
22#include <linux/kernel.h>
edf88417 23#include <linux/kvm_host.h>
6aa8b732 24#include <linux/module.h>
c7addb90 25#include <linux/moduleparam.h>
e9bda3b3 26#include <linux/mod_devicetable.h>
199b118a 27#include <linux/mm.h>
199b118a 28#include <linux/sched.h>
5a0e3ad6 29#include <linux/slab.h>
cafd6659 30#include <linux/tboot.h>
199b118a 31#include <linux/trace_events.h>
e495606d 32
199b118a 33#include <asm/apic.h>
fd8ca6da 34#include <asm/asm.h>
28b835d6 35#include <asm/cpu.h>
199b118a 36#include <asm/debugreg.h>
3b3be0d1 37#include <asm/desc.h>
952f07ec 38#include <asm/fpu/internal.h>
199b118a 39#include <asm/io.h>
efc64404 40#include <asm/irq_remapping.h>
199b118a
SC		 41#include <asm/kexec.h>
42#include <asm/perf_event.h>
43#include <asm/mce.h>
d6e41f11 44#include <asm/mmu_context.h>
773e8a04 45#include <asm/mshyperv.h>
199b118a
SC		 46#include <asm/spec-ctrl.h>
47#include <asm/virtext.h>
48#include <asm/vmx.h>
6aa8b732 49
3077c191 50#include "capabilities.h"
199b118a 51#include "cpuid.h"
4cebd747 52#include "evmcs.h"
199b118a
SC		 53#include "irq.h"
54#include "kvm_cache_regs.h"
55#include "lapic.h"
56#include "mmu.h"
55d2375e 57#include "nested.h"
89b0c9f5 58#include "ops.h"
25462f7f 59#include "pmu.h"
199b118a 60#include "trace.h"
cb1d474b 61#include "vmcs.h"
609363cf 62#include "vmcs12.h"
89b0c9f5 63#include "vmx.h"
199b118a 64#include "x86.h"
229456fc 65
6aa8b732
AK		 66MODULE_AUTHOR("Qumranet");
67MODULE_LICENSE("GPL");
68
e9bda3b3
JT		 69static const struct x86_cpu_id vmx_cpu_id[] = {
70 X86_FEATURE_MATCH(X86_FEATURE_VMX),
71 {}
72};
73MODULE_DEVICE_TABLE(x86cpu, vmx_cpu_id);
74
2c4fd91d 75bool __read_mostly enable_vpid = 1;
736caefe 76module_param_named(vpid, enable_vpid, bool, 0444);
2384d2b3 77
d02fcf50
PB		 78static bool __read_mostly enable_vnmi = 1;
79module_param_named(vnmi, enable_vnmi, bool, S_IRUGO);
80
2c4fd91d 81bool __read_mostly flexpriority_enabled = 1;
736caefe 82module_param_named(flexpriority, flexpriority_enabled, bool, S_IRUGO);
4c9fc8ef 83
2c4fd91d 84bool __read_mostly enable_ept = 1;
736caefe 85module_param_named(ept, enable_ept, bool, S_IRUGO);
d56f546d 86
2c4fd91d 87bool __read_mostly enable_unrestricted_guest = 1;
3a624e29
NK		 88module_param_named(unrestricted_guest,
89 enable_unrestricted_guest, bool, S_IRUGO);
90
2c4fd91d 91bool __read_mostly enable_ept_ad_bits = 1;
83c3a331
XH		 92module_param_named(eptad, enable_ept_ad_bits, bool, S_IRUGO);
93
a27685c3 94static bool __read_mostly emulate_invalid_guest_state = true;
c1f8bc04 95module_param(emulate_invalid_guest_state, bool, S_IRUGO);
04fa4d32 96
476bc001 97static bool __read_mostly fasteoi = 1;
58fbbf26
KT		 98module_param(fasteoi, bool, S_IRUGO);
99
5a71785d 100static bool __read_mostly enable_apicv = 1;
01e439be 101module_param(enable_apicv, bool, S_IRUGO);
83d4c286 102
801d3424
NHE		 103/*
104 * If nested=1, nested virtualization is supported, i.e., guests may use
105 * VMX and be a hypervisor for its own guests. If nested=0, guests may not
106 * use VMX instructions.
107 */
1e58e5e5 108static bool __read_mostly nested = 1;
801d3424
NHE		 109module_param(nested, bool, S_IRUGO);
110
20300099
WL		 111static u64 __read_mostly host_xss;
112
2c4fd91d 113bool __read_mostly enable_pml = 1;
843e4330
KH		 114module_param_named(pml, enable_pml, bool, S_IRUGO);
115
904e14fb
PB		 116#define MSR_BITMAP_MODE_X2APIC 1
117#define MSR_BITMAP_MODE_X2APIC_APICV 2
904e14fb 118
64903d61
HZ		 119#define KVM_VMX_TSC_MULTIPLIER_MAX 0xffffffffffffffffULL
120
64672c95
YJ		 121/* Guest_tsc -> host_tsc conversion requires 64-bit division. */
122static int __read_mostly cpu_preemption_timer_multi;
123static bool __read_mostly enable_preemption_timer = 1;
124#ifdef CONFIG_X86_64
125module_param_named(preemption_timer, enable_preemption_timer, bool, S_IRUGO);
126#endif
127
3de6347b 128#define KVM_VM_CR0_ALWAYS_OFF (X86_CR0_NW | X86_CR0_CD)
1706bd0c
SC		 129#define KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR0_NE
130#define KVM_VM_CR0_ALWAYS_ON \
131 (KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST | \
132 X86_CR0_WP | X86_CR0_PG | X86_CR0_PE)
4c38609a
AK		 133#define KVM_CR4_GUEST_OWNED_BITS \
134 (X86_CR4_PVI | X86_CR4_DE | X86_CR4_PCE | X86_CR4_OSFXSR \
fd8cb433 135 | X86_CR4_OSXMMEXCPT | X86_CR4_LA57 | X86_CR4_TSD)
4c38609a 136
5dc1f044 137#define KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST X86_CR4_VMXE
cdc0e244
AK		 138#define KVM_PMODE_VM_CR4_ALWAYS_ON (X86_CR4_PAE | X86_CR4_VMXE)
139#define KVM_RMODE_VM_CR4_ALWAYS_ON (X86_CR4_VME | X86_CR4_PAE | X86_CR4_VMXE)
140
78ac8b47
AK		 141#define RMODE_GUEST_OWNED_EFLAGS_BITS (~(X86_EFLAGS_IOPL | X86_EFLAGS_VM))
142
4b8d54f9
ZE		 143/*
144 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
145 * ple_gap: upper bound on the amount of time between two successive
146 * executions of PAUSE in a loop. Also indicate if ple enabled.
00c25bce 147 * According to test, this time is usually smaller than 128 cycles.
4b8d54f9
ZE		 148 * ple_window: upper bound on the amount of time a guest is allowed to execute
149 * in a PAUSE loop. Tests indicate that most spinlocks are held for
150 * less than 2^12 cycles
151 * Time is measured based on a counter that runs at the same rate as the TSC,
152 * refer SDM volume 3b section 21.6.13 & 22.1.3.
153 */
c8e88717 154static unsigned int ple_gap = KVM_DEFAULT_PLE_GAP;
a87c99e6 155module_param(ple_gap, uint, 0444);
b4a2d31d 156
7fbc85a5
BM		 157static unsigned int ple_window = KVM_VMX_DEFAULT_PLE_WINDOW;
158module_param(ple_window, uint, 0444);
4b8d54f9 159
b4a2d31d 160/* Default doubles per-vcpu window every exit. */
c8e88717 161static unsigned int ple_window_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
7fbc85a5 162module_param(ple_window_grow, uint, 0444);
b4a2d31d
RK		 163
164/* Default resets per-vcpu window every exit to ple_window. */
c8e88717 165static unsigned int ple_window_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
7fbc85a5 166module_param(ple_window_shrink, uint, 0444);
b4a2d31d
RK		 167
168/* Default is to compute the maximum so we can never overflow. */
7fbc85a5
BM		 169static unsigned int ple_window_max = KVM_VMX_DEFAULT_PLE_WINDOW_MAX;
170module_param(ple_window_max, uint, 0444);
b4a2d31d 171
a399477e 172static DEFINE_STATIC_KEY_FALSE(vmx_l1d_should_flush);
427362a1 173static DEFINE_STATIC_KEY_FALSE(vmx_l1d_flush_cond);
dd4bfa73 174static DEFINE_MUTEX(vmx_l1d_flush_mutex);
a399477e 175
7db92e16
TG		 176/* Storage for pre module init parameter parsing */
177static enum vmx_l1d_flush_state __read_mostly vmentry_l1d_flush_param = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 178
179static const struct {
180 const char *option;
0027ff2a 181 bool for_parse;
a399477e 182} vmentry_l1d_param[] = {
0027ff2a
PB		 183 [VMENTER_L1D_FLUSH_AUTO] = {"auto", true},
184 [VMENTER_L1D_FLUSH_NEVER] = {"never", true},
185 [VMENTER_L1D_FLUSH_COND] = {"cond", true},
186 [VMENTER_L1D_FLUSH_ALWAYS] = {"always", true},
187 [VMENTER_L1D_FLUSH_EPT_DISABLED] = {"EPT disabled", false},
188 [VMENTER_L1D_FLUSH_NOT_REQUIRED] = {"not required", false},
a399477e
KRW		 189};
190
7db92e16
TG		 191#define L1D_CACHE_ORDER 4
192static void *vmx_l1d_flush_pages;
193
194static int vmx_setup_l1d_flush(enum vmx_l1d_flush_state l1tf)
a399477e 195{
7db92e16 196 struct page *page;
288d152c 197 unsigned int i;
a399477e 198
7db92e16
TG		 199 if (!enable_ept) {
200 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_EPT_DISABLED;
201 return 0;
a399477e
KRW		 202 }
203
d806afa4
YW		 204 if (boot_cpu_has(X86_FEATURE_ARCH_CAPABILITIES)) {
205 u64 msr;
206
207 rdmsrl(MSR_IA32_ARCH_CAPABILITIES, msr);
208 if (msr & ARCH_CAP_SKIP_VMENTRY_L1DFLUSH) {
209 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_NOT_REQUIRED;
210 return 0;
211 }
212 }
8e0b2b91 213
d90a7a0e
JK		 214 /* If set to auto use the default l1tf mitigation method */
215 if (l1tf == VMENTER_L1D_FLUSH_AUTO) {
216 switch (l1tf_mitigation) {
217 case L1TF_MITIGATION_OFF:
218 l1tf = VMENTER_L1D_FLUSH_NEVER;
219 break;
220 case L1TF_MITIGATION_FLUSH_NOWARN:
221 case L1TF_MITIGATION_FLUSH:
222 case L1TF_MITIGATION_FLUSH_NOSMT:
223 l1tf = VMENTER_L1D_FLUSH_COND;
224 break;
225 case L1TF_MITIGATION_FULL:
226 case L1TF_MITIGATION_FULL_FORCE:
227 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
228 break;
229 }
230 } else if (l1tf_mitigation == L1TF_MITIGATION_FULL_FORCE) {
231 l1tf = VMENTER_L1D_FLUSH_ALWAYS;
232 }
233
7db92e16
TG		 234 if (l1tf != VMENTER_L1D_FLUSH_NEVER && !vmx_l1d_flush_pages &&
235 !boot_cpu_has(X86_FEATURE_FLUSH_L1D)) {
236 page = alloc_pages(GFP_KERNEL, L1D_CACHE_ORDER);
237 if (!page)
238 return -ENOMEM;
239 vmx_l1d_flush_pages = page_address(page);
288d152c
NS		 240
241 /*
242 * Initialize each page with a different pattern in
243 * order to protect against KSM in the nested
244 * virtualization case.
245 */
246 for (i = 0; i < 1u << L1D_CACHE_ORDER; ++i) {
247 memset(vmx_l1d_flush_pages + i * PAGE_SIZE, i + 1,
248 PAGE_SIZE);
249 }
7db92e16
TG		 250 }
251
252 l1tf_vmx_mitigation = l1tf;
253
895ae47f
TG		 254 if (l1tf != VMENTER_L1D_FLUSH_NEVER)
255 static_branch_enable(&vmx_l1d_should_flush);
256 else
257 static_branch_disable(&vmx_l1d_should_flush);
4c6523ec 258
427362a1
NS		 259 if (l1tf == VMENTER_L1D_FLUSH_COND)
260 static_branch_enable(&vmx_l1d_flush_cond);
895ae47f 261 else
427362a1 262 static_branch_disable(&vmx_l1d_flush_cond);
7db92e16
TG		 263 return 0;
264}
265
266static int vmentry_l1d_flush_parse(const char *s)
267{
268 unsigned int i;
269
270 if (s) {
271 for (i = 0; i < ARRAY_SIZE(vmentry_l1d_param); i++) {
0027ff2a
PB		 272 if (vmentry_l1d_param[i].for_parse &&
273 sysfs_streq(s, vmentry_l1d_param[i].option))
274 return i;
7db92e16
TG		 275 }
276 }
a399477e
KRW		 277 return -EINVAL;
278}
279
7db92e16
TG		 280static int vmentry_l1d_flush_set(const char *s, const struct kernel_param *kp)
281{
dd4bfa73 282 int l1tf, ret;
7db92e16 283
7db92e16
TG		 284 l1tf = vmentry_l1d_flush_parse(s);
285 if (l1tf < 0)
286 return l1tf;
287
0027ff2a
PB		 288 if (!boot_cpu_has(X86_BUG_L1TF))
289 return 0;
290
7db92e16
TG		 291 /*
292 * Has vmx_init() run already? If not then this is the pre init
293 * parameter parsing. In that case just store the value and let
294 * vmx_init() do the proper setup after enable_ept has been
295 * established.
296 */
297 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_AUTO) {
298 vmentry_l1d_flush_param = l1tf;
299 return 0;
300 }
301
dd4bfa73
TG		 302 mutex_lock(&vmx_l1d_flush_mutex);
303 ret = vmx_setup_l1d_flush(l1tf);
304 mutex_unlock(&vmx_l1d_flush_mutex);
305 return ret;
7db92e16
TG		 306}
307
a399477e
KRW		 308static int vmentry_l1d_flush_get(char *s, const struct kernel_param *kp)
309{
0027ff2a
PB		 310 if (WARN_ON_ONCE(l1tf_vmx_mitigation >= ARRAY_SIZE(vmentry_l1d_param)))
311 return sprintf(s, "???\n");
312
7db92e16 313 return sprintf(s, "%s\n", vmentry_l1d_param[l1tf_vmx_mitigation].option);
a399477e
KRW		 314}
315
316static const struct kernel_param_ops vmentry_l1d_flush_ops = {
317 .set = vmentry_l1d_flush_set,
318 .get = vmentry_l1d_flush_get,
319};
895ae47f 320module_param_cb(vmentry_l1d_flush, &vmentry_l1d_flush_ops, NULL, 0644);
a399477e 321
d99e4152
GN		 322static bool guest_state_valid(struct kvm_vcpu *vcpu);
323static u32 vmx_segment_access_rights(struct kvm_segment *var);
1e4329ee 324static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
15d45071 325 u32 msr, int type);
75880a01 326
6aa8b732 327static DEFINE_PER_CPU(struct vmcs *, vmxarea);
75edce8a 328DEFINE_PER_CPU(struct vmcs *, current_vmcs);
d462b819
NHE		 329/*
330 * We maintain a per-CPU linked-list of VMCS loaded on that CPU. This is needed
331 * when a CPU is brought down, and we need to VMCLEAR all VMCSs loaded on it.
332 */
333static DEFINE_PER_CPU(struct list_head, loaded_vmcss_on_cpu);
6aa8b732 334
bf9f6ac8
FW		 335/*
336 * We maintian a per-CPU linked-list of vCPU, so in wakeup_handler() we
337 * can find which vCPU should be waken up.
338 */
339static DEFINE_PER_CPU(struct list_head, blocked_vcpu_on_cpu);
340static DEFINE_PER_CPU(spinlock_t, blocked_vcpu_on_cpu_lock);
341
2384d2b3
SY		 342static DECLARE_BITMAP(vmx_vpid_bitmap, VMX_NR_VPIDS);
343static DEFINE_SPINLOCK(vmx_vpid_lock);
344
3077c191
SC		 345struct vmcs_config vmcs_config;
346struct vmx_capability vmx_capability;
d56f546d 347
6aa8b732
AK		 348#define VMX_SEGMENT_FIELD(seg) \
349 [VCPU_SREG_##seg] = { \
350 .selector = GUEST_##seg##_SELECTOR, \
351 .base = GUEST_##seg##_BASE, \
352 .limit = GUEST_##seg##_LIMIT, \
353 .ar_bytes = GUEST_##seg##_AR_BYTES, \
354 }
355
772e0318 356static const struct kvm_vmx_segment_field {
6aa8b732
AK		 357 unsigned selector;
358 unsigned base;
359 unsigned limit;
360 unsigned ar_bytes;
361} kvm_vmx_segment_fields[] = {
362 VMX_SEGMENT_FIELD(CS),
363 VMX_SEGMENT_FIELD(DS),
364 VMX_SEGMENT_FIELD(ES),
365 VMX_SEGMENT_FIELD(FS),
366 VMX_SEGMENT_FIELD(GS),
367 VMX_SEGMENT_FIELD(SS),
368 VMX_SEGMENT_FIELD(TR),
369 VMX_SEGMENT_FIELD(LDTR),
370};
371
cf3646eb 372u64 host_efer;
26bb0981 373
4d56c8a7 374/*
898a811f
JM		 375 * Though SYSCALL is only supported in 64-bit mode on Intel CPUs, kvm
376 * will emulate SYSCALL in legacy mode if the vendor string in guest
377 * CPUID.0:{EBX,ECX,EDX} is "AuthenticAMD" or "AMDisbetter!" To
378 * support this emulation, IA32_STAR must always be included in
379 * vmx_msr_index[], even in i386 builds.
4d56c8a7 380 */
cf3646eb 381const u32 vmx_msr_index[] = {
05b3e0c2 382#ifdef CONFIG_X86_64
44ea2b17 383 MSR_SYSCALL_MASK, MSR_LSTAR, MSR_CSTAR,
6aa8b732 384#endif
8c06585d 385 MSR_EFER, MSR_TSC_AUX, MSR_STAR,
6aa8b732 386};
6aa8b732 387
773e8a04
VK		 388#if IS_ENABLED(CONFIG_HYPERV)
389static bool __read_mostly enlightened_vmcs = true;
390module_param(enlightened_vmcs, bool, 0444);
391
877ad952
TL		 392/* check_ept_pointer() should be under protection of ept_pointer_lock. */
393static void check_ept_pointer_match(struct kvm *kvm)
394{
395 struct kvm_vcpu *vcpu;
396 u64 tmp_eptp = INVALID_PAGE;
397 int i;
398
399 kvm_for_each_vcpu(i, vcpu, kvm) {
400 if (!VALID_PAGE(tmp_eptp)) {
401 tmp_eptp = to_vmx(vcpu)->ept_pointer;
402 } else if (tmp_eptp != to_vmx(vcpu)->ept_pointer) {
403 to_kvm_vmx(kvm)->ept_pointers_match
404 = EPT_POINTERS_MISMATCH;
405 return;
406 }
407 }
408
409 to_kvm_vmx(kvm)->ept_pointers_match = EPT_POINTERS_MATCH;
410}
411
412static int vmx_hv_remote_flush_tlb(struct kvm *kvm)
413{
a5c214da
LT		 414 struct kvm_vcpu *vcpu;
415 int ret = -ENOTSUPP, i;
877ad952
TL		 416
417 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
418
419 if (to_kvm_vmx(kvm)->ept_pointers_match == EPT_POINTERS_CHECK)
420 check_ept_pointer_match(kvm);
421
5f8bb004
VK		 422 /*
423 * FLUSH_GUEST_PHYSICAL_ADDRESS_SPACE hypercall needs the address of the
424 * base of EPT PML4 table, strip off EPT configuration information.
53963a70 425 * If ept_pointer is invalid pointer, bypass the flush request.
5f8bb004 426 */
877ad952 427 if (to_kvm_vmx(kvm)->ept_pointers_match != EPT_POINTERS_MATCH) {
53963a70
LT		 428 kvm_for_each_vcpu(i, vcpu, kvm) {
429 u64 ept_pointer = to_vmx(vcpu)->ept_pointer;
430
431 if (!VALID_PAGE(ept_pointer))
432 continue;
433
a5c214da 434 ret |= hyperv_flush_guest_mapping(
53963a70
LT		 435 ept_pointer & PAGE_MASK);
436 }
a5c214da
LT		 437 } else {
438 ret = hyperv_flush_guest_mapping(
0d1e8b8d 439 to_vmx(kvm_get_vcpu(kvm, 0))->ept_pointer & PAGE_MASK);
877ad952 440 }
877ad952 441
877ad952
TL		 442 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
443 return ret;
444}
773e8a04
VK		 445#endif /* IS_ENABLED(CONFIG_HYPERV) */
446
64672c95
YJ		 447/*
448 * Comment's format: document - errata name - stepping - processor name.
449 * Refer from
450 * https://www.virtualbox.org/svn/vbox/trunk/src/VBox/VMM/VMMR0/HMR0.cpp
451 */
452static u32 vmx_preemption_cpu_tfms[] = {
453/* 323344.pdf - BA86 - D0 - Xeon 7500 Series */
4540x000206E6,
455/* 323056.pdf - AAX65 - C2 - Xeon L3406 */
456/* 322814.pdf - AAT59 - C2 - i7-600, i5-500, i5-400 and i3-300 Mobile */
457/* 322911.pdf - AAU65 - C2 - i5-600, i3-500 Desktop and Pentium G6950 */
4580x00020652,
459/* 322911.pdf - AAU65 - K0 - i5-600, i3-500 Desktop and Pentium G6950 */
4600x00020655,
461/* 322373.pdf - AAO95 - B1 - Xeon 3400 Series */
462/* 322166.pdf - AAN92 - B1 - i7-800 and i5-700 Desktop */
463/*
464 * 320767.pdf - AAP86 - B1 -
465 * i7-900 Mobile Extreme, i7-800 and i7-700 Mobile
466 */
4670x000106E5,
468/* 321333.pdf - AAM126 - C0 - Xeon 3500 */
4690x000106A0,
470/* 321333.pdf - AAM126 - C1 - Xeon 3500 */
4710x000106A1,
472/* 320836.pdf - AAJ124 - C0 - i7-900 Desktop Extreme and i7-900 Desktop */
4730x000106A4,
474 /* 321333.pdf - AAM126 - D0 - Xeon 3500 */
475 /* 321324.pdf - AAK139 - D0 - Xeon 5500 */
476 /* 320836.pdf - AAJ124 - D0 - i7-900 Extreme and i7-900 Desktop */
4770x000106A5,
3d82c565
WH		 478 /* Xeon E3-1220 V2 */
4790x000306A8,
64672c95
YJ		 480};
481
482static inline bool cpu_has_broken_vmx_preemption_timer(void)
483{
484 u32 eax = cpuid_eax(0x00000001), i;
485
486 /* Clear the reserved bits */
487 eax &= ~(0x3U << 14 | 0xfU << 28);
03f6a22a 488 for (i = 0; i < ARRAY_SIZE(vmx_preemption_cpu_tfms); i++)
64672c95
YJ		 489 if (eax == vmx_preemption_cpu_tfms[i])
490 return true;
491
492 return false;
493}
494
35754c98 495static inline bool cpu_need_virtualize_apic_accesses(struct kvm_vcpu *vcpu)
f78e0e2e 496{
35754c98 497 return flexpriority_enabled && lapic_in_kernel(vcpu);
f78e0e2e
SY		 498}
499
04547156
SY		 500static inline bool report_flexpriority(void)
501{
502 return flexpriority_enabled;
503}
504
97b7ead3 505static inline int __find_msr_index(struct vcpu_vmx *vmx, u32 msr)
7725f0ba
AK		 506{
507 int i;
508
a2fa3e9f 509 for (i = 0; i < vmx->nmsrs; ++i)
26bb0981 510 if (vmx_msr_index[vmx->guest_msrs[i].index] == msr)
a75beee6
ED		 511 return i;
512 return -1;
513}
514
97b7ead3 515struct shared_msr_entry *find_msr_entry(struct vcpu_vmx *vmx, u32 msr)
a75beee6
ED		 516{
517 int i;
518
8b9cf98c 519 i = __find_msr_index(vmx, msr);
a75beee6 520 if (i >= 0)
a2fa3e9f 521 return &vmx->guest_msrs[i];
8b6d44c7 522 return NULL;
7725f0ba
AK		 523}
524
7c97fcb3
SC		 525void loaded_vmcs_init(struct loaded_vmcs *loaded_vmcs)
526{
527 vmcs_clear(loaded_vmcs->vmcs);
528 if (loaded_vmcs->shadow_vmcs && loaded_vmcs->launched)
529 vmcs_clear(loaded_vmcs->shadow_vmcs);
530 loaded_vmcs->cpu = -1;
531 loaded_vmcs->launched = 0;
532}
533
2965faa5 534#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 535/*
536 * This bitmap is used to indicate whether the vmclear
537 * operation is enabled on all cpus. All disabled by
538 * default.
539 */
540static cpumask_t crash_vmclear_enabled_bitmap = CPU_MASK_NONE;
541
542static inline void crash_enable_local_vmclear(int cpu)
543{
544 cpumask_set_cpu(cpu, &crash_vmclear_enabled_bitmap);
545}
546
547static inline void crash_disable_local_vmclear(int cpu)
548{
549 cpumask_clear_cpu(cpu, &crash_vmclear_enabled_bitmap);
550}
551
552static inline int crash_local_vmclear_enabled(int cpu)
553{
554 return cpumask_test_cpu(cpu, &crash_vmclear_enabled_bitmap);
555}
556
557static void crash_vmclear_local_loaded_vmcss(void)
558{
559 int cpu = raw_smp_processor_id();
560 struct loaded_vmcs *v;
561
562 if (!crash_local_vmclear_enabled(cpu))
563 return;
564
565 list_for_each_entry(v, &per_cpu(loaded_vmcss_on_cpu, cpu),
566 loaded_vmcss_on_cpu_link)
567 vmcs_clear(v->vmcs);
568}
569#else
570static inline void crash_enable_local_vmclear(int cpu) { }
571static inline void crash_disable_local_vmclear(int cpu) { }
2965faa5 572#endif /* CONFIG_KEXEC_CORE */
8f536b76 573
d462b819 574static void __loaded_vmcs_clear(void *arg)
6aa8b732 575{
d462b819 576 struct loaded_vmcs *loaded_vmcs = arg;
d3b2c338 577 int cpu = raw_smp_processor_id();
6aa8b732 578
d462b819
NHE		 579 if (loaded_vmcs->cpu != cpu)
580 return; /* vcpu migration can race with cpu offline */
581 if (per_cpu(current_vmcs, cpu) == loaded_vmcs->vmcs)
6aa8b732 582 per_cpu(current_vmcs, cpu) = NULL;
8f536b76 583 crash_disable_local_vmclear(cpu);
d462b819 584 list_del(&loaded_vmcs->loaded_vmcss_on_cpu_link);
5a560f8b
XG		 585
586 /*
587 * we should ensure updating loaded_vmcs->loaded_vmcss_on_cpu_link
588 * is before setting loaded_vmcs->vcpu to -1 which is done in
589 * loaded_vmcs_init. Otherwise, other cpu can see vcpu = -1 fist
590 * then adds the vmcs into percpu list before it is deleted.
591 */
592 smp_wmb();
593
d462b819 594 loaded_vmcs_init(loaded_vmcs);
8f536b76 595 crash_enable_local_vmclear(cpu);
6aa8b732
AK		 596}
597
89b0c9f5 598void loaded_vmcs_clear(struct loaded_vmcs *loaded_vmcs)
8d0be2b3 599{
e6c7d321
XG		 600 int cpu = loaded_vmcs->cpu;
601
602 if (cpu != -1)
603 smp_call_function_single(cpu,
604 __loaded_vmcs_clear, loaded_vmcs, 1);
8d0be2b3
AK		 605}
606
2fb92db1
AK		 607static bool vmx_segment_cache_test_set(struct vcpu_vmx *vmx, unsigned seg,
608 unsigned field)
609{
610 bool ret;
611 u32 mask = 1 << (seg * SEG_FIELD_NR + field);
612
613 if (!(vmx->vcpu.arch.regs_avail & (1 << VCPU_EXREG_SEGMENTS))) {
614 vmx->vcpu.arch.regs_avail |= (1 << VCPU_EXREG_SEGMENTS);
615 vmx->segment_cache.bitmask = 0;
616 }
617 ret = vmx->segment_cache.bitmask & mask;
618 vmx->segment_cache.bitmask |= mask;
619 return ret;
620}
621
622static u16 vmx_read_guest_seg_selector(struct vcpu_vmx *vmx, unsigned seg)
623{
624 u16 *p = &vmx->segment_cache.seg[seg].selector;
625
626 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_SEL))
627 *p = vmcs_read16(kvm_vmx_segment_fields[seg].selector);
628 return *p;
629}
630
631static ulong vmx_read_guest_seg_base(struct vcpu_vmx *vmx, unsigned seg)
632{
633 ulong *p = &vmx->segment_cache.seg[seg].base;
634
635 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_BASE))
636 *p = vmcs_readl(kvm_vmx_segment_fields[seg].base);
637 return *p;
638}
639
640static u32 vmx_read_guest_seg_limit(struct vcpu_vmx *vmx, unsigned seg)
641{
642 u32 *p = &vmx->segment_cache.seg[seg].limit;
643
644 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_LIMIT))
645 *p = vmcs_read32(kvm_vmx_segment_fields[seg].limit);
646 return *p;
647}
648
649static u32 vmx_read_guest_seg_ar(struct vcpu_vmx *vmx, unsigned seg)
650{
651 u32 *p = &vmx->segment_cache.seg[seg].ar;
652
653 if (!vmx_segment_cache_test_set(vmx, seg, SEG_FIELD_AR))
654 *p = vmcs_read32(kvm_vmx_segment_fields[seg].ar_bytes);
655 return *p;
656}
657
97b7ead3 658void update_exception_bitmap(struct kvm_vcpu *vcpu)
abd3f2d6
AK		 659{
660 u32 eb;
661
fd7373cc 662 eb = (1u << PF_VECTOR) | (1u << UD_VECTOR) | (1u << MC_VECTOR) |
bd7e5b08 663 (1u << DB_VECTOR) | (1u << AC_VECTOR);
9e869480
LA		 664 /*
665 * Guest access to VMware backdoor ports could legitimately
666 * trigger #GP because of TSS I/O permission bitmap.
667 * We intercept those #GP and allow access to them anyway
668 * as VMware does.
669 */
670 if (enable_vmware_backdoor)
671 eb |= (1u << GP_VECTOR);
fd7373cc
JK		 672 if ((vcpu->guest_debug &
673 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP)) ==
674 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP))
675 eb |= 1u << BP_VECTOR;
7ffd92c5 676 if (to_vmx(vcpu)->rmode.vm86_active)
abd3f2d6 677 eb = ~0;
089d034e 678 if (enable_ept)
1439442c 679 eb &= ~(1u << PF_VECTOR); /* bypass_guest_pf = 0 */
36cf24e0
NHE		 680
681 /* When we are running a nested L2 guest and L1 specified for it a
682 * certain exception bitmap, we must trap the same exceptions and pass
683 * them to L1. When running L2, we will only handle the exceptions
684 * specified above if L1 did not want them.
685 */
686 if (is_guest_mode(vcpu))
687 eb |= get_vmcs12(vcpu)->exception_bitmap;
688
abd3f2d6
AK		 689 vmcs_write32(EXCEPTION_BITMAP, eb);
690}
691
d28b387f
KA		 692/*
693 * Check if MSR is intercepted for currently loaded MSR bitmap.
694 */
695static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
696{
697 unsigned long *msr_bitmap;
698 int f = sizeof(unsigned long);
699
700 if (!cpu_has_vmx_msr_bitmap())
701 return true;
702
703 msr_bitmap = to_vmx(vcpu)->loaded_vmcs->msr_bitmap;
704
705 if (msr <= 0x1fff) {
706 return !!test_bit(msr, msr_bitmap + 0x800 / f);
707 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
708 msr &= 0x1fff;
709 return !!test_bit(msr, msr_bitmap + 0xc00 / f);
710 }
711
712 return true;
713}
714
2961e876
GN		 715static void clear_atomic_switch_msr_special(struct vcpu_vmx *vmx,
716 unsigned long entry, unsigned long exit)
8bf00a52 717{
2961e876
GN		 718 vm_entry_controls_clearbit(vmx, entry);
719 vm_exit_controls_clearbit(vmx, exit);
8bf00a52
GN		 720}
721
ca83b4a7
KRW		 722static int find_msr(struct vmx_msrs *m, unsigned int msr)
723{
724 unsigned int i;
725
726 for (i = 0; i < m->nr; ++i) {
727 if (m->val[i].index == msr)
728 return i;
729 }
730 return -ENOENT;
731}
732
61d2ef2c
AK		 733static void clear_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr)
734{
ca83b4a7 735 int i;
61d2ef2c
AK		 736 struct msr_autoload *m = &vmx->msr_autoload;
737
8bf00a52
GN		 738 switch (msr) {
739 case MSR_EFER:
c73da3fc 740 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 741 clear_atomic_switch_msr_special(vmx,
742 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 743 VM_EXIT_LOAD_IA32_EFER);
744 return;
745 }
746 break;
747 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 748 if (cpu_has_load_perf_global_ctrl()) {
2961e876 749 clear_atomic_switch_msr_special(vmx,
8bf00a52
GN		 750 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
751 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL);
752 return;
753 }
754 break;
110312c8 755 }
ca83b4a7
KRW		 756 i = find_msr(&m->guest, msr);
757 if (i < 0)
31907093 758 goto skip_guest;
33966dd6 759 --m->guest.nr;
33966dd6 760 m->guest.val[i] = m->guest.val[m->guest.nr];
33966dd6 761 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
110312c8 762
31907093
KRW		 763skip_guest:
764 i = find_msr(&m->host, msr);
765 if (i < 0)
61d2ef2c 766 return;
31907093
KRW		 767
768 --m->host.nr;
769 m->host.val[i] = m->host.val[m->host.nr];
33966dd6 770 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c
AK		 771}
772
2961e876
GN		 773static void add_atomic_switch_msr_special(struct vcpu_vmx *vmx,
774 unsigned long entry, unsigned long exit,
775 unsigned long guest_val_vmcs, unsigned long host_val_vmcs,
776 u64 guest_val, u64 host_val)
8bf00a52
GN		 777{
778 vmcs_write64(guest_val_vmcs, guest_val);
5a5e8a15
SC		 779 if (host_val_vmcs != HOST_IA32_EFER)
780 vmcs_write64(host_val_vmcs, host_val);
2961e876
GN		 781 vm_entry_controls_setbit(vmx, entry);
782 vm_exit_controls_setbit(vmx, exit);
8bf00a52
GN		 783}
784
61d2ef2c 785static void add_atomic_switch_msr(struct vcpu_vmx *vmx, unsigned msr,
989e3992 786 u64 guest_val, u64 host_val, bool entry_only)
61d2ef2c 787{
989e3992 788 int i, j = 0;
61d2ef2c
AK		 789 struct msr_autoload *m = &vmx->msr_autoload;
790
8bf00a52
GN		 791 switch (msr) {
792 case MSR_EFER:
c73da3fc 793 if (cpu_has_load_ia32_efer()) {
2961e876
GN		 794 add_atomic_switch_msr_special(vmx,
795 VM_ENTRY_LOAD_IA32_EFER,
8bf00a52
GN		 796 VM_EXIT_LOAD_IA32_EFER,
797 GUEST_IA32_EFER,
798 HOST_IA32_EFER,
799 guest_val, host_val);
800 return;
801 }
802 break;
803 case MSR_CORE_PERF_GLOBAL_CTRL:
c73da3fc 804 if (cpu_has_load_perf_global_ctrl()) {
2961e876 805 add_atomic_switch_msr_special(vmx,
8bf00a52
GN		 806 VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL,
807 VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL,
808 GUEST_IA32_PERF_GLOBAL_CTRL,
809 HOST_IA32_PERF_GLOBAL_CTRL,
810 guest_val, host_val);
811 return;
812 }
813 break;
7099e2e1
RK		 814 case MSR_IA32_PEBS_ENABLE:
815 /* PEBS needs a quiescent period after being disabled (to write
816 * a record). Disabling PEBS through VMX MSR swapping doesn't
817 * provide that period, so a CPU could write host's record into
818 * guest's memory.
819 */
820 wrmsrl(MSR_IA32_PEBS_ENABLE, 0);
110312c8
AK		 821 }
822
ca83b4a7 823 i = find_msr(&m->guest, msr);
989e3992
KRW		 824 if (!entry_only)
825 j = find_msr(&m->host, msr);
61d2ef2c 826
31907093 827 if (i == NR_AUTOLOAD_MSRS || j == NR_AUTOLOAD_MSRS) {
60266204 828 printk_once(KERN_WARNING "Not enough msr switch entries. "
e7fc6f93
GN		 829 "Can't add msr %x\n", msr);
830 return;
61d2ef2c 831 }
31907093 832 if (i < 0) {
ca83b4a7 833 i = m->guest.nr++;
33966dd6 834 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, m->guest.nr);
31907093 835 }
989e3992
KRW		 836 m->guest.val[i].index = msr;
837 m->guest.val[i].value = guest_val;
838
839 if (entry_only)
840 return;
61d2ef2c 841
31907093
KRW		 842 if (j < 0) {
843 j = m->host.nr++;
33966dd6 844 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, m->host.nr);
61d2ef2c 845 }
31907093
KRW		 846 m->host.val[j].index = msr;
847 m->host.val[j].value = host_val;
61d2ef2c
AK		 848}
849
92c0d900 850static bool update_transition_efer(struct vcpu_vmx *vmx, int efer_offset)
2cc51560 851{
844a5fe2
PB		 852 u64 guest_efer = vmx->vcpu.arch.efer;
853 u64 ignore_bits = 0;
854
855 if (!enable_ept) {
856 /*
857 * NX is needed to handle CR0.WP=1, CR4.SMEP=1. Testing
858 * host CPUID is more efficient than testing guest CPUID
859 * or CR4. Host SMEP is anyway a requirement for guest SMEP.
860 */
861 if (boot_cpu_has(X86_FEATURE_SMEP))
862 guest_efer |= EFER_NX;
863 else if (!(guest_efer & EFER_NX))
864 ignore_bits |= EFER_NX;
865 }
3a34a881 866
51c6cf66 867 /*
844a5fe2 868 * LMA and LME handled by hardware; SCE meaningless outside long mode.
51c6cf66 869 */
844a5fe2 870 ignore_bits |= EFER_SCE;
51c6cf66
AK		 871#ifdef CONFIG_X86_64
872 ignore_bits |= EFER_LMA | EFER_LME;
873 /* SCE is meaningful only in long mode on Intel */
874 if (guest_efer & EFER_LMA)
875 ignore_bits &= ~(u64)EFER_SCE;
876#endif
84ad33ef 877
f6577a5f
AL		 878 /*
879 * On EPT, we can't emulate NX, so we must switch EFER atomically.
880 * On CPUs that support "load IA32_EFER", always switch EFER
881 * atomically, since it's faster than switching it manually.
882 */
c73da3fc 883 if (cpu_has_load_ia32_efer() ||
f6577a5f 884 (enable_ept && ((vmx->vcpu.arch.efer ^ host_efer) & EFER_NX))) {
84ad33ef
AK		 885 if (!(guest_efer & EFER_LMA))
886 guest_efer &= ~EFER_LME;
54b98bff
AL		 887 if (guest_efer != host_efer)
888 add_atomic_switch_msr(vmx, MSR_EFER,
989e3992 889 guest_efer, host_efer, false);
02343cf2
SC		 890 else
891 clear_atomic_switch_msr(vmx, MSR_EFER);
84ad33ef 892 return false;
844a5fe2 893 } else {
02343cf2
SC		 894 clear_atomic_switch_msr(vmx, MSR_EFER);
895
844a5fe2
PB		 896 guest_efer &= ~ignore_bits;
897 guest_efer |= host_efer & ignore_bits;
898
899 vmx->guest_msrs[efer_offset].data = guest_efer;
900 vmx->guest_msrs[efer_offset].mask = ~ignore_bits;
84ad33ef 901
844a5fe2
PB		 902 return true;
903 }
51c6cf66
AK		 904}
905
e28baead
AL		 906#ifdef CONFIG_X86_32
907/*
908 * On 32-bit kernels, VM exits still load the FS and GS bases from the
909 * VMCS rather than the segment table. KVM uses this helper to figure
910 * out the current bases to poke them into the VMCS before entry.
911 */
2d49ec72
GN		 912static unsigned long segment_base(u16 selector)
913{
8c2e41f7 914 struct desc_struct *table;
2d49ec72
GN		 915 unsigned long v;
916
8c2e41f7 917 if (!(selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 918 return 0;
919
45fc8757 920 table = get_current_gdt_ro();
2d49ec72 921
8c2e41f7 922 if ((selector & SEGMENT_TI_MASK) == SEGMENT_LDT) {
2d49ec72
GN		 923 u16 ldt_selector = kvm_read_ldt();
924
8c2e41f7 925 if (!(ldt_selector & ~SEGMENT_RPL_MASK))
2d49ec72
GN		 926 return 0;
927
8c2e41f7 928 table = (struct desc_struct *)segment_base(ldt_selector);
2d49ec72 929 }
8c2e41f7 930 v = get_desc_base(&table[selector >> 3]);
2d49ec72
GN		 931 return v;
932}
e28baead 933#endif
2d49ec72 934
97b7ead3 935void vmx_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
33ed6329 936{
04d2cc77 937 struct vcpu_vmx *vmx = to_vmx(vcpu);
d7ee039e 938 struct vmcs_host_state *host_state;
51e8a8cc 939#ifdef CONFIG_X86_64
35060ed6 940 int cpu = raw_smp_processor_id();
51e8a8cc 941#endif
e368b875
SC		 942 unsigned long fs_base, gs_base;
943 u16 fs_sel, gs_sel;
26bb0981 944 int i;
04d2cc77 945
d264ee0c
SC		 946 vmx->req_immediate_exit = false;
947
f48b4711
LA		 948 /*
949 * Note that guest MSRs to be saved/restored can also be changed
950 * when guest state is loaded. This happens when guest transitions
951 * to/from long-mode by setting MSR_EFER.LMA.
952 */
953 if (!vmx->loaded_cpu_state || vmx->guest_msrs_dirty) {
954 vmx->guest_msrs_dirty = false;
955 for (i = 0; i < vmx->save_nmsrs; ++i)
956 kvm_set_shared_msr(vmx->guest_msrs[i].index,
957 vmx->guest_msrs[i].data,
958 vmx->guest_msrs[i].mask);
959
960 }
961
bd9966de 962 if (vmx->loaded_cpu_state)
33ed6329
AK		 963 return;
964
bd9966de 965 vmx->loaded_cpu_state = vmx->loaded_vmcs;
d7ee039e 966 host_state = &vmx->loaded_cpu_state->host_state;
bd9966de 967
33ed6329
AK		 968 /*
969 * Set host fs and gs selectors. Unfortunately, 22.2.3 does not
970 * allow segment selectors with cpl > 0 or ti == 1.
971 */
d7ee039e 972 host_state->ldt_sel = kvm_read_ldt();
42b933b5
VK		 973
974#ifdef CONFIG_X86_64
d7ee039e
SC		 975 savesegment(ds, host_state->ds_sel);
976 savesegment(es, host_state->es_sel);
e368b875
SC		 977
978 gs_base = cpu_kernelmode_gs_base(cpu);
b062b794
VK		 979 if (likely(is_64bit_mm(current->mm))) {
980 save_fsgs_for_kvm();
e368b875
SC		 981 fs_sel = current->thread.fsindex;
982 gs_sel = current->thread.gsindex;
b062b794 983 fs_base = current->thread.fsbase;
e368b875 984 vmx->msr_host_kernel_gs_base = current->thread.gsbase;
b062b794 985 } else {
e368b875
SC		 986 savesegment(fs, fs_sel);
987 savesegment(gs, gs_sel);
b062b794 988 fs_base = read_msr(MSR_FS_BASE);
e368b875 989 vmx->msr_host_kernel_gs_base = read_msr(MSR_KERNEL_GS_BASE);
33ed6329 990 }
b2da15ac 991
4679b61f 992 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
4fde8d57 993#else
e368b875
SC		 994 savesegment(fs, fs_sel);
995 savesegment(gs, gs_sel);
996 fs_base = segment_base(fs_sel);
997 gs_base = segment_base(gs_sel);
707c0874 998#endif
e368b875 999
8f21a0bb
SC		 1000 if (unlikely(fs_sel != host_state->fs_sel)) {
1001 if (!(fs_sel & 7))
1002 vmcs_write16(HOST_FS_SELECTOR, fs_sel);
1003 else
1004 vmcs_write16(HOST_FS_SELECTOR, 0);
1005 host_state->fs_sel = fs_sel;
1006 }
1007 if (unlikely(gs_sel != host_state->gs_sel)) {
1008 if (!(gs_sel & 7))
1009 vmcs_write16(HOST_GS_SELECTOR, gs_sel);
1010 else
1011 vmcs_write16(HOST_GS_SELECTOR, 0);
1012 host_state->gs_sel = gs_sel;
1013 }
5e079c7e
SC		 1014 if (unlikely(fs_base != host_state->fs_base)) {
1015 vmcs_writel(HOST_FS_BASE, fs_base);
1016 host_state->fs_base = fs_base;
1017 }
1018 if (unlikely(gs_base != host_state->gs_base)) {
1019 vmcs_writel(HOST_GS_BASE, gs_base);
1020 host_state->gs_base = gs_base;
1021 }
33ed6329
AK		 1022}
1023
6d6095bd 1024static void vmx_prepare_switch_to_host(struct vcpu_vmx *vmx)
33ed6329 1025{
d7ee039e
SC		 1026 struct vmcs_host_state *host_state;
1027
bd9966de 1028 if (!vmx->loaded_cpu_state)
33ed6329
AK		 1029 return;
1030
bd9966de 1031 WARN_ON_ONCE(vmx->loaded_cpu_state != vmx->loaded_vmcs);
d7ee039e 1032 host_state = &vmx->loaded_cpu_state->host_state;
bd9966de 1033
e1beb1d3 1034 ++vmx->vcpu.stat.host_state_reload;
bd9966de
SC		 1035 vmx->loaded_cpu_state = NULL;
1036
c8770e7b 1037#ifdef CONFIG_X86_64
4679b61f 1038 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
c8770e7b 1039#endif
d7ee039e
SC		 1040 if (host_state->ldt_sel || (host_state->gs_sel & 7)) {
1041 kvm_load_ldt(host_state->ldt_sel);
33ed6329 1042#ifdef CONFIG_X86_64
d7ee039e 1043 load_gs_index(host_state->gs_sel);
9581d442 1044#else
d7ee039e 1045 loadsegment(gs, host_state->gs_sel);
33ed6329 1046#endif
33ed6329 1047 }
d7ee039e
SC		 1048 if (host_state->fs_sel & 7)
1049 loadsegment(fs, host_state->fs_sel);
b2da15ac 1050#ifdef CONFIG_X86_64
d7ee039e
SC		 1051 if (unlikely(host_state->ds_sel | host_state->es_sel)) {
1052 loadsegment(ds, host_state->ds_sel);
1053 loadsegment(es, host_state->es_sel);
b2da15ac 1054 }
b2da15ac 1055#endif
b7ffc44d 1056 invalidate_tss_limit();
44ea2b17 1057#ifdef CONFIG_X86_64
c8770e7b 1058 wrmsrl(MSR_KERNEL_GS_BASE, vmx->msr_host_kernel_gs_base);
44ea2b17 1059#endif
45fc8757 1060 load_fixmap_gdt(raw_smp_processor_id());
33ed6329
AK		 1061}
1062
678e315e
SC		 1063#ifdef CONFIG_X86_64
1064static u64 vmx_read_guest_kernel_gs_base(struct vcpu_vmx *vmx)
a9b21b62 1065{
4679b61f
PB		 1066 preempt_disable();
1067 if (vmx->loaded_cpu_state)
1068 rdmsrl(MSR_KERNEL_GS_BASE, vmx->msr_guest_kernel_gs_base);
1069 preempt_enable();
678e315e 1070 return vmx->msr_guest_kernel_gs_base;
a9b21b62
AK		 1071}
1072
678e315e
SC		 1073static void vmx_write_guest_kernel_gs_base(struct vcpu_vmx *vmx, u64 data)
1074{
4679b61f
PB		 1075 preempt_disable();
1076 if (vmx->loaded_cpu_state)
1077 wrmsrl(MSR_KERNEL_GS_BASE, data);
1078 preempt_enable();
678e315e
SC		 1079 vmx->msr_guest_kernel_gs_base = data;
1080}
1081#endif
1082
28b835d6
FW		 1083static void vmx_vcpu_pi_load(struct kvm_vcpu *vcpu, int cpu)
1084{
1085 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1086 struct pi_desc old, new;
1087 unsigned int dest;
1088
31afb2ea
PB		 1089 /*
1090 * In case of hot-plug or hot-unplug, we may have to undo
1091 * vmx_vcpu_pi_put even if there is no assigned device. And we
1092 * always keep PI.NDST up to date for simplicity: it makes the
1093 * code easier, and CPU migration is not a fast path.
1094 */
1095 if (!pi_test_sn(pi_desc) && vcpu->cpu == cpu)
28b835d6
FW		 1096 return;
1097
31afb2ea
PB		 1098 /*
1099 * First handle the simple case where no cmpxchg is necessary; just
1100 * allow posting non-urgent interrupts.
1101 *
1102 * If the 'nv' field is POSTED_INTR_WAKEUP_VECTOR, do not change
1103 * PI.NDST: pi_post_block will do it for us and the wakeup_handler
1104 * expects the VCPU to be on the blocked_vcpu_list that matches
1105 * PI.NDST.
1106 */
1107 if (pi_desc->nv == POSTED_INTR_WAKEUP_VECTOR ||
1108 vcpu->cpu == cpu) {
1109 pi_clear_sn(pi_desc);
28b835d6 1110 return;
31afb2ea 1111 }
28b835d6 1112
31afb2ea 1113 /* The full case. */
28b835d6
FW		 1114 do {
1115 old.control = new.control = pi_desc->control;
1116
31afb2ea 1117 dest = cpu_physical_id(cpu);
28b835d6 1118
31afb2ea
PB		 1119 if (x2apic_enabled())
1120 new.ndst = dest;
1121 else
1122 new.ndst = (dest << 8) & 0xFF00;
28b835d6 1123
28b835d6 1124 new.sn = 0;
c0a1666b
PB		 1125 } while (cmpxchg64(&pi_desc->control, old.control,
1126 new.control) != old.control);
28b835d6 1127}
1be0e61c 1128
6aa8b732
AK		 1129/*
1130 * Switches to specified vcpu, until a matching vcpu_put(), but assumes
1131 * vcpu mutex is already taken.
1132 */
97b7ead3 1133void vmx_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
6aa8b732 1134{
a2fa3e9f 1135 struct vcpu_vmx *vmx = to_vmx(vcpu);
b80c76ec 1136 bool already_loaded = vmx->loaded_vmcs->cpu == cpu;
6aa8b732 1137
b80c76ec 1138 if (!already_loaded) {
fe0e80be 1139 loaded_vmcs_clear(vmx->loaded_vmcs);
92fe13be 1140 local_irq_disable();
8f536b76 1141 crash_disable_local_vmclear(cpu);
5a560f8b
XG		 1142
1143 /*
1144 * Read loaded_vmcs->cpu should be before fetching
1145 * loaded_vmcs->loaded_vmcss_on_cpu_link.
1146 * See the comments in __loaded_vmcs_clear().
1147 */
1148 smp_rmb();
1149
d462b819
NHE		 1150 list_add(&vmx->loaded_vmcs->loaded_vmcss_on_cpu_link,
1151 &per_cpu(loaded_vmcss_on_cpu, cpu));
8f536b76 1152 crash_enable_local_vmclear(cpu);
92fe13be 1153 local_irq_enable();
b80c76ec
JM		 1154 }
1155
1156 if (per_cpu(current_vmcs, cpu) != vmx->loaded_vmcs->vmcs) {
1157 per_cpu(current_vmcs, cpu) = vmx->loaded_vmcs->vmcs;
1158 vmcs_load(vmx->loaded_vmcs->vmcs);
15d45071 1159 indirect_branch_prediction_barrier();
b80c76ec
JM		 1160 }
1161
1162 if (!already_loaded) {
59c58ceb 1163 void *gdt = get_current_gdt_ro();
b80c76ec
JM		 1164 unsigned long sysenter_esp;
1165
1166 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
92fe13be 1167
6aa8b732
AK		 1168 /*
1169 * Linux uses per-cpu TSS and GDT, so set these when switching
e0c23063 1170 * processors. See 22.2.4.
6aa8b732 1171 */
e0c23063 1172 vmcs_writel(HOST_TR_BASE,
72f5e08d 1173 (unsigned long)&get_cpu_entry_area(cpu)->tss.x86_tss);
59c58ceb 1174 vmcs_writel(HOST_GDTR_BASE, (unsigned long)gdt); /* 22.2.4 */
6aa8b732 1175
b7ffc44d
AL		 1176 /*
1177 * VM exits change the host TR limit to 0x67 after a VM
1178 * exit. This is okay, since 0x67 covers everything except
1179 * the IO bitmap and have have code to handle the IO bitmap
1180 * being lost after a VM exit.
1181 */
1182 BUILD_BUG_ON(IO_BITMAP_OFFSET - 1 != 0x67);
1183
6aa8b732
AK		 1184 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp);
1185 vmcs_writel(HOST_IA32_SYSENTER_ESP, sysenter_esp); /* 22.2.3 */
ff2c3a18 1186
d462b819 1187 vmx->loaded_vmcs->cpu = cpu;
6aa8b732 1188 }
28b835d6 1189
2680d6da
OH		 1190 /* Setup TSC multiplier */
1191 if (kvm_has_tsc_control &&
c95ba92a
PF		 1192 vmx->current_tsc_ratio != vcpu->arch.tsc_scaling_ratio)
1193 decache_tsc_multiplier(vmx);
2680d6da 1194
28b835d6 1195 vmx_vcpu_pi_load(vcpu, cpu);
1be0e61c 1196 vmx->host_pkru = read_pkru();
74c55931 1197 vmx->host_debugctlmsr = get_debugctlmsr();
28b835d6
FW		 1198}
1199
1200static void vmx_vcpu_pi_put(struct kvm_vcpu *vcpu)
1201{
1202 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
1203
1204 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 1205 !irq_remapping_cap(IRQ_POSTING_CAP) ||
1206 !kvm_vcpu_apicv_active(vcpu))
28b835d6
FW		 1207 return;
1208
1209 /* Set SN when the vCPU is preempted */
1210 if (vcpu->preempted)
1211 pi_set_sn(pi_desc);
6aa8b732
AK		 1212}
1213
97b7ead3 1214void vmx_vcpu_put(struct kvm_vcpu *vcpu)
6aa8b732 1215{
28b835d6
FW		 1216 vmx_vcpu_pi_put(vcpu);
1217
6d6095bd 1218 vmx_prepare_switch_to_host(to_vmx(vcpu));
6aa8b732
AK		 1219}
1220
f244deed
WL		 1221static bool emulation_required(struct kvm_vcpu *vcpu)
1222{
1223 return emulate_invalid_guest_state && !guest_state_valid(vcpu);
1224}
1225
edcafe3c
AK		 1226static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu);
1227
97b7ead3 1228unsigned long vmx_get_rflags(struct kvm_vcpu *vcpu)
6aa8b732 1229{
78ac8b47 1230 unsigned long rflags, save_rflags;
345dcaa8 1231
6de12732
AK		 1232 if (!test_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail)) {
1233 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1234 rflags = vmcs_readl(GUEST_RFLAGS);
1235 if (to_vmx(vcpu)->rmode.vm86_active) {
1236 rflags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
1237 save_rflags = to_vmx(vcpu)->rmode.save_rflags;
1238 rflags |= save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
1239 }
1240 to_vmx(vcpu)->rflags = rflags;
78ac8b47 1241 }
6de12732 1242 return to_vmx(vcpu)->rflags;
6aa8b732
AK		 1243}
1244
97b7ead3 1245void vmx_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
6aa8b732 1246{
f244deed
WL		 1247 unsigned long old_rflags = vmx_get_rflags(vcpu);
1248
6de12732
AK		 1249 __set_bit(VCPU_EXREG_RFLAGS, (ulong *)&vcpu->arch.regs_avail);
1250 to_vmx(vcpu)->rflags = rflags;
78ac8b47
AK		 1251 if (to_vmx(vcpu)->rmode.vm86_active) {
1252 to_vmx(vcpu)->rmode.save_rflags = rflags;
053de044 1253 rflags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
78ac8b47 1254 }
6aa8b732 1255 vmcs_writel(GUEST_RFLAGS, rflags);
f244deed
WL		 1256
1257 if ((old_rflags ^ to_vmx(vcpu)->rflags) & X86_EFLAGS_VM)
1258 to_vmx(vcpu)->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 1259}
1260
97b7ead3 1261u32 vmx_get_interrupt_shadow(struct kvm_vcpu *vcpu)
2809f5d2
GC		 1262{
1263 u32 interruptibility = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1264 int ret = 0;
1265
1266 if (interruptibility & GUEST_INTR_STATE_STI)
48005f64 1267 ret |= KVM_X86_SHADOW_INT_STI;
2809f5d2 1268 if (interruptibility & GUEST_INTR_STATE_MOV_SS)
48005f64 1269 ret |= KVM_X86_SHADOW_INT_MOV_SS;
2809f5d2 1270
37ccdcbe 1271 return ret;
2809f5d2
GC		 1272}
1273
97b7ead3 1274void vmx_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
2809f5d2
GC		 1275{
1276 u32 interruptibility_old = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO);
1277 u32 interruptibility = interruptibility_old;
1278
1279 interruptibility &= ~(GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS);
1280
48005f64 1281 if (mask & KVM_X86_SHADOW_INT_MOV_SS)
2809f5d2 1282 interruptibility |= GUEST_INTR_STATE_MOV_SS;
48005f64 1283 else if (mask & KVM_X86_SHADOW_INT_STI)
2809f5d2
GC		 1284 interruptibility |= GUEST_INTR_STATE_STI;
1285
1286 if ((interruptibility != interruptibility_old))
1287 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, interruptibility);
1288}
1289
6aa8b732
AK		 1290static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
1291{
1292 unsigned long rip;
6aa8b732 1293
5fdbf976 1294 rip = kvm_rip_read(vcpu);
6aa8b732 1295 rip += vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
5fdbf976 1296 kvm_rip_write(vcpu, rip);
6aa8b732 1297
2809f5d2
GC		 1298 /* skipping an emulated instruction also counts */
1299 vmx_set_interrupt_shadow(vcpu, 0);
6aa8b732
AK		 1300}
1301
caa057a2
WL		 1302static void vmx_clear_hlt(struct kvm_vcpu *vcpu)
1303{
1304 /*
1305 * Ensure that we clear the HLT state in the VMCS. We don't need to
1306 * explicitly skip the instruction because if the HLT state is set,
1307 * then the instruction is already executing and RIP has already been
1308 * advanced.
1309 */
1310 if (kvm_hlt_in_guest(vcpu->kvm) &&
1311 vmcs_read32(GUEST_ACTIVITY_STATE) == GUEST_ACTIVITY_HLT)
1312 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
1313}
1314
cfcd20e5 1315static void vmx_queue_exception(struct kvm_vcpu *vcpu)
298101da 1316{
77ab6db0 1317 struct vcpu_vmx *vmx = to_vmx(vcpu);
cfcd20e5
WL		 1318 unsigned nr = vcpu->arch.exception.nr;
1319 bool has_error_code = vcpu->arch.exception.has_error_code;
cfcd20e5 1320 u32 error_code = vcpu->arch.exception.error_code;
8ab2d2e2 1321 u32 intr_info = nr | INTR_INFO_VALID_MASK;
77ab6db0 1322
da998b46
JM		 1323 kvm_deliver_exception_payload(vcpu);
1324
8ab2d2e2 1325 if (has_error_code) {
77ab6db0 1326 vmcs_write32(VM_ENTRY_EXCEPTION_ERROR_CODE, error_code);
8ab2d2e2
JK		 1327 intr_info |= INTR_INFO_DELIVER_CODE_MASK;
1328 }
77ab6db0 1329
7ffd92c5 1330 if (vmx->rmode.vm86_active) {
71f9833b
SH		 1331 int inc_eip = 0;
1332 if (kvm_exception_is_soft(nr))
1333 inc_eip = vcpu->arch.event_exit_inst_len;
1334 if (kvm_inject_realmode_interrupt(vcpu, nr, inc_eip) != EMULATE_DONE)
a92601bb 1335 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
77ab6db0
JK		 1336 return;
1337 }
1338
add5ff7a
SC		 1339 WARN_ON_ONCE(vmx->emulation_required);
1340
66fd3f7f
GN		 1341 if (kvm_exception_is_soft(nr)) {
1342 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
1343 vmx->vcpu.arch.event_exit_inst_len);
8ab2d2e2
JK		 1344 intr_info |= INTR_TYPE_SOFT_EXCEPTION;
1345 } else
1346 intr_info |= INTR_TYPE_HARD_EXCEPTION;
1347
1348 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr_info);
caa057a2
WL		 1349
1350 vmx_clear_hlt(vcpu);
298101da
AK		 1351}
1352
4e47c7a6
SY		 1353static bool vmx_rdtscp_supported(void)
1354{
1355 return cpu_has_vmx_rdtscp();
1356}
1357
ad756a16
MJ		 1358static bool vmx_invpcid_supported(void)
1359{
eb4b248e 1360 return cpu_has_vmx_invpcid();
ad756a16
MJ		 1361}
1362
a75beee6
ED		 1363/*
1364 * Swap MSR entry in host/guest MSR entry array.
1365 */
8b9cf98c 1366static void move_msr_up(struct vcpu_vmx *vmx, int from, int to)
a75beee6 1367{
26bb0981 1368 struct shared_msr_entry tmp;
a2fa3e9f
GH		 1369
1370 tmp = vmx->guest_msrs[to];
1371 vmx->guest_msrs[to] = vmx->guest_msrs[from];
1372 vmx->guest_msrs[from] = tmp;
a75beee6
ED		 1373}
1374
e38aea3e
AK		 1375/*
1376 * Set up the vmcs to automatically save and restore system
1377 * msrs. Don't touch the 64-bit msrs if the guest is in legacy
1378 * mode, as fiddling with msrs is very expensive.
1379 */
8b9cf98c 1380static void setup_msrs(struct vcpu_vmx *vmx)
e38aea3e 1381{
26bb0981 1382 int save_nmsrs, index;
e38aea3e 1383
a75beee6
ED		 1384 save_nmsrs = 0;
1385#ifdef CONFIG_X86_64
84c8c5b8
JM		 1386 /*
1387 * The SYSCALL MSRs are only needed on long mode guests, and only
1388 * when EFER.SCE is set.
1389 */
1390 if (is_long_mode(&vmx->vcpu) && (vmx->vcpu.arch.efer & EFER_SCE)) {
1391 index = __find_msr_index(vmx, MSR_STAR);
a75beee6 1392 if (index >= 0)
8b9cf98c
RR		 1393 move_msr_up(vmx, index, save_nmsrs++);
1394 index = __find_msr_index(vmx, MSR_LSTAR);
a75beee6 1395 if (index >= 0)
8b9cf98c 1396 move_msr_up(vmx, index, save_nmsrs++);
84c8c5b8
JM		 1397 index = __find_msr_index(vmx, MSR_SYSCALL_MASK);
1398 if (index >= 0)
8b9cf98c 1399 move_msr_up(vmx, index, save_nmsrs++);
a75beee6
ED		 1400 }
1401#endif
92c0d900
AK		 1402 index = __find_msr_index(vmx, MSR_EFER);
1403 if (index >= 0 && update_transition_efer(vmx, index))
26bb0981 1404 move_msr_up(vmx, index, save_nmsrs++);
0023ef39
JM		 1405 index = __find_msr_index(vmx, MSR_TSC_AUX);
1406 if (index >= 0 && guest_cpuid_has(&vmx->vcpu, X86_FEATURE_RDTSCP))
1407 move_msr_up(vmx, index, save_nmsrs++);
e38aea3e 1408
26bb0981 1409 vmx->save_nmsrs = save_nmsrs;
f48b4711 1410 vmx->guest_msrs_dirty = true;
5897297b 1411
8d14695f 1412 if (cpu_has_vmx_msr_bitmap())
904e14fb 1413 vmx_update_msr_bitmap(&vmx->vcpu);
e38aea3e
AK		 1414}
1415
e79f245d 1416static u64 vmx_read_l1_tsc_offset(struct kvm_vcpu *vcpu)
6aa8b732 1417{
e79f245d 1418 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6aa8b732 1419
e79f245d
KA		 1420 if (is_guest_mode(vcpu) &&
1421 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1422 return vcpu->arch.tsc_offset - vmcs12->tsc_offset;
1423
1424 return vcpu->arch.tsc_offset;
6aa8b732
AK		 1425}
1426
326e7425 1427static u64 vmx_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
6aa8b732 1428{
45c3af97
PB		 1429 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
1430 u64 g_tsc_offset = 0;
1431
1432 /*
1433 * We're here if L1 chose not to trap WRMSR to TSC. According
1434 * to the spec, this should set L1's TSC; The offset that L1
1435 * set for L2 remains unchanged, and still needs to be added
1436 * to the newly set TSC to get L2's TSC.
1437 */
1438 if (is_guest_mode(vcpu) &&
1439 (vmcs12->cpu_based_vm_exec_control & CPU_BASED_USE_TSC_OFFSETING))
1440 g_tsc_offset = vmcs12->tsc_offset;
326e7425 1441
45c3af97
PB		 1442 trace_kvm_write_tsc_offset(vcpu->vcpu_id,
1443 vcpu->arch.tsc_offset - g_tsc_offset,
1444 offset);
1445 vmcs_write64(TSC_OFFSET, offset + g_tsc_offset);
1446 return offset + g_tsc_offset;
6aa8b732
AK		 1447}
1448
801d3424
NHE		 1449/*
1450 * nested_vmx_allowed() checks whether a guest should be allowed to use VMX
1451 * instructions and MSRs (i.e., nested VMX). Nested VMX is disabled for
1452 * all guests if the "nested" module option is off, and can also be disabled
1453 * for a single guest by disabling its VMX cpuid bit.
1454 */
7c97fcb3 1455bool nested_vmx_allowed(struct kvm_vcpu *vcpu)
801d3424 1456{
d6321d49 1457 return nested && guest_cpuid_has(vcpu, X86_FEATURE_VMX);
801d3424
NHE		 1458}
1459
55d2375e
SC		 1460static inline bool vmx_feature_control_msr_valid(struct kvm_vcpu *vcpu,
1461 uint64_t val)
62cc6b9d 1462{
55d2375e 1463 uint64_t valid_bits = to_vmx(vcpu)->msr_ia32_feature_control_valid_bits;
62cc6b9d 1464
55d2375e 1465 return !(val & ~valid_bits);
62cc6b9d
DM		 1466}
1467
55d2375e 1468static int vmx_get_msr_feature(struct kvm_msr_entry *msr)
62cc6b9d 1469{
55d2375e
SC		 1470 switch (msr->index) {
1471 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1472 if (!nested)
1473 return 1;
1474 return vmx_get_vmx_msr(&vmcs_config.nested, msr->index, &msr->data);
1475 default:
1476 return 1;
1477 }
62cc6b9d 1478
62cc6b9d
DM		 1479 return 0;
1480}
1481
55d2375e
SC		 1482/*
1483 * Reads an msr value (of 'msr_index') into 'pdata'.
1484 * Returns 0 on success, non-0 otherwise.
1485 * Assumes vcpu_load() was already called.
1486 */
1487static int vmx_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
62cc6b9d 1488{
55d2375e
SC		 1489 struct vcpu_vmx *vmx = to_vmx(vcpu);
1490 struct shared_msr_entry *msr;
62cc6b9d 1491
55d2375e
SC		 1492 switch (msr_info->index) {
1493#ifdef CONFIG_X86_64
1494 case MSR_FS_BASE:
1495 msr_info->data = vmcs_readl(GUEST_FS_BASE);
62cc6b9d 1496 break;
55d2375e
SC		 1497 case MSR_GS_BASE:
1498 msr_info->data = vmcs_readl(GUEST_GS_BASE);
62cc6b9d 1499 break;
55d2375e
SC		 1500 case MSR_KERNEL_GS_BASE:
1501 msr_info->data = vmx_read_guest_kernel_gs_base(vmx);
62cc6b9d 1502 break;
55d2375e
SC		 1503#endif
1504 case MSR_EFER:
1505 return kvm_get_msr_common(vcpu, msr_info);
1506 case MSR_IA32_SPEC_CTRL:
1507 if (!msr_info->host_initiated &&
1508 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1509 return 1;
1510
1511 msr_info->data = to_vmx(vcpu)->spec_ctrl;
62cc6b9d 1512 break;
55d2375e
SC		 1513 case MSR_IA32_ARCH_CAPABILITIES:
1514 if (!msr_info->host_initiated &&
1515 !guest_cpuid_has(vcpu, X86_FEATURE_ARCH_CAPABILITIES))
1516 return 1;
1517 msr_info->data = to_vmx(vcpu)->arch_capabilities;
28c1c9fa 1518 break;
6aa8b732 1519 case MSR_IA32_SYSENTER_CS:
609e36d3 1520 msr_info->data = vmcs_read32(GUEST_SYSENTER_CS);
6aa8b732
AK		 1521 break;
1522 case MSR_IA32_SYSENTER_EIP:
609e36d3 1523 msr_info->data = vmcs_readl(GUEST_SYSENTER_EIP);
6aa8b732
AK		 1524 break;
1525 case MSR_IA32_SYSENTER_ESP:
609e36d3 1526 msr_info->data = vmcs_readl(GUEST_SYSENTER_ESP);
6aa8b732 1527 break;
0dd376e7 1528 case MSR_IA32_BNDCFGS:
691bd434 1529 if (!kvm_mpx_supported() ||
d6321d49
RK		 1530 (!msr_info->host_initiated &&
1531 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1532 return 1;
609e36d3 1533 msr_info->data = vmcs_read64(GUEST_BNDCFGS);
0dd376e7 1534 break;
c45dcc71
AR		 1535 case MSR_IA32_MCG_EXT_CTL:
1536 if (!msr_info->host_initiated &&
a6cb099a 1537 !(vmx->msr_ia32_feature_control &
c45dcc71 1538 FEATURE_CONTROL_LMCE))
cae50139 1539 return 1;
c45dcc71
AR		 1540 msr_info->data = vcpu->arch.mcg_ext_ctl;
1541 break;
cae50139 1542 case MSR_IA32_FEATURE_CONTROL:
a6cb099a 1543 msr_info->data = vmx->msr_ia32_feature_control;
cae50139
JK		 1544 break;
1545 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
1546 if (!nested_vmx_allowed(vcpu))
1547 return 1;
6677f3da
PB		 1548 return vmx_get_vmx_msr(&vmx->nested.msrs, msr_info->index,
1549 &msr_info->data);
20300099
WL		 1550 case MSR_IA32_XSS:
1551 if (!vmx_xsaves_supported())
1552 return 1;
609e36d3 1553 msr_info->data = vcpu->arch.ia32_xss;
20300099 1554 break;
4e47c7a6 1555 case MSR_TSC_AUX:
d6321d49
RK		 1556 if (!msr_info->host_initiated &&
1557 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6
SY		 1558 return 1;
1559 /* Otherwise falls through */
6aa8b732 1560 default:
a6cb099a 1561 msr = find_msr_entry(vmx, msr_info->index);
3bab1f5d 1562 if (msr) {
609e36d3 1563 msr_info->data = msr->data;
3bab1f5d 1564 break;
6aa8b732 1565 }
609e36d3 1566 return kvm_get_msr_common(vcpu, msr_info);
6aa8b732
AK		 1567 }
1568
6aa8b732
AK		 1569 return 0;
1570}
1571
1572/*
1573 * Writes msr value into into the appropriate "register".
1574 * Returns 0 on success, non-0 otherwise.
1575 * Assumes vcpu_load() was already called.
1576 */
8fe8ab46 1577static int vmx_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
6aa8b732 1578{
a2fa3e9f 1579 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981 1580 struct shared_msr_entry *msr;
2cc51560 1581 int ret = 0;
8fe8ab46
WA		 1582 u32 msr_index = msr_info->index;
1583 u64 data = msr_info->data;
2cc51560 1584
6aa8b732 1585 switch (msr_index) {
3bab1f5d 1586 case MSR_EFER:
8fe8ab46 1587 ret = kvm_set_msr_common(vcpu, msr_info);
2cc51560 1588 break;
16175a79 1589#ifdef CONFIG_X86_64
6aa8b732 1590 case MSR_FS_BASE:
2fb92db1 1591 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1592 vmcs_writel(GUEST_FS_BASE, data);
1593 break;
1594 case MSR_GS_BASE:
2fb92db1 1595 vmx_segment_cache_clear(vmx);
6aa8b732
AK		 1596 vmcs_writel(GUEST_GS_BASE, data);
1597 break;
44ea2b17 1598 case MSR_KERNEL_GS_BASE:
678e315e 1599 vmx_write_guest_kernel_gs_base(vmx, data);
44ea2b17 1600 break;
6aa8b732
AK		 1601#endif
1602 case MSR_IA32_SYSENTER_CS:
1603 vmcs_write32(GUEST_SYSENTER_CS, data);
1604 break;
1605 case MSR_IA32_SYSENTER_EIP:
f5b42c33 1606 vmcs_writel(GUEST_SYSENTER_EIP, data);
6aa8b732
AK		 1607 break;
1608 case MSR_IA32_SYSENTER_ESP:
f5b42c33 1609 vmcs_writel(GUEST_SYSENTER_ESP, data);
6aa8b732 1610 break;
0dd376e7 1611 case MSR_IA32_BNDCFGS:
691bd434 1612 if (!kvm_mpx_supported() ||
d6321d49
RK		 1613 (!msr_info->host_initiated &&
1614 !guest_cpuid_has(vcpu, X86_FEATURE_MPX)))
93c4adc7 1615 return 1;
fd8cb433 1616 if (is_noncanonical_address(data & PAGE_MASK, vcpu) ||
4531662d 1617 (data & MSR_IA32_BNDCFGS_RSVD))
93c4adc7 1618 return 1;
0dd376e7
LJ		 1619 vmcs_write64(GUEST_BNDCFGS, data);
1620 break;
d28b387f
KA		 1621 case MSR_IA32_SPEC_CTRL:
1622 if (!msr_info->host_initiated &&
d28b387f
KA		 1623 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1624 return 1;
1625
1626 /* The STIBP bit doesn't fault even if it's not advertised */
9f65fb29 1627 if (data & ~(SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD))
d28b387f
KA		 1628 return 1;
1629
1630 vmx->spec_ctrl = data;
1631
1632 if (!data)
1633 break;
1634
1635 /*
1636 * For non-nested:
1637 * When it's written (to non-zero) for the first time, pass
1638 * it through.
1639 *
1640 * For nested:
1641 * The handling of the MSR bitmap for L2 guests is done in
1642 * nested_vmx_merge_msr_bitmap. We should not touch the
1643 * vmcs02.msr_bitmap here since it gets completely overwritten
1644 * in the merging. We update the vmcs01 here for L1 as well
1645 * since it will end up touching the MSR anyway now.
1646 */
1647 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap,
1648 MSR_IA32_SPEC_CTRL,
1649 MSR_TYPE_RW);
1650 break;
15d45071
AR		 1651 case MSR_IA32_PRED_CMD:
1652 if (!msr_info->host_initiated &&
15d45071
AR		 1653 !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL))
1654 return 1;
1655
1656 if (data & ~PRED_CMD_IBPB)
1657 return 1;
1658
1659 if (!data)
1660 break;
1661
1662 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
1663
1664 /*
1665 * For non-nested:
1666 * When it's written (to non-zero) for the first time, pass
1667 * it through.
1668 *
1669 * For nested:
1670 * The handling of the MSR bitmap for L2 guests is done in
1671 * nested_vmx_merge_msr_bitmap. We should not touch the
1672 * vmcs02.msr_bitmap here since it gets completely overwritten
1673 * in the merging.
1674 */
1675 vmx_disable_intercept_for_msr(vmx->vmcs01.msr_bitmap, MSR_IA32_PRED_CMD,
1676 MSR_TYPE_W);
1677 break;
28c1c9fa
KA		 1678 case MSR_IA32_ARCH_CAPABILITIES:
1679 if (!msr_info->host_initiated)
1680 return 1;
1681 vmx->arch_capabilities = data;
1682 break;
468d472f
SY		 1683 case MSR_IA32_CR_PAT:
1684 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT) {
4566654b
NA		 1685 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
1686 return 1;
468d472f
SY		 1687 vmcs_write64(GUEST_IA32_PAT, data);
1688 vcpu->arch.pat = data;
1689 break;
1690 }
8fe8ab46 1691 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 1692 break;
ba904635
WA		 1693 case MSR_IA32_TSC_ADJUST:
1694 ret = kvm_set_msr_common(vcpu, msr_info);
4e47c7a6 1695 break;
c45dcc71
AR		 1696 case MSR_IA32_MCG_EXT_CTL:
1697 if ((!msr_info->host_initiated &&
1698 !(to_vmx(vcpu)->msr_ia32_feature_control &
1699 FEATURE_CONTROL_LMCE)) ||
1700 (data & ~MCG_EXT_CTL_LMCE_EN))
1701 return 1;
1702 vcpu->arch.mcg_ext_ctl = data;
1703 break;
cae50139 1704 case MSR_IA32_FEATURE_CONTROL:
37e4c997 1705 if (!vmx_feature_control_msr_valid(vcpu, data) ||
3b84080b 1706 (to_vmx(vcpu)->msr_ia32_feature_control &
cae50139
JK		 1707 FEATURE_CONTROL_LOCKED && !msr_info->host_initiated))
1708 return 1;
3b84080b 1709 vmx->msr_ia32_feature_control = data;
cae50139
JK		 1710 if (msr_info->host_initiated && data == 0)
1711 vmx_leave_nested(vcpu);
1712 break;
1713 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
62cc6b9d
DM		 1714 if (!msr_info->host_initiated)
1715 return 1; /* they are read-only */
1716 if (!nested_vmx_allowed(vcpu))
1717 return 1;
1718 return vmx_set_vmx_msr(vcpu, msr_index, data);
20300099
WL		 1719 case MSR_IA32_XSS:
1720 if (!vmx_xsaves_supported())
1721 return 1;
1722 /*
1723 * The only supported bit as of Skylake is bit 8, but
1724 * it is not supported on KVM.
1725 */
1726 if (data != 0)
1727 return 1;
1728 vcpu->arch.ia32_xss = data;
1729 if (vcpu->arch.ia32_xss != host_xss)
1730 add_atomic_switch_msr(vmx, MSR_IA32_XSS,
989e3992 1731 vcpu->arch.ia32_xss, host_xss, false);
20300099
WL		 1732 else
1733 clear_atomic_switch_msr(vmx, MSR_IA32_XSS);
1734 break;
4e47c7a6 1735 case MSR_TSC_AUX:
d6321d49
RK		 1736 if (!msr_info->host_initiated &&
1737 !guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
4e47c7a6
SY		 1738 return 1;
1739 /* Check reserved bit, higher 32 bits should be zero */
1740 if ((data >> 32) != 0)
1741 return 1;
1742 /* Otherwise falls through */
6aa8b732 1743 default:
8b9cf98c 1744 msr = find_msr_entry(vmx, msr_index);
3bab1f5d 1745 if (msr) {
8b3c3104 1746 u64 old_msr_data = msr->data;
3bab1f5d 1747 msr->data = data;
2225fd56
AK		 1748 if (msr - vmx->guest_msrs < vmx->save_nmsrs) {
1749 preempt_disable();
8b3c3104
AH		 1750 ret = kvm_set_shared_msr(msr->index, msr->data,
1751 msr->mask);
2225fd56 1752 preempt_enable();
8b3c3104
AH		 1753 if (ret)
1754 msr->data = old_msr_data;
2225fd56 1755 }
3bab1f5d 1756 break;
6aa8b732 1757 }
8fe8ab46 1758 ret = kvm_set_msr_common(vcpu, msr_info);
6aa8b732
AK		 1759 }
1760
2cc51560 1761 return ret;
6aa8b732
AK		 1762}
1763
5fdbf976 1764static void vmx_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
6aa8b732 1765{
5fdbf976
MT		 1766 __set_bit(reg, (unsigned long *)&vcpu->arch.regs_avail);
1767 switch (reg) {
1768 case VCPU_REGS_RSP:
1769 vcpu->arch.regs[VCPU_REGS_RSP] = vmcs_readl(GUEST_RSP);
1770 break;
1771 case VCPU_REGS_RIP:
1772 vcpu->arch.regs[VCPU_REGS_RIP] = vmcs_readl(GUEST_RIP);
1773 break;
6de4f3ad
AK		 1774 case VCPU_EXREG_PDPTR:
1775 if (enable_ept)
1776 ept_save_pdptrs(vcpu);
1777 break;
5fdbf976
MT		 1778 default:
1779 break;
1780 }
6aa8b732
AK		 1781}
1782
6aa8b732
AK		 1783static __init int cpu_has_kvm_support(void)
1784{
6210e37b 1785 return cpu_has_vmx();
6aa8b732
AK		 1786}
1787
1788static __init int vmx_disabled_by_bios(void)
1789{
1790 u64 msr;
1791
1792 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr);
cafd6659 1793 if (msr & FEATURE_CONTROL_LOCKED) {
23f3e991 1794 /* launched w/ TXT and VMX disabled */
cafd6659
SW		 1795 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
1796 && tboot_enabled())
1797 return 1;
23f3e991 1798 /* launched w/o TXT and VMX only enabled w/ TXT */
cafd6659 1799 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
23f3e991 1800 && (msr & FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX)
f9335afe
SW		 1801 && !tboot_enabled()) {
1802 printk(KERN_WARNING "kvm: disable TXT in the BIOS or "
23f3e991 1803 "activate TXT before enabling KVM\n");
cafd6659 1804 return 1;
f9335afe 1805 }
23f3e991
JC		 1806 /* launched w/o TXT and VMX disabled */
1807 if (!(msr & FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX)
1808 && !tboot_enabled())
1809 return 1;
cafd6659
SW		 1810 }
1811
1812 return 0;
6aa8b732
AK		 1813}
1814
7725b894
DX		 1815static void kvm_cpu_vmxon(u64 addr)
1816{
fe0e80be 1817 cr4_set_bits(X86_CR4_VMXE);
1c5ac21a
AS		 1818 intel_pt_handle_vmx(1);
1819
4b1e5478 1820 asm volatile ("vmxon %0" : : "m"(addr));
7725b894
DX		 1821}
1822
13a34e06 1823static int hardware_enable(void)
6aa8b732
AK		 1824{
1825 int cpu = raw_smp_processor_id();
1826 u64 phys_addr = __pa(per_cpu(vmxarea, cpu));
cafd6659 1827 u64 old, test_bits;
6aa8b732 1828
1e02ce4c 1829 if (cr4_read_shadow() & X86_CR4_VMXE)
10474ae8
AG		 1830 return -EBUSY;
1831
773e8a04
VK		 1832 /*
1833 * This can happen if we hot-added a CPU but failed to allocate
1834 * VP assist page for it.
1835 */
1836 if (static_branch_unlikely(&enable_evmcs) &&
1837 !hv_get_vp_assist_page(cpu))
1838 return -EFAULT;
1839
d462b819 1840 INIT_LIST_HEAD(&per_cpu(loaded_vmcss_on_cpu, cpu));
bf9f6ac8
FW		 1841 INIT_LIST_HEAD(&per_cpu(blocked_vcpu_on_cpu, cpu));
1842 spin_lock_init(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
8f536b76
ZY		 1843
1844 /*
1845 * Now we can enable the vmclear operation in kdump
1846 * since the loaded_vmcss_on_cpu list on this cpu
1847 * has been initialized.
1848 *
1849 * Though the cpu is not in VMX operation now, there
1850 * is no problem to enable the vmclear operation
1851 * for the loaded_vmcss_on_cpu list is empty!
1852 */
1853 crash_enable_local_vmclear(cpu);
1854
6aa8b732 1855 rdmsrl(MSR_IA32_FEATURE_CONTROL, old);
cafd6659
SW		 1856
1857 test_bits = FEATURE_CONTROL_LOCKED;
1858 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
1859 if (tboot_enabled())
1860 test_bits |= FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX;
1861
1862 if ((old & test_bits) != test_bits) {
6aa8b732 1863 /* enable and lock */
cafd6659
SW		 1864 wrmsrl(MSR_IA32_FEATURE_CONTROL, old | test_bits);
1865 }
fe0e80be 1866 kvm_cpu_vmxon(phys_addr);
fdf288bf
DH		 1867 if (enable_ept)
1868 ept_sync_global();
10474ae8
AG		 1869
1870 return 0;
6aa8b732
AK		 1871}
1872
d462b819 1873static void vmclear_local_loaded_vmcss(void)
543e4243
AK		 1874{
1875 int cpu = raw_smp_processor_id();
d462b819 1876 struct loaded_vmcs *v, *n;
543e4243 1877
d462b819
NHE		 1878 list_for_each_entry_safe(v, n, &per_cpu(loaded_vmcss_on_cpu, cpu),
1879 loaded_vmcss_on_cpu_link)
1880 __loaded_vmcs_clear(v);
543e4243
AK		 1881}
1882
710ff4a8
EH		 1883
1884/* Just like cpu_vmxoff(), but with the __kvm_handle_fault_on_reboot()
1885 * tricks.
1886 */
1887static void kvm_cpu_vmxoff(void)
6aa8b732 1888{
4b1e5478 1889 asm volatile (__ex("vmxoff"));
1c5ac21a
AS		 1890
1891 intel_pt_handle_vmx(0);
fe0e80be 1892 cr4_clear_bits(X86_CR4_VMXE);
6aa8b732
AK		 1893}
1894
13a34e06 1895static void hardware_disable(void)
710ff4a8 1896{
fe0e80be
DH		 1897 vmclear_local_loaded_vmcss();
1898 kvm_cpu_vmxoff();
710ff4a8
EH		 1899}
1900
1c3d14fe 1901static __init int adjust_vmx_controls(u32 ctl_min, u32 ctl_opt,
d77c26fc 1902 u32 msr, u32 *result)
1c3d14fe
YS		 1903{
1904 u32 vmx_msr_low, vmx_msr_high;
1905 u32 ctl = ctl_min | ctl_opt;
1906
1907 rdmsr(msr, vmx_msr_low, vmx_msr_high);
1908
1909 ctl &= vmx_msr_high; /* bit == 0 in high word ==> must be zero */
1910 ctl |= vmx_msr_low; /* bit == 1 in low word ==> must be one */
1911
1912 /* Ensure minimum (required) set of control bits are supported. */
1913 if (ctl_min & ~ctl)
002c7f7c 1914 return -EIO;
1c3d14fe
YS		 1915
1916 *result = ctl;
1917 return 0;
1918}
1919
7caaa711
SC		 1920static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,
1921 struct vmx_capability *vmx_cap)
6aa8b732
AK		 1922{
1923 u32 vmx_msr_low, vmx_msr_high;
d56f546d 1924 u32 min, opt, min2, opt2;
1c3d14fe
YS		 1925 u32 _pin_based_exec_control = 0;
1926 u32 _cpu_based_exec_control = 0;
f78e0e2e 1927 u32 _cpu_based_2nd_exec_control = 0;
1c3d14fe
YS		 1928 u32 _vmexit_control = 0;
1929 u32 _vmentry_control = 0;
1930
1389309c 1931 memset(vmcs_conf, 0, sizeof(*vmcs_conf));
10166744 1932 min = CPU_BASED_HLT_EXITING |
1c3d14fe
YS		 1933#ifdef CONFIG_X86_64
1934 CPU_BASED_CR8_LOAD_EXITING |
1935 CPU_BASED_CR8_STORE_EXITING |
1936#endif
d56f546d
SY		 1937 CPU_BASED_CR3_LOAD_EXITING |
1938 CPU_BASED_CR3_STORE_EXITING |
8eb73e2d 1939 CPU_BASED_UNCOND_IO_EXITING |
1c3d14fe 1940 CPU_BASED_MOV_DR_EXITING |
a7052897 1941 CPU_BASED_USE_TSC_OFFSETING |
4d5422ce
WL		 1942 CPU_BASED_MWAIT_EXITING |
1943 CPU_BASED_MONITOR_EXITING |
fee84b07
AK		 1944 CPU_BASED_INVLPG_EXITING |
1945 CPU_BASED_RDPMC_EXITING;
443381a8 1946
f78e0e2e 1947 opt = CPU_BASED_TPR_SHADOW |
25c5f225 1948 CPU_BASED_USE_MSR_BITMAPS |
f78e0e2e 1949 CPU_BASED_ACTIVATE_SECONDARY_CONTROLS;
1c3d14fe
YS		 1950 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PROCBASED_CTLS,
1951 &_cpu_based_exec_control) < 0)
002c7f7c 1952 return -EIO;
6e5d865c
YS		 1953#ifdef CONFIG_X86_64
1954 if ((_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1955 _cpu_based_exec_control &= ~CPU_BASED_CR8_LOAD_EXITING &
1956 ~CPU_BASED_CR8_STORE_EXITING;
1957#endif
f78e0e2e 1958 if (_cpu_based_exec_control & CPU_BASED_ACTIVATE_SECONDARY_CONTROLS) {
d56f546d
SY		 1959 min2 = 0;
1960 opt2 = SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
8d14695f 1961 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
2384d2b3 1962 SECONDARY_EXEC_WBINVD_EXITING |
d56f546d 1963 SECONDARY_EXEC_ENABLE_VPID |
3a624e29 1964 SECONDARY_EXEC_ENABLE_EPT |
4b8d54f9 1965 SECONDARY_EXEC_UNRESTRICTED_GUEST |
4e47c7a6 1966 SECONDARY_EXEC_PAUSE_LOOP_EXITING |
0367f205 1967 SECONDARY_EXEC_DESC |
ad756a16 1968 SECONDARY_EXEC_RDTSCP |
83d4c286 1969 SECONDARY_EXEC_ENABLE_INVPCID |
c7c9c56c 1970 SECONDARY_EXEC_APIC_REGISTER_VIRT |
abc4fc58 1971 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY |
20300099 1972 SECONDARY_EXEC_SHADOW_VMCS |
843e4330 1973 SECONDARY_EXEC_XSAVES |
736fdf72
DH		 1974 SECONDARY_EXEC_RDSEED_EXITING |
1975 SECONDARY_EXEC_RDRAND_EXITING |
8b3e34e4 1976 SECONDARY_EXEC_ENABLE_PML |
2a499e49 1977 SECONDARY_EXEC_TSC_SCALING |
0b665d30
SC		 1978 SECONDARY_EXEC_ENABLE_VMFUNC |
1979 SECONDARY_EXEC_ENCLS_EXITING;
d56f546d
SY		 1980 if (adjust_vmx_controls(min2, opt2,
1981 MSR_IA32_VMX_PROCBASED_CTLS2,
f78e0e2e
SY		 1982 &_cpu_based_2nd_exec_control) < 0)
1983 return -EIO;
1984 }
1985#ifndef CONFIG_X86_64
1986 if (!(_cpu_based_2nd_exec_control &
1987 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES))
1988 _cpu_based_exec_control &= ~CPU_BASED_TPR_SHADOW;
1989#endif
83d4c286
YZ		 1990
1991 if (!(_cpu_based_exec_control & CPU_BASED_TPR_SHADOW))
1992 _cpu_based_2nd_exec_control &= ~(
8d14695f 1993 SECONDARY_EXEC_APIC_REGISTER_VIRT |
c7c9c56c
YZ		 1994 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
1995 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
83d4c286 1996
61f1dd90 1997 rdmsr_safe(MSR_IA32_VMX_EPT_VPID_CAP,
7caaa711 1998 &vmx_cap->ept, &vmx_cap->vpid);
61f1dd90 1999
d56f546d 2000 if (_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_EPT) {
a7052897
MT		 2001 /* CR3 accesses and invlpg don't need to cause VM Exits when EPT
2002 enabled */
5fff7d27
GN		 2003 _cpu_based_exec_control &= ~(CPU_BASED_CR3_LOAD_EXITING |
2004 CPU_BASED_CR3_STORE_EXITING |
2005 CPU_BASED_INVLPG_EXITING);
7caaa711
SC		 2006 } else if (vmx_cap->ept) {
2007 vmx_cap->ept = 0;
61f1dd90
WL		 2008 pr_warn_once("EPT CAP should not exist if not support "
2009 "1-setting enable EPT VM-execution control\n");
2010 }
2011 if (!(_cpu_based_2nd_exec_control & SECONDARY_EXEC_ENABLE_VPID) &&
7caaa711
SC		 2012 vmx_cap->vpid) {
2013 vmx_cap->vpid = 0;
61f1dd90
WL		 2014 pr_warn_once("VPID CAP should not exist if not support "
2015 "1-setting enable VPID VM-execution control\n");
d56f546d 2016 }
1c3d14fe 2017
91fa0f8e 2018 min = VM_EXIT_SAVE_DEBUG_CONTROLS | VM_EXIT_ACK_INTR_ON_EXIT;
1c3d14fe
YS		 2019#ifdef CONFIG_X86_64
2020 min |= VM_EXIT_HOST_ADDR_SPACE_SIZE;
2021#endif
c73da3fc
SC		 2022 opt = VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL |
2023 VM_EXIT_SAVE_IA32_PAT |
2024 VM_EXIT_LOAD_IA32_PAT |
2025 VM_EXIT_LOAD_IA32_EFER |
2026 VM_EXIT_CLEAR_BNDCFGS;
1c3d14fe
YS		 2027 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_EXIT_CTLS,
2028 &_vmexit_control) < 0)
002c7f7c 2029 return -EIO;
1c3d14fe 2030
8a1b4392
PB		 2031 min = PIN_BASED_EXT_INTR_MASK | PIN_BASED_NMI_EXITING;
2032 opt = PIN_BASED_VIRTUAL_NMIS | PIN_BASED_POSTED_INTR |
2033 PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 2034 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_PINBASED_CTLS,
2035 &_pin_based_exec_control) < 0)
2036 return -EIO;
2037
1c17c3e6
PB		 2038 if (cpu_has_broken_vmx_preemption_timer())
2039 _pin_based_exec_control &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be 2040 if (!(_cpu_based_2nd_exec_control &
91fa0f8e 2041 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY))
01e439be
YZ		 2042 _pin_based_exec_control &= ~PIN_BASED_POSTED_INTR;
2043
c845f9c6 2044 min = VM_ENTRY_LOAD_DEBUG_CONTROLS;
c73da3fc
SC		 2045 opt = VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL |
2046 VM_ENTRY_LOAD_IA32_PAT |
2047 VM_ENTRY_LOAD_IA32_EFER |
2048 VM_ENTRY_LOAD_BNDCFGS;
1c3d14fe
YS		 2049 if (adjust_vmx_controls(min, opt, MSR_IA32_VMX_ENTRY_CTLS,
2050 &_vmentry_control) < 0)
002c7f7c 2051 return -EIO;
6aa8b732 2052
c73da3fc
SC		 2053 /*
2054 * Some cpus support VM_{ENTRY,EXIT}_IA32_PERF_GLOBAL_CTRL but they
2055 * can't be used due to an errata where VM Exit may incorrectly clear
2056 * IA32_PERF_GLOBAL_CTRL[34:32]. Workaround the errata by using the
2057 * MSR load mechanism to switch IA32_PERF_GLOBAL_CTRL.
2058 */
2059 if (boot_cpu_data.x86 == 0x6) {
2060 switch (boot_cpu_data.x86_model) {
2061 case 26: /* AAK155 */
2062 case 30: /* AAP115 */
2063 case 37: /* AAT100 */
2064 case 44: /* BC86,AAY89,BD102 */
2065 case 46: /* BA97 */
2066 _vmexit_control &= ~VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL;
2067 _vmexit_control &= ~VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL;
2068 pr_warn_once("kvm: VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL "
2069 "does not work properly. Using workaround\n");
2070 break;
2071 default:
2072 break;
2073 }
2074 }
2075
2076
c68876fd 2077 rdmsr(MSR_IA32_VMX_BASIC, vmx_msr_low, vmx_msr_high);
1c3d14fe
YS		 2078
2079 /* IA-32 SDM Vol 3B: VMCS size is never greater than 4kB. */
2080 if ((vmx_msr_high & 0x1fff) > PAGE_SIZE)
002c7f7c 2081 return -EIO;
1c3d14fe
YS		 2082
2083#ifdef CONFIG_X86_64
2084 /* IA-32 SDM Vol 3B: 64-bit CPUs always have VMX_BASIC_MSR[48]==0. */
2085 if (vmx_msr_high & (1u<<16))
002c7f7c 2086 return -EIO;
1c3d14fe
YS		 2087#endif
2088
2089 /* Require Write-Back (WB) memory type for VMCS accesses. */
2090 if (((vmx_msr_high >> 18) & 15) != 6)
002c7f7c 2091 return -EIO;
1c3d14fe 2092
002c7f7c 2093 vmcs_conf->size = vmx_msr_high & 0x1fff;
16cb0255 2094 vmcs_conf->order = get_order(vmcs_conf->size);
9ac7e3e8 2095 vmcs_conf->basic_cap = vmx_msr_high & ~0x1fff;
773e8a04 2096
2307af1c 2097 vmcs_conf->revision_id = vmx_msr_low;
1c3d14fe 2098
002c7f7c
YS		 2099 vmcs_conf->pin_based_exec_ctrl = _pin_based_exec_control;
2100 vmcs_conf->cpu_based_exec_ctrl = _cpu_based_exec_control;
f78e0e2e 2101 vmcs_conf->cpu_based_2nd_exec_ctrl = _cpu_based_2nd_exec_control;
002c7f7c
YS		 2102 vmcs_conf->vmexit_ctrl = _vmexit_control;
2103 vmcs_conf->vmentry_ctrl = _vmentry_control;
1c3d14fe 2104
773e8a04
VK		 2105 if (static_branch_unlikely(&enable_evmcs))
2106 evmcs_sanitize_exec_ctrls(vmcs_conf);
2107
1c3d14fe 2108 return 0;
c68876fd 2109}
6aa8b732 2110
89b0c9f5 2111struct vmcs *alloc_vmcs_cpu(bool shadow, int cpu)
6aa8b732
AK		 2112{
2113 int node = cpu_to_node(cpu);
2114 struct page *pages;
2115 struct vmcs *vmcs;
2116
96db800f 2117 pages = __alloc_pages_node(node, GFP_KERNEL, vmcs_config.order);
6aa8b732
AK		 2118 if (!pages)
2119 return NULL;
2120 vmcs = page_address(pages);
1c3d14fe 2121 memset(vmcs, 0, vmcs_config.size);
2307af1c
LA		 2122
2123 /* KVM supports Enlightened VMCS v1 only */
2124 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2125 vmcs->hdr.revision_id = KVM_EVMCS_VERSION;
2307af1c 2126 else
392b2f25 2127 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2128
491a6038
LA		 2129 if (shadow)
2130 vmcs->hdr.shadow_vmcs = 1;
6aa8b732
AK		 2131 return vmcs;
2132}
2133
89b0c9f5 2134void free_vmcs(struct vmcs *vmcs)
6aa8b732 2135{
1c3d14fe 2136 free_pages((unsigned long)vmcs, vmcs_config.order);
6aa8b732
AK		 2137}
2138
d462b819
NHE		 2139/*
2140 * Free a VMCS, but before that VMCLEAR it on the CPU where it was last loaded
2141 */
89b0c9f5 2142void free_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
d462b819
NHE		 2143{
2144 if (!loaded_vmcs->vmcs)
2145 return;
2146 loaded_vmcs_clear(loaded_vmcs);
2147 free_vmcs(loaded_vmcs->vmcs);
2148 loaded_vmcs->vmcs = NULL;
904e14fb
PB		 2149 if (loaded_vmcs->msr_bitmap)
2150 free_page((unsigned long)loaded_vmcs->msr_bitmap);
355f4fb1 2151 WARN_ON(loaded_vmcs->shadow_vmcs != NULL);
d462b819
NHE		 2152}
2153
89b0c9f5 2154int alloc_loaded_vmcs(struct loaded_vmcs *loaded_vmcs)
f21f165e 2155{
491a6038 2156 loaded_vmcs->vmcs = alloc_vmcs(false);
f21f165e
PB		 2157 if (!loaded_vmcs->vmcs)
2158 return -ENOMEM;
2159
2160 loaded_vmcs->shadow_vmcs = NULL;
2161 loaded_vmcs_init(loaded_vmcs);
904e14fb
PB		 2162
2163 if (cpu_has_vmx_msr_bitmap()) {
2164 loaded_vmcs->msr_bitmap = (unsigned long *)__get_free_page(GFP_KERNEL);
2165 if (!loaded_vmcs->msr_bitmap)
2166 goto out_vmcs;
2167 memset(loaded_vmcs->msr_bitmap, 0xff, PAGE_SIZE);
ceef7d10 2168
1f008e11
AB		 2169 if (IS_ENABLED(CONFIG_HYPERV) &&
2170 static_branch_unlikely(&enable_evmcs) &&
ceef7d10
VK		 2171 (ms_hyperv.nested_features & HV_X64_NESTED_MSR_BITMAP)) {
2172 struct hv_enlightened_vmcs *evmcs =
2173 (struct hv_enlightened_vmcs *)loaded_vmcs->vmcs;
2174
2175 evmcs->hv_enlightenments_control.msr_bitmap = 1;
2176 }
904e14fb 2177 }
d7ee039e
SC		 2178
2179 memset(&loaded_vmcs->host_state, 0, sizeof(struct vmcs_host_state));
2180
f21f165e 2181 return 0;
904e14fb
PB		 2182
2183out_vmcs:
2184 free_loaded_vmcs(loaded_vmcs);
2185 return -ENOMEM;
f21f165e
PB		 2186}
2187
39959588 2188static void free_kvm_area(void)
6aa8b732
AK		 2189{
2190 int cpu;
2191
3230bb47 2192 for_each_possible_cpu(cpu) {
6aa8b732 2193 free_vmcs(per_cpu(vmxarea, cpu));
3230bb47
ZA		 2194 per_cpu(vmxarea, cpu) = NULL;
2195 }
6aa8b732
AK		 2196}
2197
6aa8b732
AK		 2198static __init int alloc_kvm_area(void)
2199{
2200 int cpu;
2201
3230bb47 2202 for_each_possible_cpu(cpu) {
6aa8b732
AK		 2203 struct vmcs *vmcs;
2204
491a6038 2205 vmcs = alloc_vmcs_cpu(false, cpu);
6aa8b732
AK		 2206 if (!vmcs) {
2207 free_kvm_area();
2208 return -ENOMEM;
2209 }
2210
2307af1c
LA		 2211 /*
2212 * When eVMCS is enabled, alloc_vmcs_cpu() sets
2213 * vmcs->revision_id to KVM_EVMCS_VERSION instead of
2214 * revision_id reported by MSR_IA32_VMX_BASIC.
2215 *
2216 * However, even though not explictly documented by
2217 * TLFS, VMXArea passed as VMXON argument should
2218 * still be marked with revision_id reported by
2219 * physical CPU.
2220 */
2221 if (static_branch_unlikely(&enable_evmcs))
392b2f25 2222 vmcs->hdr.revision_id = vmcs_config.revision_id;
2307af1c 2223
6aa8b732
AK		 2224 per_cpu(vmxarea, cpu) = vmcs;
2225 }
2226 return 0;
2227}
2228
91b0aa2c 2229static void fix_pmode_seg(struct kvm_vcpu *vcpu, int seg,
d99e4152 2230 struct kvm_segment *save)
6aa8b732 2231{
d99e4152
GN		 2232 if (!emulate_invalid_guest_state) {
2233 /*
2234 * CS and SS RPL should be equal during guest entry according
2235 * to VMX spec, but in reality it is not always so. Since vcpu
2236 * is in the middle of the transition from real mode to
2237 * protected mode it is safe to assume that RPL 0 is a good
2238 * default value.
2239 */
2240 if (seg == VCPU_SREG_CS || seg == VCPU_SREG_SS)
b32a9918
NA		 2241 save->selector &= ~SEGMENT_RPL_MASK;
2242 save->dpl = save->selector & SEGMENT_RPL_MASK;
d99e4152 2243 save->s = 1;
6aa8b732 2244 }
d99e4152 2245 vmx_set_segment(vcpu, save, seg);
6aa8b732
AK		 2246}
2247
2248static void enter_pmode(struct kvm_vcpu *vcpu)
2249{
2250 unsigned long flags;
a89a8fb9 2251 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732 2252
d99e4152
GN		 2253 /*
2254 * Update real mode segment cache. It may be not up-to-date if sement
2255 * register was written while vcpu was in a guest mode.
2256 */
2257 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2258 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2259 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2260 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
2261 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2262 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
2263
7ffd92c5 2264 vmx->rmode.vm86_active = 0;
6aa8b732 2265
2fb92db1
AK		 2266 vmx_segment_cache_clear(vmx);
2267
f5f7b2fe 2268 vmx_set_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
6aa8b732
AK		 2269
2270 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47
AK		 2271 flags &= RMODE_GUEST_OWNED_EFLAGS_BITS;
2272 flags |= vmx->rmode.save_rflags & ~RMODE_GUEST_OWNED_EFLAGS_BITS;
6aa8b732
AK		 2273 vmcs_writel(GUEST_RFLAGS, flags);
2274
66aee91a
RR		 2275 vmcs_writel(GUEST_CR4, (vmcs_readl(GUEST_CR4) & ~X86_CR4_VME) |
2276 (vmcs_readl(CR4_READ_SHADOW) & X86_CR4_VME));
6aa8b732
AK		 2277
2278 update_exception_bitmap(vcpu);
2279
91b0aa2c
GN		 2280 fix_pmode_seg(vcpu, VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2281 fix_pmode_seg(vcpu, VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2282 fix_pmode_seg(vcpu, VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2283 fix_pmode_seg(vcpu, VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2284 fix_pmode_seg(vcpu, VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
2285 fix_pmode_seg(vcpu, VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
6aa8b732
AK		 2286}
2287
f5f7b2fe 2288static void fix_rmode_seg(int seg, struct kvm_segment *save)
6aa8b732 2289{
772e0318 2290 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
d99e4152
GN		 2291 struct kvm_segment var = *save;
2292
2293 var.dpl = 0x3;
2294 if (seg == VCPU_SREG_CS)
2295 var.type = 0x3;
2296
2297 if (!emulate_invalid_guest_state) {
2298 var.selector = var.base >> 4;
2299 var.base = var.base & 0xffff0;
2300 var.limit = 0xffff;
2301 var.g = 0;
2302 var.db = 0;
2303 var.present = 1;
2304 var.s = 1;
2305 var.l = 0;
2306 var.unusable = 0;
2307 var.type = 0x3;
2308 var.avl = 0;
2309 if (save->base & 0xf)
2310 printk_once(KERN_WARNING "kvm: segment base is not "
2311 "paragraph aligned when entering "
2312 "protected mode (seg=%d)", seg);
2313 }
6aa8b732 2314
d99e4152 2315 vmcs_write16(sf->selector, var.selector);
96794e4e 2316 vmcs_writel(sf->base, var.base);
d99e4152
GN		 2317 vmcs_write32(sf->limit, var.limit);
2318 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(&var));
6aa8b732
AK		 2319}
2320
2321static void enter_rmode(struct kvm_vcpu *vcpu)
2322{
2323 unsigned long flags;
a89a8fb9 2324 struct vcpu_vmx *vmx = to_vmx(vcpu);
40bbb9d0 2325 struct kvm_vmx *kvm_vmx = to_kvm_vmx(vcpu->kvm);
6aa8b732 2326
f5f7b2fe
AK		 2327 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_TR], VCPU_SREG_TR);
2328 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_ES], VCPU_SREG_ES);
2329 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_DS], VCPU_SREG_DS);
2330 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_FS], VCPU_SREG_FS);
2331 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_GS], VCPU_SREG_GS);
c6ad1153
GN		 2332 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_SS], VCPU_SREG_SS);
2333 vmx_get_segment(vcpu, &vmx->rmode.segs[VCPU_SREG_CS], VCPU_SREG_CS);
f5f7b2fe 2334
7ffd92c5 2335 vmx->rmode.vm86_active = 1;
6aa8b732 2336
776e58ea
GN		 2337 /*
2338 * Very old userspace does not call KVM_SET_TSS_ADDR before entering
4918c6ca 2339 * vcpu. Warn the user that an update is overdue.
776e58ea 2340 */
40bbb9d0 2341 if (!kvm_vmx->tss_addr)
776e58ea
GN		 2342 printk_once(KERN_WARNING "kvm: KVM_SET_TSS_ADDR need to be "
2343 "called before entering vcpu\n");
776e58ea 2344
2fb92db1
AK		 2345 vmx_segment_cache_clear(vmx);
2346
40bbb9d0 2347 vmcs_writel(GUEST_TR_BASE, kvm_vmx->tss_addr);
6aa8b732 2348 vmcs_write32(GUEST_TR_LIMIT, RMODE_TSS_SIZE - 1);
6aa8b732
AK		 2349 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
2350
2351 flags = vmcs_readl(GUEST_RFLAGS);
78ac8b47 2352 vmx->rmode.save_rflags = flags;
6aa8b732 2353
053de044 2354 flags |= X86_EFLAGS_IOPL | X86_EFLAGS_VM;
6aa8b732
AK		 2355
2356 vmcs_writel(GUEST_RFLAGS, flags);
66aee91a 2357 vmcs_writel(GUEST_CR4, vmcs_readl(GUEST_CR4) | X86_CR4_VME);
6aa8b732
AK		 2358 update_exception_bitmap(vcpu);
2359
d99e4152
GN		 2360 fix_rmode_seg(VCPU_SREG_SS, &vmx->rmode.segs[VCPU_SREG_SS]);
2361 fix_rmode_seg(VCPU_SREG_CS, &vmx->rmode.segs[VCPU_SREG_CS]);
2362 fix_rmode_seg(VCPU_SREG_ES, &vmx->rmode.segs[VCPU_SREG_ES]);
2363 fix_rmode_seg(VCPU_SREG_DS, &vmx->rmode.segs[VCPU_SREG_DS]);
2364 fix_rmode_seg(VCPU_SREG_GS, &vmx->rmode.segs[VCPU_SREG_GS]);
2365 fix_rmode_seg(VCPU_SREG_FS, &vmx->rmode.segs[VCPU_SREG_FS]);
b246dd5d 2366
8668a3c4 2367 kvm_mmu_reset_context(vcpu);
6aa8b732
AK		 2368}
2369
97b7ead3 2370void vmx_set_efer(struct kvm_vcpu *vcpu, u64 efer)
401d10de
AS		 2371{
2372 struct vcpu_vmx *vmx = to_vmx(vcpu);
26bb0981
AK		 2373 struct shared_msr_entry *msr = find_msr_entry(vmx, MSR_EFER);
2374
2375 if (!msr)
2376 return;
401d10de 2377
f6801dff 2378 vcpu->arch.efer = efer;
401d10de 2379 if (efer & EFER_LMA) {
2961e876 2380 vm_entry_controls_setbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2381 msr->data = efer;
2382 } else {
2961e876 2383 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
401d10de
AS		 2384
2385 msr->data = efer & ~EFER_LME;
2386 }
2387 setup_msrs(vmx);
2388}
2389
05b3e0c2 2390#ifdef CONFIG_X86_64
6aa8b732
AK		 2391
2392static void enter_lmode(struct kvm_vcpu *vcpu)
2393{
2394 u32 guest_tr_ar;
2395
2fb92db1
AK		 2396 vmx_segment_cache_clear(to_vmx(vcpu));
2397
6aa8b732 2398 guest_tr_ar = vmcs_read32(GUEST_TR_AR_BYTES);
4d283ec9 2399 if ((guest_tr_ar & VMX_AR_TYPE_MASK) != VMX_AR_TYPE_BUSY_64_TSS) {
bd80158a
JK		 2400 pr_debug_ratelimited("%s: tss fixup for long mode. \n",
2401 __func__);
6aa8b732 2402 vmcs_write32(GUEST_TR_AR_BYTES,
4d283ec9
AL		 2403 (guest_tr_ar & ~VMX_AR_TYPE_MASK)
2404 | VMX_AR_TYPE_BUSY_64_TSS);
6aa8b732 2405 }
da38f438 2406 vmx_set_efer(vcpu, vcpu->arch.efer | EFER_LMA);
6aa8b732
AK		 2407}
2408
2409static void exit_lmode(struct kvm_vcpu *vcpu)
2410{
2961e876 2411 vm_entry_controls_clearbit(to_vmx(vcpu), VM_ENTRY_IA32E_MODE);
da38f438 2412 vmx_set_efer(vcpu, vcpu->arch.efer & ~EFER_LMA);
6aa8b732
AK		 2413}
2414
2415#endif
2416
faff8758
JS		 2417static void vmx_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t addr)
2418{
2419 int vpid = to_vmx(vcpu)->vpid;
2420
2421 if (!vpid_sync_vcpu_addr(vpid, addr))
2422 vpid_sync_context(vpid);
2423
2424 /*
2425 * If VPIDs are not supported or enabled, then the above is a no-op.
2426 * But we don't really need a TLB flush in that case anyway, because
2427 * each VM entry/exit includes an implicit flush when VPID is 0.
2428 */
2429}
2430
e8467fda
AK		 2431static void vmx_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
2432{
2433 ulong cr0_guest_owned_bits = vcpu->arch.cr0_guest_owned_bits;
2434
2435 vcpu->arch.cr0 &= ~cr0_guest_owned_bits;
2436 vcpu->arch.cr0 |= vmcs_readl(GUEST_CR0) & cr0_guest_owned_bits;
2437}
2438
aff48baa
AK		 2439static void vmx_decache_cr3(struct kvm_vcpu *vcpu)
2440{
b4d18517 2441 if (enable_unrestricted_guest || (enable_ept && is_paging(vcpu)))
aff48baa
AK		 2442 vcpu->arch.cr3 = vmcs_readl(GUEST_CR3);
2443 __set_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail);
2444}
2445
25c4c276 2446static void vmx_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
399badf3 2447{
fc78f519
AK		 2448 ulong cr4_guest_owned_bits = vcpu->arch.cr4_guest_owned_bits;
2449
2450 vcpu->arch.cr4 &= ~cr4_guest_owned_bits;
2451 vcpu->arch.cr4 |= vmcs_readl(GUEST_CR4) & cr4_guest_owned_bits;
399badf3
AK		 2452}
2453
1439442c
SY		 2454static void ept_load_pdptrs(struct kvm_vcpu *vcpu)
2455{
d0d538b9
GN		 2456 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2457
6de4f3ad
AK		 2458 if (!test_bit(VCPU_EXREG_PDPTR,
2459 (unsigned long *)&vcpu->arch.regs_dirty))
2460 return;
2461
1439442c 2462 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 2463 vmcs_write64(GUEST_PDPTR0, mmu->pdptrs[0]);
2464 vmcs_write64(GUEST_PDPTR1, mmu->pdptrs[1]);
2465 vmcs_write64(GUEST_PDPTR2, mmu->pdptrs[2]);
2466 vmcs_write64(GUEST_PDPTR3, mmu->pdptrs[3]);
1439442c
SY		 2467 }
2468}
2469
97b7ead3 2470void ept_save_pdptrs(struct kvm_vcpu *vcpu)
8f5d549f 2471{
d0d538b9
GN		 2472 struct kvm_mmu *mmu = vcpu->arch.walk_mmu;
2473
8f5d549f 2474 if (is_paging(vcpu) && is_pae(vcpu) && !is_long_mode(vcpu)) {
d0d538b9
GN		 2475 mmu->pdptrs[0] = vmcs_read64(GUEST_PDPTR0);
2476 mmu->pdptrs[1] = vmcs_read64(GUEST_PDPTR1);
2477 mmu->pdptrs[2] = vmcs_read64(GUEST_PDPTR2);
2478 mmu->pdptrs[3] = vmcs_read64(GUEST_PDPTR3);
8f5d549f 2479 }
6de4f3ad
AK		 2480
2481 __set_bit(VCPU_EXREG_PDPTR,
2482 (unsigned long *)&vcpu->arch.regs_avail);
2483 __set_bit(VCPU_EXREG_PDPTR,
2484 (unsigned long *)&vcpu->arch.regs_dirty);
8f5d549f
AK		 2485}
2486
1439442c
SY		 2487static void ept_update_paging_mode_cr0(unsigned long *hw_cr0,
2488 unsigned long cr0,
2489 struct kvm_vcpu *vcpu)
2490{
5233dd51
MT		 2491 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
2492 vmx_decache_cr3(vcpu);
1439442c
SY		 2493 if (!(cr0 & X86_CR0_PG)) {
2494 /* From paging/starting to nonpaging */
2495 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2496 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) |
1439442c
SY		 2497 (CPU_BASED_CR3_LOAD_EXITING |
2498 CPU_BASED_CR3_STORE_EXITING));
2499 vcpu->arch.cr0 = cr0;
fc78f519 2500 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c
SY		 2501 } else if (!is_paging(vcpu)) {
2502 /* From nonpaging to paging */
2503 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL,
65267ea1 2504 vmcs_read32(CPU_BASED_VM_EXEC_CONTROL) &
1439442c
SY		 2505 ~(CPU_BASED_CR3_LOAD_EXITING |
2506 CPU_BASED_CR3_STORE_EXITING));
2507 vcpu->arch.cr0 = cr0;
fc78f519 2508 vmx_set_cr4(vcpu, kvm_read_cr4(vcpu));
1439442c 2509 }
95eb84a7
SY		 2510
2511 if (!(cr0 & X86_CR0_WP))
2512 *hw_cr0 &= ~X86_CR0_WP;
1439442c
SY		 2513}
2514
97b7ead3 2515void vmx_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
6aa8b732 2516{
7ffd92c5 2517 struct vcpu_vmx *vmx = to_vmx(vcpu);
3a624e29
NK		 2518 unsigned long hw_cr0;
2519
3de6347b 2520 hw_cr0 = (cr0 & ~KVM_VM_CR0_ALWAYS_OFF);
3a624e29 2521 if (enable_unrestricted_guest)
5037878e 2522 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON_UNRESTRICTED_GUEST;
218e763f 2523 else {
5037878e 2524 hw_cr0 |= KVM_VM_CR0_ALWAYS_ON;
1439442c 2525
218e763f
GN		 2526 if (vmx->rmode.vm86_active && (cr0 & X86_CR0_PE))
2527 enter_pmode(vcpu);
6aa8b732 2528
218e763f
GN		 2529 if (!vmx->rmode.vm86_active && !(cr0 & X86_CR0_PE))
2530 enter_rmode(vcpu);
2531 }
6aa8b732 2532
05b3e0c2 2533#ifdef CONFIG_X86_64
f6801dff 2534 if (vcpu->arch.efer & EFER_LME) {
707d92fa 2535 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG))
6aa8b732 2536 enter_lmode(vcpu);
707d92fa 2537 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG))
6aa8b732
AK		 2538 exit_lmode(vcpu);
2539 }
2540#endif
2541
b4d18517 2542 if (enable_ept && !enable_unrestricted_guest)
1439442c
SY		 2543 ept_update_paging_mode_cr0(&hw_cr0, cr0, vcpu);
2544
6aa8b732 2545 vmcs_writel(CR0_READ_SHADOW, cr0);
1439442c 2546 vmcs_writel(GUEST_CR0, hw_cr0);
ad312c7c 2547 vcpu->arch.cr0 = cr0;
14168786
GN		 2548
2549 /* depends on vcpu->arch.cr0 to be set to a new value */
2550 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 2551}
2552
855feb67
YZ		 2553static int get_ept_level(struct kvm_vcpu *vcpu)
2554{
2555 if (cpu_has_vmx_ept_5levels() && (cpuid_maxphyaddr(vcpu) > 48))
2556 return 5;
2557 return 4;
2558}
2559
89b0c9f5 2560u64 construct_eptp(struct kvm_vcpu *vcpu, unsigned long root_hpa)
1439442c 2561{
855feb67
YZ		 2562 u64 eptp = VMX_EPTP_MT_WB;
2563
2564 eptp |= (get_ept_level(vcpu) == 5) ? VMX_EPTP_PWL_5 : VMX_EPTP_PWL_4;
1439442c 2565
995f00a6
PF		 2566 if (enable_ept_ad_bits &&
2567 (!is_guest_mode(vcpu) || nested_ept_ad_enabled(vcpu)))
bb97a016 2568 eptp |= VMX_EPTP_AD_ENABLE_BIT;
1439442c
SY		 2569 eptp |= (root_hpa & PAGE_MASK);
2570
2571 return eptp;
2572}
2573
97b7ead3 2574void vmx_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
6aa8b732 2575{
877ad952 2576 struct kvm *kvm = vcpu->kvm;
1439442c
SY		 2577 unsigned long guest_cr3;
2578 u64 eptp;
2579
2580 guest_cr3 = cr3;
089d034e 2581 if (enable_ept) {
995f00a6 2582 eptp = construct_eptp(vcpu, cr3);
1439442c 2583 vmcs_write64(EPT_POINTER, eptp);
877ad952
TL		 2584
2585 if (kvm_x86_ops->tlb_remote_flush) {
2586 spin_lock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2587 to_vmx(vcpu)->ept_pointer = eptp;
2588 to_kvm_vmx(kvm)->ept_pointers_match
2589 = EPT_POINTERS_CHECK;
2590 spin_unlock(&to_kvm_vmx(kvm)->ept_pointer_lock);
2591 }
2592
e90008df
SC		 2593 if (enable_unrestricted_guest || is_paging(vcpu) ||
2594 is_guest_mode(vcpu))
59ab5a8f
JK		 2595 guest_cr3 = kvm_read_cr3(vcpu);
2596 else
877ad952 2597 guest_cr3 = to_kvm_vmx(kvm)->ept_identity_map_addr;
7c93be44 2598 ept_load_pdptrs(vcpu);
1439442c
SY		 2599 }
2600
1439442c 2601 vmcs_writel(GUEST_CR3, guest_cr3);
6aa8b732
AK		 2602}
2603
97b7ead3 2604int vmx_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
6aa8b732 2605{
085e68ee
BS		 2606 /*
2607 * Pass through host's Machine Check Enable value to hw_cr4, which
2608 * is in force while we are in guest mode. Do not let guests control
2609 * this bit, even if host CR4.MCE == 0.
2610 */
5dc1f044
SC		 2611 unsigned long hw_cr4;
2612
2613 hw_cr4 = (cr4_read_shadow() & X86_CR4_MCE) | (cr4 & ~X86_CR4_MCE);
2614 if (enable_unrestricted_guest)
2615 hw_cr4 |= KVM_VM_CR4_ALWAYS_ON_UNRESTRICTED_GUEST;
2616 else if (to_vmx(vcpu)->rmode.vm86_active)
2617 hw_cr4 |= KVM_RMODE_VM_CR4_ALWAYS_ON;
2618 else
2619 hw_cr4 |= KVM_PMODE_VM_CR4_ALWAYS_ON;
1439442c 2620
64f7a115
SC		 2621 if (!boot_cpu_has(X86_FEATURE_UMIP) && vmx_umip_emulated()) {
2622 if (cr4 & X86_CR4_UMIP) {
2623 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
0367f205 2624 SECONDARY_EXEC_DESC);
64f7a115
SC		 2625 hw_cr4 &= ~X86_CR4_UMIP;
2626 } else if (!is_guest_mode(vcpu) ||
2627 !nested_cpu_has2(get_vmcs12(vcpu), SECONDARY_EXEC_DESC))
2628 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
2629 SECONDARY_EXEC_DESC);
2630 }
0367f205 2631
5e1746d6
NHE		 2632 if (cr4 & X86_CR4_VMXE) {
2633 /*
2634 * To use VMXON (and later other VMX instructions), a guest
2635 * must first be able to turn on cr4.VMXE (see handle_vmon()).
2636 * So basically the check on whether to allow nested VMX
5bea5123
PB		 2637 * is here. We operate under the default treatment of SMM,
2638 * so VMX cannot be enabled under SMM.
5e1746d6 2639 */
5bea5123 2640 if (!nested_vmx_allowed(vcpu) || is_smm(vcpu))
5e1746d6 2641 return 1;
1a0d74e6 2642 }
3899152c
DM		 2643
2644 if (to_vmx(vcpu)->nested.vmxon && !nested_cr4_valid(vcpu, cr4))
5e1746d6
NHE		 2645 return 1;
2646
ad312c7c 2647 vcpu->arch.cr4 = cr4;
5dc1f044
SC		 2648
2649 if (!enable_unrestricted_guest) {
2650 if (enable_ept) {
2651 if (!is_paging(vcpu)) {
2652 hw_cr4 &= ~X86_CR4_PAE;
2653 hw_cr4 |= X86_CR4_PSE;
2654 } else if (!(cr4 & X86_CR4_PAE)) {
2655 hw_cr4 &= ~X86_CR4_PAE;
2656 }
bc23008b 2657 }
1439442c 2658
656ec4a4 2659 /*
ddba2628
HH		 2660 * SMEP/SMAP/PKU is disabled if CPU is in non-paging mode in
2661 * hardware. To emulate this behavior, SMEP/SMAP/PKU needs
2662 * to be manually disabled when guest switches to non-paging
2663 * mode.
2664 *
2665 * If !enable_unrestricted_guest, the CPU is always running
2666 * with CR0.PG=1 and CR4 needs to be modified.
2667 * If enable_unrestricted_guest, the CPU automatically
2668 * disables SMEP/SMAP/PKU when the guest sets CR0.PG=0.
656ec4a4 2669 */
5dc1f044
SC		 2670 if (!is_paging(vcpu))
2671 hw_cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
2672 }
656ec4a4 2673
1439442c
SY		 2674 vmcs_writel(CR4_READ_SHADOW, cr4);
2675 vmcs_writel(GUEST_CR4, hw_cr4);
5e1746d6 2676 return 0;
6aa8b732
AK		 2677}
2678
97b7ead3 2679void vmx_get_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
6aa8b732 2680{
a9179499 2681 struct vcpu_vmx *vmx = to_vmx(vcpu);
6aa8b732
AK		 2682 u32 ar;
2683
c6ad1153 2684 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
f5f7b2fe 2685 *var = vmx->rmode.segs[seg];
a9179499 2686 if (seg == VCPU_SREG_TR
2fb92db1 2687 || var->selector == vmx_read_guest_seg_selector(vmx, seg))
f5f7b2fe 2688 return;
1390a28b
AK		 2689 var->base = vmx_read_guest_seg_base(vmx, seg);
2690 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2691 return;
a9179499 2692 }
2fb92db1
AK		 2693 var->base = vmx_read_guest_seg_base(vmx, seg);
2694 var->limit = vmx_read_guest_seg_limit(vmx, seg);
2695 var->selector = vmx_read_guest_seg_selector(vmx, seg);
2696 ar = vmx_read_guest_seg_ar(vmx, seg);
03617c18 2697 var->unusable = (ar >> 16) & 1;
6aa8b732
AK		 2698 var->type = ar & 15;
2699 var->s = (ar >> 4) & 1;
2700 var->dpl = (ar >> 5) & 3;
03617c18
GN		 2701 /*
2702 * Some userspaces do not preserve unusable property. Since usable
2703 * segment has to be present according to VMX spec we can use present
2704 * property to amend userspace bug by making unusable segment always
2705 * nonpresent. vmx_segment_access_rights() already marks nonpresent
2706 * segment as unusable.
2707 */
2708 var->present = !var->unusable;
6aa8b732
AK		 2709 var->avl = (ar >> 12) & 1;
2710 var->l = (ar >> 13) & 1;
2711 var->db = (ar >> 14) & 1;
2712 var->g = (ar >> 15) & 1;
6aa8b732
AK		 2713}
2714
a9179499
AK		 2715static u64 vmx_get_segment_base(struct kvm_vcpu *vcpu, int seg)
2716{
a9179499
AK		 2717 struct kvm_segment s;
2718
2719 if (to_vmx(vcpu)->rmode.vm86_active) {
2720 vmx_get_segment(vcpu, &s, seg);
2721 return s.base;
2722 }
2fb92db1 2723 return vmx_read_guest_seg_base(to_vmx(vcpu), seg);
a9179499
AK		 2724}
2725
97b7ead3 2726int vmx_get_cpl(struct kvm_vcpu *vcpu)
2e4d2653 2727{
b09408d0
MT		 2728 struct vcpu_vmx *vmx = to_vmx(vcpu);
2729
ae9fedc7 2730 if (unlikely(vmx->rmode.vm86_active))
2e4d2653 2731 return 0;
ae9fedc7
PB		 2732 else {
2733 int ar = vmx_read_guest_seg_ar(vmx, VCPU_SREG_SS);
4d283ec9 2734 return VMX_AR_DPL(ar);
69c73028 2735 }
69c73028
AK		 2736}
2737
653e3108 2738static u32 vmx_segment_access_rights(struct kvm_segment *var)
6aa8b732 2739{
6aa8b732
AK		 2740 u32 ar;
2741
f0495f9b 2742 if (var->unusable || !var->present)
6aa8b732
AK		 2743 ar = 1 << 16;
2744 else {
2745 ar = var->type & 15;
2746 ar |= (var->s & 1) << 4;
2747 ar |= (var->dpl & 3) << 5;
2748 ar |= (var->present & 1) << 7;
2749 ar |= (var->avl & 1) << 12;
2750 ar |= (var->l & 1) << 13;
2751 ar |= (var->db & 1) << 14;
2752 ar |= (var->g & 1) << 15;
2753 }
653e3108
AK		 2754
2755 return ar;
2756}
2757
97b7ead3 2758void vmx_set_segment(struct kvm_vcpu *vcpu, struct kvm_segment *var, int seg)
653e3108 2759{
7ffd92c5 2760 struct vcpu_vmx *vmx = to_vmx(vcpu);
772e0318 2761 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
653e3108 2762
2fb92db1
AK		 2763 vmx_segment_cache_clear(vmx);
2764
1ecd50a9
GN		 2765 if (vmx->rmode.vm86_active && seg != VCPU_SREG_LDTR) {
2766 vmx->rmode.segs[seg] = *var;
2767 if (seg == VCPU_SREG_TR)
2768 vmcs_write16(sf->selector, var->selector);
2769 else if (var->s)
2770 fix_rmode_seg(seg, &vmx->rmode.segs[seg]);
d99e4152 2771 goto out;
653e3108 2772 }
1ecd50a9 2773
653e3108
AK		 2774 vmcs_writel(sf->base, var->base);
2775 vmcs_write32(sf->limit, var->limit);
2776 vmcs_write16(sf->selector, var->selector);
3a624e29
NK		 2777
2778 /*
2779 * Fix the "Accessed" bit in AR field of segment registers for older
2780 * qemu binaries.
2781 * IA32 arch specifies that at the time of processor reset the
2782 * "Accessed" bit in the AR field of segment registers is 1. And qemu
0fa06071 2783 * is setting it to 0 in the userland code. This causes invalid guest
3a624e29
NK		 2784 * state vmexit when "unrestricted guest" mode is turned on.
2785 * Fix for this setup issue in cpu_reset is being pushed in the qemu
2786 * tree. Newer qemu binaries with that qemu fix would not need this
2787 * kvm hack.
2788 */
2789 if (enable_unrestricted_guest && (seg != VCPU_SREG_LDTR))
f924d66d 2790 var->type |= 0x1; /* Accessed */
3a624e29 2791
f924d66d 2792 vmcs_write32(sf->ar_bytes, vmx_segment_access_rights(var));
d99e4152
GN		 2793
2794out:
98eb2f8b 2795 vmx->emulation_required = emulation_required(vcpu);
6aa8b732
AK		 2796}
2797
6aa8b732
AK		 2798static void vmx_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
2799{
2fb92db1 2800 u32 ar = vmx_read_guest_seg_ar(to_vmx(vcpu), VCPU_SREG_CS);
6aa8b732
AK		 2801
2802 *db = (ar >> 14) & 1;
2803 *l = (ar >> 13) & 1;
2804}
2805
89a27f4d 2806static void vmx_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2807{
89a27f4d
GN		 2808 dt->size = vmcs_read32(GUEST_IDTR_LIMIT);
2809 dt->address = vmcs_readl(GUEST_IDTR_BASE);
6aa8b732
AK		 2810}
2811
89a27f4d 2812static void vmx_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2813{
89a27f4d
GN		 2814 vmcs_write32(GUEST_IDTR_LIMIT, dt->size);
2815 vmcs_writel(GUEST_IDTR_BASE, dt->address);
6aa8b732
AK		 2816}
2817
89a27f4d 2818static void vmx_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2819{
89a27f4d
GN		 2820 dt->size = vmcs_read32(GUEST_GDTR_LIMIT);
2821 dt->address = vmcs_readl(GUEST_GDTR_BASE);
6aa8b732
AK		 2822}
2823
89a27f4d 2824static void vmx_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
6aa8b732 2825{
89a27f4d
GN		 2826 vmcs_write32(GUEST_GDTR_LIMIT, dt->size);
2827 vmcs_writel(GUEST_GDTR_BASE, dt->address);
6aa8b732
AK		 2828}
2829
648dfaa7
MG		 2830static bool rmode_segment_valid(struct kvm_vcpu *vcpu, int seg)
2831{
2832 struct kvm_segment var;
2833 u32 ar;
2834
2835 vmx_get_segment(vcpu, &var, seg);
07f42f5f 2836 var.dpl = 0x3;
0647f4aa
GN		 2837 if (seg == VCPU_SREG_CS)
2838 var.type = 0x3;
648dfaa7
MG		 2839 ar = vmx_segment_access_rights(&var);
2840
2841 if (var.base != (var.selector << 4))
2842 return false;
89efbed0 2843 if (var.limit != 0xffff)
648dfaa7 2844 return false;
07f42f5f 2845 if (ar != 0xf3)
648dfaa7
MG		 2846 return false;
2847
2848 return true;
2849}
2850
2851static bool code_segment_valid(struct kvm_vcpu *vcpu)
2852{
2853 struct kvm_segment cs;
2854 unsigned int cs_rpl;
2855
2856 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
b32a9918 2857 cs_rpl = cs.selector & SEGMENT_RPL_MASK;
648dfaa7 2858
1872a3f4
AK		 2859 if (cs.unusable)
2860 return false;
4d283ec9 2861 if (~cs.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_ACCESSES_MASK))
648dfaa7
MG		 2862 return false;
2863 if (!cs.s)
2864 return false;
4d283ec9 2865 if (cs.type & VMX_AR_TYPE_WRITEABLE_MASK) {
648dfaa7
MG		 2866 if (cs.dpl > cs_rpl)
2867 return false;
1872a3f4 2868 } else {
648dfaa7
MG		 2869 if (cs.dpl != cs_rpl)
2870 return false;
2871 }
2872 if (!cs.present)
2873 return false;
2874
2875 /* TODO: Add Reserved field check, this'll require a new member in the kvm_segment_field structure */
2876 return true;
2877}
2878
2879static bool stack_segment_valid(struct kvm_vcpu *vcpu)
2880{
2881 struct kvm_segment ss;
2882 unsigned int ss_rpl;
2883
2884 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
b32a9918 2885 ss_rpl = ss.selector & SEGMENT_RPL_MASK;
648dfaa7 2886
1872a3f4
AK		 2887 if (ss.unusable)
2888 return true;
2889 if (ss.type != 3 && ss.type != 7)
648dfaa7
MG		 2890 return false;
2891 if (!ss.s)
2892 return false;
2893 if (ss.dpl != ss_rpl) /* DPL != RPL */
2894 return false;
2895 if (!ss.present)
2896 return false;
2897
2898 return true;
2899}
2900
2901static bool data_segment_valid(struct kvm_vcpu *vcpu, int seg)
2902{
2903 struct kvm_segment var;
2904 unsigned int rpl;
2905
2906 vmx_get_segment(vcpu, &var, seg);
b32a9918 2907 rpl = var.selector & SEGMENT_RPL_MASK;
648dfaa7 2908
1872a3f4
AK		 2909 if (var.unusable)
2910 return true;
648dfaa7
MG		 2911 if (!var.s)
2912 return false;
2913 if (!var.present)
2914 return false;
4d283ec9 2915 if (~var.type & (VMX_AR_TYPE_CODE_MASK|VMX_AR_TYPE_WRITEABLE_MASK)) {
648dfaa7
MG		 2916 if (var.dpl < rpl) /* DPL < RPL */
2917 return false;
2918 }
2919
2920 /* TODO: Add other members to kvm_segment_field to allow checking for other access
2921 * rights flags
2922 */
2923 return true;
2924}
2925
2926static bool tr_valid(struct kvm_vcpu *vcpu)
2927{
2928 struct kvm_segment tr;
2929
2930 vmx_get_segment(vcpu, &tr, VCPU_SREG_TR);
2931
1872a3f4
AK		 2932 if (tr.unusable)
2933 return false;
b32a9918 2934 if (tr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7 2935 return false;
1872a3f4 2936 if (tr.type != 3 && tr.type != 11) /* TODO: Check if guest is in IA32e mode */
648dfaa7
MG		 2937 return false;
2938 if (!tr.present)
2939 return false;
2940
2941 return true;
2942}
2943
2944static bool ldtr_valid(struct kvm_vcpu *vcpu)
2945{
2946 struct kvm_segment ldtr;
2947
2948 vmx_get_segment(vcpu, &ldtr, VCPU_SREG_LDTR);
2949
1872a3f4
AK		 2950 if (ldtr.unusable)
2951 return true;
b32a9918 2952 if (ldtr.selector & SEGMENT_TI_MASK) /* TI = 1 */
648dfaa7
MG		 2953 return false;
2954 if (ldtr.type != 2)
2955 return false;
2956 if (!ldtr.present)
2957 return false;
2958
2959 return true;
2960}
2961
2962static bool cs_ss_rpl_check(struct kvm_vcpu *vcpu)
2963{
2964 struct kvm_segment cs, ss;
2965
2966 vmx_get_segment(vcpu, &cs, VCPU_SREG_CS);
2967 vmx_get_segment(vcpu, &ss, VCPU_SREG_SS);
2968
b32a9918
NA		 2969 return ((cs.selector & SEGMENT_RPL_MASK) ==
2970 (ss.selector & SEGMENT_RPL_MASK));
648dfaa7
MG		 2971}
2972
2973/*
2974 * Check if guest state is valid. Returns true if valid, false if
2975 * not.
2976 * We assume that registers are always usable
2977 */
2978static bool guest_state_valid(struct kvm_vcpu *vcpu)
2979{
c5e97c80
GN		 2980 if (enable_unrestricted_guest)
2981 return true;
2982
648dfaa7 2983 /* real mode guest state checks */
f13882d8 2984 if (!is_protmode(vcpu) || (vmx_get_rflags(vcpu) & X86_EFLAGS_VM)) {
648dfaa7
MG		 2985 if (!rmode_segment_valid(vcpu, VCPU_SREG_CS))
2986 return false;
2987 if (!rmode_segment_valid(vcpu, VCPU_SREG_SS))
2988 return false;
2989 if (!rmode_segment_valid(vcpu, VCPU_SREG_DS))
2990 return false;
2991 if (!rmode_segment_valid(vcpu, VCPU_SREG_ES))
2992 return false;
2993 if (!rmode_segment_valid(vcpu, VCPU_SREG_FS))
2994 return false;
2995 if (!rmode_segment_valid(vcpu, VCPU_SREG_GS))
2996 return false;
2997 } else {
2998 /* protected mode guest state checks */
2999 if (!cs_ss_rpl_check(vcpu))
3000 return false;
3001 if (!code_segment_valid(vcpu))
3002 return false;
3003 if (!stack_segment_valid(vcpu))
3004 return false;
3005 if (!data_segment_valid(vcpu, VCPU_SREG_DS))
3006 return false;
3007 if (!data_segment_valid(vcpu, VCPU_SREG_ES))
3008 return false;
3009 if (!data_segment_valid(vcpu, VCPU_SREG_FS))
3010 return false;
3011 if (!data_segment_valid(vcpu, VCPU_SREG_GS))
3012 return false;
3013 if (!tr_valid(vcpu))
3014 return false;
3015 if (!ldtr_valid(vcpu))
3016 return false;
3017 }
3018 /* TODO:
3019 * - Add checks on RIP
3020 * - Add checks on RFLAGS
3021 */
3022
3023 return true;
3024}
3025
d77c26fc 3026static int init_rmode_tss(struct kvm *kvm)
6aa8b732 3027{
40dcaa9f 3028 gfn_t fn;
195aefde 3029 u16 data = 0;
1f755a82 3030 int idx, r;
6aa8b732 3031
40dcaa9f 3032 idx = srcu_read_lock(&kvm->srcu);
40bbb9d0 3033 fn = to_kvm_vmx(kvm)->tss_addr >> PAGE_SHIFT;
195aefde
IE		 3034 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3035 if (r < 0)
10589a46 3036 goto out;
195aefde 3037 data = TSS_BASE_SIZE + TSS_REDIRECTION_SIZE;
464d17c8
SY		 3038 r = kvm_write_guest_page(kvm, fn++, &data,
3039 TSS_IOPB_BASE_OFFSET, sizeof(u16));
195aefde 3040 if (r < 0)
10589a46 3041 goto out;
195aefde
IE		 3042 r = kvm_clear_guest_page(kvm, fn++, 0, PAGE_SIZE);
3043 if (r < 0)
10589a46 3044 goto out;
195aefde
IE		 3045 r = kvm_clear_guest_page(kvm, fn, 0, PAGE_SIZE);
3046 if (r < 0)
10589a46 3047 goto out;
195aefde 3048 data = ~0;
10589a46
MT		 3049 r = kvm_write_guest_page(kvm, fn, &data,
3050 RMODE_TSS_SIZE - 2 * PAGE_SIZE - 1,
3051 sizeof(u8));
10589a46 3052out:
40dcaa9f 3053 srcu_read_unlock(&kvm->srcu, idx);
1f755a82 3054 return r;
6aa8b732
AK		 3055}
3056
b7ebfb05
SY		 3057static int init_rmode_identity_map(struct kvm *kvm)
3058{
40bbb9d0 3059 struct kvm_vmx *kvm_vmx = to_kvm_vmx(kvm);
f51770ed 3060 int i, idx, r = 0;
ba049e93 3061 kvm_pfn_t identity_map_pfn;
b7ebfb05
SY		 3062 u32 tmp;
3063
40bbb9d0 3064 /* Protect kvm_vmx->ept_identity_pagetable_done. */
a255d479
TC		 3065 mutex_lock(&kvm->slots_lock);
3066
40bbb9d0 3067 if (likely(kvm_vmx->ept_identity_pagetable_done))
a255d479 3068 goto out2;
a255d479 3069
40bbb9d0
SC		 3070 if (!kvm_vmx->ept_identity_map_addr)
3071 kvm_vmx->ept_identity_map_addr = VMX_EPT_IDENTITY_PAGETABLE_ADDR;
3072 identity_map_pfn = kvm_vmx->ept_identity_map_addr >> PAGE_SHIFT;
a255d479 3073
d8a6e365 3074 r = __x86_set_memory_region(kvm, IDENTITY_PAGETABLE_PRIVATE_MEMSLOT,
40bbb9d0 3075 kvm_vmx->ept_identity_map_addr, PAGE_SIZE);
f51770ed 3076 if (r < 0)
a255d479
TC		 3077 goto out2;
3078
40dcaa9f 3079 idx = srcu_read_lock(&kvm->srcu);
b7ebfb05
SY		 3080 r = kvm_clear_guest_page(kvm, identity_map_pfn, 0, PAGE_SIZE);
3081 if (r < 0)
3082 goto out;
3083 /* Set up identity-mapping pagetable for EPT in real mode */
3084 for (i = 0; i < PT32_ENT_PER_PAGE; i++) {
3085 tmp = (i << 22) + (_PAGE_PRESENT | _PAGE_RW | _PAGE_USER |
3086 _PAGE_ACCESSED | _PAGE_DIRTY | _PAGE_PSE);
3087 r = kvm_write_guest_page(kvm, identity_map_pfn,
3088 &tmp, i * sizeof(tmp), sizeof(tmp));
3089 if (r < 0)
3090 goto out;
3091 }
40bbb9d0 3092 kvm_vmx->ept_identity_pagetable_done = true;
f51770ed 3093
b7ebfb05 3094out:
40dcaa9f 3095 srcu_read_unlock(&kvm->srcu, idx);
a255d479
TC		 3096
3097out2:
3098 mutex_unlock(&kvm->slots_lock);
f51770ed 3099 return r;
b7ebfb05
SY		 3100}
3101
6aa8b732
AK		 3102static void seg_setup(int seg)
3103{
772e0318 3104 const struct kvm_vmx_segment_field *sf = &kvm_vmx_segment_fields[seg];
3a624e29 3105 unsigned int ar;
6aa8b732
AK		 3106
3107 vmcs_write16(sf->selector, 0);
3108 vmcs_writel(sf->base, 0);
3109 vmcs_write32(sf->limit, 0xffff);
d54d07b2
GN		 3110 ar = 0x93;
3111 if (seg == VCPU_SREG_CS)
3112 ar |= 0x08; /* code segment */
3a624e29
NK		 3113
3114 vmcs_write32(sf->ar_bytes, ar);
6aa8b732
AK		 3115}
3116
f78e0e2e
SY		 3117static int alloc_apic_access_page(struct kvm *kvm)
3118{
4484141a 3119 struct page *page;
f78e0e2e
SY		 3120 int r = 0;
3121
79fac95e 3122 mutex_lock(&kvm->slots_lock);
c24ae0dc 3123 if (kvm->arch.apic_access_page_done)
f78e0e2e 3124 goto out;
1d8007bd
PB		 3125 r = __x86_set_memory_region(kvm, APIC_ACCESS_PAGE_PRIVATE_MEMSLOT,
3126 APIC_DEFAULT_PHYS_BASE, PAGE_SIZE);
f78e0e2e
SY		 3127 if (r)
3128 goto out;
72dc67a6 3129
73a6d941 3130 page = gfn_to_page(kvm, APIC_DEFAULT_PHYS_BASE >> PAGE_SHIFT);
4484141a
XG		 3131 if (is_error_page(page)) {
3132 r = -EFAULT;
3133 goto out;
3134 }
3135
c24ae0dc
TC		 3136 /*
3137 * Do not pin the page in memory, so that memory hot-unplug
3138 * is able to migrate it.
3139 */
3140 put_page(page);
3141 kvm->arch.apic_access_page_done = true;
f78e0e2e 3142out:
79fac95e 3143 mutex_unlock(&kvm->slots_lock);
f78e0e2e
SY		 3144 return r;
3145}
3146
97b7ead3 3147int allocate_vpid(void)
2384d2b3
SY		 3148{
3149 int vpid;
3150
919818ab 3151 if (!enable_vpid)
991e7a0e 3152 return 0;
2384d2b3
SY		 3153 spin_lock(&vmx_vpid_lock);
3154 vpid = find_first_zero_bit(vmx_vpid_bitmap, VMX_NR_VPIDS);
991e7a0e 3155 if (vpid < VMX_NR_VPIDS)
2384d2b3 3156 __set_bit(vpid, vmx_vpid_bitmap);
991e7a0e
WL		 3157 else
3158 vpid = 0;
2384d2b3 3159 spin_unlock(&vmx_vpid_lock);
991e7a0e 3160 return vpid;
2384d2b3
SY		 3161}
3162
97b7ead3 3163void free_vpid(int vpid)
cdbecfc3 3164{
991e7a0e 3165 if (!enable_vpid || vpid == 0)
cdbecfc3
LJ		 3166 return;
3167 spin_lock(&vmx_vpid_lock);
991e7a0e 3168 __clear_bit(vpid, vmx_vpid_bitmap);
cdbecfc3
LJ		 3169 spin_unlock(&vmx_vpid_lock);
3170}
3171
1e4329ee 3172static __always_inline void vmx_disable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb 3173 u32 msr, int type)
25c5f225 3174{
3e7c73e9 3175 int f = sizeof(unsigned long);
25c5f225
SY		 3176
3177 if (!cpu_has_vmx_msr_bitmap())
3178 return;
3179
ceef7d10
VK		 3180 if (static_branch_unlikely(&enable_evmcs))
3181 evmcs_touch_msr_bitmap();
3182
25c5f225
SY		 3183 /*
3184 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3185 * have the write-low and read-high bitmap offsets the wrong way round.
3186 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3187 */
25c5f225 3188 if (msr <= 0x1fff) {
8d14695f
YZ		 3189 if (type & MSR_TYPE_R)
3190 /* read-low */
3191 __clear_bit(msr, msr_bitmap + 0x000 / f);
3192
3193 if (type & MSR_TYPE_W)
3194 /* write-low */
3195 __clear_bit(msr, msr_bitmap + 0x800 / f);
3196
25c5f225
SY		 3197 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3198 msr &= 0x1fff;
8d14695f
YZ		 3199 if (type & MSR_TYPE_R)
3200 /* read-high */
3201 __clear_bit(msr, msr_bitmap + 0x400 / f);
3202
3203 if (type & MSR_TYPE_W)
3204 /* write-high */
3205 __clear_bit(msr, msr_bitmap + 0xc00 / f);
3206
3207 }
3208}
3209
1e4329ee 3210static __always_inline void vmx_enable_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3211 u32 msr, int type)
3212{
3213 int f = sizeof(unsigned long);
3214
3215 if (!cpu_has_vmx_msr_bitmap())
3216 return;
3217
ceef7d10
VK		 3218 if (static_branch_unlikely(&enable_evmcs))
3219 evmcs_touch_msr_bitmap();
3220
904e14fb
PB		 3221 /*
3222 * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals
3223 * have the write-low and read-high bitmap offsets the wrong way round.
3224 * We can control MSRs 0x00000000-0x00001fff and 0xc0000000-0xc0001fff.
3225 */
3226 if (msr <= 0x1fff) {
3227 if (type & MSR_TYPE_R)
3228 /* read-low */
3229 __set_bit(msr, msr_bitmap + 0x000 / f);
3230
3231 if (type & MSR_TYPE_W)
3232 /* write-low */
3233 __set_bit(msr, msr_bitmap + 0x800 / f);
3234
3235 } else if ((msr >= 0xc0000000) && (msr <= 0xc0001fff)) {
3236 msr &= 0x1fff;
3237 if (type & MSR_TYPE_R)
3238 /* read-high */
3239 __set_bit(msr, msr_bitmap + 0x400 / f);
3240
3241 if (type & MSR_TYPE_W)
3242 /* write-high */
3243 __set_bit(msr, msr_bitmap + 0xc00 / f);
3244
3245 }
3246}
3247
1e4329ee 3248static __always_inline void vmx_set_intercept_for_msr(unsigned long *msr_bitmap,
904e14fb
PB		 3249 u32 msr, int type, bool value)
3250{
3251 if (value)
3252 vmx_enable_intercept_for_msr(msr_bitmap, msr, type);
3253 else
3254 vmx_disable_intercept_for_msr(msr_bitmap, msr, type);
3255}
3256
904e14fb 3257static u8 vmx_msr_bitmap_mode(struct kvm_vcpu *vcpu)
5897297b 3258{
904e14fb
PB		 3259 u8 mode = 0;
3260
3261 if (cpu_has_secondary_exec_ctrls() &&
3262 (vmcs_read32(SECONDARY_VM_EXEC_CONTROL) &
3263 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE)) {
3264 mode |= MSR_BITMAP_MODE_X2APIC;
3265 if (enable_apicv && kvm_vcpu_apicv_active(vcpu))
3266 mode |= MSR_BITMAP_MODE_X2APIC_APICV;
3267 }
3268
904e14fb 3269 return mode;
8d14695f
YZ		 3270}
3271
904e14fb
PB		 3272static void vmx_update_msr_bitmap_x2apic(unsigned long *msr_bitmap,
3273 u8 mode)
8d14695f 3274{
904e14fb
PB		 3275 int msr;
3276
3277 for (msr = 0x800; msr <= 0x8ff; msr += BITS_PER_LONG) {
3278 unsigned word = msr / BITS_PER_LONG;
3279 msr_bitmap[word] = (mode & MSR_BITMAP_MODE_X2APIC_APICV) ? 0 : ~0;
3280 msr_bitmap[word + (0x800 / sizeof(long))] = ~0;
3281 }
3282
3283 if (mode & MSR_BITMAP_MODE_X2APIC) {
3284 /*
3285 * TPR reads and writes can be virtualized even if virtual interrupt
3286 * delivery is not in use.
3287 */
3288 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TASKPRI), MSR_TYPE_RW);
3289 if (mode & MSR_BITMAP_MODE_X2APIC_APICV) {
3290 vmx_enable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_TMCCT), MSR_TYPE_R);
3291 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_EOI), MSR_TYPE_W);
3292 vmx_disable_intercept_for_msr(msr_bitmap, X2APIC_MSR(APIC_SELF_IPI), MSR_TYPE_W);
3293 }
f6e90f9e 3294 }
5897297b
AK		 3295}
3296
97b7ead3 3297void vmx_update_msr_bitmap(struct kvm_vcpu *vcpu)
904e14fb
PB		 3298{
3299 struct vcpu_vmx *vmx = to_vmx(vcpu);
3300 unsigned long *msr_bitmap = vmx->vmcs01.msr_bitmap;
3301 u8 mode = vmx_msr_bitmap_mode(vcpu);
3302 u8 changed = mode ^ vmx->msr_bitmap_mode;
3303
3304 if (!changed)
3305 return;
3306
904e14fb
PB		 3307 if (changed & (MSR_BITMAP_MODE_X2APIC | MSR_BITMAP_MODE_X2APIC_APICV))
3308 vmx_update_msr_bitmap_x2apic(msr_bitmap, mode);
3309
3310 vmx->msr_bitmap_mode = mode;
3311}
3312
b2a05fef 3313static bool vmx_get_enable_apicv(struct kvm_vcpu *vcpu)
d50ab6c1 3314{
d62caabb 3315 return enable_apicv;
d50ab6c1
PB		 3316}
3317
e6c67d8c
LA		 3318static bool vmx_guest_apic_has_interrupt(struct kvm_vcpu *vcpu)
3319{
3320 struct vcpu_vmx *vmx = to_vmx(vcpu);
3321 void *vapic_page;
3322 u32 vppr;
3323 int rvi;
3324
3325 if (WARN_ON_ONCE(!is_guest_mode(vcpu)) ||
3326 !nested_cpu_has_vid(get_vmcs12(vcpu)) ||
3327 WARN_ON_ONCE(!vmx->nested.virtual_apic_page))
3328 return false;
3329
7e712684 3330 rvi = vmx_get_rvi();
e6c67d8c
LA		 3331
3332 vapic_page = kmap(vmx->nested.virtual_apic_page);
3333 vppr = *((u32 *)(vapic_page + APIC_PROCPRI));
3334 kunmap(vmx->nested.virtual_apic_page);
3335
3336 return ((rvi & 0xf0) > (vppr & 0xf0));
3337}
3338
06a5524f
WV		 3339static inline bool kvm_vcpu_trigger_posted_interrupt(struct kvm_vcpu *vcpu,
3340 bool nested)
21bc8dc5
RK		 3341{
3342#ifdef CONFIG_SMP
06a5524f
WV		 3343 int pi_vec = nested ? POSTED_INTR_NESTED_VECTOR : POSTED_INTR_VECTOR;
3344
21bc8dc5 3345 if (vcpu->mode == IN_GUEST_MODE) {
28b835d6 3346 /*
5753743f
HZ		 3347 * The vector of interrupt to be delivered to vcpu had
3348 * been set in PIR before this function.
3349 *
3350 * Following cases will be reached in this block, and
3351 * we always send a notification event in all cases as
3352 * explained below.
3353 *
3354 * Case 1: vcpu keeps in non-root mode. Sending a
3355 * notification event posts the interrupt to vcpu.
3356 *
3357 * Case 2: vcpu exits to root mode and is still
3358 * runnable. PIR will be synced to vIRR before the
3359 * next vcpu entry. Sending a notification event in
3360 * this case has no effect, as vcpu is not in root
3361 * mode.
28b835d6 3362 *
5753743f
HZ		 3363 * Case 3: vcpu exits to root mode and is blocked.
3364 * vcpu_block() has already synced PIR to vIRR and
3365 * never blocks vcpu if vIRR is not cleared. Therefore,
3366 * a blocked vcpu here does not wait for any requested
3367 * interrupts in PIR, and sending a notification event
3368 * which has no effect is safe here.
28b835d6 3369 */
28b835d6 3370
06a5524f 3371 apic->send_IPI_mask(get_cpu_mask(vcpu->cpu), pi_vec);
21bc8dc5
RK		 3372 return true;
3373 }
3374#endif
3375 return false;
3376}
3377
705699a1
WV		 3378static int vmx_deliver_nested_posted_interrupt(struct kvm_vcpu *vcpu,
3379 int vector)
3380{
3381 struct vcpu_vmx *vmx = to_vmx(vcpu);
3382
3383 if (is_guest_mode(vcpu) &&
3384 vector == vmx->nested.posted_intr_nv) {
705699a1
WV		 3385 /*
3386 * If a posted intr is not recognized by hardware,
3387 * we will accomplish it in the next vmentry.
3388 */
3389 vmx->nested.pi_pending = true;
3390 kvm_make_request(KVM_REQ_EVENT, vcpu);
6b697711
LA		 3391 /* the PIR and ON have been set by L1. */
3392 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, true))
3393 kvm_vcpu_kick(vcpu);
705699a1
WV		 3394 return 0;
3395 }
3396 return -1;
3397}
a20ed54d
YZ		 3398/*
3399 * Send interrupt to vcpu via posted interrupt way.
3400 * 1. If target vcpu is running(non-root mode), send posted interrupt
3401 * notification to vcpu and hardware will sync PIR to vIRR atomically.
3402 * 2. If target vcpu isn't running(root mode), kick it to pick up the
3403 * interrupt from PIR in next vmentry.
3404 */
3405static void vmx_deliver_posted_interrupt(struct kvm_vcpu *vcpu, int vector)
3406{
3407 struct vcpu_vmx *vmx = to_vmx(vcpu);
3408 int r;
3409
705699a1
WV		 3410 r = vmx_deliver_nested_posted_interrupt(vcpu, vector);
3411 if (!r)
3412 return;
3413
a20ed54d
YZ		 3414 if (pi_test_and_set_pir(vector, &vmx->pi_desc))
3415 return;
3416
b95234c8
PB		 3417 /* If a previous notification has sent the IPI, nothing to do. */
3418 if (pi_test_and_set_on(&vmx->pi_desc))
3419 return;
3420
06a5524f 3421 if (!kvm_vcpu_trigger_posted_interrupt(vcpu, false))
a20ed54d
YZ		 3422 kvm_vcpu_kick(vcpu);
3423}
3424
a3a8ff8e
NHE		 3425/*
3426 * Set up the vmcs's constant host-state fields, i.e., host-state fields that
3427 * will not change in the lifetime of the guest.
3428 * Note that host-state that does change is set elsewhere. E.g., host-state
3429 * that is set differently for each CPU is set in vmx_vcpu_load(), not here.
3430 */
97b7ead3 3431void vmx_set_constant_host_state(struct vcpu_vmx *vmx)
a3a8ff8e
NHE		 3432{
3433 u32 low32, high32;
3434 unsigned long tmpl;
3435 struct desc_ptr dt;
d6e41f11 3436 unsigned long cr0, cr3, cr4;
a3a8ff8e 3437
04ac88ab
AL		 3438 cr0 = read_cr0();
3439 WARN_ON(cr0 & X86_CR0_TS);
3440 vmcs_writel(HOST_CR0, cr0); /* 22.2.3 */
d6e41f11
AL		 3441
3442 /*
3443 * Save the most likely value for this task's CR3 in the VMCS.
3444 * We can't use __get_current_cr3_fast() because we're not atomic.
3445 */
6c690ee1 3446 cr3 = __read_cr3();
d6e41f11 3447 vmcs_writel(HOST_CR3, cr3); /* 22.2.3 FIXME: shadow tables */
d7ee039e 3448 vmx->loaded_vmcs->host_state.cr3 = cr3;
a3a8ff8e 3449
d974baa3 3450 /* Save the most likely value for this task's CR4 in the VMCS. */
1e02ce4c 3451 cr4 = cr4_read_shadow();
d974baa3 3452 vmcs_writel(HOST_CR4, cr4); /* 22.2.3, 22.2.5 */
d7ee039e 3453 vmx->loaded_vmcs->host_state.cr4 = cr4;
d974baa3 3454
a3a8ff8e 3455 vmcs_write16(HOST_CS_SELECTOR, __KERNEL_CS); /* 22.2.4 */
b2da15ac
AK		 3456#ifdef CONFIG_X86_64
3457 /*
3458 * Load null selectors, so we can avoid reloading them in
6d6095bd
SC		 3459 * vmx_prepare_switch_to_host(), in case userspace uses
3460 * the null selectors too (the expected case).
b2da15ac
AK		 3461 */
3462 vmcs_write16(HOST_DS_SELECTOR, 0);
3463 vmcs_write16(HOST_ES_SELECTOR, 0);
3464#else
a3a8ff8e
NHE		 3465 vmcs_write16(HOST_DS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3466 vmcs_write16(HOST_ES_SELECTOR, __KERNEL_DS); /* 22.2.4 */
b2da15ac 3467#endif
a3a8ff8e
NHE		 3468 vmcs_write16(HOST_SS_SELECTOR, __KERNEL_DS); /* 22.2.4 */
3469 vmcs_write16(HOST_TR_SELECTOR, GDT_ENTRY_TSS*8); /* 22.2.4 */
3470
87930019 3471 store_idt(&dt);
a3a8ff8e 3472 vmcs_writel(HOST_IDTR_BASE, dt.address); /* 22.2.4 */
a547c6db 3473 vmx->host_idt_base = dt.address;
a3a8ff8e 3474
83287ea4 3475 vmcs_writel(HOST_RIP, vmx_return); /* 22.2.5 */
a3a8ff8e
NHE		 3476
3477 rdmsr(MSR_IA32_SYSENTER_CS, low32, high32);
3478 vmcs_write32(HOST_IA32_SYSENTER_CS, low32);
3479 rdmsrl(MSR_IA32_SYSENTER_EIP, tmpl);
3480 vmcs_writel(HOST_IA32_SYSENTER_EIP, tmpl); /* 22.2.3 */
3481
3482 if (vmcs_config.vmexit_ctrl & VM_EXIT_LOAD_IA32_PAT) {
3483 rdmsr(MSR_IA32_CR_PAT, low32, high32);
3484 vmcs_write64(HOST_IA32_PAT, low32 | ((u64) high32 << 32));
3485 }
5a5e8a15 3486
c73da3fc 3487 if (cpu_has_load_ia32_efer())
5a5e8a15 3488 vmcs_write64(HOST_IA32_EFER, host_efer);
a3a8ff8e
NHE		 3489}
3490
97b7ead3 3491void set_cr4_guest_host_mask(struct vcpu_vmx *vmx)
bf8179a0
NHE		 3492{
3493 vmx->vcpu.arch.cr4_guest_owned_bits = KVM_CR4_GUEST_OWNED_BITS;
3494 if (enable_ept)
3495 vmx->vcpu.arch.cr4_guest_owned_bits |= X86_CR4_PGE;
fe3ef05c
NHE		 3496 if (is_guest_mode(&vmx->vcpu))
3497 vmx->vcpu.arch.cr4_guest_owned_bits &=
3498 ~get_vmcs12(&vmx->vcpu)->cr4_guest_host_mask;
bf8179a0
NHE		 3499 vmcs_writel(CR4_GUEST_HOST_MASK, ~vmx->vcpu.arch.cr4_guest_owned_bits);
3500}
3501
01e439be
YZ		 3502static u32 vmx_pin_based_exec_ctrl(struct vcpu_vmx *vmx)
3503{
3504 u32 pin_based_exec_ctrl = vmcs_config.pin_based_exec_ctrl;
3505
d62caabb 3506 if (!kvm_vcpu_apicv_active(&vmx->vcpu))
01e439be 3507 pin_based_exec_ctrl &= ~PIN_BASED_POSTED_INTR;
d02fcf50
PB		 3508
3509 if (!enable_vnmi)
3510 pin_based_exec_ctrl &= ~PIN_BASED_VIRTUAL_NMIS;
3511
64672c95
YJ		 3512 /* Enable the preemption timer dynamically */
3513 pin_based_exec_ctrl &= ~PIN_BASED_VMX_PREEMPTION_TIMER;
01e439be
YZ		 3514 return pin_based_exec_ctrl;
3515}
3516
d62caabb
AS		 3517static void vmx_refresh_apicv_exec_ctrl(struct kvm_vcpu *vcpu)
3518{
3519 struct vcpu_vmx *vmx = to_vmx(vcpu);
3520
3521 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
3ce424e4
RK		 3522 if (cpu_has_secondary_exec_ctrls()) {
3523 if (kvm_vcpu_apicv_active(vcpu))
3524 vmcs_set_bits(SECONDARY_VM_EXEC_CONTROL,
3525 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3526 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3527 else
3528 vmcs_clear_bits(SECONDARY_VM_EXEC_CONTROL,
3529 SECONDARY_EXEC_APIC_REGISTER_VIRT |
3530 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
3531 }
3532
3533 if (cpu_has_vmx_msr_bitmap())
904e14fb 3534 vmx_update_msr_bitmap(vcpu);
d62caabb
AS		 3535}
3536
89b0c9f5
SC		 3537u32 vmx_exec_control(struct vcpu_vmx *vmx)
3538{
3539 u32 exec_control = vmcs_config.cpu_based_exec_ctrl;
3540
3541 if (vmx->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT)
3542 exec_control &= ~CPU_BASED_MOV_DR_EXITING;
3543
3544 if (!cpu_need_tpr_shadow(&vmx->vcpu)) {
3545 exec_control &= ~CPU_BASED_TPR_SHADOW;
3546#ifdef CONFIG_X86_64
3547 exec_control |= CPU_BASED_CR8_STORE_EXITING |
3548 CPU_BASED_CR8_LOAD_EXITING;
3549#endif
3550 }
3551 if (!enable_ept)
3552 exec_control |= CPU_BASED_CR3_STORE_EXITING |
3553 CPU_BASED_CR3_LOAD_EXITING |
3554 CPU_BASED_INVLPG_EXITING;
3555 if (kvm_mwait_in_guest(vmx->vcpu.kvm))
3556 exec_control &= ~(CPU_BASED_MWAIT_EXITING |
3557 CPU_BASED_MONITOR_EXITING);
3558 if (kvm_hlt_in_guest(vmx->vcpu.kvm))
3559 exec_control &= ~CPU_BASED_HLT_EXITING;
3560 return exec_control;
3561}
3562
3563
80154d77 3564static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)
bf8179a0 3565{
80154d77
PB		 3566 struct kvm_vcpu *vcpu = &vmx->vcpu;
3567
bf8179a0 3568 u32 exec_control = vmcs_config.cpu_based_2nd_exec_ctrl;
0367f205 3569
80154d77 3570 if (!cpu_need_virtualize_apic_accesses(vcpu))
bf8179a0
NHE		 3571 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
3572 if (vmx->vpid == 0)
3573 exec_control &= ~SECONDARY_EXEC_ENABLE_VPID;
3574 if (!enable_ept) {
3575 exec_control &= ~SECONDARY_EXEC_ENABLE_EPT;
3576 enable_unrestricted_guest = 0;
3577 }
3578 if (!enable_unrestricted_guest)
3579 exec_control &= ~SECONDARY_EXEC_UNRESTRICTED_GUEST;
b31c114b 3580 if (kvm_pause_in_guest(vmx->vcpu.kvm))
bf8179a0 3581 exec_control &= ~SECONDARY_EXEC_PAUSE_LOOP_EXITING;
80154d77 3582 if (!kvm_vcpu_apicv_active(vcpu))
c7c9c56c
YZ		 3583 exec_control &= ~(SECONDARY_EXEC_APIC_REGISTER_VIRT |
3584 SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY);
8d14695f 3585 exec_control &= ~SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
0367f205
PB		 3586
3587 /* SECONDARY_EXEC_DESC is enabled/disabled on writes to CR4.UMIP,
3588 * in vmx_set_cr4. */
3589 exec_control &= ~SECONDARY_EXEC_DESC;
3590
abc4fc58
AG		 3591 /* SECONDARY_EXEC_SHADOW_VMCS is enabled when L1 executes VMPTRLD
3592 (handle_vmptrld).
3593 We can NOT enable shadow_vmcs here because we don't have yet
3594 a current VMCS12
3595 */
3596 exec_control &= ~SECONDARY_EXEC_SHADOW_VMCS;
a3eaa864
KH		 3597
3598 if (!enable_pml)
3599 exec_control &= ~SECONDARY_EXEC_ENABLE_PML;
843e4330 3600
3db13480
PB		 3601 if (vmx_xsaves_supported()) {
3602 /* Exposing XSAVES only when XSAVE is exposed */
3603 bool xsaves_enabled =
3604 guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3605 guest_cpuid_has(vcpu, X86_FEATURE_XSAVES);
3606
3607 if (!xsaves_enabled)
3608 exec_control &= ~SECONDARY_EXEC_XSAVES;
3609
3610 if (nested) {
3611 if (xsaves_enabled)
6677f3da 3612 vmx->nested.msrs.secondary_ctls_high |=
3db13480
PB		 3613 SECONDARY_EXEC_XSAVES;
3614 else
6677f3da 3615 vmx->nested.msrs.secondary_ctls_high &=
3db13480
PB		 3616 ~SECONDARY_EXEC_XSAVES;
3617 }
3618 }
3619
80154d77
PB		 3620 if (vmx_rdtscp_supported()) {
3621 bool rdtscp_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP);
3622 if (!rdtscp_enabled)
3623 exec_control &= ~SECONDARY_EXEC_RDTSCP;
3624
3625 if (nested) {
3626 if (rdtscp_enabled)
6677f3da 3627 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 3628 SECONDARY_EXEC_RDTSCP;
3629 else
6677f3da 3630 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 3631 ~SECONDARY_EXEC_RDTSCP;
3632 }
3633 }
3634
3635 if (vmx_invpcid_supported()) {
3636 /* Exposing INVPCID only when PCID is exposed */
3637 bool invpcid_enabled =
3638 guest_cpuid_has(vcpu, X86_FEATURE_INVPCID) &&
3639 guest_cpuid_has(vcpu, X86_FEATURE_PCID);
3640
3641 if (!invpcid_enabled) {
3642 exec_control &= ~SECONDARY_EXEC_ENABLE_INVPCID;
3643 guest_cpuid_clear(vcpu, X86_FEATURE_INVPCID);
3644 }
3645
3646 if (nested) {
3647 if (invpcid_enabled)
6677f3da 3648 vmx->nested.msrs.secondary_ctls_high |=
80154d77
PB		 3649 SECONDARY_EXEC_ENABLE_INVPCID;
3650 else
6677f3da 3651 vmx->nested.msrs.secondary_ctls_high &=
80154d77
PB		 3652 ~SECONDARY_EXEC_ENABLE_INVPCID;
3653 }
3654 }
3655
45ec368c
JM		 3656 if (vmx_rdrand_supported()) {
3657 bool rdrand_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDRAND);
3658 if (rdrand_enabled)
736fdf72 3659 exec_control &= ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 3660
3661 if (nested) {
3662 if (rdrand_enabled)
6677f3da 3663 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 3664 SECONDARY_EXEC_RDRAND_EXITING;
45ec368c 3665 else
6677f3da 3666 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 3667 ~SECONDARY_EXEC_RDRAND_EXITING;
45ec368c
JM		 3668 }
3669 }
3670
75f4fc8d
JM		 3671 if (vmx_rdseed_supported()) {
3672 bool rdseed_enabled = guest_cpuid_has(vcpu, X86_FEATURE_RDSEED);
3673 if (rdseed_enabled)
736fdf72 3674 exec_control &= ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 3675
3676 if (nested) {
3677 if (rdseed_enabled)
6677f3da 3678 vmx->nested.msrs.secondary_ctls_high |=
736fdf72 3679 SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d 3680 else
6677f3da 3681 vmx->nested.msrs.secondary_ctls_high &=
736fdf72 3682 ~SECONDARY_EXEC_RDSEED_EXITING;
75f4fc8d
JM		 3683 }
3684 }
3685
80154d77 3686 vmx->secondary_exec_control = exec_control;
bf8179a0
NHE		 3687}
3688
ce88decf
XG		 3689static void ept_set_mmio_spte_mask(void)
3690{
3691 /*
3692 * EPT Misconfigurations can be generated if the value of bits 2:0
3693 * of an EPT paging-structure entry is 110b (write/execute).
ce88decf 3694 */
dcdca5fe
PF		 3695 kvm_mmu_set_mmio_spte_mask(VMX_EPT_RWX_MASK,
3696 VMX_EPT_MISCONFIG_WX_VALUE);
ce88decf
XG		 3697}
3698
f53cd63c 3699#define VMX_XSS_EXIT_BITMAP 0
6aa8b732 3700
944c3464
SC		 3701/*
3702 * Sets up the vmcs for emulated real mode.
3703 */
3704static void vmx_vcpu_setup(struct vcpu_vmx *vmx)
3705{
3706 int i;
3707
3708 if (nested)
3709 nested_vmx_vcpu_setup();
3710
25c5f225 3711 if (cpu_has_vmx_msr_bitmap())
904e14fb 3712 vmcs_write64(MSR_BITMAP, __pa(vmx->vmcs01.msr_bitmap));
25c5f225 3713
6aa8b732
AK		 3714 vmcs_write64(VMCS_LINK_POINTER, -1ull); /* 22.3.1.5 */
3715
6aa8b732 3716 /* Control */
01e439be 3717 vmcs_write32(PIN_BASED_VM_EXEC_CONTROL, vmx_pin_based_exec_ctrl(vmx));
64672c95 3718 vmx->hv_deadline_tsc = -1;
6e5d865c 3719
bf8179a0 3720 vmcs_write32(CPU_BASED_VM_EXEC_CONTROL, vmx_exec_control(vmx));
6aa8b732 3721
dfa169bb 3722 if (cpu_has_secondary_exec_ctrls()) {
80154d77 3723 vmx_compute_secondary_exec_control(vmx);
bf8179a0 3724 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
80154d77 3725 vmx->secondary_exec_control);
dfa169bb 3726 }
f78e0e2e 3727
d62caabb 3728 if (kvm_vcpu_apicv_active(&vmx->vcpu)) {
c7c9c56c
YZ		 3729 vmcs_write64(EOI_EXIT_BITMAP0, 0);
3730 vmcs_write64(EOI_EXIT_BITMAP1, 0);
3731 vmcs_write64(EOI_EXIT_BITMAP2, 0);
3732 vmcs_write64(EOI_EXIT_BITMAP3, 0);
3733
3734 vmcs_write16(GUEST_INTR_STATUS, 0);
01e439be 3735
0bcf261c 3736 vmcs_write16(POSTED_INTR_NV, POSTED_INTR_VECTOR);
01e439be 3737 vmcs_write64(POSTED_INTR_DESC_ADDR, __pa((&vmx->pi_desc)));
c7c9c56c
YZ		 3738 }
3739
b31c114b 3740 if (!kvm_pause_in_guest(vmx->vcpu.kvm)) {
4b8d54f9 3741 vmcs_write32(PLE_GAP, ple_gap);
a7653ecd
RK		 3742 vmx->ple_window = ple_window;
3743 vmx->ple_window_dirty = true;
4b8d54f9
ZE		 3744 }
3745
c3707958
XG		 3746 vmcs_write32(PAGE_FAULT_ERROR_CODE_MASK, 0);
3747 vmcs_write32(PAGE_FAULT_ERROR_CODE_MATCH, 0);
6aa8b732
AK		 3748 vmcs_write32(CR3_TARGET_COUNT, 0); /* 22.2.1 */
3749
9581d442
AK		 3750 vmcs_write16(HOST_FS_SELECTOR, 0); /* 22.2.4 */
3751 vmcs_write16(HOST_GS_SELECTOR, 0); /* 22.2.4 */
a547c6db 3752 vmx_set_constant_host_state(vmx);
6aa8b732
AK		 3753 vmcs_writel(HOST_FS_BASE, 0); /* 22.2.4 */
3754 vmcs_writel(HOST_GS_BASE, 0); /* 22.2.4 */
6aa8b732 3755
2a499e49
BD		 3756 if (cpu_has_vmx_vmfunc())
3757 vmcs_write64(VM_FUNCTION_CONTROL, 0);
3758
2cc51560
ED		 3759 vmcs_write32(VM_EXIT_MSR_STORE_COUNT, 0);
3760 vmcs_write32(VM_EXIT_MSR_LOAD_COUNT, 0);
33966dd6 3761 vmcs_write64(VM_EXIT_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.host.val));
2cc51560 3762 vmcs_write32(VM_ENTRY_MSR_LOAD_COUNT, 0);
33966dd6 3763 vmcs_write64(VM_ENTRY_MSR_LOAD_ADDR, __pa(vmx->msr_autoload.guest.val));
6aa8b732 3764
74545705
RK		 3765 if (vmcs_config.vmentry_ctrl & VM_ENTRY_LOAD_IA32_PAT)
3766 vmcs_write64(GUEST_IA32_PAT, vmx->vcpu.arch.pat);
468d472f 3767
03916db9 3768 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i) {
6aa8b732
AK		 3769 u32 index = vmx_msr_index[i];
3770 u32 data_low, data_high;
a2fa3e9f 3771 int j = vmx->nmsrs;
6aa8b732
AK		 3772
3773 if (rdmsr_safe(index, &data_low, &data_high) < 0)
3774 continue;
432bd6cb
AK		 3775 if (wrmsr_safe(index, data_low, data_high) < 0)
3776 continue;
26bb0981
AK		 3777 vmx->guest_msrs[j].index = i;
3778 vmx->guest_msrs[j].data = 0;
d5696725 3779 vmx->guest_msrs[j].mask = -1ull;
a2fa3e9f 3780 ++vmx->nmsrs;
6aa8b732 3781 }
6aa8b732 3782
5b76a3cf 3783 vmx->arch_capabilities = kvm_get_arch_capabilities();
2961e876 3784
c73da3fc 3785 vm_exit_controls_init(vmx, vmx_vmexit_ctrl());
6aa8b732
AK		 3786
3787 /* 22.2.1, 20.8.1 */
c73da3fc 3788 vm_entry_controls_init(vmx, vmx_vmentry_ctrl());
1c3d14fe 3789
bd7e5b08
PB		 3790 vmx->vcpu.arch.cr0_guest_owned_bits = X86_CR0_TS;
3791 vmcs_writel(CR0_GUEST_HOST_MASK, ~X86_CR0_TS);
3792
bf8179a0 3793 set_cr4_guest_host_mask(vmx);
e00c8cf2 3794
f53cd63c
WL		 3795 if (vmx_xsaves_supported())
3796 vmcs_write64(XSS_EXIT_BITMAP, VMX_XSS_EXIT_BITMAP);
3797
4e59516a 3798 if (enable_pml) {
4e59516a
PF		 3799 vmcs_write64(PML_ADDRESS, page_to_phys(vmx->pml_pg));
3800 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
3801 }
0b665d30
SC		 3802
3803 if (cpu_has_vmx_encls_vmexit())
3804 vmcs_write64(ENCLS_EXITING_BITMAP, -1ull);
e00c8cf2
AK		 3805}
3806
d28bc9dd 3807static void vmx_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
e00c8cf2
AK		 3808{
3809 struct vcpu_vmx *vmx = to_vmx(vcpu);
58cb628d 3810 struct msr_data apic_base_msr;
d28bc9dd 3811 u64 cr0;
e00c8cf2 3812
7ffd92c5 3813 vmx->rmode.vm86_active = 0;
d28b387f 3814 vmx->spec_ctrl = 0;
e00c8cf2 3815
518e7b94 3816 vcpu->arch.microcode_version = 0x100000000ULL;
ad312c7c 3817 vmx->vcpu.arch.regs[VCPU_REGS_RDX] = get_rdx_init_val();
d28bc9dd
NA		 3818 kvm_set_cr8(vcpu, 0);
3819
3820 if (!init_event) {
3821 apic_base_msr.data = APIC_DEFAULT_PHYS_BASE |
3822 MSR_IA32_APICBASE_ENABLE;
3823 if (kvm_vcpu_is_reset_bsp(vcpu))
3824 apic_base_msr.data |= MSR_IA32_APICBASE_BSP;
3825 apic_base_msr.host_initiated = true;
3826 kvm_set_apic_base(vcpu, &apic_base_msr);
3827 }
e00c8cf2 3828
2fb92db1
AK		 3829 vmx_segment_cache_clear(vmx);
3830
5706be0d 3831 seg_setup(VCPU_SREG_CS);
66450a21 3832 vmcs_write16(GUEST_CS_SELECTOR, 0xf000);
f3531054 3833 vmcs_writel(GUEST_CS_BASE, 0xffff0000ul);
e00c8cf2
AK		 3834
3835 seg_setup(VCPU_SREG_DS);
3836 seg_setup(VCPU_SREG_ES);
3837 seg_setup(VCPU_SREG_FS);
3838 seg_setup(VCPU_SREG_GS);
3839 seg_setup(VCPU_SREG_SS);
3840
3841 vmcs_write16(GUEST_TR_SELECTOR, 0);
3842 vmcs_writel(GUEST_TR_BASE, 0);
3843 vmcs_write32(GUEST_TR_LIMIT, 0xffff);
3844 vmcs_write32(GUEST_TR_AR_BYTES, 0x008b);
3845
3846 vmcs_write16(GUEST_LDTR_SELECTOR, 0);
3847 vmcs_writel(GUEST_LDTR_BASE, 0);
3848 vmcs_write32(GUEST_LDTR_LIMIT, 0xffff);
3849 vmcs_write32(GUEST_LDTR_AR_BYTES, 0x00082);
3850
d28bc9dd
NA		 3851 if (!init_event) {
3852 vmcs_write32(GUEST_SYSENTER_CS, 0);
3853 vmcs_writel(GUEST_SYSENTER_ESP, 0);
3854 vmcs_writel(GUEST_SYSENTER_EIP, 0);
3855 vmcs_write64(GUEST_IA32_DEBUGCTL, 0);
3856 }
e00c8cf2 3857
c37c2873 3858 kvm_set_rflags(vcpu, X86_EFLAGS_FIXED);
66450a21 3859 kvm_rip_write(vcpu, 0xfff0);
e00c8cf2 3860
e00c8cf2
AK		 3861 vmcs_writel(GUEST_GDTR_BASE, 0);
3862 vmcs_write32(GUEST_GDTR_LIMIT, 0xffff);
3863
3864 vmcs_writel(GUEST_IDTR_BASE, 0);
3865 vmcs_write32(GUEST_IDTR_LIMIT, 0xffff);
3866
443381a8 3867 vmcs_write32(GUEST_ACTIVITY_STATE, GUEST_ACTIVITY_ACTIVE);
e00c8cf2 3868 vmcs_write32(GUEST_INTERRUPTIBILITY_INFO, 0);
f3531054 3869 vmcs_writel(GUEST_PENDING_DBG_EXCEPTIONS, 0);
a554d207
WL		 3870 if (kvm_mpx_supported())
3871 vmcs_write64(GUEST_BNDCFGS, 0);
e00c8cf2 3872
e00c8cf2
AK		 3873 setup_msrs(vmx);
3874
6aa8b732
AK		 3875 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0); /* 22.2.1 */
3876
d28bc9dd 3877 if (cpu_has_vmx_tpr_shadow() && !init_event) {
f78e0e2e 3878 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR, 0);
35754c98 3879 if (cpu_need_tpr_shadow(vcpu))
f78e0e2e 3880 vmcs_write64(VIRTUAL_APIC_PAGE_ADDR,
d28bc9dd 3881 __pa(vcpu->arch.apic->regs));
f78e0e2e
SY		 3882 vmcs_write32(TPR_THRESHOLD, 0);
3883 }
3884
a73896cb 3885 kvm_make_request(KVM_REQ_APIC_PAGE_RELOAD, vcpu);
6aa8b732 3886
2384d2b3
SY		 3887 if (vmx->vpid != 0)
3888 vmcs_write16(VIRTUAL_PROCESSOR_ID, vmx->vpid);
3889
d28bc9dd 3890 cr0 = X86_CR0_NW | X86_CR0_CD | X86_CR0_ET;
d28bc9dd 3891 vmx->vcpu.arch.cr0 = cr0;
f2463247 3892 vmx_set_cr0(vcpu, cr0); /* enter rmode */
d28bc9dd 3893 vmx_set_cr4(vcpu, 0);
5690891b 3894 vmx_set_efer(vcpu, 0);
bd7e5b08 3895
d28bc9dd 3896 update_exception_bitmap(vcpu);
6aa8b732 3897
dd5f5341 3898 vpid_sync_context(vmx->vpid);
caa057a2
WL		 3899 if (init_event)
3900 vmx_clear_hlt(vcpu);
6aa8b732
AK		 3901}
3902
55d2375e 3903static void enable_irq_window(struct kvm_vcpu *vcpu)
3b86cd99 3904{
47c0152e
PB		 3905 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
3906 CPU_BASED_VIRTUAL_INTR_PENDING);
3b86cd99
JK		 3907}
3908
c9a7953f 3909static void enable_nmi_window(struct kvm_vcpu *vcpu)
3b86cd99 3910{
d02fcf50 3911 if (!enable_vnmi ||
8a1b4392 3912 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_STI) {
c9a7953f
JK		 3913 enable_irq_window(vcpu);
3914 return;
3915 }
3b86cd99 3916
47c0152e
PB		 3917 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL,
3918 CPU_BASED_VIRTUAL_NMI_PENDING);
3b86cd99
JK		 3919}
3920
66fd3f7f 3921static void vmx_inject_irq(struct kvm_vcpu *vcpu)
85f455f7 3922{
9c8cba37 3923 struct vcpu_vmx *vmx = to_vmx(vcpu);
66fd3f7f
GN		 3924 uint32_t intr;
3925 int irq = vcpu->arch.interrupt.nr;
9c8cba37 3926
229456fc 3927 trace_kvm_inj_virq(irq);
2714d1d3 3928
fa89a817 3929 ++vcpu->stat.irq_injections;
7ffd92c5 3930 if (vmx->rmode.vm86_active) {
71f9833b
SH		 3931 int inc_eip = 0;
3932 if (vcpu->arch.interrupt.soft)
3933 inc_eip = vcpu->arch.event_exit_inst_len;
3934 if (kvm_inject_realmode_interrupt(vcpu, irq, inc_eip) != EMULATE_DONE)
a92601bb 3935 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
85f455f7
ED		 3936 return;
3937 }
66fd3f7f
GN		 3938 intr = irq | INTR_INFO_VALID_MASK;
3939 if (vcpu->arch.interrupt.soft) {
3940 intr |= INTR_TYPE_SOFT_INTR;
3941 vmcs_write32(VM_ENTRY_INSTRUCTION_LEN,
3942 vmx->vcpu.arch.event_exit_inst_len);
3943 } else
3944 intr |= INTR_TYPE_EXT_INTR;
3945 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, intr);
caa057a2
WL		 3946
3947 vmx_clear_hlt(vcpu);
85f455f7
ED		 3948}
3949
f08864b4
SY		 3950static void vmx_inject_nmi(struct kvm_vcpu *vcpu)
3951{
66a5a347
JK		 3952 struct vcpu_vmx *vmx = to_vmx(vcpu);
3953
d02fcf50 3954 if (!enable_vnmi) {
8a1b4392
PB		 3955 /*
3956 * Tracking the NMI-blocked state in software is built upon
3957 * finding the next open IRQ window. This, in turn, depends on
3958 * well-behaving guests: They have to keep IRQs disabled at
3959 * least as long as the NMI handler runs. Otherwise we may
3960 * cause NMI nesting, maybe breaking the guest. But as this is
3961 * highly unlikely, we can live with the residual risk.
3962 */
3963 vmx->loaded_vmcs->soft_vnmi_blocked = 1;
3964 vmx->loaded_vmcs->vnmi_blocked_time = 0;
3965 }
3966
4c4a6f79
PB		 3967 ++vcpu->stat.nmi_injections;
3968 vmx->loaded_vmcs->nmi_known_unmasked = false;
3b86cd99 3969
7ffd92c5 3970 if (vmx->rmode.vm86_active) {
71f9833b 3971 if (kvm_inject_realmode_interrupt(vcpu, NMI_VECTOR, 0) != EMULATE_DONE)
a92601bb 3972 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
66a5a347
JK		 3973 return;
3974 }
c5a6d5f7 3975
f08864b4
SY		 3976 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD,
3977 INTR_TYPE_NMI_INTR | INTR_INFO_VALID_MASK | NMI_VECTOR);
caa057a2
WL		 3978
3979 vmx_clear_hlt(vcpu);
f08864b4
SY		 3980}
3981
97b7ead3 3982bool vmx_get_nmi_mask(struct kvm_vcpu *vcpu)
3cfc3092 3983{
4c4a6f79
PB		 3984 struct vcpu_vmx *vmx = to_vmx(vcpu);
3985 bool masked;
3986
d02fcf50 3987 if (!enable_vnmi)
8a1b4392 3988 return vmx->loaded_vmcs->soft_vnmi_blocked;
4c4a6f79 3989 if (vmx->loaded_vmcs->nmi_known_unmasked)
9d58b931 3990 return false;
4c4a6f79
PB		 3991 masked = vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) & GUEST_INTR_STATE_NMI;
3992 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
3993 return masked;
3cfc3092
JK		 3994}
3995
97b7ead3 3996void vmx_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3cfc3092
JK		 3997{
3998 struct vcpu_vmx *vmx = to_vmx(vcpu);
3999
d02fcf50 4000 if (!enable_vnmi) {
8a1b4392
PB		 4001 if (vmx->loaded_vmcs->soft_vnmi_blocked != masked) {
4002 vmx->loaded_vmcs->soft_vnmi_blocked = masked;
4003 vmx->loaded_vmcs->vnmi_blocked_time = 0;
4004 }
4005 } else {
4006 vmx->loaded_vmcs->nmi_known_unmasked = !masked;
4007 if (masked)
4008 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
4009 GUEST_INTR_STATE_NMI);
4010 else
4011 vmcs_clear_bits(GUEST_INTERRUPTIBILITY_INFO,
4012 GUEST_INTR_STATE_NMI);
4013 }
3cfc3092
JK		 4014}
4015
2505dc9f
JK		 4016static int vmx_nmi_allowed(struct kvm_vcpu *vcpu)
4017{
b6b8a145
JK		 4018 if (to_vmx(vcpu)->nested.nested_run_pending)
4019 return 0;
ea8ceb83 4020
d02fcf50 4021 if (!enable_vnmi &&
8a1b4392
PB		 4022 to_vmx(vcpu)->loaded_vmcs->soft_vnmi_blocked)
4023 return 0;
4024
2505dc9f
JK		 4025 return !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4026 (GUEST_INTR_STATE_MOV_SS | GUEST_INTR_STATE_STI
4027 | GUEST_INTR_STATE_NMI));
4028}
4029
78646121
GN		 4030static int vmx_interrupt_allowed(struct kvm_vcpu *vcpu)
4031{
b6b8a145
JK		 4032 return (!to_vmx(vcpu)->nested.nested_run_pending &&
4033 vmcs_readl(GUEST_RFLAGS) & X86_EFLAGS_IF) &&
c4282df9
GN		 4034 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO) &
4035 (GUEST_INTR_STATE_STI | GUEST_INTR_STATE_MOV_SS));
78646121
GN		 4036}
4037
cbc94022
IE		 4038static int vmx_set_tss_addr(struct kvm *kvm, unsigned int addr)
4039{
4040 int ret;
cbc94022 4041
f7eaeb0a
SC		 4042 if (enable_unrestricted_guest)
4043 return 0;
4044
1d8007bd
PB		 4045 ret = x86_set_memory_region(kvm, TSS_PRIVATE_MEMSLOT, addr,
4046 PAGE_SIZE * 3);
cbc94022
IE		 4047 if (ret)
4048 return ret;
40bbb9d0 4049 to_kvm_vmx(kvm)->tss_addr = addr;
1f755a82 4050 return init_rmode_tss(kvm);
cbc94022
IE		 4051}
4052
2ac52ab8
SC		 4053static int vmx_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
4054{
40bbb9d0 4055 to_kvm_vmx(kvm)->ept_identity_map_addr = ident_addr;
2ac52ab8
SC		 4056 return 0;
4057}
4058
0ca1b4f4 4059static bool rmode_exception(struct kvm_vcpu *vcpu, int vec)
6aa8b732 4060{
77ab6db0 4061 switch (vec) {
77ab6db0 4062 case BP_VECTOR:
c573cd22
JK		 4063 /*
4064 * Update instruction length as we may reinject the exception
4065 * from user space while in guest debugging mode.
4066 */
4067 to_vmx(vcpu)->vcpu.arch.event_exit_inst_len =
4068 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
d0bfb940 4069 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
0ca1b4f4
GN		 4070 return false;
4071 /* fall through */
4072 case DB_VECTOR:
4073 if (vcpu->guest_debug &
4074 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
4075 return false;
d0bfb940
JK		 4076 /* fall through */
4077 case DE_VECTOR:
77ab6db0
JK		 4078 case OF_VECTOR:
4079 case BR_VECTOR:
4080 case UD_VECTOR:
4081 case DF_VECTOR:
4082 case SS_VECTOR:
4083 case GP_VECTOR:
4084 case MF_VECTOR:
0ca1b4f4
GN		 4085 return true;
4086 break;
77ab6db0 4087 }
0ca1b4f4
GN		 4088 return false;
4089}
4090
4091static int handle_rmode_exception(struct kvm_vcpu *vcpu,
4092 int vec, u32 err_code)
4093{
4094 /*
4095 * Instruction with address size override prefix opcode 0x67
4096 * Cause the #SS fault with 0 error code in VM86 mode.
4097 */
4098 if (((vec == GP_VECTOR) || (vec == SS_VECTOR)) && err_code == 0) {
0ce97a2b 4099 if (kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE) {
0ca1b4f4
GN		 4100 if (vcpu->arch.halt_request) {
4101 vcpu->arch.halt_request = 0;
5cb56059 4102 return kvm_vcpu_halt(vcpu);
0ca1b4f4
GN		 4103 }
4104 return 1;
4105 }
4106 return 0;
4107 }
4108
4109 /*
4110 * Forward all other exceptions that are valid in real mode.
4111 * FIXME: Breaks guest debugging in real mode, needs to be fixed with
4112 * the required debugging infrastructure rework.
4113 */
4114 kvm_queue_exception(vcpu, vec);
4115 return 1;
6aa8b732
AK		 4116}
4117
a0861c02
AK		 4118/*
4119 * Trigger machine check on the host. We assume all the MSRs are already set up
4120 * by the CPU and that we still run on the same CPU as the MCE occurred on.
4121 * We pass a fake environment to the machine check handler because we want
4122 * the guest to be always treated like user space, no matter what context
4123 * it used internally.
4124 */
4125static void kvm_machine_check(void)
4126{
4127#if defined(CONFIG_X86_MCE) && defined(CONFIG_X86_64)
4128 struct pt_regs regs = {
4129 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
4130 .flags = X86_EFLAGS_IF,
4131 };
4132
4133 do_machine_check(&regs, 0);
4134#endif
4135}
4136
851ba692 4137static int handle_machine_check(struct kvm_vcpu *vcpu)
a0861c02
AK		 4138{
4139 /* already handled by vcpu_run */
4140 return 1;
4141}
4142
851ba692 4143static int handle_exception(struct kvm_vcpu *vcpu)
6aa8b732 4144{
1155f76a 4145 struct vcpu_vmx *vmx = to_vmx(vcpu);
851ba692 4146 struct kvm_run *kvm_run = vcpu->run;
d0bfb940 4147 u32 intr_info, ex_no, error_code;
42dbaa5a 4148 unsigned long cr2, rip, dr6;
6aa8b732
AK		 4149 u32 vect_info;
4150 enum emulation_result er;
4151
1155f76a 4152 vect_info = vmx->idt_vectoring_info;
88786475 4153 intr_info = vmx->exit_intr_info;
6aa8b732 4154
a0861c02 4155 if (is_machine_check(intr_info))
851ba692 4156 return handle_machine_check(vcpu);
a0861c02 4157
ef85b673 4158 if (is_nmi(intr_info))
1b6269db 4159 return 1; /* already handled by vmx_vcpu_run() */
2ab455cc 4160
082d06ed
WL		 4161 if (is_invalid_opcode(intr_info))
4162 return handle_ud(vcpu);
7aa81cc0 4163
6aa8b732 4164 error_code = 0;
2e11384c 4165 if (intr_info & INTR_INFO_DELIVER_CODE_MASK)
6aa8b732 4166 error_code = vmcs_read32(VM_EXIT_INTR_ERROR_CODE);
bf4ca23e 4167
9e869480
LA		 4168 if (!vmx->rmode.vm86_active && is_gp_fault(intr_info)) {
4169 WARN_ON_ONCE(!enable_vmware_backdoor);
0ce97a2b 4170 er = kvm_emulate_instruction(vcpu,
9e869480
LA		 4171 EMULTYPE_VMWARE | EMULTYPE_NO_UD_ON_FAIL);
4172 if (er == EMULATE_USER_EXIT)
4173 return 0;
4174 else if (er != EMULATE_DONE)
4175 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
4176 return 1;
4177 }
4178
bf4ca23e
XG		 4179 /*
4180 * The #PF with PFEC.RSVD = 1 indicates the guest is accessing
4181 * MMIO, it is better to report an internal error.
4182 * See the comments in vmx_handle_exit.
4183 */
4184 if ((vect_info & VECTORING_INFO_VALID_MASK) &&
4185 !(is_page_fault(intr_info) && !(error_code & PFERR_RSVD_MASK))) {
4186 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4187 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_SIMUL_EX;
80f0e95d 4188 vcpu->run->internal.ndata = 3;
bf4ca23e
XG		 4189 vcpu->run->internal.data[0] = vect_info;
4190 vcpu->run->internal.data[1] = intr_info;
80f0e95d 4191 vcpu->run->internal.data[2] = error_code;
bf4ca23e
XG		 4192 return 0;
4193 }
4194
6aa8b732
AK		 4195 if (is_page_fault(intr_info)) {
4196 cr2 = vmcs_readl(EXIT_QUALIFICATION);
1261bfa3
WL		 4197 /* EPT won't cause page fault directly */
4198 WARN_ON_ONCE(!vcpu->arch.apf.host_apf_reason && enable_ept);
d0006530 4199 return kvm_handle_page_fault(vcpu, error_code, cr2, NULL, 0);
6aa8b732
AK		 4200 }
4201
d0bfb940 4202 ex_no = intr_info & INTR_INFO_VECTOR_MASK;
0ca1b4f4
GN		 4203
4204 if (vmx->rmode.vm86_active && rmode_exception(vcpu, ex_no))
4205 return handle_rmode_exception(vcpu, ex_no, error_code);
4206
42dbaa5a 4207 switch (ex_no) {
54a20552
EN		 4208 case AC_VECTOR:
4209 kvm_queue_exception_e(vcpu, AC_VECTOR, error_code);
4210 return 1;
42dbaa5a
JK		 4211 case DB_VECTOR:
4212 dr6 = vmcs_readl(EXIT_QUALIFICATION);
4213 if (!(vcpu->guest_debug &
4214 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))) {
8246bf52 4215 vcpu->arch.dr6 &= ~15;
6f43ed01 4216 vcpu->arch.dr6 |= dr6 | DR6_RTM;
32d43cd3 4217 if (is_icebp(intr_info))
fd2a445a
HD		 4218 skip_emulated_instruction(vcpu);
4219
42dbaa5a
JK		 4220 kvm_queue_exception(vcpu, DB_VECTOR);
4221 return 1;
4222 }
4223 kvm_run->debug.arch.dr6 = dr6 | DR6_FIXED_1;
4224 kvm_run->debug.arch.dr7 = vmcs_readl(GUEST_DR7);
4225 /* fall through */
4226 case BP_VECTOR:
c573cd22
JK		 4227 /*
4228 * Update instruction length as we may reinject #BP from
4229 * user space while in guest debugging mode. Reading it for
4230 * #DB as well causes no harm, it is not used in that case.
4231 */
4232 vmx->vcpu.arch.event_exit_inst_len =
4233 vmcs_read32(VM_EXIT_INSTRUCTION_LEN);
6aa8b732 4234 kvm_run->exit_reason = KVM_EXIT_DEBUG;
0a434bb2 4235 rip = kvm_rip_read(vcpu);
d0bfb940
JK		 4236 kvm_run->debug.arch.pc = vmcs_readl(GUEST_CS_BASE) + rip;
4237 kvm_run->debug.arch.exception = ex_no;
42dbaa5a
JK		 4238 break;
4239 default:
d0bfb940
JK		 4240 kvm_run->exit_reason = KVM_EXIT_EXCEPTION;
4241 kvm_run->ex.exception = ex_no;
4242 kvm_run->ex.error_code = error_code;
42dbaa5a 4243 break;
6aa8b732 4244 }
6aa8b732
AK		 4245 return 0;
4246}
4247
851ba692 4248static int handle_external_interrupt(struct kvm_vcpu *vcpu)
6aa8b732 4249{
1165f5fe 4250 ++vcpu->stat.irq_exits;
6aa8b732
AK		 4251 return 1;
4252}
4253
851ba692 4254static int handle_triple_fault(struct kvm_vcpu *vcpu)
988ad74f 4255{
851ba692 4256 vcpu->run->exit_reason = KVM_EXIT_SHUTDOWN;
bbeac283 4257 vcpu->mmio_needed = 0;
988ad74f
AK		 4258 return 0;
4259}
6aa8b732 4260
851ba692 4261static int handle_io(struct kvm_vcpu *vcpu)
6aa8b732 4262{
bfdaab09 4263 unsigned long exit_qualification;
dca7f128 4264 int size, in, string;
039576c0 4265 unsigned port;
6aa8b732 4266
bfdaab09 4267 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
039576c0 4268 string = (exit_qualification & 16) != 0;
e70669ab 4269
cf8f70bf 4270 ++vcpu->stat.io_exits;
e70669ab 4271
432baf60 4272 if (string)
0ce97a2b 4273 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
e70669ab 4274
cf8f70bf
GN		 4275 port = exit_qualification >> 16;
4276 size = (exit_qualification & 7) + 1;
432baf60 4277 in = (exit_qualification & 8) != 0;
cf8f70bf 4278
dca7f128 4279 return kvm_fast_pio(vcpu, size, port, in);
6aa8b732
AK		 4280}
4281
102d8325
IM		 4282static void
4283vmx_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4284{
4285 /*
4286 * Patch in the VMCALL instruction:
4287 */
4288 hypercall[0] = 0x0f;
4289 hypercall[1] = 0x01;
4290 hypercall[2] = 0xc1;
102d8325
IM		 4291}
4292
0fa06071 4293/* called to set cr0 as appropriate for a mov-to-cr0 exit. */
eeadf9e7
NHE		 4294static int handle_set_cr0(struct kvm_vcpu *vcpu, unsigned long val)
4295{
eeadf9e7 4296 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4297 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4298 unsigned long orig_val = val;
4299
eeadf9e7
NHE		 4300 /*
4301 * We get here when L2 changed cr0 in a way that did not change
4302 * any of L1's shadowed bits (see nested_vmx_exit_handled_cr),
1a0d74e6
JK		 4303 * but did change L0 shadowed bits. So we first calculate the
4304 * effective cr0 value that L1 would like to write into the
4305 * hardware. It consists of the L2-owned bits from the new
4306 * value combined with the L1-owned bits from L1's guest_cr0.
eeadf9e7 4307 */
1a0d74e6
JK		 4308 val = (val & ~vmcs12->cr0_guest_host_mask) |
4309 (vmcs12->guest_cr0 & vmcs12->cr0_guest_host_mask);
4310
3899152c 4311 if (!nested_guest_cr0_valid(vcpu, val))
eeadf9e7 4312 return 1;
1a0d74e6
JK		 4313
4314 if (kvm_set_cr0(vcpu, val))
4315 return 1;
4316 vmcs_writel(CR0_READ_SHADOW, orig_val);
eeadf9e7 4317 return 0;
1a0d74e6
JK		 4318 } else {
4319 if (to_vmx(vcpu)->nested.vmxon &&
3899152c 4320 !nested_host_cr0_valid(vcpu, val))
1a0d74e6 4321 return 1;
3899152c 4322
eeadf9e7 4323 return kvm_set_cr0(vcpu, val);
1a0d74e6 4324 }
eeadf9e7
NHE		 4325}
4326
4327static int handle_set_cr4(struct kvm_vcpu *vcpu, unsigned long val)
4328{
4329 if (is_guest_mode(vcpu)) {
1a0d74e6
JK		 4330 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
4331 unsigned long orig_val = val;
4332
4333 /* analogously to handle_set_cr0 */
4334 val = (val & ~vmcs12->cr4_guest_host_mask) |
4335 (vmcs12->guest_cr4 & vmcs12->cr4_guest_host_mask);
4336 if (kvm_set_cr4(vcpu, val))
eeadf9e7 4337 return 1;
1a0d74e6 4338 vmcs_writel(CR4_READ_SHADOW, orig_val);
eeadf9e7
NHE		 4339 return 0;
4340 } else
4341 return kvm_set_cr4(vcpu, val);
4342}
4343
0367f205
PB		 4344static int handle_desc(struct kvm_vcpu *vcpu)
4345{
4346 WARN_ON(!(vcpu->arch.cr4 & X86_CR4_UMIP));
0ce97a2b 4347 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
0367f205
PB		 4348}
4349
851ba692 4350static int handle_cr(struct kvm_vcpu *vcpu)
6aa8b732 4351{
229456fc 4352 unsigned long exit_qualification, val;
6aa8b732
AK		 4353 int cr;
4354 int reg;
49a9b07e 4355 int err;
6affcbed 4356 int ret;
6aa8b732 4357
bfdaab09 4358 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
6aa8b732
AK		 4359 cr = exit_qualification & 15;
4360 reg = (exit_qualification >> 8) & 15;
4361 switch ((exit_qualification >> 4) & 3) {
4362 case 0: /* mov to cr */
1e32c079 4363 val = kvm_register_readl(vcpu, reg);
229456fc 4364 trace_kvm_cr_write(cr, val);
6aa8b732
AK		 4365 switch (cr) {
4366 case 0:
eeadf9e7 4367 err = handle_set_cr0(vcpu, val);
6affcbed 4368 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4369 case 3:
e1de91cc 4370 WARN_ON_ONCE(enable_unrestricted_guest);
2390218b 4371 err = kvm_set_cr3(vcpu, val);
6affcbed 4372 return kvm_complete_insn_gp(vcpu, err);
6aa8b732 4373 case 4:
eeadf9e7 4374 err = handle_set_cr4(vcpu, val);
6affcbed 4375 return kvm_complete_insn_gp(vcpu, err);
0a5fff19
GN		 4376 case 8: {
4377 u8 cr8_prev = kvm_get_cr8(vcpu);
1e32c079 4378 u8 cr8 = (u8)val;
eea1cff9 4379 err = kvm_set_cr8(vcpu, cr8);
6affcbed 4380 ret = kvm_complete_insn_gp(vcpu, err);
35754c98 4381 if (lapic_in_kernel(vcpu))
6affcbed 4382 return ret;
0a5fff19 4383 if (cr8_prev <= cr8)
6affcbed
KH		 4384 return ret;
4385 /*
4386 * TODO: we might be squashing a
4387 * KVM_GUESTDBG_SINGLESTEP-triggered
4388 * KVM_EXIT_DEBUG here.
4389 */
851ba692 4390 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
0a5fff19
GN		 4391 return 0;
4392 }
4b8073e4 4393 }
6aa8b732 4394 break;
25c4c276 4395 case 2: /* clts */
bd7e5b08
PB		 4396 WARN_ONCE(1, "Guest should always own CR0.TS");
4397 vmx_set_cr0(vcpu, kvm_read_cr0_bits(vcpu, ~X86_CR0_TS));
4d4ec087 4398 trace_kvm_cr_write(0, kvm_read_cr0(vcpu));
6affcbed 4399 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4400 case 1: /*mov from cr*/
4401 switch (cr) {
4402 case 3:
e1de91cc 4403 WARN_ON_ONCE(enable_unrestricted_guest);
9f8fe504
AK		 4404 val = kvm_read_cr3(vcpu);
4405 kvm_register_write(vcpu, reg, val);
4406 trace_kvm_cr_read(cr, val);
6affcbed 4407 return kvm_skip_emulated_instruction(vcpu);
6aa8b732 4408 case 8:
229456fc
MT		 4409 val = kvm_get_cr8(vcpu);
4410 kvm_register_write(vcpu, reg, val);
4411 trace_kvm_cr_read(cr, val);
6affcbed 4412 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4413 }
4414 break;
4415 case 3: /* lmsw */
a1f83a74 4416 val = (exit_qualification >> LMSW_SOURCE_DATA_SHIFT) & 0x0f;
4d4ec087 4417 trace_kvm_cr_write(0, (kvm_read_cr0(vcpu) & ~0xful) | val);
a1f83a74 4418 kvm_lmsw(vcpu, val);
6aa8b732 4419
6affcbed 4420 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4421 default:
4422 break;
4423 }
851ba692 4424 vcpu->run->exit_reason = 0;
a737f256 4425 vcpu_unimpl(vcpu, "unhandled control register: op %d cr %d\n",
6aa8b732
AK		 4426 (int)(exit_qualification >> 4) & 3, cr);
4427 return 0;
4428}
4429
851ba692 4430static int handle_dr(struct kvm_vcpu *vcpu)
6aa8b732 4431{
bfdaab09 4432 unsigned long exit_qualification;
16f8a6f9
NA		 4433 int dr, dr7, reg;
4434
4435 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4436 dr = exit_qualification & DEBUG_REG_ACCESS_NUM;
4437
4438 /* First, if DR does not exist, trigger UD */
4439 if (!kvm_require_dr(vcpu, dr))
4440 return 1;
6aa8b732 4441
f2483415 4442 /* Do not handle if the CPL > 0, will trigger GP on re-entry */
0a79b009
AK		 4443 if (!kvm_require_cpl(vcpu, 0))
4444 return 1;
16f8a6f9
NA		 4445 dr7 = vmcs_readl(GUEST_DR7);
4446 if (dr7 & DR7_GD) {
42dbaa5a
JK		 4447 /*
4448 * As the vm-exit takes precedence over the debug trap, we
4449 * need to emulate the latter, either for the host or the
4450 * guest debugging itself.
4451 */
4452 if (vcpu->guest_debug & KVM_GUESTDBG_USE_HW_BP) {
851ba692 4453 vcpu->run->debug.arch.dr6 = vcpu->arch.dr6;
16f8a6f9 4454 vcpu->run->debug.arch.dr7 = dr7;
82b32774 4455 vcpu->run->debug.arch.pc = kvm_get_linear_rip(vcpu);
851ba692
AK		 4456 vcpu->run->debug.arch.exception = DB_VECTOR;
4457 vcpu->run->exit_reason = KVM_EXIT_DEBUG;
42dbaa5a
JK		 4458 return 0;
4459 } else {
7305eb5d 4460 vcpu->arch.dr6 &= ~15;
6f43ed01 4461 vcpu->arch.dr6 |= DR6_BD | DR6_RTM;
42dbaa5a
JK		 4462 kvm_queue_exception(vcpu, DB_VECTOR);
4463 return 1;
4464 }
4465 }
4466
81908bf4 4467 if (vcpu->guest_debug == 0) {
8f22372f
PB		 4468 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
4469 CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4470
4471 /*
4472 * No more DR vmexits; force a reload of the debug registers
4473 * and reenter on this instruction. The next vmexit will
4474 * retrieve the full state of the debug registers.
4475 */
4476 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
4477 return 1;
4478 }
4479
42dbaa5a
JK		 4480 reg = DEBUG_REG_ACCESS_REG(exit_qualification);
4481 if (exit_qualification & TYPE_MOV_FROM_DR) {
020df079 4482 unsigned long val;
4c4d563b
JK		 4483
4484 if (kvm_get_dr(vcpu, dr, &val))
4485 return 1;
4486 kvm_register_write(vcpu, reg, val);
020df079 4487 } else
5777392e 4488 if (kvm_set_dr(vcpu, dr, kvm_register_readl(vcpu, reg)))
4c4d563b
JK		 4489 return 1;
4490
6affcbed 4491 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4492}
4493
73aaf249
JK		 4494static u64 vmx_get_dr6(struct kvm_vcpu *vcpu)
4495{
4496 return vcpu->arch.dr6;
4497}
4498
4499static void vmx_set_dr6(struct kvm_vcpu *vcpu, unsigned long val)
4500{
4501}
4502
81908bf4
PB		 4503static void vmx_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
4504{
81908bf4
PB		 4505 get_debugreg(vcpu->arch.db[0], 0);
4506 get_debugreg(vcpu->arch.db[1], 1);
4507 get_debugreg(vcpu->arch.db[2], 2);
4508 get_debugreg(vcpu->arch.db[3], 3);
4509 get_debugreg(vcpu->arch.dr6, 6);
4510 vcpu->arch.dr7 = vmcs_readl(GUEST_DR7);
4511
4512 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
8f22372f 4513 vmcs_set_bits(CPU_BASED_VM_EXEC_CONTROL, CPU_BASED_MOV_DR_EXITING);
81908bf4
PB		 4514}
4515
020df079
GN		 4516static void vmx_set_dr7(struct kvm_vcpu *vcpu, unsigned long val)
4517{
4518 vmcs_writel(GUEST_DR7, val);
4519}
4520
851ba692 4521static int handle_cpuid(struct kvm_vcpu *vcpu)
6aa8b732 4522{
6a908b62 4523 return kvm_emulate_cpuid(vcpu);
6aa8b732
AK		 4524}
4525
851ba692 4526static int handle_rdmsr(struct kvm_vcpu *vcpu)
6aa8b732 4527{
ad312c7c 4528 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
609e36d3 4529 struct msr_data msr_info;
6aa8b732 4530
609e36d3
PB		 4531 msr_info.index = ecx;
4532 msr_info.host_initiated = false;
4533 if (vmx_get_msr(vcpu, &msr_info)) {
59200273 4534 trace_kvm_msr_read_ex(ecx);
c1a5d4f9 4535 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4536 return 1;
4537 }
4538
609e36d3 4539 trace_kvm_msr_read(ecx, msr_info.data);
2714d1d3 4540
6aa8b732 4541 /* FIXME: handling of bits 32:63 of rax, rdx */
609e36d3
PB		 4542 vcpu->arch.regs[VCPU_REGS_RAX] = msr_info.data & -1u;
4543 vcpu->arch.regs[VCPU_REGS_RDX] = (msr_info.data >> 32) & -1u;
6affcbed 4544 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4545}
4546
851ba692 4547static int handle_wrmsr(struct kvm_vcpu *vcpu)
6aa8b732 4548{
8fe8ab46 4549 struct msr_data msr;
ad312c7c
ZX		 4550 u32 ecx = vcpu->arch.regs[VCPU_REGS_RCX];
4551 u64 data = (vcpu->arch.regs[VCPU_REGS_RAX] & -1u)
4552 | ((u64)(vcpu->arch.regs[VCPU_REGS_RDX] & -1u) << 32);
6aa8b732 4553
8fe8ab46
WA		 4554 msr.data = data;
4555 msr.index = ecx;
4556 msr.host_initiated = false;
854e8bb1 4557 if (kvm_set_msr(vcpu, &msr) != 0) {
59200273 4558 trace_kvm_msr_write_ex(ecx, data);
c1a5d4f9 4559 kvm_inject_gp(vcpu, 0);
6aa8b732
AK		 4560 return 1;
4561 }
4562
59200273 4563 trace_kvm_msr_write(ecx, data);
6affcbed 4564 return kvm_skip_emulated_instruction(vcpu);
6aa8b732
AK		 4565}
4566
851ba692 4567static int handle_tpr_below_threshold(struct kvm_vcpu *vcpu)
6e5d865c 4568{
eb90f341 4569 kvm_apic_update_ppr(vcpu);
6e5d865c
YS		 4570 return 1;
4571}
4572
851ba692 4573static int handle_interrupt_window(struct kvm_vcpu *vcpu)
6aa8b732 4574{
47c0152e
PB		 4575 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
4576 CPU_BASED_VIRTUAL_INTR_PENDING);
2714d1d3 4577
3842d135
AK		 4578 kvm_make_request(KVM_REQ_EVENT, vcpu);
4579
a26bf12a 4580 ++vcpu->stat.irq_window_exits;
6aa8b732
AK		 4581 return 1;
4582}
4583
851ba692 4584static int handle_halt(struct kvm_vcpu *vcpu)
6aa8b732 4585{
d3bef15f 4586 return kvm_emulate_halt(vcpu);
6aa8b732
AK		 4587}
4588
851ba692 4589static int handle_vmcall(struct kvm_vcpu *vcpu)
c21415e8 4590{
0d9c055e 4591 return kvm_emulate_hypercall(vcpu);
c21415e8
IM		 4592}
4593
ec25d5e6
GN		 4594static int handle_invd(struct kvm_vcpu *vcpu)
4595{
0ce97a2b 4596 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
ec25d5e6
GN		 4597}
4598
851ba692 4599static int handle_invlpg(struct kvm_vcpu *vcpu)
a7052897 4600{
f9c617f6 4601 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
a7052897
MT		 4602
4603 kvm_mmu_invlpg(vcpu, exit_qualification);
6affcbed 4604 return kvm_skip_emulated_instruction(vcpu);
a7052897
MT		 4605}
4606
fee84b07
AK		 4607static int handle_rdpmc(struct kvm_vcpu *vcpu)
4608{
4609 int err;
4610
4611 err = kvm_rdpmc(vcpu);
6affcbed 4612 return kvm_complete_insn_gp(vcpu, err);
fee84b07
AK		 4613}
4614
851ba692 4615static int handle_wbinvd(struct kvm_vcpu *vcpu)
e5edaa01 4616{
6affcbed 4617 return kvm_emulate_wbinvd(vcpu);
e5edaa01
ED		 4618}
4619
2acf923e
DC		 4620static int handle_xsetbv(struct kvm_vcpu *vcpu)
4621{
4622 u64 new_bv = kvm_read_edx_eax(vcpu);
4623 u32 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
4624
4625 if (kvm_set_xcr(vcpu, index, new_bv) == 0)
6affcbed 4626 return kvm_skip_emulated_instruction(vcpu);
2acf923e
DC		 4627 return 1;
4628}
4629
f53cd63c
WL		 4630static int handle_xsaves(struct kvm_vcpu *vcpu)
4631{
6affcbed 4632 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL		 4633 WARN(1, "this should never happen\n");
4634 return 1;
4635}
4636
4637static int handle_xrstors(struct kvm_vcpu *vcpu)
4638{
6affcbed 4639 kvm_skip_emulated_instruction(vcpu);
f53cd63c
WL		 4640 WARN(1, "this should never happen\n");
4641 return 1;
4642}
4643
851ba692 4644static int handle_apic_access(struct kvm_vcpu *vcpu)
f78e0e2e 4645{
58fbbf26
KT		 4646 if (likely(fasteoi)) {
4647 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4648 int access_type, offset;
4649
4650 access_type = exit_qualification & APIC_ACCESS_TYPE;
4651 offset = exit_qualification & APIC_ACCESS_OFFSET;
4652 /*
4653 * Sane guest uses MOV to write EOI, with written value
4654 * not cared. So make a short-circuit here by avoiding
4655 * heavy instruction emulation.
4656 */
4657 if ((access_type == TYPE_LINEAR_APIC_INST_WRITE) &&
4658 (offset == APIC_EOI)) {
4659 kvm_lapic_set_eoi(vcpu);
6affcbed 4660 return kvm_skip_emulated_instruction(vcpu);
58fbbf26
KT		 4661 }
4662 }
0ce97a2b 4663 return kvm_emulate_instruction(vcpu, 0) == EMULATE_DONE;
f78e0e2e
SY		 4664}
4665
c7c9c56c
YZ		 4666static int handle_apic_eoi_induced(struct kvm_vcpu *vcpu)
4667{
4668 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4669 int vector = exit_qualification & 0xff;
4670
4671 /* EOI-induced VM exit is trap-like and thus no need to adjust IP */
4672 kvm_apic_set_eoi_accelerated(vcpu, vector);
4673 return 1;
4674}
4675
83d4c286
YZ		 4676static int handle_apic_write(struct kvm_vcpu *vcpu)
4677{
4678 unsigned long exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4679 u32 offset = exit_qualification & 0xfff;
4680
4681 /* APIC-write VM exit is trap-like and thus no need to adjust IP */
4682 kvm_apic_write_nodecode(vcpu, offset);
4683 return 1;
4684}
4685
851ba692 4686static int handle_task_switch(struct kvm_vcpu *vcpu)
37817f29 4687{
60637aac 4688 struct vcpu_vmx *vmx = to_vmx(vcpu);
37817f29 4689 unsigned long exit_qualification;
e269fb21
JK		 4690 bool has_error_code = false;
4691 u32 error_code = 0;
37817f29 4692 u16 tss_selector;
7f3d35fd 4693 int reason, type, idt_v, idt_index;
64a7ec06
GN		 4694
4695 idt_v = (vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK);
7f3d35fd 4696 idt_index = (vmx->idt_vectoring_info & VECTORING_INFO_VECTOR_MASK);
64a7ec06 4697 type = (vmx->idt_vectoring_info & VECTORING_INFO_TYPE_MASK);
37817f29
IE		 4698
4699 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
4700
4701 reason = (u32)exit_qualification >> 30;
64a7ec06
GN		 4702 if (reason == TASK_SWITCH_GATE && idt_v) {
4703 switch (type) {
4704 case INTR_TYPE_NMI_INTR:
4705 vcpu->arch.nmi_injected = false;
654f06fc 4706 vmx_set_nmi_mask(vcpu, true);
64a7ec06
GN		 4707 break;
4708 case INTR_TYPE_EXT_INTR:
66fd3f7f 4709 case INTR_TYPE_SOFT_INTR:
64a7ec06
GN		 4710 kvm_clear_interrupt_queue(vcpu);
4711 break;
4712 case INTR_TYPE_HARD_EXCEPTION:
e269fb21
JK		 4713 if (vmx->idt_vectoring_info &
4714 VECTORING_INFO_DELIVER_CODE_MASK) {
4715 has_error_code = true;
4716 error_code =
4717 vmcs_read32(IDT_VECTORING_ERROR_CODE);
4718 }
4719 /* fall through */
64a7ec06
GN		 4720 case INTR_TYPE_SOFT_EXCEPTION:
4721 kvm_clear_exception_queue(vcpu);
4722 break;
4723 default:
4724 break;
4725 }
60637aac 4726 }
37817f29
IE		 4727 tss_selector = exit_qualification;
4728
64a7ec06
GN		 4729 if (!idt_v || (type != INTR_TYPE_HARD_EXCEPTION &&
4730 type != INTR_TYPE_EXT_INTR &&
4731 type != INTR_TYPE_NMI_INTR))
4732 skip_emulated_instruction(vcpu);
4733
7f3d35fd
KW		 4734 if (kvm_task_switch(vcpu, tss_selector,
4735 type == INTR_TYPE_SOFT_INTR ? idt_index : -1, reason,
4736 has_error_code, error_code) == EMULATE_FAIL) {
acb54517
GN		 4737 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4738 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4739 vcpu->run->internal.ndata = 0;
42dbaa5a 4740 return 0;
acb54517 4741 }
42dbaa5a 4742
42dbaa5a
JK		 4743 /*
4744 * TODO: What about debug traps on tss switch?
4745 * Are we supposed to inject them and update dr6?
4746 */
4747
4748 return 1;
37817f29
IE		 4749}
4750
851ba692 4751static int handle_ept_violation(struct kvm_vcpu *vcpu)
1439442c 4752{
f9c617f6 4753 unsigned long exit_qualification;
1439442c 4754 gpa_t gpa;
eebed243 4755 u64 error_code;
1439442c 4756
f9c617f6 4757 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
1439442c 4758
0be9c7a8
GN		 4759 /*
4760 * EPT violation happened while executing iret from NMI,
4761 * "blocked by NMI" bit has to be set before next VM entry.
4762 * There are errata that may cause this bit to not be set:
4763 * AAK134, BY25.
4764 */
bcd1c294 4765 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
d02fcf50 4766 enable_vnmi &&
bcd1c294 4767 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
0be9c7a8
GN		 4768 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO, GUEST_INTR_STATE_NMI);
4769
1439442c 4770 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
229456fc 4771 trace_kvm_page_fault(gpa, exit_qualification);
4f5982a5 4772
27959a44 4773 /* Is it a read fault? */
ab22a473 4774 error_code = (exit_qualification & EPT_VIOLATION_ACC_READ)
27959a44
JS		 4775 ? PFERR_USER_MASK : 0;
4776 /* Is it a write fault? */
ab22a473 4777 error_code |= (exit_qualification & EPT_VIOLATION_ACC_WRITE)
27959a44
JS		 4778 ? PFERR_WRITE_MASK : 0;
4779 /* Is it a fetch fault? */
ab22a473 4780 error_code |= (exit_qualification & EPT_VIOLATION_ACC_INSTR)
27959a44
JS		 4781 ? PFERR_FETCH_MASK : 0;
4782 /* ept page table entry is present? */
4783 error_code |= (exit_qualification &
4784 (EPT_VIOLATION_READABLE | EPT_VIOLATION_WRITABLE |
4785 EPT_VIOLATION_EXECUTABLE))
4786 ? PFERR_PRESENT_MASK : 0;
4f5982a5 4787
eebed243
PB		 4788 error_code |= (exit_qualification & 0x100) != 0 ?
4789 PFERR_GUEST_FINAL_MASK : PFERR_GUEST_PAGE_MASK;
25d92081 4790
25d92081 4791 vcpu->arch.exit_qualification = exit_qualification;
4f5982a5 4792 return kvm_mmu_page_fault(vcpu, gpa, error_code, NULL, 0);
1439442c
SY		 4793}
4794
851ba692 4795static int handle_ept_misconfig(struct kvm_vcpu *vcpu)
68f89400 4796{
68f89400
MT		 4797 gpa_t gpa;
4798
9034e6e8
PB		 4799 /*
4800 * A nested guest cannot optimize MMIO vmexits, because we have an
4801 * nGPA here instead of the required GPA.
4802 */
68f89400 4803 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS);
9034e6e8
PB		 4804 if (!is_guest_mode(vcpu) &&
4805 !kvm_io_bus_write(vcpu, KVM_FAST_MMIO_BUS, gpa, 0, NULL)) {
931c33b1 4806 trace_kvm_fast_mmio(gpa);
d391f120
VK		 4807 /*
4808 * Doing kvm_skip_emulated_instruction() depends on undefined
4809 * behavior: Intel's manual doesn't mandate
4810 * VM_EXIT_INSTRUCTION_LEN to be set in VMCS when EPT MISCONFIG
4811 * occurs and while on real hardware it was observed to be set,
4812 * other hypervisors (namely Hyper-V) don't set it, we end up
4813 * advancing IP with some random value. Disable fast mmio when
4814 * running nested and keep it for real hardware in hope that
4815 * VM_EXIT_INSTRUCTION_LEN will always be set correctly.
4816 */
4817 if (!static_cpu_has(X86_FEATURE_HYPERVISOR))
4818 return kvm_skip_emulated_instruction(vcpu);
4819 else
0ce97a2b 4820 return kvm_emulate_instruction(vcpu, EMULTYPE_SKIP) ==
c4409905 4821 EMULATE_DONE;
68c3b4d1 4822 }
68f89400 4823
c75d0edc 4824 return kvm_mmu_page_fault(vcpu, gpa, PFERR_RSVD_MASK, NULL, 0);
68f89400
MT		 4825}
4826
851ba692 4827static int handle_nmi_window(struct kvm_vcpu *vcpu)
f08864b4 4828{
d02fcf50 4829 WARN_ON_ONCE(!enable_vnmi);
47c0152e
PB		 4830 vmcs_clear_bits(CPU_BASED_VM_EXEC_CONTROL,
4831 CPU_BASED_VIRTUAL_NMI_PENDING);
f08864b4 4832 ++vcpu->stat.nmi_window_exits;
3842d135 4833 kvm_make_request(KVM_REQ_EVENT, vcpu);
f08864b4
SY		 4834
4835 return 1;
4836}
4837
80ced186 4838static int handle_invalid_guest_state(struct kvm_vcpu *vcpu)
ea953ef0 4839{
8b3079a5
AK		 4840 struct vcpu_vmx *vmx = to_vmx(vcpu);
4841 enum emulation_result err = EMULATE_DONE;
80ced186 4842 int ret = 1;
49e9d557
AK		 4843 u32 cpu_exec_ctrl;
4844 bool intr_window_requested;
b8405c18 4845 unsigned count = 130;
49e9d557 4846
2bb8cafe
SC		 4847 /*
4848 * We should never reach the point where we are emulating L2
4849 * due to invalid guest state as that means we incorrectly
4850 * allowed a nested VMEntry with an invalid vmcs12.
4851 */
4852 WARN_ON_ONCE(vmx->emulation_required && vmx->nested.nested_run_pending);
4853
49e9d557
AK		 4854 cpu_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
4855 intr_window_requested = cpu_exec_ctrl & CPU_BASED_VIRTUAL_INTR_PENDING;
ea953ef0 4856
98eb2f8b 4857 while (vmx->emulation_required && count-- != 0) {
bdea48e3 4858 if (intr_window_requested && vmx_interrupt_allowed(vcpu))
49e9d557
AK		 4859 return handle_interrupt_window(&vmx->vcpu);
4860
72875d8a 4861 if (kvm_test_request(KVM_REQ_EVENT, vcpu))
de87dcdd
AK		 4862 return 1;
4863
0ce97a2b 4864 err = kvm_emulate_instruction(vcpu, 0);
ea953ef0 4865
ac0a48c3 4866 if (err == EMULATE_USER_EXIT) {
94452b9e 4867 ++vcpu->stat.mmio_exits;
80ced186
MG		 4868 ret = 0;
4869 goto out;
4870 }
1d5a4d9b 4871
add5ff7a
SC		 4872 if (err != EMULATE_DONE)
4873 goto emulation_error;
4874
4875 if (vmx->emulation_required && !vmx->rmode.vm86_active &&
4876 vcpu->arch.exception.pending)
4877 goto emulation_error;
ea953ef0 4878
8d76c49e
GN		 4879 if (vcpu->arch.halt_request) {
4880 vcpu->arch.halt_request = 0;
5cb56059 4881 ret = kvm_vcpu_halt(vcpu);
8d76c49e
GN		 4882 goto out;
4883 }
4884
ea953ef0 4885 if (signal_pending(current))
80ced186 4886 goto out;
ea953ef0
MG		 4887 if (need_resched())
4888 schedule();
4889 }
4890
80ced186
MG		 4891out:
4892 return ret;
b4a2d31d 4893
add5ff7a
SC		 4894emulation_error:
4895 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
4896 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
4897 vcpu->run->internal.ndata = 0;
4898 return 0;
b4a2d31d
RK		 4899}
4900
4901static void grow_ple_window(struct kvm_vcpu *vcpu)
4902{
4903 struct vcpu_vmx *vmx = to_vmx(vcpu);
4904 int old = vmx->ple_window;
4905
c8e88717
BM		 4906 vmx->ple_window = __grow_ple_window(old, ple_window,
4907 ple_window_grow,
4908 ple_window_max);
b4a2d31d
RK		 4909
4910 if (vmx->ple_window != old)
4911 vmx->ple_window_dirty = true;
7b46268d
RK		 4912
4913 trace_kvm_ple_window_grow(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 4914}
4915
4916static void shrink_ple_window(struct kvm_vcpu *vcpu)
4917{
4918 struct vcpu_vmx *vmx = to_vmx(vcpu);
4919 int old = vmx->ple_window;
4920
c8e88717
BM		 4921 vmx->ple_window = __shrink_ple_window(old, ple_window,
4922 ple_window_shrink,
4923 ple_window);
b4a2d31d
RK		 4924
4925 if (vmx->ple_window != old)
4926 vmx->ple_window_dirty = true;
7b46268d
RK		 4927
4928 trace_kvm_ple_window_shrink(vcpu->vcpu_id, vmx->ple_window, old);
b4a2d31d
RK		 4929}
4930
bf9f6ac8
FW		 4931/*
4932 * Handler for POSTED_INTERRUPT_WAKEUP_VECTOR.
4933 */
4934static void wakeup_handler(void)
4935{
4936 struct kvm_vcpu *vcpu;
4937 int cpu = smp_processor_id();
4938
4939 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
4940 list_for_each_entry(vcpu, &per_cpu(blocked_vcpu_on_cpu, cpu),
4941 blocked_vcpu_list) {
4942 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
4943
4944 if (pi_test_on(pi_desc) == 1)
4945 kvm_vcpu_kick(vcpu);
4946 }
4947 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, cpu));
4948}
4949
e01bca2f 4950static void vmx_enable_tdp(void)
f160c7b7
JS		 4951{
4952 kvm_mmu_set_mask_ptes(VMX_EPT_READABLE_MASK,
4953 enable_ept_ad_bits ? VMX_EPT_ACCESS_BIT : 0ull,
4954 enable_ept_ad_bits ? VMX_EPT_DIRTY_BIT : 0ull,
4955 0ull, VMX_EPT_EXECUTABLE_MASK,
4956 cpu_has_vmx_ept_execute_only() ? 0ull : VMX_EPT_READABLE_MASK,
d0ec49d4 4957 VMX_EPT_RWX_MASK, 0ull);
f160c7b7
JS		 4958
4959 ept_set_mmio_spte_mask();
4960 kvm_enable_tdp();
4961}
4962
4b8d54f9
ZE		 4963/*
4964 * Indicate a busy-waiting vcpu in spinlock. We do not enable the PAUSE
4965 * exiting, so only get here on cpu with PAUSE-Loop-Exiting.
4966 */
9fb41ba8 4967static int handle_pause(struct kvm_vcpu *vcpu)
4b8d54f9 4968{
b31c114b 4969 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d
RK		 4970 grow_ple_window(vcpu);
4971
de63ad4c
LM		 4972 /*
4973 * Intel sdm vol3 ch-25.1.3 says: The "PAUSE-loop exiting"
4974 * VM-execution control is ignored if CPL > 0. OTOH, KVM
4975 * never set PAUSE_EXITING and just set PLE if supported,
4976 * so the vcpu must be CPL=0 if it gets a PAUSE exit.
4977 */
4978 kvm_vcpu_on_spin(vcpu, true);
6affcbed 4979 return kvm_skip_emulated_instruction(vcpu);
4b8d54f9
ZE		 4980}
4981
87c00572 4982static int handle_nop(struct kvm_vcpu *vcpu)
59708670 4983{
6affcbed 4984 return kvm_skip_emulated_instruction(vcpu);
59708670
SY		 4985}
4986
87c00572
GS		 4987static int handle_mwait(struct kvm_vcpu *vcpu)
4988{
4989 printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
4990 return handle_nop(vcpu);
4991}
4992
45ec368c
JM		 4993static int handle_invalid_op(struct kvm_vcpu *vcpu)
4994{
4995 kvm_queue_exception(vcpu, UD_VECTOR);
4996 return 1;
4997}
4998
5f3d45e7
MD		 4999static int handle_monitor_trap(struct kvm_vcpu *vcpu)
5000{
5001 return 1;
5002}
5003
87c00572
GS		 5004static int handle_monitor(struct kvm_vcpu *vcpu)
5005{
5006 printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
5007 return handle_nop(vcpu);
5008}
5009
55d2375e 5010static int handle_invpcid(struct kvm_vcpu *vcpu)
19677e32 5011{
55d2375e
SC		 5012 u32 vmx_instruction_info;
5013 unsigned long type;
5014 bool pcid_enabled;
5015 gva_t gva;
5016 struct x86_exception e;
5017 unsigned i;
5018 unsigned long roots_to_free = 0;
5019 struct {
5020 u64 pcid;
5021 u64 gla;
5022 } operand;
f9eb4af6 5023
55d2375e 5024 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
19677e32
BD		 5025 kvm_queue_exception(vcpu, UD_VECTOR);
5026 return 1;
5027 }
5028
55d2375e
SC		 5029 vmx_instruction_info = vmcs_read32(VMX_INSTRUCTION_INFO);
5030 type = kvm_register_readl(vcpu, (vmx_instruction_info >> 28) & 0xf);
5031
5032 if (type > 3) {
5033 kvm_inject_gp(vcpu, 0);
f9eb4af6
EK		 5034 return 1;
5035 }
5036
55d2375e
SC		 5037 /* According to the Intel instruction reference, the memory operand
5038 * is read even if it isn't needed (e.g., for type==all)
5039 */
3573e22c 5040 if (get_vmx_mem_address(vcpu, vmcs_readl(EXIT_QUALIFICATION),
55d2375e 5041 vmx_instruction_info, false, &gva))
3573e22c
BD		 5042 return 1;
5043
55d2375e 5044 if (kvm_read_guest_virt(vcpu, gva, &operand, sizeof(operand), &e)) {
3573e22c
BD		 5045 kvm_inject_page_fault(vcpu, &e);
5046 return 1;
5047 }
5048
55d2375e
SC		 5049 if (operand.pcid >> 12 != 0) {
5050 kvm_inject_gp(vcpu, 0);
5051 return 1;
abfc52c6 5052 }
e29acc55 5053
55d2375e 5054 pcid_enabled = kvm_read_cr4_bits(vcpu, X86_CR4_PCIDE);
e29acc55 5055
55d2375e
SC		 5056 switch (type) {
5057 case INVPCID_TYPE_INDIV_ADDR:
5058 if ((!pcid_enabled && (operand.pcid != 0)) ||
5059 is_noncanonical_address(operand.gla, vcpu)) {
5060 kvm_inject_gp(vcpu, 0);
5061 return 1;
5062 }
5063 kvm_mmu_invpcid_gva(vcpu, operand.gla, operand.pcid);
5064 return kvm_skip_emulated_instruction(vcpu);
61ada748 5065
55d2375e
SC		 5066 case INVPCID_TYPE_SINGLE_CTXT:
5067 if (!pcid_enabled && (operand.pcid != 0)) {
5068 kvm_inject_gp(vcpu, 0);
5069 return 1;
5070 }
e29acc55 5071
55d2375e
SC		 5072 if (kvm_get_active_pcid(vcpu) == operand.pcid) {
5073 kvm_mmu_sync_roots(vcpu);
5074 kvm_make_request(KVM_REQ_TLB_FLUSH, vcpu);
5075 }
e29acc55 5076
55d2375e
SC		 5077 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5078 if (kvm_get_pcid(vcpu, vcpu->arch.mmu->prev_roots[i].cr3)
5079 == operand.pcid)
5080 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
63aff655 5081
55d2375e
SC		 5082 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, roots_to_free);
5083 /*
5084 * If neither the current cr3 nor any of the prev_roots use the
5085 * given PCID, then nothing needs to be done here because a
5086 * resync will happen anyway before switching to any other CR3.
5087 */
e29acc55 5088
55d2375e 5089 return kvm_skip_emulated_instruction(vcpu);
61ada748 5090
55d2375e
SC		 5091 case INVPCID_TYPE_ALL_NON_GLOBAL:
5092 /*
5093 * Currently, KVM doesn't mark global entries in the shadow
5094 * page tables, so a non-global flush just degenerates to a
5095 * global flush. If needed, we could optimize this later by
5096 * keeping track of global entries in shadow page tables.
5097 */
e29acc55 5098
55d2375e
SC		 5099 /* fall-through */
5100 case INVPCID_TYPE_ALL_INCL_GLOBAL:
5101 kvm_mmu_unload(vcpu);
5102 return kvm_skip_emulated_instruction(vcpu);
e29acc55 5103
55d2375e
SC		 5104 default:
5105 BUG(); /* We have already checked above that type <= 3 */
5106 }
e29acc55
JM		 5107}
5108
55d2375e 5109static int handle_pml_full(struct kvm_vcpu *vcpu)
ec378aee 5110{
55d2375e 5111 unsigned long exit_qualification;
b3897a49 5112
55d2375e 5113 trace_kvm_pml_full(vcpu->vcpu_id);
b3897a49 5114
55d2375e 5115 exit_qualification = vmcs_readl(EXIT_QUALIFICATION);
cbf71279
RK		 5116
5117 /*
55d2375e
SC		 5118 * PML buffer FULL happened while executing iret from NMI,
5119 * "blocked by NMI" bit has to be set before next VM entry.
cbf71279 5120 */
55d2375e
SC		 5121 if (!(to_vmx(vcpu)->idt_vectoring_info & VECTORING_INFO_VALID_MASK) &&
5122 enable_vnmi &&
5123 (exit_qualification & INTR_INFO_UNBLOCK_NMI))
5124 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5125 GUEST_INTR_STATE_NMI);
e49fcb8b 5126
55d2375e
SC		 5127 /*
5128 * PML buffer already flushed at beginning of VMEXIT. Nothing to do
5129 * here.., and there's no userspace involvement needed for PML.
5130 */
ec378aee
NHE		 5131 return 1;
5132}
5133
55d2375e 5134static int handle_preemption_timer(struct kvm_vcpu *vcpu)
8ca44e88 5135{
55d2375e
SC		 5136 if (!to_vmx(vcpu)->req_immediate_exit)
5137 kvm_lapic_expired_hv_timer(vcpu);
5138 return 1;
8ca44e88
DM		 5139}
5140
55d2375e
SC		 5141/*
5142 * When nested=0, all VMX instruction VM Exits filter here. The handlers
5143 * are overwritten by nested_vmx_setup() when nested=1.
5144 */
5145static int handle_vmx_instruction(struct kvm_vcpu *vcpu)
b8bbab92 5146{
55d2375e
SC		 5147 kvm_queue_exception(vcpu, UD_VECTOR);
5148 return 1;
b8bbab92
VK		 5149}
5150
55d2375e 5151static int handle_encls(struct kvm_vcpu *vcpu)
e7953d7f 5152{
55d2375e
SC		 5153 /*
5154 * SGX virtualization is not yet supported. There is no software
5155 * enable bit for SGX, so we have to trap ENCLS and inject a #UD
5156 * to prevent the guest from executing ENCLS.
5157 */
5158 kvm_queue_exception(vcpu, UD_VECTOR);
5159 return 1;
e7953d7f
AG		 5160}
5161
ec378aee 5162/*
55d2375e
SC		 5163 * The exit handlers return 1 if the exit was handled fully and guest execution
5164 * may resume. Otherwise they set the kvm_run parameter to indicate what needs
5165 * to be done to userspace and return 0.
ec378aee 5166 */
55d2375e
SC		 5167static int (*kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = {
5168 [EXIT_REASON_EXCEPTION_NMI] = handle_exception,
5169 [EXIT_REASON_EXTERNAL_INTERRUPT] = handle_external_interrupt,
5170 [EXIT_REASON_TRIPLE_FAULT] = handle_triple_fault,
5171 [EXIT_REASON_NMI_WINDOW] = handle_nmi_window,
5172 [EXIT_REASON_IO_INSTRUCTION] = handle_io,
5173 [EXIT_REASON_CR_ACCESS] = handle_cr,
5174 [EXIT_REASON_DR_ACCESS] = handle_dr,
5175 [EXIT_REASON_CPUID] = handle_cpuid,
5176 [EXIT_REASON_MSR_READ] = handle_rdmsr,
5177 [EXIT_REASON_MSR_WRITE] = handle_wrmsr,
5178 [EXIT_REASON_PENDING_INTERRUPT] = handle_interrupt_window,
5179 [EXIT_REASON_HLT] = handle_halt,
5180 [EXIT_REASON_INVD] = handle_invd,
5181 [EXIT_REASON_INVLPG] = handle_invlpg,
5182 [EXIT_REASON_RDPMC] = handle_rdpmc,
5183 [EXIT_REASON_VMCALL] = handle_vmcall,
5184 [EXIT_REASON_VMCLEAR] = handle_vmx_instruction,
5185 [EXIT_REASON_VMLAUNCH] = handle_vmx_instruction,
5186 [EXIT_REASON_VMPTRLD] = handle_vmx_instruction,
5187 [EXIT_REASON_VMPTRST] = handle_vmx_instruction,
5188 [EXIT_REASON_VMREAD] = handle_vmx_instruction,
5189 [EXIT_REASON_VMRESUME] = handle_vmx_instruction,
5190 [EXIT_REASON_VMWRITE] = handle_vmx_instruction,
5191 [EXIT_REASON_VMOFF] = handle_vmx_instruction,
5192 [EXIT_REASON_VMON] = handle_vmx_instruction,
5193 [EXIT_REASON_TPR_BELOW_THRESHOLD] = handle_tpr_below_threshold,
5194 [EXIT_REASON_APIC_ACCESS] = handle_apic_access,
5195 [EXIT_REASON_APIC_WRITE] = handle_apic_write,
5196 [EXIT_REASON_EOI_INDUCED] = handle_apic_eoi_induced,
5197 [EXIT_REASON_WBINVD] = handle_wbinvd,
5198 [EXIT_REASON_XSETBV] = handle_xsetbv,
5199 [EXIT_REASON_TASK_SWITCH] = handle_task_switch,
5200 [EXIT_REASON_MCE_DURING_VMENTRY] = handle_machine_check,
5201 [EXIT_REASON_GDTR_IDTR] = handle_desc,
5202 [EXIT_REASON_LDTR_TR] = handle_desc,
5203 [EXIT_REASON_EPT_VIOLATION] = handle_ept_violation,
5204 [EXIT_REASON_EPT_MISCONFIG] = handle_ept_misconfig,
5205 [EXIT_REASON_PAUSE_INSTRUCTION] = handle_pause,
5206 [EXIT_REASON_MWAIT_INSTRUCTION] = handle_mwait,
5207 [EXIT_REASON_MONITOR_TRAP_FLAG] = handle_monitor_trap,
5208 [EXIT_REASON_MONITOR_INSTRUCTION] = handle_monitor,
5209 [EXIT_REASON_INVEPT] = handle_vmx_instruction,
5210 [EXIT_REASON_INVVPID] = handle_vmx_instruction,
5211 [EXIT_REASON_RDRAND] = handle_invalid_op,
5212 [EXIT_REASON_RDSEED] = handle_invalid_op,
5213 [EXIT_REASON_XSAVES] = handle_xsaves,
5214 [EXIT_REASON_XRSTORS] = handle_xrstors,
5215 [EXIT_REASON_PML_FULL] = handle_pml_full,
5216 [EXIT_REASON_INVPCID] = handle_invpcid,
5217 [EXIT_REASON_VMFUNC] = handle_vmx_instruction,
5218 [EXIT_REASON_PREEMPTION_TIMER] = handle_preemption_timer,
5219 [EXIT_REASON_ENCLS] = handle_encls,
5220};
b8bbab92 5221
55d2375e
SC		 5222static const int kvm_vmx_max_exit_handlers =
5223 ARRAY_SIZE(kvm_vmx_exit_handlers);
ec378aee 5224
55d2375e 5225static void vmx_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
ec378aee 5226{
55d2375e
SC		 5227 *info1 = vmcs_readl(EXIT_QUALIFICATION);
5228 *info2 = vmcs_read32(VM_EXIT_INTR_INFO);
ec378aee
NHE		 5229}
5230
55d2375e 5231static void vmx_destroy_pml_buffer(struct vcpu_vmx *vmx)
27d6c865 5232{
55d2375e
SC		 5233 if (vmx->pml_pg) {
5234 __free_page(vmx->pml_pg);
5235 vmx->pml_pg = NULL;
b8bbab92 5236 }
27d6c865
NHE		 5237}
5238
55d2375e 5239static void vmx_flush_pml_buffer(struct kvm_vcpu *vcpu)
cd232ad0 5240{
55d2375e
SC		 5241 struct vcpu_vmx *vmx = to_vmx(vcpu);
5242 u64 *pml_buf;
5243 u16 pml_idx;
cd232ad0 5244
55d2375e 5245 pml_idx = vmcs_read16(GUEST_PML_INDEX);
cd232ad0 5246
55d2375e
SC		 5247 /* Do nothing if PML buffer is empty */
5248 if (pml_idx == (PML_ENTITY_NUM - 1))
5249 return;
cd232ad0 5250
55d2375e
SC		 5251 /* PML index always points to next available PML buffer entity */
5252 if (pml_idx >= PML_ENTITY_NUM)
5253 pml_idx = 0;
5254 else
5255 pml_idx++;
945679e3 5256
55d2375e
SC		 5257 pml_buf = page_address(vmx->pml_pg);
5258 for (; pml_idx < PML_ENTITY_NUM; pml_idx++) {
5259 u64 gpa;
945679e3 5260
55d2375e
SC		 5261 gpa = pml_buf[pml_idx];
5262 WARN_ON(gpa & (PAGE_SIZE - 1));
5263 kvm_vcpu_mark_page_dirty(vcpu, gpa >> PAGE_SHIFT);
945679e3
VK		 5264 }
5265
55d2375e
SC		 5266 /* reset PML index */
5267 vmcs_write16(GUEST_PML_INDEX, PML_ENTITY_NUM - 1);
945679e3
VK		 5268}
5269
f4160e45 5270/*
55d2375e
SC		 5271 * Flush all vcpus' PML buffer and update logged GPAs to dirty_bitmap.
5272 * Called before reporting dirty_bitmap to userspace.
f4160e45 5273 */
55d2375e 5274static void kvm_flush_pml_buffers(struct kvm *kvm)
49f705c5 5275{
55d2375e
SC		 5276 int i;
5277 struct kvm_vcpu *vcpu;
49f705c5 5278 /*
55d2375e
SC		 5279 * We only need to kick vcpu out of guest mode here, as PML buffer
5280 * is flushed at beginning of all VMEXITs, and it's obvious that only
5281 * vcpus running in guest are possible to have unflushed GPAs in PML
5282 * buffer.
49f705c5 5283 */
55d2375e
SC		 5284 kvm_for_each_vcpu(i, vcpu, kvm)
5285 kvm_vcpu_kick(vcpu);
49f705c5
NHE		 5286}
5287
55d2375e 5288static void vmx_dump_sel(char *name, uint32_t sel)
49f705c5 5289{
55d2375e
SC		 5290 pr_err("%s sel=0x%04x, attr=0x%05x, limit=0x%08x, base=0x%016lx\n",
5291 name, vmcs_read16(sel),
5292 vmcs_read32(sel + GUEST_ES_AR_BYTES - GUEST_ES_SELECTOR),
5293 vmcs_read32(sel + GUEST_ES_LIMIT - GUEST_ES_SELECTOR),
5294 vmcs_readl(sel + GUEST_ES_BASE - GUEST_ES_SELECTOR));
49f705c5
NHE		 5295}
5296
55d2375e 5297static void vmx_dump_dtsel(char *name, uint32_t limit)
a8bc284e 5298{
55d2375e
SC		 5299 pr_err("%s limit=0x%08x, base=0x%016lx\n",
5300 name, vmcs_read32(limit),
5301 vmcs_readl(limit + GUEST_GDTR_BASE - GUEST_GDTR_LIMIT));
a8bc284e
JM		 5302}
5303
55d2375e 5304static void dump_vmcs(void)
63846663 5305{
55d2375e
SC		 5306 u32 vmentry_ctl = vmcs_read32(VM_ENTRY_CONTROLS);
5307 u32 vmexit_ctl = vmcs_read32(VM_EXIT_CONTROLS);
5308 u32 cpu_based_exec_ctrl = vmcs_read32(CPU_BASED_VM_EXEC_CONTROL);
5309 u32 pin_based_exec_ctrl = vmcs_read32(PIN_BASED_VM_EXEC_CONTROL);
5310 u32 secondary_exec_control = 0;
5311 unsigned long cr4 = vmcs_readl(GUEST_CR4);
5312 u64 efer = vmcs_read64(GUEST_IA32_EFER);
5313 int i, n;
63846663 5314
55d2375e
SC		 5315 if (cpu_has_secondary_exec_ctrls())
5316 secondary_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
14c07ad8 5317
55d2375e
SC		 5318 pr_err("*** Guest State ***\n");
5319 pr_err("CR0: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5320 vmcs_readl(GUEST_CR0), vmcs_readl(CR0_READ_SHADOW),
5321 vmcs_readl(CR0_GUEST_HOST_MASK));
5322 pr_err("CR4: actual=0x%016lx, shadow=0x%016lx, gh_mask=%016lx\n",
5323 cr4, vmcs_readl(CR4_READ_SHADOW), vmcs_readl(CR4_GUEST_HOST_MASK));
5324 pr_err("CR3 = 0x%016lx\n", vmcs_readl(GUEST_CR3));
5325 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT) &&
5326 (cr4 & X86_CR4_PAE) && !(efer & EFER_LMA))
5327 {
5328 pr_err("PDPTR0 = 0x%016llx PDPTR1 = 0x%016llx\n",
5329 vmcs_read64(GUEST_PDPTR0), vmcs_read64(GUEST_PDPTR1));
5330 pr_err("PDPTR2 = 0x%016llx PDPTR3 = 0x%016llx\n",
5331 vmcs_read64(GUEST_PDPTR2), vmcs_read64(GUEST_PDPTR3));
e9ac033e 5332 }
55d2375e
SC		 5333 pr_err("RSP = 0x%016lx RIP = 0x%016lx\n",
5334 vmcs_readl(GUEST_RSP), vmcs_readl(GUEST_RIP));
5335 pr_err("RFLAGS=0x%08lx DR7 = 0x%016lx\n",
5336 vmcs_readl(GUEST_RFLAGS), vmcs_readl(GUEST_DR7));
5337 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5338 vmcs_readl(GUEST_SYSENTER_ESP),
5339 vmcs_read32(GUEST_SYSENTER_CS), vmcs_readl(GUEST_SYSENTER_EIP));
5340 vmx_dump_sel("CS: ", GUEST_CS_SELECTOR);
5341 vmx_dump_sel("DS: ", GUEST_DS_SELECTOR);
5342 vmx_dump_sel("SS: ", GUEST_SS_SELECTOR);
5343 vmx_dump_sel("ES: ", GUEST_ES_SELECTOR);
5344 vmx_dump_sel("FS: ", GUEST_FS_SELECTOR);
5345 vmx_dump_sel("GS: ", GUEST_GS_SELECTOR);
5346 vmx_dump_dtsel("GDTR:", GUEST_GDTR_LIMIT);
5347 vmx_dump_sel("LDTR:", GUEST_LDTR_SELECTOR);
5348 vmx_dump_dtsel("IDTR:", GUEST_IDTR_LIMIT);
5349 vmx_dump_sel("TR: ", GUEST_TR_SELECTOR);
5350 if ((vmexit_ctl & (VM_EXIT_SAVE_IA32_PAT | VM_EXIT_SAVE_IA32_EFER)) ||
5351 (vmentry_ctl & (VM_ENTRY_LOAD_IA32_PAT | VM_ENTRY_LOAD_IA32_EFER)))
5352 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5353 efer, vmcs_read64(GUEST_IA32_PAT));
5354 pr_err("DebugCtl = 0x%016llx DebugExceptions = 0x%016lx\n",
5355 vmcs_read64(GUEST_IA32_DEBUGCTL),
5356 vmcs_readl(GUEST_PENDING_DBG_EXCEPTIONS));
5357 if (cpu_has_load_perf_global_ctrl() &&
5358 vmentry_ctl & VM_ENTRY_LOAD_IA32_PERF_GLOBAL_CTRL)
5359 pr_err("PerfGlobCtl = 0x%016llx\n",
5360 vmcs_read64(GUEST_IA32_PERF_GLOBAL_CTRL));
5361 if (vmentry_ctl & VM_ENTRY_LOAD_BNDCFGS)
5362 pr_err("BndCfgS = 0x%016llx\n", vmcs_read64(GUEST_BNDCFGS));
5363 pr_err("Interruptibility = %08x ActivityState = %08x\n",
5364 vmcs_read32(GUEST_INTERRUPTIBILITY_INFO),
5365 vmcs_read32(GUEST_ACTIVITY_STATE));
5366 if (secondary_exec_control & SECONDARY_EXEC_VIRTUAL_INTR_DELIVERY)
5367 pr_err("InterruptStatus = %04x\n",
5368 vmcs_read16(GUEST_INTR_STATUS));
ff651cb6 5369
55d2375e
SC		 5370 pr_err("*** Host State ***\n");
5371 pr_err("RIP = 0x%016lx RSP = 0x%016lx\n",
5372 vmcs_readl(HOST_RIP), vmcs_readl(HOST_RSP));
5373 pr_err("CS=%04x SS=%04x DS=%04x ES=%04x FS=%04x GS=%04x TR=%04x\n",
5374 vmcs_read16(HOST_CS_SELECTOR), vmcs_read16(HOST_SS_SELECTOR),
5375 vmcs_read16(HOST_DS_SELECTOR), vmcs_read16(HOST_ES_SELECTOR),
5376 vmcs_read16(HOST_FS_SELECTOR), vmcs_read16(HOST_GS_SELECTOR),
5377 vmcs_read16(HOST_TR_SELECTOR));
5378 pr_err("FSBase=%016lx GSBase=%016lx TRBase=%016lx\n",
5379 vmcs_readl(HOST_FS_BASE), vmcs_readl(HOST_GS_BASE),
5380 vmcs_readl(HOST_TR_BASE));
5381 pr_err("GDTBase=%016lx IDTBase=%016lx\n",
5382 vmcs_readl(HOST_GDTR_BASE), vmcs_readl(HOST_IDTR_BASE));
5383 pr_err("CR0=%016lx CR3=%016lx CR4=%016lx\n",
5384 vmcs_readl(HOST_CR0), vmcs_readl(HOST_CR3),
5385 vmcs_readl(HOST_CR4));
5386 pr_err("Sysenter RSP=%016lx CS:RIP=%04x:%016lx\n",
5387 vmcs_readl(HOST_IA32_SYSENTER_ESP),
5388 vmcs_read32(HOST_IA32_SYSENTER_CS),
5389 vmcs_readl(HOST_IA32_SYSENTER_EIP));
5390 if (vmexit_ctl & (VM_EXIT_LOAD_IA32_PAT | VM_EXIT_LOAD_IA32_EFER))
5391 pr_err("EFER = 0x%016llx PAT = 0x%016llx\n",
5392 vmcs_read64(HOST_IA32_EFER),
5393 vmcs_read64(HOST_IA32_PAT));
5394 if (cpu_has_load_perf_global_ctrl() &&
5395 vmexit_ctl & VM_EXIT_LOAD_IA32_PERF_GLOBAL_CTRL)
5396 pr_err("PerfGlobCtl = 0x%016llx\n",
5397 vmcs_read64(HOST_IA32_PERF_GLOBAL_CTRL));
ff651cb6 5398
55d2375e
SC		 5399 pr_err("*** Control State ***\n");
5400 pr_err("PinBased=%08x CPUBased=%08x SecondaryExec=%08x\n",
5401 pin_based_exec_ctrl, cpu_based_exec_ctrl, secondary_exec_control);
5402 pr_err("EntryControls=%08x ExitControls=%08x\n", vmentry_ctl, vmexit_ctl);
5403 pr_err("ExceptionBitmap=%08x PFECmask=%08x PFECmatch=%08x\n",
5404 vmcs_read32(EXCEPTION_BITMAP),
5405 vmcs_read32(PAGE_FAULT_ERROR_CODE_MASK),
5406 vmcs_read32(PAGE_FAULT_ERROR_CODE_MATCH));
5407 pr_err("VMEntry: intr_info=%08x errcode=%08x ilen=%08x\n",
5408 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5409 vmcs_read32(VM_ENTRY_EXCEPTION_ERROR_CODE),
5410 vmcs_read32(VM_ENTRY_INSTRUCTION_LEN));
5411 pr_err("VMExit: intr_info=%08x errcode=%08x ilen=%08x\n",
5412 vmcs_read32(VM_EXIT_INTR_INFO),
5413 vmcs_read32(VM_EXIT_INTR_ERROR_CODE),
5414 vmcs_read32(VM_EXIT_INSTRUCTION_LEN));
5415 pr_err(" reason=%08x qualification=%016lx\n",
5416 vmcs_read32(VM_EXIT_REASON), vmcs_readl(EXIT_QUALIFICATION));
5417 pr_err("IDTVectoring: info=%08x errcode=%08x\n",
5418 vmcs_read32(IDT_VECTORING_INFO_FIELD),
5419 vmcs_read32(IDT_VECTORING_ERROR_CODE));
5420 pr_err("TSC Offset = 0x%016llx\n", vmcs_read64(TSC_OFFSET));
5421 if (secondary_exec_control & SECONDARY_EXEC_TSC_SCALING)
5422 pr_err("TSC Multiplier = 0x%016llx\n",
5423 vmcs_read64(TSC_MULTIPLIER));
5424 if (cpu_based_exec_ctrl & CPU_BASED_TPR_SHADOW)
5425 pr_err("TPR Threshold = 0x%02x\n", vmcs_read32(TPR_THRESHOLD));
5426 if (pin_based_exec_ctrl & PIN_BASED_POSTED_INTR)
5427 pr_err("PostedIntrVec = 0x%02x\n", vmcs_read16(POSTED_INTR_NV));
5428 if ((secondary_exec_control & SECONDARY_EXEC_ENABLE_EPT))
5429 pr_err("EPT pointer = 0x%016llx\n", vmcs_read64(EPT_POINTER));
5430 n = vmcs_read32(CR3_TARGET_COUNT);
5431 for (i = 0; i + 1 < n; i += 4)
5432 pr_err("CR3 target%u=%016lx target%u=%016lx\n",
5433 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2),
5434 i + 1, vmcs_readl(CR3_TARGET_VALUE0 + i * 2 + 2));
5435 if (i < n)
5436 pr_err("CR3 target%u=%016lx\n",
5437 i, vmcs_readl(CR3_TARGET_VALUE0 + i * 2));
5438 if (secondary_exec_control & SECONDARY_EXEC_PAUSE_LOOP_EXITING)
5439 pr_err("PLE Gap=%08x Window=%08x\n",
5440 vmcs_read32(PLE_GAP), vmcs_read32(PLE_WINDOW));
5441 if (secondary_exec_control & SECONDARY_EXEC_ENABLE_VPID)
5442 pr_err("Virtual processor ID = 0x%04x\n",
5443 vmcs_read16(VIRTUAL_PROCESSOR_ID));
ff651cb6
WV		 5444}
5445
55d2375e
SC		 5446/*
5447 * The guest has exited. See if we can fix it or if we need userspace
5448 * assistance.
5449 */
5450static int vmx_handle_exit(struct kvm_vcpu *vcpu)
ff651cb6 5451{
55d2375e
SC		 5452 struct vcpu_vmx *vmx = to_vmx(vcpu);
5453 u32 exit_reason = vmx->exit_reason;
5454 u32 vectoring_info = vmx->idt_vectoring_info;
ff651cb6 5455
55d2375e 5456 trace_kvm_exit(exit_reason, vcpu, KVM_ISA_VMX);
ff651cb6 5457
55d2375e
SC		 5458 /*
5459 * Flush logged GPAs PML buffer, this will make dirty_bitmap more
5460 * updated. Another good is, in kvm_vm_ioctl_get_dirty_log, before
5461 * querying dirty_bitmap, we only need to kick all vcpus out of guest
5462 * mode as if vcpus is in root mode, the PML buffer must has been
5463 * flushed already.
5464 */
5465 if (enable_pml)
5466 vmx_flush_pml_buffer(vcpu);
1dc35dac 5467
55d2375e
SC		 5468 /* If guest state is invalid, start emulating */
5469 if (vmx->emulation_required)
5470 return handle_invalid_guest_state(vcpu);
1dc35dac 5471
55d2375e
SC		 5472 if (is_guest_mode(vcpu) && nested_vmx_exit_reflected(vcpu, exit_reason))
5473 return nested_vmx_reflect_vmexit(vcpu, exit_reason);
9ed38ffa 5474
55d2375e
SC		 5475 if (exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY) {
5476 dump_vmcs();
5477 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5478 vcpu->run->fail_entry.hardware_entry_failure_reason
5479 = exit_reason;
5480 return 0;
9ed38ffa
LP		 5481 }
5482
55d2375e
SC		 5483 if (unlikely(vmx->fail)) {
5484 vcpu->run->exit_reason = KVM_EXIT_FAIL_ENTRY;
5485 vcpu->run->fail_entry.hardware_entry_failure_reason
5486 = vmcs_read32(VM_INSTRUCTION_ERROR);
5487 return 0;
5488 }
50c28f21 5489
55d2375e
SC		 5490 /*
5491 * Note:
5492 * Do not try to fix EXIT_REASON_EPT_MISCONFIG if it caused by
5493 * delivery event since it indicates guest is accessing MMIO.
5494 * The vm-exit can be triggered again after return to guest that
5495 * will cause infinite loop.
5496 */
5497 if ((vectoring_info & VECTORING_INFO_VALID_MASK) &&
5498 (exit_reason != EXIT_REASON_EXCEPTION_NMI &&
5499 exit_reason != EXIT_REASON_EPT_VIOLATION &&
5500 exit_reason != EXIT_REASON_PML_FULL &&
5501 exit_reason != EXIT_REASON_TASK_SWITCH)) {
5502 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
5503 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_DELIVERY_EV;
5504 vcpu->run->internal.ndata = 3;
5505 vcpu->run->internal.data[0] = vectoring_info;
5506 vcpu->run->internal.data[1] = exit_reason;
5507 vcpu->run->internal.data[2] = vcpu->arch.exit_qualification;
5508 if (exit_reason == EXIT_REASON_EPT_MISCONFIG) {
5509 vcpu->run->internal.ndata++;
5510 vcpu->run->internal.data[3] =
5511 vmcs_read64(GUEST_PHYSICAL_ADDRESS);
5512 }
5513 return 0;
5514 }
50c28f21 5515
55d2375e
SC		 5516 if (unlikely(!enable_vnmi &&
5517 vmx->loaded_vmcs->soft_vnmi_blocked)) {
5518 if (vmx_interrupt_allowed(vcpu)) {
5519 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5520 } else if (vmx->loaded_vmcs->vnmi_blocked_time > 1000000000LL &&
5521 vcpu->arch.nmi_pending) {
5522 /*
5523 * This CPU don't support us in finding the end of an
5524 * NMI-blocked window if the guest runs with IRQs
5525 * disabled. So we pull the trigger after 1 s of
5526 * futile waiting, but inform the user about this.
5527 */
5528 printk(KERN_WARNING "%s: Breaking out of NMI-blocked "
5529 "state on VCPU %d after 1 s timeout\n",
5530 __func__, vcpu->vcpu_id);
5531 vmx->loaded_vmcs->soft_vnmi_blocked = 0;
5532 }
5533 }
50c28f21 5534
55d2375e
SC		 5535 if (exit_reason < kvm_vmx_max_exit_handlers
5536 && kvm_vmx_exit_handlers[exit_reason])
5537 return kvm_vmx_exit_handlers[exit_reason](vcpu);
5538 else {
5539 vcpu_unimpl(vcpu, "vmx: unexpected exit reason 0x%x\n",
5540 exit_reason);
5541 kvm_queue_exception(vcpu, UD_VECTOR);
5542 return 1;
5543 }
9ed38ffa
LP		 5544}
5545
efebf0aa 5546/*
55d2375e
SC		 5547 * Software based L1D cache flush which is used when microcode providing
5548 * the cache control MSR is not loaded.
efebf0aa 5549 *
55d2375e
SC		 5550 * The L1D cache is 32 KiB on Nehalem and later microarchitectures, but to
5551 * flush it is required to read in 64 KiB because the replacement algorithm
5552 * is not exactly LRU. This could be sized at runtime via topology
5553 * information but as all relevant affected CPUs have 32KiB L1D cache size
5554 * there is no point in doing so.
efebf0aa 5555 */
55d2375e 5556static void vmx_l1d_flush(struct kvm_vcpu *vcpu)
fe3ef05c 5557{
55d2375e 5558 int size = PAGE_SIZE << L1D_CACHE_ORDER;
25a2e4fe
PB		 5559
5560 /*
55d2375e
SC		 5561 * This code is only executed when the the flush mode is 'cond' or
5562 * 'always'
25a2e4fe 5563 */
55d2375e
SC		 5564 if (static_branch_likely(&vmx_l1d_flush_cond)) {
5565 bool flush_l1d;
25a2e4fe 5566
55d2375e
SC		 5567 /*
5568 * Clear the per-vcpu flush bit, it gets set again
5569 * either from vcpu_run() or from one of the unsafe
5570 * VMEXIT handlers.
5571 */
5572 flush_l1d = vcpu->arch.l1tf_flush_l1d;
5573 vcpu->arch.l1tf_flush_l1d = false;
25a2e4fe 5574
55d2375e
SC		 5575 /*
5576 * Clear the per-cpu flush bit, it gets set again from
5577 * the interrupt handlers.
5578 */
5579 flush_l1d |= kvm_get_cpu_l1tf_flush_l1d();
5580 kvm_clear_cpu_l1tf_flush_l1d();
25a2e4fe 5581
55d2375e
SC		 5582 if (!flush_l1d)
5583 return;
5584 }
09abe320 5585
55d2375e 5586 vcpu->stat.l1d_flush++;
25a2e4fe 5587
55d2375e
SC		 5588 if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
5589 wrmsrl(MSR_IA32_FLUSH_CMD, L1D_FLUSH);
5590 return;
5591 }
25a2e4fe 5592
55d2375e
SC		 5593 asm volatile(
5594 /* First ensure the pages are in the TLB */
5595 "xorl %%eax, %%eax\n"
5596 ".Lpopulate_tlb:\n\t"
5597 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5598 "addl $4096, %%eax\n\t"
5599 "cmpl %%eax, %[size]\n\t"
5600 "jne .Lpopulate_tlb\n\t"
5601 "xorl %%eax, %%eax\n\t"
5602 "cpuid\n\t"
5603 /* Now fill the cache */
5604 "xorl %%eax, %%eax\n"
5605 ".Lfill_cache:\n"
5606 "movzbl (%[flush_pages], %%" _ASM_AX "), %%ecx\n\t"
5607 "addl $64, %%eax\n\t"
5608 "cmpl %%eax, %[size]\n\t"
5609 "jne .Lfill_cache\n\t"
5610 "lfence\n"
5611 :: [flush_pages] "r" (vmx_l1d_flush_pages),
5612 [size] "r" (size)
5613 : "eax", "ebx", "ecx", "edx");
09abe320 5614}
25a2e4fe 5615
55d2375e 5616static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
09abe320 5617{
55d2375e 5618 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
09abe320 5619
55d2375e
SC		 5620 if (is_guest_mode(vcpu) &&
5621 nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
5622 return;
25a2e4fe 5623
55d2375e
SC		 5624 if (irr == -1 || tpr < irr) {
5625 vmcs_write32(TPR_THRESHOLD, 0);
5626 return;
25a2e4fe 5627 }
55d2375e
SC		 5628
5629 vmcs_write32(TPR_THRESHOLD, irr);
8665c3f9
PB		 5630}
5631
55d2375e 5632void vmx_set_virtual_apic_mode(struct kvm_vcpu *vcpu)
8665c3f9 5633{
55d2375e 5634 u32 sec_exec_control;
8665c3f9 5635
55d2375e
SC		 5636 if (!lapic_in_kernel(vcpu))
5637 return;
9314006d 5638
55d2375e
SC		 5639 if (!flexpriority_enabled &&
5640 !cpu_has_vmx_virtualize_x2apic_mode())
5641 return;
705699a1 5642
55d2375e
SC		 5643 /* Postpone execution until vmcs01 is the current VMCS. */
5644 if (is_guest_mode(vcpu)) {
5645 to_vmx(vcpu)->nested.change_vmcs01_virtual_apic_mode = true;
5646 return;
6beb7bd5 5647 }
fe3ef05c 5648
55d2375e
SC		 5649 sec_exec_control = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
5650 sec_exec_control &= ~(SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
5651 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE);
09abe320 5652
55d2375e
SC		 5653 switch (kvm_get_apic_mode(vcpu)) {
5654 case LAPIC_MODE_INVALID:
5655 WARN_ONCE(true, "Invalid local APIC state");
5656 case LAPIC_MODE_DISABLED:
5657 break;
5658 case LAPIC_MODE_XAPIC:
5659 if (flexpriority_enabled) {
5660 sec_exec_control |=
5661 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES;
5662 vmx_flush_tlb(vcpu, true);
5663 }
5664 break;
5665 case LAPIC_MODE_X2APIC:
5666 if (cpu_has_vmx_virtualize_x2apic_mode())
5667 sec_exec_control |=
5668 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE;
5669 break;
09abe320 5670 }
55d2375e 5671 vmcs_write32(SECONDARY_VM_EXEC_CONTROL, sec_exec_control);
09abe320 5672
55d2375e
SC		 5673 vmx_update_msr_bitmap(vcpu);
5674}
0238ea91 5675
55d2375e
SC		 5676static void vmx_set_apic_access_page_addr(struct kvm_vcpu *vcpu, hpa_t hpa)
5677{
5678 if (!is_guest_mode(vcpu)) {
5679 vmcs_write64(APIC_ACCESS_ADDR, hpa);
5680 vmx_flush_tlb(vcpu, true);
5681 }
5682}
fe3ef05c 5683
55d2375e
SC		 5684static void vmx_hwapic_isr_update(struct kvm_vcpu *vcpu, int max_isr)
5685{
5686 u16 status;
5687 u8 old;
32c7acf0 5688
55d2375e
SC		 5689 if (max_isr == -1)
5690 max_isr = 0;
608406e2 5691
55d2375e
SC		 5692 status = vmcs_read16(GUEST_INTR_STATUS);
5693 old = status >> 8;
5694 if (max_isr != old) {
5695 status &= 0xff;
5696 status |= max_isr << 8;
5697 vmcs_write16(GUEST_INTR_STATUS, status);
5698 }
5699}
6beb7bd5 5700
55d2375e
SC		 5701static void vmx_set_rvi(int vector)
5702{
5703 u16 status;
5704 u8 old;
0b665d30 5705
55d2375e
SC		 5706 if (vector == -1)
5707 vector = 0;
fe3ef05c 5708
55d2375e
SC		 5709 status = vmcs_read16(GUEST_INTR_STATUS);
5710 old = (u8)status & 0xff;
5711 if ((u8)vector != old) {
5712 status &= ~0xff;
5713 status |= (u8)vector;
5714 vmcs_write16(GUEST_INTR_STATUS, status);
09abe320 5715 }
55d2375e 5716}
09abe320 5717
55d2375e
SC		 5718static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
5719{
09abe320 5720 /*
55d2375e
SC		 5721 * When running L2, updating RVI is only relevant when
5722 * vmcs12 virtual-interrupt-delivery enabled.
5723 * However, it can be enabled only when L1 also
5724 * intercepts external-interrupts and in that case
5725 * we should not update vmcs02 RVI but instead intercept
5726 * interrupt. Therefore, do nothing when running L2.
fe3ef05c 5727 */
55d2375e
SC		 5728 if (!is_guest_mode(vcpu))
5729 vmx_set_rvi(max_irr);
5730}
fe3ef05c 5731
55d2375e
SC		 5732static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
5733{
5734 struct vcpu_vmx *vmx = to_vmx(vcpu);
5735 int max_irr;
5736 bool max_irr_updated;
a7c0b07d 5737
55d2375e
SC		 5738 WARN_ON(!vcpu->arch.apicv_active);
5739 if (pi_test_on(&vmx->pi_desc)) {
5740 pi_clear_on(&vmx->pi_desc);
5741 /*
5742 * IOMMU can write to PIR.ON, so the barrier matters even on UP.
5743 * But on x86 this is just a compiler barrier anyway.
5744 */
5745 smp_mb__after_atomic();
5746 max_irr_updated =
5747 kvm_apic_update_irr(vcpu, vmx->pi_desc.pir, &max_irr);
c4ebd629
VK		 5748
5749 /*
55d2375e
SC		 5750 * If we are running L2 and L1 has a new pending interrupt
5751 * which can be injected, we should re-evaluate
5752 * what should be done with this new L1 interrupt.
5753 * If L1 intercepts external-interrupts, we should
5754 * exit from L2 to L1. Otherwise, interrupt should be
5755 * delivered directly to L2.
c4ebd629 5756 */
55d2375e
SC		 5757 if (is_guest_mode(vcpu) && max_irr_updated) {
5758 if (nested_exit_on_intr(vcpu))
5759 kvm_vcpu_exiting_guest_mode(vcpu);
5760 else
5761 kvm_make_request(KVM_REQ_EVENT, vcpu);
c4ebd629 5762 }
55d2375e
SC		 5763 } else {
5764 max_irr = kvm_lapic_find_highest_irr(vcpu);
a7c0b07d 5765 }
55d2375e
SC		 5766 vmx_hwapic_irr_update(vcpu, max_irr);
5767 return max_irr;
5768}
a7c0b07d 5769
55d2375e
SC		 5770static void vmx_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
5771{
5772 if (!kvm_vcpu_apicv_active(vcpu))
5773 return;
25a2e4fe 5774
55d2375e
SC		 5775 vmcs_write64(EOI_EXIT_BITMAP0, eoi_exit_bitmap[0]);
5776 vmcs_write64(EOI_EXIT_BITMAP1, eoi_exit_bitmap[1]);
5777 vmcs_write64(EOI_EXIT_BITMAP2, eoi_exit_bitmap[2]);
5778 vmcs_write64(EOI_EXIT_BITMAP3, eoi_exit_bitmap[3]);
8665c3f9
PB		 5779}
5780
55d2375e 5781static void vmx_apicv_post_state_restore(struct kvm_vcpu *vcpu)
8665c3f9
PB		 5782{
5783 struct vcpu_vmx *vmx = to_vmx(vcpu);
9d1887ef 5784
55d2375e
SC		 5785 pi_clear_on(&vmx->pi_desc);
5786 memset(vmx->pi_desc.pir, 0, sizeof(vmx->pi_desc.pir));
5787}
8665c3f9 5788
55d2375e
SC		 5789static void vmx_complete_atomic_exit(struct vcpu_vmx *vmx)
5790{
5791 u32 exit_intr_info = 0;
5792 u16 basic_exit_reason = (u16)vmx->exit_reason;
fe3ef05c 5793
55d2375e
SC		 5794 if (!(basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY
5795 || basic_exit_reason == EXIT_REASON_EXCEPTION_NMI))
5796 return;
fe3ef05c 5797
55d2375e
SC		 5798 if (!(vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
5799 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5800 vmx->exit_intr_info = exit_intr_info;
fe3ef05c 5801
55d2375e
SC		 5802 /* if exit due to PF check for async PF */
5803 if (is_page_fault(exit_intr_info))
5804 vmx->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
e79f245d 5805
55d2375e
SC		 5806 /* Handle machine checks before interrupts are enabled */
5807 if (basic_exit_reason == EXIT_REASON_MCE_DURING_VMENTRY ||
5808 is_machine_check(exit_intr_info))
5809 kvm_machine_check();
fe3ef05c 5810
55d2375e
SC		 5811 /* We need to handle NMIs before interrupts are enabled */
5812 if (is_nmi(exit_intr_info)) {
5813 kvm_before_interrupt(&vmx->vcpu);
5814 asm("int $2");
5815 kvm_after_interrupt(&vmx->vcpu);
fe3ef05c 5816 }
55d2375e 5817}
fe3ef05c 5818
55d2375e
SC		 5819static void vmx_handle_external_intr(struct kvm_vcpu *vcpu)
5820{
5821 u32 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
fe3ef05c 5822
55d2375e
SC		 5823 if ((exit_intr_info & (INTR_INFO_VALID_MASK | INTR_INFO_INTR_TYPE_MASK))
5824 == (INTR_INFO_VALID_MASK | INTR_TYPE_EXT_INTR)) {
5825 unsigned int vector;
5826 unsigned long entry;
5827 gate_desc *desc;
5828 struct vcpu_vmx *vmx = to_vmx(vcpu);
5829#ifdef CONFIG_X86_64
5830 unsigned long tmp;
5831#endif
fe3ef05c 5832
55d2375e
SC		 5833 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5834 desc = (gate_desc *)vmx->host_idt_base + vector;
5835 entry = gate_offset(desc);
5836 asm volatile(
5837#ifdef CONFIG_X86_64
5838 "mov %%" _ASM_SP ", %[sp]\n\t"
5839 "and $0xfffffffffffffff0, %%" _ASM_SP "\n\t"
5840 "push $%c[ss]\n\t"
5841 "push %[sp]\n\t"
5842#endif
5843 "pushf\n\t"
5844 __ASM_SIZE(push) " $%c[cs]\n\t"
5845 CALL_NOSPEC
5846 :
5847#ifdef CONFIG_X86_64
5848 [sp]"=&r"(tmp),
5849#endif
5850 ASM_CALL_CONSTRAINT
5851 :
5852 THUNK_TARGET(entry),
5853 [ss]"i"(__KERNEL_DS),
5854 [cs]"i"(__KERNEL_CS)
5855 );
5856 }
5857}
5858STACK_FRAME_NON_STANDARD(vmx_handle_external_intr);
5a6a9748 5859
55d2375e
SC		 5860static bool vmx_has_emulated_msr(int index)
5861{
5862 switch (index) {
5863 case MSR_IA32_SMBASE:
5864 /*
5865 * We cannot do SMM unless we can run the guest in big
5866 * real mode.
5867 */
5868 return enable_unrestricted_guest || emulate_invalid_guest_state;
5869 case MSR_AMD64_VIRT_SPEC_CTRL:
5870 /* This is AMD only. */
5871 return false;
5872 default:
5873 return true;
3184a995 5874 }
55d2375e 5875}
2bb8cafe 5876
55d2375e
SC		 5877static void vmx_recover_nmi_blocking(struct vcpu_vmx *vmx)
5878{
5879 u32 exit_intr_info;
5880 bool unblock_nmi;
5881 u8 vector;
5882 bool idtv_info_valid;
7ca29de2 5883
55d2375e 5884 idtv_info_valid = vmx->idt_vectoring_info & VECTORING_INFO_VALID_MASK;
feaf0c7d 5885
55d2375e
SC		 5886 if (enable_vnmi) {
5887 if (vmx->loaded_vmcs->nmi_known_unmasked)
5888 return;
5889 /*
5890 * Can't use vmx->exit_intr_info since we're not sure what
5891 * the exit reason is.
5892 */
5893 exit_intr_info = vmcs_read32(VM_EXIT_INTR_INFO);
5894 unblock_nmi = (exit_intr_info & INTR_INFO_UNBLOCK_NMI) != 0;
5895 vector = exit_intr_info & INTR_INFO_VECTOR_MASK;
5896 /*
5897 * SDM 3: 27.7.1.2 (September 2008)
5898 * Re-set bit "block by NMI" before VM entry if vmexit caused by
5899 * a guest IRET fault.
5900 * SDM 3: 23.2.2 (September 2008)
5901 * Bit 12 is undefined in any of the following cases:
5902 * If the VM exit sets the valid bit in the IDT-vectoring
5903 * information field.
5904 * If the VM exit is due to a double fault.
5905 */
5906 if ((exit_intr_info & INTR_INFO_VALID_MASK) && unblock_nmi &&
5907 vector != DF_VECTOR && !idtv_info_valid)
5908 vmcs_set_bits(GUEST_INTERRUPTIBILITY_INFO,
5909 GUEST_INTR_STATE_NMI);
5910 else
5911 vmx->loaded_vmcs->nmi_known_unmasked =
5912 !(vmcs_read32(GUEST_INTERRUPTIBILITY_INFO)
5913 & GUEST_INTR_STATE_NMI);
5914 } else if (unlikely(vmx->loaded_vmcs->soft_vnmi_blocked))
5915 vmx->loaded_vmcs->vnmi_blocked_time +=
5916 ktime_to_ns(ktime_sub(ktime_get(),
5917 vmx->loaded_vmcs->entry_time));
fe3ef05c
NHE		 5918}
5919
55d2375e
SC		 5920static void __vmx_complete_interrupts(struct kvm_vcpu *vcpu,
5921 u32 idt_vectoring_info,
5922 int instr_len_field,
5923 int error_code_field)
0c7f650e 5924{
55d2375e
SC		 5925 u8 vector;
5926 int type;
5927 bool idtv_info_valid;
0c7f650e 5928
55d2375e 5929 idtv_info_valid = idt_vectoring_info & VECTORING_INFO_VALID_MASK;
0c7f650e 5930
55d2375e
SC		 5931 vcpu->arch.nmi_injected = false;
5932 kvm_clear_exception_queue(vcpu);
5933 kvm_clear_interrupt_queue(vcpu);
27c42a1b 5934
55d2375e
SC		 5935 if (!idtv_info_valid)
5936 return;
c7c2c709 5937
55d2375e 5938 kvm_make_request(KVM_REQ_EVENT, vcpu);
ca0bde28 5939
55d2375e
SC		 5940 vector = idt_vectoring_info & VECTORING_INFO_VECTOR_MASK;
5941 type = idt_vectoring_info & VECTORING_INFO_TYPE_MASK;
64a919f7 5942
55d2375e
SC		 5943 switch (type) {
5944 case INTR_TYPE_NMI_INTR:
5945 vcpu->arch.nmi_injected = true;
5946 /*
5947 * SDM 3: 27.7.1.2 (September 2008)
5948 * Clear bit "block by NMI" before VM entry if a NMI
5949 * delivery faulted.
5950 */
5951 vmx_set_nmi_mask(vcpu, false);
5952 break;
5953 case INTR_TYPE_SOFT_EXCEPTION:
5954 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
5955 /* fall through */
5956 case INTR_TYPE_HARD_EXCEPTION:
5957 if (idt_vectoring_info & VECTORING_INFO_DELIVER_CODE_MASK) {
5958 u32 err = vmcs_read32(error_code_field);
5959 kvm_requeue_exception_e(vcpu, vector, err);
5960 } else
5961 kvm_requeue_exception(vcpu, vector);
5962 break;
5963 case INTR_TYPE_SOFT_INTR:
5964 vcpu->arch.event_exit_inst_len = vmcs_read32(instr_len_field);
5965 /* fall through */
5966 case INTR_TYPE_EXT_INTR:
5967 kvm_queue_interrupt(vcpu, vector, type == INTR_TYPE_SOFT_INTR);
5968 break;
5969 default:
5970 break;
0447378a 5971 }
ca0bde28
JM		 5972}
5973
55d2375e 5974static void vmx_complete_interrupts(struct vcpu_vmx *vmx)
f145d90d 5975{
55d2375e
SC		 5976 __vmx_complete_interrupts(&vmx->vcpu, vmx->idt_vectoring_info,
5977 VM_EXIT_INSTRUCTION_LEN,
5978 IDT_VECTORING_ERROR_CODE);
f145d90d
LA		 5979}
5980
55d2375e 5981static void vmx_cancel_injection(struct kvm_vcpu *vcpu)
ca0bde28 5982{
55d2375e
SC		 5983 __vmx_complete_interrupts(vcpu,
5984 vmcs_read32(VM_ENTRY_INTR_INFO_FIELD),
5985 VM_ENTRY_INSTRUCTION_LEN,
5986 VM_ENTRY_EXCEPTION_ERROR_CODE);
f1b026a3 5987
55d2375e 5988 vmcs_write32(VM_ENTRY_INTR_INFO_FIELD, 0);
ca0bde28
JM		 5989}
5990
55d2375e 5991static void atomic_switch_perf_msrs(struct vcpu_vmx *vmx)
52017608 5992{
55d2375e
SC		 5993 int i, nr_msrs;
5994 struct perf_guest_switch_msr *msrs;
7c177938 5995
55d2375e 5996 msrs = perf_guest_get_msrs(&nr_msrs);
384bb783 5997
55d2375e
SC		 5998 if (!msrs)
5999 return;
f1b026a3 6000
55d2375e
SC		 6001 for (i = 0; i < nr_msrs; i++)
6002 if (msrs[i].host == msrs[i].guest)
6003 clear_atomic_switch_msr(vmx, msrs[i].msr);
6004 else
6005 add_atomic_switch_msr(vmx, msrs[i].msr, msrs[i].guest,
6006 msrs[i].host, false);
ca0bde28 6007}
52017608 6008
55d2375e
SC		 6009static void vmx_arm_hv_timer(struct vcpu_vmx *vmx, u32 val)
6010{
6011 vmcs_write32(VMX_PREEMPTION_TIMER_VALUE, val);
6012 if (!vmx->loaded_vmcs->hv_timer_armed)
6013 vmcs_set_bits(PIN_BASED_VM_EXEC_CONTROL,
6014 PIN_BASED_VMX_PREEMPTION_TIMER);
6015 vmx->loaded_vmcs->hv_timer_armed = true;
6016}
ca0bde28 6017
55d2375e 6018static void vmx_update_hv_timer(struct kvm_vcpu *vcpu)
858e25c0
JM		 6019{
6020 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e
SC		 6021 u64 tscl;
6022 u32 delta_tsc;
52017608 6023
55d2375e
SC		 6024 if (vmx->req_immediate_exit) {
6025 vmx_arm_hv_timer(vmx, 0);
6026 return;
16fb9a46
SC		 6027 }
6028
55d2375e
SC		 6029 if (vmx->hv_deadline_tsc != -1) {
6030 tscl = rdtsc();
6031 if (vmx->hv_deadline_tsc > tscl)
6032 /* set_hv_timer ensures the delta fits in 32-bits */
6033 delta_tsc = (u32)((vmx->hv_deadline_tsc - tscl) >>
6034 cpu_preemption_timer_multi);
6035 else
6036 delta_tsc = 0;
858e25c0 6037
55d2375e
SC		 6038 vmx_arm_hv_timer(vmx, delta_tsc);
6039 return;
7f7f1ba3 6040 }
858e25c0 6041
55d2375e
SC		 6042 if (vmx->loaded_vmcs->hv_timer_armed)
6043 vmcs_clear_bits(PIN_BASED_VM_EXEC_CONTROL,
6044 PIN_BASED_VMX_PREEMPTION_TIMER);
6045 vmx->loaded_vmcs->hv_timer_armed = false;
858e25c0
JM		 6046}
6047
55d2375e 6048static void __noclone vmx_vcpu_run(struct kvm_vcpu *vcpu)
ca0bde28 6049{
ca0bde28 6050 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6051 unsigned long cr3, cr4, evmcs_rsp;
b3f1dfb6 6052
55d2375e
SC		 6053 /* Record the guest's net vcpu time for enforced NMI injections. */
6054 if (unlikely(!enable_vnmi &&
6055 vmx->loaded_vmcs->soft_vnmi_blocked))
6056 vmx->loaded_vmcs->entry_time = ktime_get();
ca0bde28 6057
55d2375e
SC		 6058 /* Don't enter VMX if guest state is invalid, let the exit handler
6059 start emulation until we arrive back to a valid state */
6060 if (vmx->emulation_required)
6061 return;
384bb783 6062
55d2375e
SC		 6063 if (vmx->ple_window_dirty) {
6064 vmx->ple_window_dirty = false;
6065 vmcs_write32(PLE_WINDOW, vmx->ple_window);
6066 }
ff651cb6 6067
55d2375e
SC		 6068 if (vmx->nested.need_vmcs12_sync)
6069 nested_sync_from_vmcs12(vcpu);
c595ceee 6070
55d2375e
SC		 6071 if (test_bit(VCPU_REGS_RSP, (unsigned long *)&vcpu->arch.regs_dirty))
6072 vmcs_writel(GUEST_RSP, vcpu->arch.regs[VCPU_REGS_RSP]);
6073 if (test_bit(VCPU_REGS_RIP, (unsigned long *)&vcpu->arch.regs_dirty))
6074 vmcs_writel(GUEST_RIP, vcpu->arch.regs[VCPU_REGS_RIP]);
61ada748 6075
55d2375e
SC		 6076 cr3 = __get_current_cr3_fast();
6077 if (unlikely(cr3 != vmx->loaded_vmcs->host_state.cr3)) {
6078 vmcs_writel(HOST_CR3, cr3);
6079 vmx->loaded_vmcs->host_state.cr3 = cr3;
6514dc38 6080 }
cd232ad0 6081
55d2375e
SC		 6082 cr4 = cr4_read_shadow();
6083 if (unlikely(cr4 != vmx->loaded_vmcs->host_state.cr4)) {
6084 vmcs_writel(HOST_CR4, cr4);
6085 vmx->loaded_vmcs->host_state.cr4 = cr4;
6086 }
4704d0be 6087
55d2375e
SC		 6088 /* When single-stepping over STI and MOV SS, we must clear the
6089 * corresponding interruptibility bits in the guest state. Otherwise
6090 * vmentry fails as it then expects bit 14 (BS) in pending debug
6091 * exceptions being set, but that's not correct for the guest debugging
6092 * case. */
6093 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
6094 vmx_set_interrupt_shadow(vcpu, 0);
4704d0be 6095
55d2375e
SC		 6096 if (static_cpu_has(X86_FEATURE_PKU) &&
6097 kvm_read_cr4_bits(vcpu, X86_CR4_PKE) &&
6098 vcpu->arch.pkru != vmx->host_pkru)
6099 __write_pkru(vcpu->arch.pkru);
5f3d5799 6100
55d2375e 6101 atomic_switch_perf_msrs(vmx);
5f3d5799 6102
55d2375e 6103 vmx_update_hv_timer(vcpu);
5f3d5799 6104
55d2375e
SC		 6105 /*
6106 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
6107 * it's non-zero. Since vmentry is serialising on affected CPUs, there
6108 * is no need to worry about the conditional branch over the wrmsr
6109 * being speculatively taken.
6110 */
6111 x86_spec_ctrl_set_guest(vmx->spec_ctrl, 0);
5f3d5799 6112
55d2375e 6113 vmx->__launched = vmx->loaded_vmcs->launched;
5f3d5799 6114
55d2375e
SC		 6115 evmcs_rsp = static_branch_unlikely(&enable_evmcs) ?
6116 (unsigned long)&current_evmcs->host_rsp : 0;
5f3d5799 6117
55d2375e
SC		 6118 if (static_branch_unlikely(&vmx_l1d_should_flush))
6119 vmx_l1d_flush(vcpu);
bfcf83b1 6120
55d2375e
SC		 6121 asm(
6122 /* Store host registers */
6123 "push %%" _ASM_DX "; push %%" _ASM_BP ";"
6124 "push %%" _ASM_CX " \n\t" /* placeholder for guest rcx */
6125 "push %%" _ASM_CX " \n\t"
6126 "cmp %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6127 "je 1f \n\t"
6128 "mov %%" _ASM_SP ", %c[host_rsp](%0) \n\t"
6129 /* Avoid VMWRITE when Enlightened VMCS is in use */
6130 "test %%" _ASM_SI ", %%" _ASM_SI " \n\t"
6131 "jz 2f \n\t"
6132 "mov %%" _ASM_SP ", (%%" _ASM_SI ") \n\t"
6133 "jmp 1f \n\t"
6134 "2: \n\t"
6135 __ex("vmwrite %%" _ASM_SP ", %%" _ASM_DX) "\n\t"
6136 "1: \n\t"
6137 /* Reload cr2 if changed */
6138 "mov %c[cr2](%0), %%" _ASM_AX " \n\t"
6139 "mov %%cr2, %%" _ASM_DX " \n\t"
6140 "cmp %%" _ASM_AX ", %%" _ASM_DX " \n\t"
6141 "je 3f \n\t"
6142 "mov %%" _ASM_AX", %%cr2 \n\t"
6143 "3: \n\t"
6144 /* Check if vmlaunch or vmresume is needed */
6145 "cmpl $0, %c[launched](%0) \n\t"
6146 /* Load guest registers. Don't clobber flags. */
6147 "mov %c[rax](%0), %%" _ASM_AX " \n\t"
6148 "mov %c[rbx](%0), %%" _ASM_BX " \n\t"
6149 "mov %c[rdx](%0), %%" _ASM_DX " \n\t"
6150 "mov %c[rsi](%0), %%" _ASM_SI " \n\t"
6151 "mov %c[rdi](%0), %%" _ASM_DI " \n\t"
6152 "mov %c[rbp](%0), %%" _ASM_BP " \n\t"
6153#ifdef CONFIG_X86_64
6154 "mov %c[r8](%0), %%r8 \n\t"
6155 "mov %c[r9](%0), %%r9 \n\t"
6156 "mov %c[r10](%0), %%r10 \n\t"
6157 "mov %c[r11](%0), %%r11 \n\t"
6158 "mov %c[r12](%0), %%r12 \n\t"
6159 "mov %c[r13](%0), %%r13 \n\t"
6160 "mov %c[r14](%0), %%r14 \n\t"
6161 "mov %c[r15](%0), %%r15 \n\t"
6162#endif
6163 "mov %c[rcx](%0), %%" _ASM_CX " \n\t" /* kills %0 (ecx) */
f4124500 6164
55d2375e
SC		 6165 /* Enter guest mode */
6166 "jne 1f \n\t"
6167 __ex("vmlaunch") "\n\t"
6168 "jmp 2f \n\t"
6169 "1: " __ex("vmresume") "\n\t"
6170 "2: "
6171 /* Save guest registers, load host registers, keep flags */
6172 "mov %0, %c[wordsize](%%" _ASM_SP ") \n\t"
6173 "pop %0 \n\t"
6174 "setbe %c[fail](%0)\n\t"
6175 "mov %%" _ASM_AX ", %c[rax](%0) \n\t"
6176 "mov %%" _ASM_BX ", %c[rbx](%0) \n\t"
6177 __ASM_SIZE(pop) " %c[rcx](%0) \n\t"
6178 "mov %%" _ASM_DX ", %c[rdx](%0) \n\t"
6179 "mov %%" _ASM_SI ", %c[rsi](%0) \n\t"
6180 "mov %%" _ASM_DI ", %c[rdi](%0) \n\t"
6181 "mov %%" _ASM_BP ", %c[rbp](%0) \n\t"
6182#ifdef CONFIG_X86_64
6183 "mov %%r8, %c[r8](%0) \n\t"
6184 "mov %%r9, %c[r9](%0) \n\t"
6185 "mov %%r10, %c[r10](%0) \n\t"
6186 "mov %%r11, %c[r11](%0) \n\t"
6187 "mov %%r12, %c[r12](%0) \n\t"
6188 "mov %%r13, %c[r13](%0) \n\t"
6189 "mov %%r14, %c[r14](%0) \n\t"
6190 "mov %%r15, %c[r15](%0) \n\t"
b6b8a145 6191 /*
55d2375e
SC		 6192 * Clear host registers marked as clobbered to prevent
6193 * speculative use.
6194 */
6195 "xor %%r8d, %%r8d \n\t"
6196 "xor %%r9d, %%r9d \n\t"
6197 "xor %%r10d, %%r10d \n\t"
6198 "xor %%r11d, %%r11d \n\t"
6199 "xor %%r12d, %%r12d \n\t"
6200 "xor %%r13d, %%r13d \n\t"
6201 "xor %%r14d, %%r14d \n\t"
6202 "xor %%r15d, %%r15d \n\t"
6203#endif
6204 "mov %%cr2, %%" _ASM_AX " \n\t"
6205 "mov %%" _ASM_AX ", %c[cr2](%0) \n\t"
b6b8a145 6206
55d2375e
SC		 6207 "xor %%eax, %%eax \n\t"
6208 "xor %%ebx, %%ebx \n\t"
6209 "xor %%esi, %%esi \n\t"
6210 "xor %%edi, %%edi \n\t"
6211 "pop %%" _ASM_BP "; pop %%" _ASM_DX " \n\t"
6212 ".pushsection .rodata \n\t"
6213 ".global vmx_return \n\t"
6214 "vmx_return: " _ASM_PTR " 2b \n\t"
6215 ".popsection"
6216 : : "c"(vmx), "d"((unsigned long)HOST_RSP), "S"(evmcs_rsp),
6217 [launched]"i"(offsetof(struct vcpu_vmx, __launched)),
6218 [fail]"i"(offsetof(struct vcpu_vmx, fail)),
6219 [host_rsp]"i"(offsetof(struct vcpu_vmx, host_rsp)),
6220 [rax]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RAX])),
6221 [rbx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBX])),
6222 [rcx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RCX])),
6223 [rdx]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDX])),
6224 [rsi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RSI])),
6225 [rdi]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RDI])),
6226 [rbp]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_RBP])),
6227#ifdef CONFIG_X86_64
6228 [r8]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R8])),
6229 [r9]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R9])),
6230 [r10]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R10])),
6231 [r11]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R11])),
6232 [r12]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R12])),
6233 [r13]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R13])),
6234 [r14]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R14])),
6235 [r15]"i"(offsetof(struct vcpu_vmx, vcpu.arch.regs[VCPU_REGS_R15])),
6236#endif
6237 [cr2]"i"(offsetof(struct vcpu_vmx, vcpu.arch.cr2)),
6238 [wordsize]"i"(sizeof(ulong))
6239 : "cc", "memory"
6240#ifdef CONFIG_X86_64
6241 , "rax", "rbx", "rdi"
6242 , "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
6243#else
6244 , "eax", "ebx", "edi"
6245#endif
6246 );
b6b8a145 6247
55d2375e
SC		 6248 /*
6249 * We do not use IBRS in the kernel. If this vCPU has used the
6250 * SPEC_CTRL MSR it may have left it on; save the value and
6251 * turn it off. This is much more efficient than blindly adding
6252 * it to the atomic save/restore list. Especially as the former
6253 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
6254 *
6255 * For non-nested case:
6256 * If the L01 MSR bitmap does not intercept the MSR, then we need to
6257 * save it.
6258 *
6259 * For nested case:
6260 * If the L02 MSR bitmap does not intercept the MSR, then we need to
6261 * save it.
6262 */
6263 if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
6264 vmx->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
b6b8a145 6265
55d2375e 6266 x86_spec_ctrl_restore_host(vmx->spec_ctrl, 0);
d264ee0c 6267
55d2375e
SC		 6268 /* Eliminate branch target predictions from guest mode */
6269 vmexit_fill_RSB();
f4124500 6270
55d2375e
SC		 6271 /* All fields are clean at this point */
6272 if (static_branch_unlikely(&enable_evmcs))
6273 current_evmcs->hv_clean_fields |=
6274 HV_VMX_ENLIGHTENED_CLEAN_FIELD_ALL;
f4124500 6275
55d2375e
SC		 6276 /* MSR_IA32_DEBUGCTLMSR is zeroed on vmexit. Restore it if needed */
6277 if (vmx->host_debugctlmsr)
6278 update_debugctlmsr(vmx->host_debugctlmsr);
f4124500 6279
55d2375e
SC		 6280#ifndef CONFIG_X86_64
6281 /*
6282 * The sysexit path does not restore ds/es, so we must set them to
6283 * a reasonable value ourselves.
6284 *
6285 * We can't defer this to vmx_prepare_switch_to_host() since that
6286 * function may be executed in interrupt context, which saves and
6287 * restore segments around it, nullifying its effect.
6288 */
6289 loadsegment(ds, __USER_DS);
6290 loadsegment(es, __USER_DS);
6291#endif
4704d0be 6292
55d2375e
SC		 6293 vcpu->arch.regs_avail = ~((1 << VCPU_REGS_RIP) | (1 << VCPU_REGS_RSP)
6294 | (1 << VCPU_EXREG_RFLAGS)
6295 | (1 << VCPU_EXREG_PDPTR)
6296 | (1 << VCPU_EXREG_SEGMENTS)
6297 | (1 << VCPU_EXREG_CR3));
6298 vcpu->arch.regs_dirty = 0;
7854cbca 6299
3633cfc3 6300 /*
55d2375e
SC		 6301 * eager fpu is enabled if PKEY is supported and CR4 is switched
6302 * back on host, so it is safe to read guest PKRU from current
6303 * XSAVE.
3633cfc3 6304 */
55d2375e
SC		 6305 if (static_cpu_has(X86_FEATURE_PKU) &&
6306 kvm_read_cr4_bits(vcpu, X86_CR4_PKE)) {
6307 vcpu->arch.pkru = __read_pkru();
6308 if (vcpu->arch.pkru != vmx->host_pkru)
6309 __write_pkru(vmx->host_pkru);
3633cfc3
NHE		 6310 }
6311
55d2375e
SC		 6312 vmx->nested.nested_run_pending = 0;
6313 vmx->idt_vectoring_info = 0;
119a9c01 6314
55d2375e
SC		 6315 vmx->exit_reason = vmx->fail ? 0xdead : vmcs_read32(VM_EXIT_REASON);
6316 if (vmx->fail || (vmx->exit_reason & VMX_EXIT_REASONS_FAILED_VMENTRY))
6317 return;
608406e2 6318
55d2375e
SC		 6319 vmx->loaded_vmcs->launched = 1;
6320 vmx->idt_vectoring_info = vmcs_read32(IDT_VECTORING_INFO_FIELD);
c18911a2 6321
55d2375e
SC		 6322 vmx_complete_atomic_exit(vmx);
6323 vmx_recover_nmi_blocking(vmx);
6324 vmx_complete_interrupts(vmx);
6325}
6326STACK_FRAME_NON_STANDARD(vmx_vcpu_run);
2996fca0 6327
55d2375e
SC		 6328static struct kvm *vmx_vm_alloc(void)
6329{
6330 struct kvm_vmx *kvm_vmx = vzalloc(sizeof(struct kvm_vmx));
6331 return &kvm_vmx->kvm;
cf8b84f4
JM		 6332}
6333
55d2375e
SC		 6334static void vmx_vm_free(struct kvm *kvm)
6335{
6336 vfree(to_kvm_vmx(kvm));
6337}
6338
6339static void vmx_free_vcpu(struct kvm_vcpu *vcpu)
cf8b84f4 6340{
55d2375e 6341 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 6342
55d2375e
SC		 6343 if (enable_pml)
6344 vmx_destroy_pml_buffer(vmx);
6345 free_vpid(vmx->vpid);
6346 leave_guest_mode(vcpu);
6347 nested_vmx_free_vcpu(vcpu);
6348 free_loaded_vmcs(vmx->loaded_vmcs);
6349 kfree(vmx->guest_msrs);
6350 kvm_vcpu_uninit(vcpu);
b666a4b6 6351 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
55d2375e
SC		 6352 kmem_cache_free(kvm_vcpu_cache, vmx);
6353}
4704d0be 6354
55d2375e
SC		 6355static struct kvm_vcpu *vmx_create_vcpu(struct kvm *kvm, unsigned int id)
6356{
6357 int err;
6358 struct vcpu_vmx *vmx = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
6359 unsigned long *msr_bitmap;
6360 int cpu;
7313c698 6361
55d2375e
SC		 6362 if (!vmx)
6363 return ERR_PTR(-ENOMEM);
4704d0be 6364
b666a4b6
MO		 6365 vmx->vcpu.arch.guest_fpu = kmem_cache_zalloc(x86_fpu_cache, GFP_KERNEL);
6366 if (!vmx->vcpu.arch.guest_fpu) {
6367 printk(KERN_ERR "kvm: failed to allocate vcpu's fpu\n");
6368 err = -ENOMEM;
6369 goto free_partial_vcpu;
6370 }
6371
55d2375e 6372 vmx->vpid = allocate_vpid();
7cdc2d62 6373
55d2375e
SC		 6374 err = kvm_vcpu_init(&vmx->vcpu, kvm, id);
6375 if (err)
6376 goto free_vcpu;
5f3d5799 6377
55d2375e 6378 err = -ENOMEM;
5f3d5799
JK		 6379
6380 /*
55d2375e
SC		 6381 * If PML is turned on, failure on enabling PML just results in failure
6382 * of creating the vcpu, therefore we can simplify PML logic (by
6383 * avoiding dealing with cases, such as enabling PML partially on vcpus
6384 * for the guest, etc.
5f3d5799 6385 */
55d2375e
SC		 6386 if (enable_pml) {
6387 vmx->pml_pg = alloc_page(GFP_KERNEL | __GFP_ZERO);
6388 if (!vmx->pml_pg)
6389 goto uninit_vcpu;
6390 }
4704d0be 6391
55d2375e
SC		 6392 vmx->guest_msrs = kmalloc(PAGE_SIZE, GFP_KERNEL);
6393 BUILD_BUG_ON(ARRAY_SIZE(vmx_msr_index) * sizeof(vmx->guest_msrs[0])
6394 > PAGE_SIZE);
21feb4eb 6395
55d2375e
SC		 6396 if (!vmx->guest_msrs)
6397 goto free_pml;
4704d0be 6398
55d2375e
SC		 6399 err = alloc_loaded_vmcs(&vmx->vmcs01);
6400 if (err < 0)
6401 goto free_msrs;
cb61de2f 6402
55d2375e
SC		 6403 msr_bitmap = vmx->vmcs01.msr_bitmap;
6404 vmx_disable_intercept_for_msr(msr_bitmap, MSR_FS_BASE, MSR_TYPE_RW);
6405 vmx_disable_intercept_for_msr(msr_bitmap, MSR_GS_BASE, MSR_TYPE_RW);
6406 vmx_disable_intercept_for_msr(msr_bitmap, MSR_KERNEL_GS_BASE, MSR_TYPE_RW);
6407 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_CS, MSR_TYPE_RW);
6408 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_ESP, MSR_TYPE_RW);
6409 vmx_disable_intercept_for_msr(msr_bitmap, MSR_IA32_SYSENTER_EIP, MSR_TYPE_RW);
6410 vmx->msr_bitmap_mode = 0;
4704d0be 6411
55d2375e
SC		 6412 vmx->loaded_vmcs = &vmx->vmcs01;
6413 cpu = get_cpu();
6414 vmx_vcpu_load(&vmx->vcpu, cpu);
6415 vmx->vcpu.cpu = cpu;
6416 vmx_vcpu_setup(vmx);
6417 vmx_vcpu_put(&vmx->vcpu);
6418 put_cpu();
6419 if (cpu_need_virtualize_apic_accesses(&vmx->vcpu)) {
6420 err = alloc_apic_access_page(kvm);
6421 if (err)
6422 goto free_vmcs;
6423 }
6424
6425 if (enable_ept && !enable_unrestricted_guest) {
6426 err = init_rmode_identity_map(kvm);
6427 if (err)
6428 goto free_vmcs;
6429 }
4704d0be 6430
55d2375e
SC		 6431 if (nested)
6432 nested_vmx_setup_ctls_msrs(&vmx->nested.msrs,
6433 vmx_capability.ept,
6434 kvm_vcpu_apicv_active(&vmx->vcpu));
6435 else
6436 memset(&vmx->nested.msrs, 0, sizeof(vmx->nested.msrs));
bd18bffc 6437
55d2375e
SC		 6438 vmx->nested.posted_intr_nv = -1;
6439 vmx->nested.current_vmptr = -1ull;
bd18bffc 6440
55d2375e 6441 vmx->msr_ia32_feature_control_valid_bits = FEATURE_CONTROL_LOCKED;
feaf0c7d 6442
6f1e03bc 6443 /*
55d2375e
SC		 6444 * Enforce invariant: pi_desc.nv is always either POSTED_INTR_VECTOR
6445 * or POSTED_INTR_WAKEUP_VECTOR.
6f1e03bc 6446 */
55d2375e
SC		 6447 vmx->pi_desc.nv = POSTED_INTR_VECTOR;
6448 vmx->pi_desc.sn = 1;
4704d0be 6449
53963a70
LT		 6450 vmx->ept_pointer = INVALID_PAGE;
6451
55d2375e 6452 return &vmx->vcpu;
4704d0be 6453
55d2375e
SC		 6454free_vmcs:
6455 free_loaded_vmcs(vmx->loaded_vmcs);
6456free_msrs:
6457 kfree(vmx->guest_msrs);
6458free_pml:
6459 vmx_destroy_pml_buffer(vmx);
6460uninit_vcpu:
6461 kvm_vcpu_uninit(&vmx->vcpu);
6462free_vcpu:
6463 free_vpid(vmx->vpid);
b666a4b6
MO		 6464 kmem_cache_free(x86_fpu_cache, vmx->vcpu.arch.guest_fpu);
6465free_partial_vcpu:
55d2375e
SC		 6466 kmem_cache_free(kvm_vcpu_cache, vmx);
6467 return ERR_PTR(err);
6468}
36be0b9d 6469
55d2375e
SC		 6470#define L1TF_MSG_SMT "L1TF CPU bug present and SMT on, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
6471#define L1TF_MSG_L1D "L1TF CPU bug present and virtualization mitigation disabled, data leak possible. See CVE-2018-3646 and https://www.kernel.org/doc/html/latest/admin-guide/l1tf.html for details.\n"
21feb4eb 6472
55d2375e
SC		 6473static int vmx_vm_init(struct kvm *kvm)
6474{
6475 spin_lock_init(&to_kvm_vmx(kvm)->ept_pointer_lock);
ff651cb6 6476
55d2375e
SC		 6477 if (!ple_gap)
6478 kvm->arch.pause_in_guest = true;
3af18d9c 6479
55d2375e
SC		 6480 if (boot_cpu_has(X86_BUG_L1TF) && enable_ept) {
6481 switch (l1tf_mitigation) {
6482 case L1TF_MITIGATION_OFF:
6483 case L1TF_MITIGATION_FLUSH_NOWARN:
6484 /* 'I explicitly don't care' is set */
6485 break;
6486 case L1TF_MITIGATION_FLUSH:
6487 case L1TF_MITIGATION_FLUSH_NOSMT:
6488 case L1TF_MITIGATION_FULL:
6489 /*
6490 * Warn upon starting the first VM in a potentially
6491 * insecure environment.
6492 */
6493 if (cpu_smt_control == CPU_SMT_ENABLED)
6494 pr_warn_once(L1TF_MSG_SMT);
6495 if (l1tf_vmx_mitigation == VMENTER_L1D_FLUSH_NEVER)
6496 pr_warn_once(L1TF_MSG_L1D);
6497 break;
6498 case L1TF_MITIGATION_FULL_FORCE:
6499 /* Flush is enforced */
6500 break;
6501 }
6502 }
6503 return 0;
4704d0be
NHE		 6504}
6505
55d2375e 6506static void __init vmx_check_processor_compat(void *rtn)
bd18bffc 6507{
55d2375e
SC		 6508 struct vmcs_config vmcs_conf;
6509 struct vmx_capability vmx_cap;
bd18bffc 6510
55d2375e
SC		 6511 *(int *)rtn = 0;
6512 if (setup_vmcs_config(&vmcs_conf, &vmx_cap) < 0)
6513 *(int *)rtn = -EIO;
6514 if (nested)
6515 nested_vmx_setup_ctls_msrs(&vmcs_conf.nested, vmx_cap.ept,
6516 enable_apicv);
6517 if (memcmp(&vmcs_config, &vmcs_conf, sizeof(struct vmcs_config)) != 0) {
6518 printk(KERN_ERR "kvm: CPU %d feature inconsistency!\n",
6519 smp_processor_id());
6520 *(int *)rtn = -EIO;
bd18bffc 6521 }
bd18bffc
SC		 6522}
6523
55d2375e 6524static u64 vmx_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
bd18bffc 6525{
55d2375e
SC		 6526 u8 cache;
6527 u64 ipat = 0;
bd18bffc 6528
55d2375e
SC		 6529 /* For VT-d and EPT combination
6530 * 1. MMIO: always map as UC
6531 * 2. EPT with VT-d:
6532 * a. VT-d without snooping control feature: can't guarantee the
6533 * result, try to trust guest.
6534 * b. VT-d with snooping control feature: snooping control feature of
6535 * VT-d engine can guarantee the cache correctness. Just set it
6536 * to WB to keep consistent with host. So the same as item 3.
6537 * 3. EPT without VT-d: always map as WB and set IPAT=1 to keep
6538 * consistent with host MTRR
bd18bffc 6539 */
55d2375e
SC		 6540 if (is_mmio) {
6541 cache = MTRR_TYPE_UNCACHABLE;
6542 goto exit;
6543 }
bd18bffc 6544
55d2375e
SC		 6545 if (!kvm_arch_has_noncoherent_dma(vcpu->kvm)) {
6546 ipat = VMX_EPT_IPAT_BIT;
6547 cache = MTRR_TYPE_WRBACK;
6548 goto exit;
6549 }
bd18bffc 6550
55d2375e
SC		 6551 if (kvm_read_cr0(vcpu) & X86_CR0_CD) {
6552 ipat = VMX_EPT_IPAT_BIT;
6553 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
6554 cache = MTRR_TYPE_WRBACK;
6555 else
6556 cache = MTRR_TYPE_UNCACHABLE;
6557 goto exit;
6558 }
bd18bffc 6559
55d2375e 6560 cache = kvm_mtrr_get_guest_memory_type(vcpu, gfn);
bd18bffc 6561
55d2375e
SC		 6562exit:
6563 return (cache << VMX_EPT_MT_EPTE_SHIFT) | ipat;
6564}
bd18bffc 6565
55d2375e
SC		 6566static int vmx_get_lpage_level(void)
6567{
6568 if (enable_ept && !cpu_has_vmx_ept_1g_page())
6569 return PT_DIRECTORY_LEVEL;
6570 else
6571 /* For shadow and EPT supported 1GB page */
6572 return PT_PDPE_LEVEL;
6573}
bd18bffc 6574
55d2375e
SC		 6575static void vmcs_set_secondary_exec_control(u32 new_ctl)
6576{
bd18bffc 6577 /*
55d2375e
SC		 6578 * These bits in the secondary execution controls field
6579 * are dynamic, the others are mostly based on the hypervisor
6580 * architecture and the guest's CPUID. Do not touch the
6581 * dynamic bits.
bd18bffc 6582 */
55d2375e
SC		 6583 u32 mask =
6584 SECONDARY_EXEC_SHADOW_VMCS |
6585 SECONDARY_EXEC_VIRTUALIZE_X2APIC_MODE |
6586 SECONDARY_EXEC_VIRTUALIZE_APIC_ACCESSES |
6587 SECONDARY_EXEC_DESC;
bd18bffc 6588
55d2375e 6589 u32 cur_ctl = vmcs_read32(SECONDARY_VM_EXEC_CONTROL);
bd18bffc 6590
55d2375e
SC		 6591 vmcs_write32(SECONDARY_VM_EXEC_CONTROL,
6592 (new_ctl & ~mask) | (cur_ctl & mask));
bd18bffc
SC		 6593}
6594
4704d0be 6595/*
55d2375e
SC		 6596 * Generate MSR_IA32_VMX_CR{0,4}_FIXED1 according to CPUID. Only set bits
6597 * (indicating "allowed-1") if they are supported in the guest's CPUID.
4704d0be 6598 */
55d2375e 6599static void nested_vmx_cr_fixed1_bits_update(struct kvm_vcpu *vcpu)
4704d0be
NHE		 6600{
6601 struct vcpu_vmx *vmx = to_vmx(vcpu);
55d2375e 6602 struct kvm_cpuid_entry2 *entry;
4704d0be 6603
55d2375e
SC		 6604 vmx->nested.msrs.cr0_fixed1 = 0xffffffff;
6605 vmx->nested.msrs.cr4_fixed1 = X86_CR4_PCE;
e79f245d 6606
55d2375e
SC		 6607#define cr4_fixed1_update(_cr4_mask, _reg, _cpuid_mask) do { \
6608 if (entry && (entry->_reg & (_cpuid_mask))) \
6609 vmx->nested.msrs.cr4_fixed1 |= (_cr4_mask); \
6610} while (0)
ff651cb6 6611
55d2375e
SC		 6612 entry = kvm_find_cpuid_entry(vcpu, 0x1, 0);
6613 cr4_fixed1_update(X86_CR4_VME, edx, bit(X86_FEATURE_VME));
6614 cr4_fixed1_update(X86_CR4_PVI, edx, bit(X86_FEATURE_VME));
6615 cr4_fixed1_update(X86_CR4_TSD, edx, bit(X86_FEATURE_TSC));
6616 cr4_fixed1_update(X86_CR4_DE, edx, bit(X86_FEATURE_DE));
6617 cr4_fixed1_update(X86_CR4_PSE, edx, bit(X86_FEATURE_PSE));
6618 cr4_fixed1_update(X86_CR4_PAE, edx, bit(X86_FEATURE_PAE));
6619 cr4_fixed1_update(X86_CR4_MCE, edx, bit(X86_FEATURE_MCE));
6620 cr4_fixed1_update(X86_CR4_PGE, edx, bit(X86_FEATURE_PGE));
6621 cr4_fixed1_update(X86_CR4_OSFXSR, edx, bit(X86_FEATURE_FXSR));
6622 cr4_fixed1_update(X86_CR4_OSXMMEXCPT, edx, bit(X86_FEATURE_XMM));
6623 cr4_fixed1_update(X86_CR4_VMXE, ecx, bit(X86_FEATURE_VMX));
6624 cr4_fixed1_update(X86_CR4_SMXE, ecx, bit(X86_FEATURE_SMX));
6625 cr4_fixed1_update(X86_CR4_PCIDE, ecx, bit(X86_FEATURE_PCID));
6626 cr4_fixed1_update(X86_CR4_OSXSAVE, ecx, bit(X86_FEATURE_XSAVE));
61ada748 6627
55d2375e
SC		 6628 entry = kvm_find_cpuid_entry(vcpu, 0x7, 0);
6629 cr4_fixed1_update(X86_CR4_FSGSBASE, ebx, bit(X86_FEATURE_FSGSBASE));
6630 cr4_fixed1_update(X86_CR4_SMEP, ebx, bit(X86_FEATURE_SMEP));
6631 cr4_fixed1_update(X86_CR4_SMAP, ebx, bit(X86_FEATURE_SMAP));
6632 cr4_fixed1_update(X86_CR4_PKE, ecx, bit(X86_FEATURE_PKU));
6633 cr4_fixed1_update(X86_CR4_UMIP, ecx, bit(X86_FEATURE_UMIP));
cf3215d9 6634
55d2375e
SC		 6635#undef cr4_fixed1_update
6636}
36c3cc42 6637
55d2375e
SC		 6638static void nested_vmx_entry_exit_ctls_update(struct kvm_vcpu *vcpu)
6639{
6640 struct vcpu_vmx *vmx = to_vmx(vcpu);
f459a707 6641
55d2375e
SC		 6642 if (kvm_mpx_supported()) {
6643 bool mpx_enabled = guest_cpuid_has(vcpu, X86_FEATURE_MPX);
4704d0be 6644
55d2375e
SC		 6645 if (mpx_enabled) {
6646 vmx->nested.msrs.entry_ctls_high |= VM_ENTRY_LOAD_BNDCFGS;
6647 vmx->nested.msrs.exit_ctls_high |= VM_EXIT_CLEAR_BNDCFGS;
6648 } else {
6649 vmx->nested.msrs.entry_ctls_high &= ~VM_ENTRY_LOAD_BNDCFGS;
6650 vmx->nested.msrs.exit_ctls_high &= ~VM_EXIT_CLEAR_BNDCFGS;
6651 }
dccbfcf5 6652 }
55d2375e 6653}
4704d0be 6654
55d2375e
SC		 6655static void vmx_cpuid_update(struct kvm_vcpu *vcpu)
6656{
6657 struct vcpu_vmx *vmx = to_vmx(vcpu);
4704d0be 6658
55d2375e
SC		 6659 if (cpu_has_secondary_exec_ctrls()) {
6660 vmx_compute_secondary_exec_control(vmx);
6661 vmcs_set_secondary_exec_control(vmx->secondary_exec_control);
705699a1 6662 }
4704d0be 6663
55d2375e
SC		 6664 if (nested_vmx_allowed(vcpu))
6665 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
6666 FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
6667 else
6668 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
6669 ~FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX;
4f350c6d 6670
55d2375e
SC		 6671 if (nested_vmx_allowed(vcpu)) {
6672 nested_vmx_cr_fixed1_bits_update(vcpu);
6673 nested_vmx_entry_exit_ctls_update(vcpu);
4f350c6d 6674 }
55d2375e 6675}
09abb5e3 6676
55d2375e
SC		 6677static void vmx_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
6678{
6679 if (func == 1 && nested)
6680 entry->ecx |= bit(X86_FEATURE_VMX);
4704d0be
NHE		 6681}
6682
55d2375e 6683static void vmx_request_immediate_exit(struct kvm_vcpu *vcpu)
42124925 6684{
55d2375e 6685 to_vmx(vcpu)->req_immediate_exit = true;
7c177938
NHE		 6686}
6687
8a76d7f2
JR		 6688static int vmx_check_intercept(struct kvm_vcpu *vcpu,
6689 struct x86_instruction_info *info,
6690 enum x86_intercept_stage stage)
6691{
fb6d4d34
PB		 6692 struct vmcs12 *vmcs12 = get_vmcs12(vcpu);
6693 struct x86_emulate_ctxt *ctxt = &vcpu->arch.emulate_ctxt;
6694
6695 /*
6696 * RDPID causes #UD if disabled through secondary execution controls.
6697 * Because it is marked as EmulateOnUD, we need to intercept it here.
6698 */
6699 if (info->intercept == x86_intercept_rdtscp &&
6700 !nested_cpu_has2(vmcs12, SECONDARY_EXEC_RDTSCP)) {
6701 ctxt->exception.vector = UD_VECTOR;
6702 ctxt->exception.error_code_valid = false;
6703 return X86EMUL_PROPAGATE_FAULT;
6704 }
6705
6706 /* TODO: check more intercepts... */
8a76d7f2
JR		 6707 return X86EMUL_CONTINUE;
6708}
6709
64672c95
YJ		 6710#ifdef CONFIG_X86_64
6711/* (a << shift) / divisor, return 1 if overflow otherwise 0 */
6712static inline int u64_shl_div_u64(u64 a, unsigned int shift,
6713 u64 divisor, u64 *result)
6714{
6715 u64 low = a << shift, high = a >> (64 - shift);
6716
6717 /* To avoid the overflow on divq */
6718 if (high >= divisor)
6719 return 1;
6720
6721 /* Low hold the result, high hold rem which is discarded */
6722 asm("divq %2\n\t" : "=a" (low), "=d" (high) :
6723 "rm" (divisor), "0" (low), "1" (high));
6724 *result = low;
6725
6726 return 0;
6727}
6728
6729static int vmx_set_hv_timer(struct kvm_vcpu *vcpu, u64 guest_deadline_tsc)
6730{
386c6ddb 6731 struct vcpu_vmx *vmx;
c5ce8235 6732 u64 tscl, guest_tscl, delta_tsc, lapic_timer_advance_cycles;
386c6ddb
KA		 6733
6734 if (kvm_mwait_in_guest(vcpu->kvm))
6735 return -EOPNOTSUPP;
6736
6737 vmx = to_vmx(vcpu);
6738 tscl = rdtsc();
6739 guest_tscl = kvm_read_l1_tsc(vcpu, tscl);
6740 delta_tsc = max(guest_deadline_tsc, guest_tscl) - guest_tscl;
c5ce8235
WL		 6741 lapic_timer_advance_cycles = nsec_to_cycles(vcpu, lapic_timer_advance_ns);
6742
6743 if (delta_tsc > lapic_timer_advance_cycles)
6744 delta_tsc -= lapic_timer_advance_cycles;
6745 else
6746 delta_tsc = 0;
64672c95
YJ		 6747
6748 /* Convert to host delta tsc if tsc scaling is enabled */
6749 if (vcpu->arch.tsc_scaling_ratio != kvm_default_tsc_scaling_ratio &&
6750 u64_shl_div_u64(delta_tsc,
6751 kvm_tsc_scaling_ratio_frac_bits,
6752 vcpu->arch.tsc_scaling_ratio,
6753 &delta_tsc))
6754 return -ERANGE;
6755
6756 /*
6757 * If the delta tsc can't fit in the 32 bit after the multi shift,
6758 * we can't use the preemption timer.
6759 * It's possible that it fits on later vmentries, but checking
6760 * on every vmentry is costly so we just use an hrtimer.
6761 */
6762 if (delta_tsc >> (cpu_preemption_timer_multi + 32))
6763 return -ERANGE;
6764
6765 vmx->hv_deadline_tsc = tscl + delta_tsc;
c8533544 6766 return delta_tsc == 0;
64672c95
YJ		 6767}
6768
6769static void vmx_cancel_hv_timer(struct kvm_vcpu *vcpu)
6770{
f459a707 6771 to_vmx(vcpu)->hv_deadline_tsc = -1;
64672c95
YJ		 6772}
6773#endif
6774
48d89b92 6775static void vmx_sched_in(struct kvm_vcpu *vcpu, int cpu)
ae97a3b8 6776{
b31c114b 6777 if (!kvm_pause_in_guest(vcpu->kvm))
b4a2d31d 6778 shrink_ple_window(vcpu);
ae97a3b8
RK		 6779}
6780
843e4330
KH		 6781static void vmx_slot_enable_log_dirty(struct kvm *kvm,
6782 struct kvm_memory_slot *slot)
6783{
6784 kvm_mmu_slot_leaf_clear_dirty(kvm, slot);
6785 kvm_mmu_slot_largepage_remove_write_access(kvm, slot);
6786}
6787
6788static void vmx_slot_disable_log_dirty(struct kvm *kvm,
6789 struct kvm_memory_slot *slot)
6790{
6791 kvm_mmu_slot_set_dirty(kvm, slot);
6792}
6793
6794static void vmx_flush_log_dirty(struct kvm *kvm)
6795{
6796 kvm_flush_pml_buffers(kvm);
6797}
6798
c5f983f6
BD		 6799static int vmx_write_pml_buffer(struct kvm_vcpu *vcpu)
6800{
6801 struct vmcs12 *vmcs12;
6802 struct vcpu_vmx *vmx = to_vmx(vcpu);
6803 gpa_t gpa;
6804 struct page *page = NULL;
6805 u64 *pml_address;
6806
6807 if (is_guest_mode(vcpu)) {
6808 WARN_ON_ONCE(vmx->nested.pml_full);
6809
6810 /*
6811 * Check if PML is enabled for the nested guest.
6812 * Whether eptp bit 6 is set is already checked
6813 * as part of A/D emulation.
6814 */
6815 vmcs12 = get_vmcs12(vcpu);
6816 if (!nested_cpu_has_pml(vmcs12))
6817 return 0;
6818
4769886b 6819 if (vmcs12->guest_pml_index >= PML_ENTITY_NUM) {
c5f983f6
BD		 6820 vmx->nested.pml_full = true;
6821 return 1;
6822 }
6823
6824 gpa = vmcs_read64(GUEST_PHYSICAL_ADDRESS) & ~0xFFFull;
6825
5e2f30b7
DH		 6826 page = kvm_vcpu_gpa_to_page(vcpu, vmcs12->pml_address);
6827 if (is_error_page(page))
c5f983f6
BD		 6828 return 0;
6829
6830 pml_address = kmap(page);
6831 pml_address[vmcs12->guest_pml_index--] = gpa;
6832 kunmap(page);
53a70daf 6833 kvm_release_page_clean(page);
c5f983f6
BD		 6834 }
6835
6836 return 0;
6837}
6838
843e4330
KH		 6839static void vmx_enable_log_dirty_pt_masked(struct kvm *kvm,
6840 struct kvm_memory_slot *memslot,
6841 gfn_t offset, unsigned long mask)
6842{
6843 kvm_mmu_clear_dirty_pt_masked(kvm, memslot, offset, mask);
6844}
6845
cd39e117
PB		 6846static void __pi_post_block(struct kvm_vcpu *vcpu)
6847{
6848 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6849 struct pi_desc old, new;
6850 unsigned int dest;
cd39e117
PB		 6851
6852 do {
6853 old.control = new.control = pi_desc->control;
8b306e2f
PB		 6854 WARN(old.nv != POSTED_INTR_WAKEUP_VECTOR,
6855 "Wakeup handler not enabled while the VCPU is blocked\n");
cd39e117
PB		 6856
6857 dest = cpu_physical_id(vcpu->cpu);
6858
6859 if (x2apic_enabled())
6860 new.ndst = dest;
6861 else
6862 new.ndst = (dest << 8) & 0xFF00;
6863
cd39e117
PB		 6864 /* set 'NV' to 'notification vector' */
6865 new.nv = POSTED_INTR_VECTOR;
c0a1666b
PB		 6866 } while (cmpxchg64(&pi_desc->control, old.control,
6867 new.control) != old.control);
cd39e117 6868
8b306e2f
PB		 6869 if (!WARN_ON_ONCE(vcpu->pre_pcpu == -1)) {
6870 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117 6871 list_del(&vcpu->blocked_vcpu_list);
8b306e2f 6872 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
cd39e117
PB		 6873 vcpu->pre_pcpu = -1;
6874 }
6875}
6876
bf9f6ac8
FW		 6877/*
6878 * This routine does the following things for vCPU which is going
6879 * to be blocked if VT-d PI is enabled.
6880 * - Store the vCPU to the wakeup list, so when interrupts happen
6881 * we can find the right vCPU to wake up.
6882 * - Change the Posted-interrupt descriptor as below:
6883 * 'NDST' <-- vcpu->pre_pcpu
6884 * 'NV' <-- POSTED_INTR_WAKEUP_VECTOR
6885 * - If 'ON' is set during this process, which means at least one
6886 * interrupt is posted for this vCPU, we cannot block it, in
6887 * this case, return 1, otherwise, return 0.
6888 *
6889 */
bc22512b 6890static int pi_pre_block(struct kvm_vcpu *vcpu)
bf9f6ac8 6891{
bf9f6ac8
FW		 6892 unsigned int dest;
6893 struct pi_desc old, new;
6894 struct pi_desc *pi_desc = vcpu_to_pi_desc(vcpu);
6895
6896 if (!kvm_arch_has_assigned_device(vcpu->kvm) ||
a0052191
YZ		 6897 !irq_remapping_cap(IRQ_POSTING_CAP) ||
6898 !kvm_vcpu_apicv_active(vcpu))
bf9f6ac8
FW		 6899 return 0;
6900
8b306e2f
PB		 6901 WARN_ON(irqs_disabled());
6902 local_irq_disable();
6903 if (!WARN_ON_ONCE(vcpu->pre_pcpu != -1)) {
6904 vcpu->pre_pcpu = vcpu->cpu;
6905 spin_lock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
6906 list_add_tail(&vcpu->blocked_vcpu_list,
6907 &per_cpu(blocked_vcpu_on_cpu,
6908 vcpu->pre_pcpu));
6909 spin_unlock(&per_cpu(blocked_vcpu_on_cpu_lock, vcpu->pre_pcpu));
6910 }
bf9f6ac8
FW		 6911
6912 do {
6913 old.control = new.control = pi_desc->control;
6914
bf9f6ac8
FW		 6915 WARN((pi_desc->sn == 1),
6916 "Warning: SN field of posted-interrupts "
6917 "is set before blocking\n");
6918
6919 /*
6920 * Since vCPU can be preempted during this process,
6921 * vcpu->cpu could be different with pre_pcpu, we
6922 * need to set pre_pcpu as the destination of wakeup
6923 * notification event, then we can find the right vCPU
6924 * to wakeup in wakeup handler if interrupts happen
6925 * when the vCPU is in blocked state.
6926 */
6927 dest = cpu_physical_id(vcpu->pre_pcpu);
6928
6929 if (x2apic_enabled())
6930 new.ndst = dest;
6931 else
6932 new.ndst = (dest << 8) & 0xFF00;
6933
6934 /* set 'NV' to 'wakeup vector' */
6935 new.nv = POSTED_INTR_WAKEUP_VECTOR;
c0a1666b
PB		 6936 } while (cmpxchg64(&pi_desc->control, old.control,
6937 new.control) != old.control);
bf9f6ac8 6938
8b306e2f
PB		 6939 /* We should not block the vCPU if an interrupt is posted for it. */
6940 if (pi_test_on(pi_desc) == 1)
6941 __pi_post_block(vcpu);
6942
6943 local_irq_enable();
6944 return (vcpu->pre_pcpu == -1);
bf9f6ac8
FW		 6945}
6946
bc22512b
YJ		 6947static int vmx_pre_block(struct kvm_vcpu *vcpu)
6948{
6949 if (pi_pre_block(vcpu))
6950 return 1;
6951
64672c95
YJ		 6952 if (kvm_lapic_hv_timer_in_use(vcpu))
6953 kvm_lapic_switch_to_sw_timer(vcpu);
6954
bc22512b
YJ		 6955 return 0;
6956}
6957
6958static void pi_post_block(struct kvm_vcpu *vcpu)
bf9f6ac8 6959{
8b306e2f 6960 if (vcpu->pre_pcpu == -1)
bf9f6ac8
FW		 6961 return;
6962
8b306e2f
PB		 6963 WARN_ON(irqs_disabled());
6964 local_irq_disable();
cd39e117 6965 __pi_post_block(vcpu);
8b306e2f 6966 local_irq_enable();
bf9f6ac8
FW		 6967}
6968
bc22512b
YJ		 6969static void vmx_post_block(struct kvm_vcpu *vcpu)
6970{
64672c95
YJ		 6971 if (kvm_x86_ops->set_hv_timer)
6972 kvm_lapic_switch_to_hv_timer(vcpu);
6973
bc22512b
YJ		 6974 pi_post_block(vcpu);
6975}
6976
efc64404
FW		 6977/*
6978 * vmx_update_pi_irte - set IRTE for Posted-Interrupts
6979 *
6980 * @kvm: kvm
6981 * @host_irq: host irq of the interrupt
6982 * @guest_irq: gsi of the interrupt
6983 * @set: set or unset PI
6984 * returns 0 on success, < 0 on failure
6985 */
6986static int vmx_update_pi_irte(struct kvm *kvm, unsigned int host_irq,
6987 uint32_t guest_irq, bool set)
6988{
6989 struct kvm_kernel_irq_routing_entry *e;
6990 struct kvm_irq_routing_table *irq_rt;
6991 struct kvm_lapic_irq irq;
6992 struct kvm_vcpu *vcpu;
6993 struct vcpu_data vcpu_info;
3a8b0677 6994 int idx, ret = 0;
efc64404
FW		 6995
6996 if (!kvm_arch_has_assigned_device(kvm) ||
a0052191
YZ		 6997 !irq_remapping_cap(IRQ_POSTING_CAP) ||
6998 !kvm_vcpu_apicv_active(kvm->vcpus[0]))
efc64404
FW		 6999 return 0;
7000
7001 idx = srcu_read_lock(&kvm->irq_srcu);
7002 irq_rt = srcu_dereference(kvm->irq_routing, &kvm->irq_srcu);
3a8b0677
JS		 7003 if (guest_irq >= irq_rt->nr_rt_entries ||
7004 hlist_empty(&irq_rt->map[guest_irq])) {
7005 pr_warn_once("no route for guest_irq %u/%u (broken user space?)\n",
7006 guest_irq, irq_rt->nr_rt_entries);
7007 goto out;
7008 }
efc64404
FW		 7009
7010 hlist_for_each_entry(e, &irq_rt->map[guest_irq], link) {
7011 if (e->type != KVM_IRQ_ROUTING_MSI)
7012 continue;
7013 /*
7014 * VT-d PI cannot support posting multicast/broadcast
7015 * interrupts to a vCPU, we still use interrupt remapping
7016 * for these kind of interrupts.
7017 *
7018 * For lowest-priority interrupts, we only support
7019 * those with single CPU as the destination, e.g. user
7020 * configures the interrupts via /proc/irq or uses
7021 * irqbalance to make the interrupts single-CPU.
7022 *
7023 * We will support full lowest-priority interrupt later.
7024 */
7025
37131313 7026 kvm_set_msi_irq(kvm, e, &irq);
23a1c257
FW		 7027 if (!kvm_intr_is_single_vcpu(kvm, &irq, &vcpu)) {
7028 /*
7029 * Make sure the IRTE is in remapped mode if
7030 * we don't handle it in posted mode.
7031 */
7032 ret = irq_set_vcpu_affinity(host_irq, NULL);
7033 if (ret < 0) {
7034 printk(KERN_INFO
7035 "failed to back to remapped mode, irq: %u\n",
7036 host_irq);
7037 goto out;
7038 }
7039
efc64404 7040 continue;
23a1c257 7041 }
efc64404
FW		 7042
7043 vcpu_info.pi_desc_addr = __pa(vcpu_to_pi_desc(vcpu));
7044 vcpu_info.vector = irq.vector;
7045
2698d82e 7046 trace_kvm_pi_irte_update(host_irq, vcpu->vcpu_id, e->gsi,
efc64404
FW		 7047 vcpu_info.vector, vcpu_info.pi_desc_addr, set);
7048
7049 if (set)
7050 ret = irq_set_vcpu_affinity(host_irq, &vcpu_info);
dc91f2eb 7051 else
efc64404 7052 ret = irq_set_vcpu_affinity(host_irq, NULL);
efc64404
FW		 7053
7054 if (ret < 0) {
7055 printk(KERN_INFO "%s: failed to update PI IRTE\n",
7056 __func__);
7057 goto out;
7058 }
7059 }
7060
7061 ret = 0;
7062out:
7063 srcu_read_unlock(&kvm->irq_srcu, idx);
7064 return ret;
7065}
7066
c45dcc71
AR		 7067static void vmx_setup_mce(struct kvm_vcpu *vcpu)
7068{
7069 if (vcpu->arch.mcg_cap & MCG_LMCE_P)
7070 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits |=
7071 FEATURE_CONTROL_LMCE;
7072 else
7073 to_vmx(vcpu)->msr_ia32_feature_control_valid_bits &=
7074 ~FEATURE_CONTROL_LMCE;
7075}
7076
72d7b374
LP		 7077static int vmx_smi_allowed(struct kvm_vcpu *vcpu)
7078{
72e9cbdb
LP		 7079 /* we need a nested vmexit to enter SMM, postpone if run is pending */
7080 if (to_vmx(vcpu)->nested.nested_run_pending)
7081 return 0;
72d7b374
LP		 7082 return 1;
7083}
7084
0234bf88
LP		 7085static int vmx_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
7086{
72e9cbdb
LP		 7087 struct vcpu_vmx *vmx = to_vmx(vcpu);
7088
7089 vmx->nested.smm.guest_mode = is_guest_mode(vcpu);
7090 if (vmx->nested.smm.guest_mode)
7091 nested_vmx_vmexit(vcpu, -1, 0, 0);
7092
7093 vmx->nested.smm.vmxon = vmx->nested.vmxon;
7094 vmx->nested.vmxon = false;
caa057a2 7095 vmx_clear_hlt(vcpu);
0234bf88
LP		 7096 return 0;
7097}
7098
7099static int vmx_pre_leave_smm(struct kvm_vcpu *vcpu, u64 smbase)
7100{
72e9cbdb
LP		 7101 struct vcpu_vmx *vmx = to_vmx(vcpu);
7102 int ret;
7103
7104 if (vmx->nested.smm.vmxon) {
7105 vmx->nested.vmxon = true;
7106 vmx->nested.smm.vmxon = false;
7107 }
7108
7109 if (vmx->nested.smm.guest_mode) {
7110 vcpu->arch.hflags &= ~HF_SMM_MASK;
a633e41e 7111 ret = nested_vmx_enter_non_root_mode(vcpu, false);
72e9cbdb
LP		 7112 vcpu->arch.hflags |= HF_SMM_MASK;
7113 if (ret)
7114 return ret;
7115
7116 vmx->nested.smm.guest_mode = false;
7117 }
0234bf88
LP		 7118 return 0;
7119}
7120
cc3d967f
LP		 7121static int enable_smi_window(struct kvm_vcpu *vcpu)
7122{
7123 return 0;
7124}
7125
a3203381
SC		 7126static __init int hardware_setup(void)
7127{
7128 unsigned long host_bndcfgs;
7129 int r, i;
7130
7131 rdmsrl_safe(MSR_EFER, &host_efer);
7132
7133 for (i = 0; i < ARRAY_SIZE(vmx_msr_index); ++i)
7134 kvm_define_shared_msr(i, vmx_msr_index[i]);
7135
7136 if (setup_vmcs_config(&vmcs_config, &vmx_capability) < 0)
7137 return -EIO;
7138
7139 if (boot_cpu_has(X86_FEATURE_NX))
7140 kvm_enable_efer_bits(EFER_NX);
7141
7142 if (boot_cpu_has(X86_FEATURE_MPX)) {
7143 rdmsrl(MSR_IA32_BNDCFGS, host_bndcfgs);
7144 WARN_ONCE(host_bndcfgs, "KVM: BNDCFGS in host will be lost");
7145 }
7146
7147 if (boot_cpu_has(X86_FEATURE_XSAVES))
7148 rdmsrl(MSR_IA32_XSS, host_xss);
7149
7150 if (!cpu_has_vmx_vpid() || !cpu_has_vmx_invvpid() ||
7151 !(cpu_has_vmx_invvpid_single() || cpu_has_vmx_invvpid_global()))
7152 enable_vpid = 0;
7153
7154 if (!cpu_has_vmx_ept() ||
7155 !cpu_has_vmx_ept_4levels() ||
7156 !cpu_has_vmx_ept_mt_wb() ||
7157 !cpu_has_vmx_invept_global())
7158 enable_ept = 0;
7159
7160 if (!cpu_has_vmx_ept_ad_bits() || !enable_ept)
7161 enable_ept_ad_bits = 0;
7162
7163 if (!cpu_has_vmx_unrestricted_guest() || !enable_ept)
7164 enable_unrestricted_guest = 0;
7165
7166 if (!cpu_has_vmx_flexpriority())
7167 flexpriority_enabled = 0;
7168
7169 if (!cpu_has_virtual_nmis())
7170 enable_vnmi = 0;
7171
7172 /*
7173 * set_apic_access_page_addr() is used to reload apic access
7174 * page upon invalidation. No need to do anything if not
7175 * using the APIC_ACCESS_ADDR VMCS field.
7176 */
7177 if (!flexpriority_enabled)
7178 kvm_x86_ops->set_apic_access_page_addr = NULL;
7179
7180 if (!cpu_has_vmx_tpr_shadow())
7181 kvm_x86_ops->update_cr8_intercept = NULL;
7182
7183 if (enable_ept && !cpu_has_vmx_ept_2m_page())
7184 kvm_disable_largepages();
7185
7186#if IS_ENABLED(CONFIG_HYPERV)
7187 if (ms_hyperv.nested_features & HV_X64_NESTED_GUEST_MAPPING_FLUSH
7188 && enable_ept)
7189 kvm_x86_ops->tlb_remote_flush = vmx_hv_remote_flush_tlb;
7190#endif
7191
7192 if (!cpu_has_vmx_ple()) {
7193 ple_gap = 0;
7194 ple_window = 0;
7195 ple_window_grow = 0;
7196 ple_window_max = 0;
7197 ple_window_shrink = 0;
7198 }
7199
7200 if (!cpu_has_vmx_apicv()) {
7201 enable_apicv = 0;
7202 kvm_x86_ops->sync_pir_to_irr = NULL;
7203 }
7204
7205 if (cpu_has_vmx_tsc_scaling()) {
7206 kvm_has_tsc_control = true;
7207 kvm_max_tsc_scaling_ratio = KVM_VMX_TSC_MULTIPLIER_MAX;
7208 kvm_tsc_scaling_ratio_frac_bits = 48;
7209 }
7210
7211 set_bit(0, vmx_vpid_bitmap); /* 0 is reserved for host */
7212
7213 if (enable_ept)
7214 vmx_enable_tdp();
7215 else
7216 kvm_disable_tdp();
7217
a3203381
SC		 7218 /*
7219 * Only enable PML when hardware supports PML feature, and both EPT
7220 * and EPT A/D bit features are enabled -- PML depends on them to work.
7221 */
7222 if (!enable_ept || !enable_ept_ad_bits || !cpu_has_vmx_pml())
7223 enable_pml = 0;
7224
7225 if (!enable_pml) {
7226 kvm_x86_ops->slot_enable_log_dirty = NULL;
7227 kvm_x86_ops->slot_disable_log_dirty = NULL;
7228 kvm_x86_ops->flush_log_dirty = NULL;
7229 kvm_x86_ops->enable_log_dirty_pt_masked = NULL;
7230 }
7231
7232 if (!cpu_has_vmx_preemption_timer())
7233 kvm_x86_ops->request_immediate_exit = __kvm_request_immediate_exit;
7234
7235 if (cpu_has_vmx_preemption_timer() && enable_preemption_timer) {
7236 u64 vmx_msr;
7237
7238 rdmsrl(MSR_IA32_VMX_MISC, vmx_msr);
7239 cpu_preemption_timer_multi =
7240 vmx_msr & VMX_MISC_PREEMPTION_TIMER_RATE_MASK;
7241 } else {
7242 kvm_x86_ops->set_hv_timer = NULL;
7243 kvm_x86_ops->cancel_hv_timer = NULL;
7244 }
7245
a3203381 7246 kvm_set_posted_intr_wakeup_handler(wakeup_handler);
a3203381
SC		 7247
7248 kvm_mce_cap_supported |= MCG_LMCE_P;
7249
7250 if (nested) {
3e8eaccc
SC		 7251 nested_vmx_setup_ctls_msrs(&vmcs_config.nested,
7252 vmx_capability.ept, enable_apicv);
7253
e4027cfa 7254 r = nested_vmx_hardware_setup(kvm_vmx_exit_handlers);
a3203381
SC		 7255 if (r)
7256 return r;
7257 }
7258
7259 r = alloc_kvm_area();
7260 if (r)
7261 nested_vmx_hardware_unsetup();
7262 return r;
7263}
7264
7265static __exit void hardware_unsetup(void)
7266{
7267 if (nested)
7268 nested_vmx_hardware_unsetup();
7269
7270 free_kvm_area();
7271}
7272
404f6aac 7273static struct kvm_x86_ops vmx_x86_ops __ro_after_init = {
6aa8b732
AK		 7274 .cpu_has_kvm_support = cpu_has_kvm_support,
7275 .disabled_by_bios = vmx_disabled_by_bios,
7276 .hardware_setup = hardware_setup,
7277 .hardware_unsetup = hardware_unsetup,
002c7f7c 7278 .check_processor_compatibility = vmx_check_processor_compat,
6aa8b732
AK		 7279 .hardware_enable = hardware_enable,
7280 .hardware_disable = hardware_disable,
04547156 7281 .cpu_has_accelerated_tpr = report_flexpriority,
bc226f07 7282 .has_emulated_msr = vmx_has_emulated_msr,
6aa8b732 7283
b31c114b 7284 .vm_init = vmx_vm_init,
434a1e94
SC		 7285 .vm_alloc = vmx_vm_alloc,
7286 .vm_free = vmx_vm_free,
b31c114b 7287
6aa8b732
AK		 7288 .vcpu_create = vmx_create_vcpu,
7289 .vcpu_free = vmx_free_vcpu,
04d2cc77 7290 .vcpu_reset = vmx_vcpu_reset,
6aa8b732 7291
6d6095bd 7292 .prepare_guest_switch = vmx_prepare_switch_to_guest,
6aa8b732
AK		 7293 .vcpu_load = vmx_vcpu_load,
7294 .vcpu_put = vmx_vcpu_put,
7295
a96036b8 7296 .update_bp_intercept = update_exception_bitmap,
801e459a 7297 .get_msr_feature = vmx_get_msr_feature,
6aa8b732
AK		 7298 .get_msr = vmx_get_msr,
7299 .set_msr = vmx_set_msr,
7300 .get_segment_base = vmx_get_segment_base,
7301 .get_segment = vmx_get_segment,
7302 .set_segment = vmx_set_segment,
2e4d2653 7303 .get_cpl = vmx_get_cpl,
6aa8b732 7304 .get_cs_db_l_bits = vmx_get_cs_db_l_bits,
e8467fda 7305 .decache_cr0_guest_bits = vmx_decache_cr0_guest_bits,
aff48baa 7306 .decache_cr3 = vmx_decache_cr3,
25c4c276 7307 .decache_cr4_guest_bits = vmx_decache_cr4_guest_bits,
6aa8b732 7308 .set_cr0 = vmx_set_cr0,
6aa8b732
AK		 7309 .set_cr3 = vmx_set_cr3,
7310 .set_cr4 = vmx_set_cr4,
6aa8b732 7311 .set_efer = vmx_set_efer,
6aa8b732
AK		 7312 .get_idt = vmx_get_idt,
7313 .set_idt = vmx_set_idt,
7314 .get_gdt = vmx_get_gdt,
7315 .set_gdt = vmx_set_gdt,
73aaf249
JK		 7316 .get_dr6 = vmx_get_dr6,
7317 .set_dr6 = vmx_set_dr6,
020df079 7318 .set_dr7 = vmx_set_dr7,
81908bf4 7319 .sync_dirty_debug_regs = vmx_sync_dirty_debug_regs,
5fdbf976 7320 .cache_reg = vmx_cache_reg,
6aa8b732
AK		 7321 .get_rflags = vmx_get_rflags,
7322 .set_rflags = vmx_set_rflags,
be94f6b7 7323
6aa8b732 7324 .tlb_flush = vmx_flush_tlb,
faff8758 7325 .tlb_flush_gva = vmx_flush_tlb_gva,
6aa8b732 7326
6aa8b732 7327 .run = vmx_vcpu_run,
6062d012 7328 .handle_exit = vmx_handle_exit,
6aa8b732 7329 .skip_emulated_instruction = skip_emulated_instruction,
2809f5d2
GC		 7330 .set_interrupt_shadow = vmx_set_interrupt_shadow,
7331 .get_interrupt_shadow = vmx_get_interrupt_shadow,
102d8325 7332 .patch_hypercall = vmx_patch_hypercall,
2a8067f1 7333 .set_irq = vmx_inject_irq,
95ba8273 7334 .set_nmi = vmx_inject_nmi,
298101da 7335 .queue_exception = vmx_queue_exception,
b463a6f7 7336 .cancel_injection = vmx_cancel_injection,
78646121 7337 .interrupt_allowed = vmx_interrupt_allowed,
95ba8273 7338 .nmi_allowed = vmx_nmi_allowed,
3cfc3092
JK		 7339 .get_nmi_mask = vmx_get_nmi_mask,
7340 .set_nmi_mask = vmx_set_nmi_mask,
95ba8273
GN		 7341 .enable_nmi_window = enable_nmi_window,
7342 .enable_irq_window = enable_irq_window,
7343 .update_cr8_intercept = update_cr8_intercept,
8d860bbe 7344 .set_virtual_apic_mode = vmx_set_virtual_apic_mode,
38b99173 7345 .set_apic_access_page_addr = vmx_set_apic_access_page_addr,
d62caabb
AS		 7346 .get_enable_apicv = vmx_get_enable_apicv,
7347 .refresh_apicv_exec_ctrl = vmx_refresh_apicv_exec_ctrl,
c7c9c56c 7348 .load_eoi_exitmap = vmx_load_eoi_exitmap,
967235d3 7349 .apicv_post_state_restore = vmx_apicv_post_state_restore,
c7c9c56c
YZ		 7350 .hwapic_irr_update = vmx_hwapic_irr_update,
7351 .hwapic_isr_update = vmx_hwapic_isr_update,
e6c67d8c 7352 .guest_apic_has_interrupt = vmx_guest_apic_has_interrupt,
a20ed54d
YZ		 7353 .sync_pir_to_irr = vmx_sync_pir_to_irr,
7354 .deliver_posted_interrupt = vmx_deliver_posted_interrupt,
95ba8273 7355
cbc94022 7356 .set_tss_addr = vmx_set_tss_addr,
2ac52ab8 7357 .set_identity_map_addr = vmx_set_identity_map_addr,
67253af5 7358 .get_tdp_level = get_ept_level,
4b12f0de 7359 .get_mt_mask = vmx_get_mt_mask,
229456fc 7360
586f9607 7361 .get_exit_info = vmx_get_exit_info,
586f9607 7362
17cc3935 7363 .get_lpage_level = vmx_get_lpage_level,
0e851880
SY		 7364
7365 .cpuid_update = vmx_cpuid_update,
4e47c7a6
SY		 7366
7367 .rdtscp_supported = vmx_rdtscp_supported,
ad756a16 7368 .invpcid_supported = vmx_invpcid_supported,
d4330ef2
JR		 7369
7370 .set_supported_cpuid = vmx_set_supported_cpuid,
f5f48ee1
SY		 7371
7372 .has_wbinvd_exit = cpu_has_vmx_wbinvd_exit,
99e3e30a 7373
e79f245d 7374 .read_l1_tsc_offset = vmx_read_l1_tsc_offset,
326e7425 7375 .write_l1_tsc_offset = vmx_write_l1_tsc_offset,
1c97f0a0
JR		 7376
7377 .set_tdp_cr3 = vmx_set_cr3,
8a76d7f2
JR		 7378
7379 .check_intercept = vmx_check_intercept,
a547c6db 7380 .handle_external_intr = vmx_handle_external_intr,
da8999d3 7381 .mpx_supported = vmx_mpx_supported,
55412b2e 7382 .xsaves_supported = vmx_xsaves_supported,
66336cab 7383 .umip_emulated = vmx_umip_emulated,
b6b8a145 7384
d264ee0c 7385 .request_immediate_exit = vmx_request_immediate_exit,
ae97a3b8
RK		 7386
7387 .sched_in = vmx_sched_in,
843e4330
KH		 7388
7389 .slot_enable_log_dirty = vmx_slot_enable_log_dirty,
7390 .slot_disable_log_dirty = vmx_slot_disable_log_dirty,
7391 .flush_log_dirty = vmx_flush_log_dirty,
7392 .enable_log_dirty_pt_masked = vmx_enable_log_dirty_pt_masked,
c5f983f6 7393 .write_log_dirty = vmx_write_pml_buffer,
25462f7f 7394
bf9f6ac8
FW		 7395 .pre_block = vmx_pre_block,
7396 .post_block = vmx_post_block,
7397
25462f7f 7398 .pmu_ops = &intel_pmu_ops,
efc64404
FW		 7399
7400 .update_pi_irte = vmx_update_pi_irte,
64672c95
YJ		 7401
7402#ifdef CONFIG_X86_64
7403 .set_hv_timer = vmx_set_hv_timer,
7404 .cancel_hv_timer = vmx_cancel_hv_timer,
7405#endif
c45dcc71
AR		 7406
7407 .setup_mce = vmx_setup_mce,
0234bf88 7408
72d7b374 7409 .smi_allowed = vmx_smi_allowed,
0234bf88
LP		 7410 .pre_enter_smm = vmx_pre_enter_smm,
7411 .pre_leave_smm = vmx_pre_leave_smm,
cc3d967f 7412 .enable_smi_window = enable_smi_window,
57b119da 7413
e4027cfa
SC		 7414 .check_nested_events = NULL,
7415 .get_nested_state = NULL,
7416 .set_nested_state = NULL,
7417 .get_vmcs12_pages = NULL,
7418 .nested_enable_evmcs = NULL,
6aa8b732
AK		 7419};
7420
72c6d2db 7421static void vmx_cleanup_l1d_flush(void)
a47dd5f0
PB		 7422{
7423 if (vmx_l1d_flush_pages) {
7424 free_pages((unsigned long)vmx_l1d_flush_pages, L1D_CACHE_ORDER);
7425 vmx_l1d_flush_pages = NULL;
7426 }
72c6d2db
TG		 7427 /* Restore state so sysfs ignores VMX */
7428 l1tf_vmx_mitigation = VMENTER_L1D_FLUSH_AUTO;
a399477e
KRW		 7429}
7430
a7b9020b
TG		 7431static void vmx_exit(void)
7432{
7433#ifdef CONFIG_KEXEC_CORE
7434 RCU_INIT_POINTER(crash_vmclear_loaded_vmcss, NULL);
7435 synchronize_rcu();
7436#endif
7437
7438 kvm_exit();
7439
7440#if IS_ENABLED(CONFIG_HYPERV)
7441 if (static_branch_unlikely(&enable_evmcs)) {
7442 int cpu;
7443 struct hv_vp_assist_page *vp_ap;
7444 /*
7445 * Reset everything to support using non-enlightened VMCS
7446 * access later (e.g. when we reload the module with
7447 * enlightened_vmcs=0)
7448 */
7449 for_each_online_cpu(cpu) {
7450 vp_ap = hv_get_vp_assist_page(cpu);
7451
7452 if (!vp_ap)
7453 continue;
7454
7455 vp_ap->current_nested_vmcs = 0;
7456 vp_ap->enlighten_vmentry = 0;
7457 }
7458
7459 static_branch_disable(&enable_evmcs);
7460 }
7461#endif
7462 vmx_cleanup_l1d_flush();
7463}
7464module_exit(vmx_exit);
7465
6aa8b732
AK		 7466static int __init vmx_init(void)
7467{
773e8a04
VK		 7468 int r;
7469
7470#if IS_ENABLED(CONFIG_HYPERV)
7471 /*
7472 * Enlightened VMCS usage should be recommended and the host needs
7473 * to support eVMCS v1 or above. We can also disable eVMCS support
7474 * with module parameter.
7475 */
7476 if (enlightened_vmcs &&
7477 ms_hyperv.hints & HV_X64_ENLIGHTENED_VMCS_RECOMMENDED &&
7478 (ms_hyperv.nested_features & HV_X64_ENLIGHTENED_VMCS_VERSION) >=
7479 KVM_EVMCS_VERSION) {
7480 int cpu;
7481
7482 /* Check that we have assist pages on all online CPUs */
7483 for_each_online_cpu(cpu) {
7484 if (!hv_get_vp_assist_page(cpu)) {
7485 enlightened_vmcs = false;
7486 break;
7487 }
7488 }
7489
7490 if (enlightened_vmcs) {
7491 pr_info("KVM: vmx: using Hyper-V Enlightened VMCS\n");
7492 static_branch_enable(&enable_evmcs);
7493 }
7494 } else {
7495 enlightened_vmcs = false;
7496 }
7497#endif
7498
7499 r = kvm_init(&vmx_x86_ops, sizeof(struct vcpu_vmx),
a7b9020b 7500 __alignof__(struct vcpu_vmx), THIS_MODULE);
fdef3ad1 7501 if (r)
34a1cd60 7502 return r;
25c5f225 7503
a7b9020b 7504 /*
7db92e16
TG		 7505 * Must be called after kvm_init() so enable_ept is properly set
7506 * up. Hand the parameter mitigation value in which was stored in
7507 * the pre module init parser. If no parameter was given, it will
7508 * contain 'auto' which will be turned into the default 'cond'
7509 * mitigation mode.
7510 */
7511 if (boot_cpu_has(X86_BUG_L1TF)) {
7512 r = vmx_setup_l1d_flush(vmentry_l1d_flush_param);
7513 if (r) {
7514 vmx_exit();
7515 return r;
7516 }
a47dd5f0 7517 }
25c5f225 7518
2965faa5 7519#ifdef CONFIG_KEXEC_CORE
8f536b76
ZY		 7520 rcu_assign_pointer(crash_vmclear_loaded_vmcss,
7521 crash_vmclear_local_loaded_vmcss);
7522#endif
21ebf53b 7523 vmx_check_vmcs12_offsets();
8f536b76 7524
fdef3ad1 7525 return 0;
6aa8b732 7526}
a7b9020b 7527module_init(vmx_init);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git