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KVM: VMX: conditionally disable 2M pages
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
043405e1
CO		 40
41#include <asm/uaccess.h>
d825ed0a 42#include <asm/msr.h>
a5f61300 43#include <asm/desc.h>
0bed3b56 44#include <asm/mtrr.h>
890ca9ae 45#include <asm/mce.h>
043405e1 46
313a3dc7 47#define MAX_IO_MSRS 256
a03490ed
CO		 48#define CR0_RESERVED_BITS \
49 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
50 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
51 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
52#define CR4_RESERVED_BITS \
53 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
54 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
55 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
56 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
57
58#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 59
60#define KVM_MAX_MCE_BANKS 32
61#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
62
50a37eb4
JR		 63/* EFER defaults:
64 * - enable syscall per default because its emulated by KVM
65 * - enable LME and LMA per default on 64 bit KVM
66 */
67#ifdef CONFIG_X86_64
68static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
69#else
70static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
71#endif
313a3dc7 72
ba1389b7
AK		 73#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
74#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 75
674eea0f
AK		 76static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
77 struct kvm_cpuid_entry2 __user *entries);
d8017474
AG		 78struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
79 u32 function, u32 index);
674eea0f 80
97896d04 81struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 82EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 83
417bc304 84struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 85 { "pf_fixed", VCPU_STAT(pf_fixed) },
86 { "pf_guest", VCPU_STAT(pf_guest) },
87 { "tlb_flush", VCPU_STAT(tlb_flush) },
88 { "invlpg", VCPU_STAT(invlpg) },
89 { "exits", VCPU_STAT(exits) },
90 { "io_exits", VCPU_STAT(io_exits) },
91 { "mmio_exits", VCPU_STAT(mmio_exits) },
92 { "signal_exits", VCPU_STAT(signal_exits) },
93 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 94 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 95 { "halt_exits", VCPU_STAT(halt_exits) },
96 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 97 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 98 { "request_irq", VCPU_STAT(request_irq_exits) },
99 { "irq_exits", VCPU_STAT(irq_exits) },
100 { "host_state_reload", VCPU_STAT(host_state_reload) },
101 { "efer_reload", VCPU_STAT(efer_reload) },
102 { "fpu_reload", VCPU_STAT(fpu_reload) },
103 { "insn_emulation", VCPU_STAT(insn_emulation) },
104 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 105 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 106 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 107 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
108 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
109 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
110 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
111 { "mmu_flooded", VM_STAT(mmu_flooded) },
112 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 113 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 114 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 115 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 116 { "largepages", VM_STAT(lpages) },
417bc304
HB		 117 { NULL }
118};
119
5fb76f9b
CO		 120unsigned long segment_base(u16 selector)
121{
122 struct descriptor_table gdt;
a5f61300 123 struct desc_struct *d;
5fb76f9b
CO		 124 unsigned long table_base;
125 unsigned long v;
126
127 if (selector == 0)
128 return 0;
129
130 asm("sgdt %0" : "=m"(gdt));
131 table_base = gdt.base;
132
133 if (selector & 4) { /* from ldt */
134 u16 ldt_selector;
135
136 asm("sldt %0" : "=g"(ldt_selector));
137 table_base = segment_base(ldt_selector);
138 }
a5f61300
AK		 139 d = (struct desc_struct *)(table_base + (selector & ~7));
140 v = d->base0 | ((unsigned long)d->base1 << 16) |
141 ((unsigned long)d->base2 << 24);
5fb76f9b 142#ifdef CONFIG_X86_64
a5f61300
AK		 143 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
144 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 145#endif
146 return v;
147}
148EXPORT_SYMBOL_GPL(segment_base);
149
6866b83e
CO		 150u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
151{
152 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 153 return vcpu->arch.apic_base;
6866b83e 154 else
ad312c7c 155 return vcpu->arch.apic_base;
6866b83e
CO		 156}
157EXPORT_SYMBOL_GPL(kvm_get_apic_base);
158
159void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
160{
161 /* TODO: reserve bits check */
162 if (irqchip_in_kernel(vcpu->kvm))
163 kvm_lapic_set_base(vcpu, data);
164 else
ad312c7c 165 vcpu->arch.apic_base = data;
6866b83e
CO		 166}
167EXPORT_SYMBOL_GPL(kvm_set_apic_base);
168
298101da
AK		 169void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
170{
ad312c7c
ZX		 171 WARN_ON(vcpu->arch.exception.pending);
172 vcpu->arch.exception.pending = true;
173 vcpu->arch.exception.has_error_code = false;
174 vcpu->arch.exception.nr = nr;
298101da
AK		 175}
176EXPORT_SYMBOL_GPL(kvm_queue_exception);
177
c3c91fee
AK		 178void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
179 u32 error_code)
180{
181 ++vcpu->stat.pf_guest;
d8017474 182
71c4dfaf
JR		 183 if (vcpu->arch.exception.pending) {
184 if (vcpu->arch.exception.nr == PF_VECTOR) {
185 printk(KERN_DEBUG "kvm: inject_page_fault:"
186 " double fault 0x%lx\n", addr);
187 vcpu->arch.exception.nr = DF_VECTOR;
188 vcpu->arch.exception.error_code = 0;
189 } else if (vcpu->arch.exception.nr == DF_VECTOR) {
190 /* triple fault -> shutdown */
191 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
192 }
c3c91fee
AK		 193 return;
194 }
ad312c7c 195 vcpu->arch.cr2 = addr;
c3c91fee
AK		 196 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
197}
198
3419ffc8
SY		 199void kvm_inject_nmi(struct kvm_vcpu *vcpu)
200{
201 vcpu->arch.nmi_pending = 1;
202}
203EXPORT_SYMBOL_GPL(kvm_inject_nmi);
204
298101da
AK		 205void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
206{
ad312c7c
ZX		 207 WARN_ON(vcpu->arch.exception.pending);
208 vcpu->arch.exception.pending = true;
209 vcpu->arch.exception.has_error_code = true;
210 vcpu->arch.exception.nr = nr;
211 vcpu->arch.exception.error_code = error_code;
298101da
AK		 212}
213EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
214
215static void __queue_exception(struct kvm_vcpu *vcpu)
216{
ad312c7c
ZX		 217 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
218 vcpu->arch.exception.has_error_code,
219 vcpu->arch.exception.error_code);
298101da
AK		 220}
221
a03490ed
CO		 222/*
223 * Load the pae pdptrs. Return true is they are all valid.
224 */
225int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
226{
227 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
228 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
229 int i;
230 int ret;
ad312c7c 231 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 232
a03490ed
CO		 233 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
234 offset * sizeof(u64), sizeof(pdpte));
235 if (ret < 0) {
236 ret = 0;
237 goto out;
238 }
239 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 240 if (is_present_gpte(pdpte[i]) &&
20c466b5 241 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 242 ret = 0;
243 goto out;
244 }
245 }
246 ret = 1;
247
ad312c7c 248 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 249 __set_bit(VCPU_EXREG_PDPTR,
250 (unsigned long *)&vcpu->arch.regs_avail);
251 __set_bit(VCPU_EXREG_PDPTR,
252 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 253out:
a03490ed
CO		 254
255 return ret;
256}
cc4b6871 257EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 258
d835dfec
AK		 259static bool pdptrs_changed(struct kvm_vcpu *vcpu)
260{
ad312c7c 261 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 262 bool changed = true;
263 int r;
264
265 if (is_long_mode(vcpu) || !is_pae(vcpu))
266 return false;
267
6de4f3ad
AK		 268 if (!test_bit(VCPU_EXREG_PDPTR,
269 (unsigned long *)&vcpu->arch.regs_avail))
270 return true;
271
ad312c7c 272 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 273 if (r < 0)
274 goto out;
ad312c7c 275 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 276out:
d835dfec
AK		 277
278 return changed;
279}
280
2d3ad1f4 281void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 282{
283 if (cr0 & CR0_RESERVED_BITS) {
284 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 285 cr0, vcpu->arch.cr0);
c1a5d4f9 286 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 287 return;
288 }
289
290 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
291 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 292 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 293 return;
294 }
295
296 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
297 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
298 "and a clear PE flag\n");
c1a5d4f9 299 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 300 return;
301 }
302
303 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
304#ifdef CONFIG_X86_64
ad312c7c 305 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 306 int cs_db, cs_l;
307
308 if (!is_pae(vcpu)) {
309 printk(KERN_DEBUG "set_cr0: #GP, start paging "
310 "in long mode while PAE is disabled\n");
c1a5d4f9 311 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 312 return;
313 }
314 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
315 if (cs_l) {
316 printk(KERN_DEBUG "set_cr0: #GP, start paging "
317 "in long mode while CS.L == 1\n");
c1a5d4f9 318 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 319 return;
320
321 }
322 } else
323#endif
ad312c7c 324 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 325 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
326 "reserved bits\n");
c1a5d4f9 327 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 328 return;
329 }
330
331 }
332
333 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 334 vcpu->arch.cr0 = cr0;
a03490ed 335
a03490ed 336 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 337 return;
338}
2d3ad1f4 339EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 340
2d3ad1f4 341void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 342{
2d3ad1f4 343 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
2714d1d3
FEL		 344 KVMTRACE_1D(LMSW, vcpu,
345 (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
346 handler);
a03490ed 347}
2d3ad1f4 348EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 349
2d3ad1f4 350void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 351{
a2edf57f
AK		 352 unsigned long old_cr4 = vcpu->arch.cr4;
353 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
354
a03490ed
CO		 355 if (cr4 & CR4_RESERVED_BITS) {
356 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 357 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 358 return;
359 }
360
361 if (is_long_mode(vcpu)) {
362 if (!(cr4 & X86_CR4_PAE)) {
363 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
364 "in long mode\n");
c1a5d4f9 365 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 366 return;
367 }
a2edf57f
AK		 368 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
369 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 370 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 371 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 372 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 373 return;
374 }
375
376 if (cr4 & X86_CR4_VMXE) {
377 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 378 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 379 return;
380 }
381 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 382 vcpu->arch.cr4 = cr4;
5a41accd 383 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 384 kvm_mmu_reset_context(vcpu);
a03490ed 385}
2d3ad1f4 386EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 387
2d3ad1f4 388void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 389{
ad312c7c 390 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 391 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 392 kvm_mmu_flush_tlb(vcpu);
393 return;
394 }
395
a03490ed
CO		 396 if (is_long_mode(vcpu)) {
397 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
398 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 399 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 400 return;
401 }
402 } else {
403 if (is_pae(vcpu)) {
404 if (cr3 & CR3_PAE_RESERVED_BITS) {
405 printk(KERN_DEBUG
406 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 407 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 408 return;
409 }
410 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
411 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
412 "reserved bits\n");
c1a5d4f9 413 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 414 return;
415 }
416 }
417 /*
418 * We don't check reserved bits in nonpae mode, because
419 * this isn't enforced, and VMware depends on this.
420 */
421 }
422
a03490ed
CO		 423 /*
424 * Does the new cr3 value map to physical memory? (Note, we
425 * catch an invalid cr3 even in real-mode, because it would
426 * cause trouble later on when we turn on paging anyway.)
427 *
428 * A real CPU would silently accept an invalid cr3 and would
429 * attempt to use it - with largely undefined (and often hard
430 * to debug) behavior on the guest side.
431 */
432 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 433 kvm_inject_gp(vcpu, 0);
a03490ed 434 else {
ad312c7c
ZX		 435 vcpu->arch.cr3 = cr3;
436 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 437 }
a03490ed 438}
2d3ad1f4 439EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 440
2d3ad1f4 441void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 442{
443 if (cr8 & CR8_RESERVED_BITS) {
444 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 445 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 446 return;
447 }
448 if (irqchip_in_kernel(vcpu->kvm))
449 kvm_lapic_set_tpr(vcpu, cr8);
450 else
ad312c7c 451 vcpu->arch.cr8 = cr8;
a03490ed 452}
2d3ad1f4 453EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 454
2d3ad1f4 455unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 456{
457 if (irqchip_in_kernel(vcpu->kvm))
458 return kvm_lapic_get_cr8(vcpu);
459 else
ad312c7c 460 return vcpu->arch.cr8;
a03490ed 461}
2d3ad1f4 462EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 463
d8017474
AG		 464static inline u32 bit(int bitno)
465{
466 return 1 << (bitno & 31);
467}
468
043405e1
CO		 469/*
470 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
471 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
472 *
473 * This list is modified at module load time to reflect the
474 * capabilities of the host cpu.
475 */
476static u32 msrs_to_save[] = {
477 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
478 MSR_K6_STAR,
479#ifdef CONFIG_X86_64
480 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
481#endif
af24a4e4 482 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 483 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 484};
485
486static unsigned num_msrs_to_save;
487
488static u32 emulated_msrs[] = {
489 MSR_IA32_MISC_ENABLE,
490};
491
15c4a640
CO		 492static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
493{
f2b4b7dd 494 if (efer & efer_reserved_bits) {
15c4a640
CO		 495 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
496 efer);
c1a5d4f9 497 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 498 return;
499 }
500
501 if (is_paging(vcpu)
ad312c7c 502 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 503 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 504 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 505 return;
506 }
507
1b2fd70c
AG		 508 if (efer & EFER_FFXSR) {
509 struct kvm_cpuid_entry2 *feat;
510
511 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
512 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
513 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
514 kvm_inject_gp(vcpu, 0);
515 return;
516 }
517 }
518
d8017474
AG		 519 if (efer & EFER_SVME) {
520 struct kvm_cpuid_entry2 *feat;
521
522 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
523 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
524 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
525 kvm_inject_gp(vcpu, 0);
526 return;
527 }
528 }
529
15c4a640
CO		 530 kvm_x86_ops->set_efer(vcpu, efer);
531
532 efer &= ~EFER_LMA;
ad312c7c 533 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 534
ad312c7c 535 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 536
537 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
538 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 539}
540
f2b4b7dd
JR		 541void kvm_enable_efer_bits(u64 mask)
542{
543 efer_reserved_bits &= ~mask;
544}
545EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
546
547
15c4a640
CO		 548/*
549 * Writes msr value into into the appropriate "register".
550 * Returns 0 on success, non-0 otherwise.
551 * Assumes vcpu_load() was already called.
552 */
553int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
554{
555 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
556}
557
313a3dc7
CO		 558/*
559 * Adapt set_msr() to msr_io()'s calling convention
560 */
561static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
562{
563 return kvm_set_msr(vcpu, index, *data);
564}
565
18068523
GOC		 566static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
567{
568 static int version;
50d0a0f9
GH		 569 struct pvclock_wall_clock wc;
570 struct timespec now, sys, boot;
18068523
GOC		 571
572 if (!wall_clock)
573 return;
574
575 version++;
576
18068523
GOC		 577 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
578
50d0a0f9
GH		 579 /*
580 * The guest calculates current wall clock time by adding
581 * system time (updated by kvm_write_guest_time below) to the
582 * wall clock specified here. guest system time equals host
583 * system time for us, thus we must fill in host boot time here.
584 */
585 now = current_kernel_time();
586 ktime_get_ts(&sys);
587 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
588
589 wc.sec = boot.tv_sec;
590 wc.nsec = boot.tv_nsec;
591 wc.version = version;
18068523
GOC		 592
593 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
594
595 version++;
596 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 597}
598
50d0a0f9
GH		 599static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
600{
601 uint32_t quotient, remainder;
602
603 /* Don't try to replace with do_div(), this one calculates
604 * "(dividend << 32) / divisor" */
605 __asm__ ( "divl %4"
606 : "=a" (quotient), "=d" (remainder)
607 : "0" (0), "1" (dividend), "r" (divisor) );
608 return quotient;
609}
610
611static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
612{
613 uint64_t nsecs = 1000000000LL;
614 int32_t shift = 0;
615 uint64_t tps64;
616 uint32_t tps32;
617
618 tps64 = tsc_khz * 1000LL;
619 while (tps64 > nsecs*2) {
620 tps64 >>= 1;
621 shift--;
622 }
623
624 tps32 = (uint32_t)tps64;
625 while (tps32 <= (uint32_t)nsecs) {
626 tps32 <<= 1;
627 shift++;
628 }
629
630 hv_clock->tsc_shift = shift;
631 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
632
633 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 634 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 635 hv_clock->tsc_to_system_mul);
636}
637
c8076604
GH		 638static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
639
18068523
GOC		 640static void kvm_write_guest_time(struct kvm_vcpu *v)
641{
642 struct timespec ts;
643 unsigned long flags;
644 struct kvm_vcpu_arch *vcpu = &v->arch;
645 void *shared_kaddr;
463656c0 646 unsigned long this_tsc_khz;
18068523
GOC		 647
648 if ((!vcpu->time_page))
649 return;
650
463656c0
AK		 651 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
652 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
653 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
654 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 655 }
463656c0 656 put_cpu_var(cpu_tsc_khz);
50d0a0f9 657
18068523
GOC		 658 /* Keep irq disabled to prevent changes to the clock */
659 local_irq_save(flags);
af24a4e4 660 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 661 ktime_get_ts(&ts);
662 local_irq_restore(flags);
663
664 /* With all the info we got, fill in the values */
665
666 vcpu->hv_clock.system_time = ts.tv_nsec +
667 (NSEC_PER_SEC * (u64)ts.tv_sec);
668 /*
669 * The interface expects us to write an even number signaling that the
670 * update is finished. Since the guest won't see the intermediate
50d0a0f9 671 * state, we just increase by 2 at the end.
18068523 672 */
50d0a0f9 673 vcpu->hv_clock.version += 2;
18068523
GOC		 674
675 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
676
677 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 678 sizeof(vcpu->hv_clock));
18068523
GOC		 679
680 kunmap_atomic(shared_kaddr, KM_USER0);
681
682 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
683}
684
c8076604
GH		 685static int kvm_request_guest_time_update(struct kvm_vcpu *v)
686{
687 struct kvm_vcpu_arch *vcpu = &v->arch;
688
689 if (!vcpu->time_page)
690 return 0;
691 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
692 return 1;
693}
694
9ba075a6
AK		 695static bool msr_mtrr_valid(unsigned msr)
696{
697 switch (msr) {
698 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
699 case MSR_MTRRfix64K_00000:
700 case MSR_MTRRfix16K_80000:
701 case MSR_MTRRfix16K_A0000:
702 case MSR_MTRRfix4K_C0000:
703 case MSR_MTRRfix4K_C8000:
704 case MSR_MTRRfix4K_D0000:
705 case MSR_MTRRfix4K_D8000:
706 case MSR_MTRRfix4K_E0000:
707 case MSR_MTRRfix4K_E8000:
708 case MSR_MTRRfix4K_F0000:
709 case MSR_MTRRfix4K_F8000:
710 case MSR_MTRRdefType:
711 case MSR_IA32_CR_PAT:
712 return true;
713 case 0x2f8:
714 return true;
715 }
716 return false;
717}
718
d6289b93
MT		 719static bool valid_pat_type(unsigned t)
720{
721 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
722}
723
724static bool valid_mtrr_type(unsigned t)
725{
726 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
727}
728
729static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
730{
731 int i;
732
733 if (!msr_mtrr_valid(msr))
734 return false;
735
736 if (msr == MSR_IA32_CR_PAT) {
737 for (i = 0; i < 8; i++)
738 if (!valid_pat_type((data >> (i * 8)) & 0xff))
739 return false;
740 return true;
741 } else if (msr == MSR_MTRRdefType) {
742 if (data & ~0xcff)
743 return false;
744 return valid_mtrr_type(data & 0xff);
745 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
746 for (i = 0; i < 8 ; i++)
747 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
748 return false;
749 return true;
750 }
751
752 /* variable MTRRs */
753 return valid_mtrr_type(data & 0xff);
754}
755
9ba075a6
AK		 756static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
757{
0bed3b56
SY		 758 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
759
d6289b93 760 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 761 return 1;
762
0bed3b56
SY		 763 if (msr == MSR_MTRRdefType) {
764 vcpu->arch.mtrr_state.def_type = data;
765 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
766 } else if (msr == MSR_MTRRfix64K_00000)
767 p[0] = data;
768 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
769 p[1 + msr - MSR_MTRRfix16K_80000] = data;
770 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
771 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
772 else if (msr == MSR_IA32_CR_PAT)
773 vcpu->arch.pat = data;
774 else { /* Variable MTRRs */
775 int idx, is_mtrr_mask;
776 u64 *pt;
777
778 idx = (msr - 0x200) / 2;
779 is_mtrr_mask = msr - 0x200 - 2 * idx;
780 if (!is_mtrr_mask)
781 pt =
782 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
783 else
784 pt =
785 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
786 *pt = data;
787 }
788
789 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 790 return 0;
791}
15c4a640 792
890ca9ae 793static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 794{
890ca9ae
HY		 795 u64 mcg_cap = vcpu->arch.mcg_cap;
796 unsigned bank_num = mcg_cap & 0xff;
797
15c4a640 798 switch (msr) {
15c4a640 799 case MSR_IA32_MCG_STATUS:
890ca9ae 800 vcpu->arch.mcg_status = data;
15c4a640 801 break;
c7ac679c 802 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 803 if (!(mcg_cap & MCG_CTL_P))
804 return 1;
805 if (data != 0 && data != ~(u64)0)
806 return -1;
807 vcpu->arch.mcg_ctl = data;
808 break;
809 default:
810 if (msr >= MSR_IA32_MC0_CTL &&
811 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
812 u32 offset = msr - MSR_IA32_MC0_CTL;
813 /* only 0 or all 1s can be written to IA32_MCi_CTL */
814 if ((offset & 0x3) == 0 &&
815 data != 0 && data != ~(u64)0)
816 return -1;
817 vcpu->arch.mce_banks[offset] = data;
818 break;
819 }
820 return 1;
821 }
822 return 0;
823}
824
825int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
826{
827 switch (msr) {
828 case MSR_EFER:
829 set_efer(vcpu, data);
c7ac679c 830 break;
b5e2fec0
AG		 831 case MSR_IA32_DEBUGCTLMSR:
832 if (!data) {
833 /* We support the non-activated case already */
834 break;
835 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
836 /* Values other than LBR and BTF are vendor-specific,
837 thus reserved and should throw a #GP */
838 return 1;
839 }
840 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
841 __func__, data);
842 break;
15c4a640
CO		 843 case MSR_IA32_UCODE_REV:
844 case MSR_IA32_UCODE_WRITE:
61a6bd67 845 case MSR_VM_HSAVE_PA:
15c4a640 846 break;
9ba075a6
AK		 847 case 0x200 ... 0x2ff:
848 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 849 case MSR_IA32_APICBASE:
850 kvm_set_apic_base(vcpu, data);
851 break;
852 case MSR_IA32_MISC_ENABLE:
ad312c7c 853 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 854 break;
18068523
GOC		 855 case MSR_KVM_WALL_CLOCK:
856 vcpu->kvm->arch.wall_clock = data;
857 kvm_write_wall_clock(vcpu->kvm, data);
858 break;
859 case MSR_KVM_SYSTEM_TIME: {
860 if (vcpu->arch.time_page) {
861 kvm_release_page_dirty(vcpu->arch.time_page);
862 vcpu->arch.time_page = NULL;
863 }
864
865 vcpu->arch.time = data;
866
867 /* we verify if the enable bit is set... */
868 if (!(data & 1))
869 break;
870
871 /* ...but clean it before doing the actual write */
872 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
873
18068523
GOC		 874 vcpu->arch.time_page =
875 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 876
877 if (is_error_page(vcpu->arch.time_page)) {
878 kvm_release_page_clean(vcpu->arch.time_page);
879 vcpu->arch.time_page = NULL;
880 }
881
c8076604 882 kvm_request_guest_time_update(vcpu);
18068523
GOC		 883 break;
884 }
890ca9ae
HY		 885 case MSR_IA32_MCG_CTL:
886 case MSR_IA32_MCG_STATUS:
887 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
888 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 889
890 /* Performance counters are not protected by a CPUID bit,
891 * so we should check all of them in the generic path for the sake of
892 * cross vendor migration.
893 * Writing a zero into the event select MSRs disables them,
894 * which we perfectly emulate ;-). Any other value should be at least
895 * reported, some guests depend on them.
896 */
897 case MSR_P6_EVNTSEL0:
898 case MSR_P6_EVNTSEL1:
899 case MSR_K7_EVNTSEL0:
900 case MSR_K7_EVNTSEL1:
901 case MSR_K7_EVNTSEL2:
902 case MSR_K7_EVNTSEL3:
903 if (data != 0)
904 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
905 "0x%x data 0x%llx\n", msr, data);
906 break;
907 /* at least RHEL 4 unconditionally writes to the perfctr registers,
908 * so we ignore writes to make it happy.
909 */
910 case MSR_P6_PERFCTR0:
911 case MSR_P6_PERFCTR1:
912 case MSR_K7_PERFCTR0:
913 case MSR_K7_PERFCTR1:
914 case MSR_K7_PERFCTR2:
915 case MSR_K7_PERFCTR3:
916 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
917 "0x%x data 0x%llx\n", msr, data);
918 break;
15c4a640 919 default:
565f1fbd 920 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
15c4a640
CO		 921 return 1;
922 }
923 return 0;
924}
925EXPORT_SYMBOL_GPL(kvm_set_msr_common);
926
927
928/*
929 * Reads an msr value (of 'msr_index') into 'pdata'.
930 * Returns 0 on success, non-0 otherwise.
931 * Assumes vcpu_load() was already called.
932 */
933int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
934{
935 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
936}
937
9ba075a6
AK		 938static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
939{
0bed3b56
SY		 940 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
941
9ba075a6
AK		 942 if (!msr_mtrr_valid(msr))
943 return 1;
944
0bed3b56
SY		 945 if (msr == MSR_MTRRdefType)
946 *pdata = vcpu->arch.mtrr_state.def_type +
947 (vcpu->arch.mtrr_state.enabled << 10);
948 else if (msr == MSR_MTRRfix64K_00000)
949 *pdata = p[0];
950 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
951 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
952 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
953 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
954 else if (msr == MSR_IA32_CR_PAT)
955 *pdata = vcpu->arch.pat;
956 else { /* Variable MTRRs */
957 int idx, is_mtrr_mask;
958 u64 *pt;
959
960 idx = (msr - 0x200) / 2;
961 is_mtrr_mask = msr - 0x200 - 2 * idx;
962 if (!is_mtrr_mask)
963 pt =
964 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
965 else
966 pt =
967 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
968 *pdata = *pt;
969 }
970
9ba075a6
AK		 971 return 0;
972}
973
890ca9ae 974static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 975{
976 u64 data;
890ca9ae
HY		 977 u64 mcg_cap = vcpu->arch.mcg_cap;
978 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 979
980 switch (msr) {
15c4a640
CO		 981 case MSR_IA32_P5_MC_ADDR:
982 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 983 data = 0;
984 break;
15c4a640 985 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 986 data = vcpu->arch.mcg_cap;
987 break;
c7ac679c 988 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 989 if (!(mcg_cap & MCG_CTL_P))
990 return 1;
991 data = vcpu->arch.mcg_ctl;
992 break;
993 case MSR_IA32_MCG_STATUS:
994 data = vcpu->arch.mcg_status;
995 break;
996 default:
997 if (msr >= MSR_IA32_MC0_CTL &&
998 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
999 u32 offset = msr - MSR_IA32_MC0_CTL;
1000 data = vcpu->arch.mce_banks[offset];
1001 break;
1002 }
1003 return 1;
1004 }
1005 *pdata = data;
1006 return 0;
1007}
1008
1009int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1010{
1011 u64 data;
1012
1013 switch (msr) {
890ca9ae 1014 case MSR_IA32_PLATFORM_ID:
15c4a640 1015 case MSR_IA32_UCODE_REV:
15c4a640 1016 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1017 case MSR_IA32_DEBUGCTLMSR:
1018 case MSR_IA32_LASTBRANCHFROMIP:
1019 case MSR_IA32_LASTBRANCHTOIP:
1020 case MSR_IA32_LASTINTFROMIP:
1021 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1022 case MSR_K8_SYSCFG:
1023 case MSR_K7_HWCR:
61a6bd67 1024 case MSR_VM_HSAVE_PA:
7fe29e0f
AS		 1025 case MSR_P6_EVNTSEL0:
1026 case MSR_P6_EVNTSEL1:
9e699624 1027 case MSR_K7_EVNTSEL0:
15c4a640
CO		 1028 data = 0;
1029 break;
9ba075a6
AK		 1030 case MSR_MTRRcap:
1031 data = 0x500 | KVM_NR_VAR_MTRR;
1032 break;
1033 case 0x200 ... 0x2ff:
1034 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1035 case 0xcd: /* fsb frequency */
1036 data = 3;
1037 break;
1038 case MSR_IA32_APICBASE:
1039 data = kvm_get_apic_base(vcpu);
1040 break;
1041 case MSR_IA32_MISC_ENABLE:
ad312c7c 1042 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1043 break;
847f0ad8
AG		 1044 case MSR_IA32_PERF_STATUS:
1045 /* TSC increment by tick */
1046 data = 1000ULL;
1047 /* CPU multiplier */
1048 data |= (((uint64_t)4ULL) << 40);
1049 break;
15c4a640 1050 case MSR_EFER:
ad312c7c 1051 data = vcpu->arch.shadow_efer;
15c4a640 1052 break;
18068523
GOC		 1053 case MSR_KVM_WALL_CLOCK:
1054 data = vcpu->kvm->arch.wall_clock;
1055 break;
1056 case MSR_KVM_SYSTEM_TIME:
1057 data = vcpu->arch.time;
1058 break;
890ca9ae
HY		 1059 case MSR_IA32_P5_MC_ADDR:
1060 case MSR_IA32_P5_MC_TYPE:
1061 case MSR_IA32_MCG_CAP:
1062 case MSR_IA32_MCG_CTL:
1063 case MSR_IA32_MCG_STATUS:
1064 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1065 return get_msr_mce(vcpu, msr, pdata);
15c4a640
CO		 1066 default:
1067 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1068 return 1;
1069 }
1070 *pdata = data;
1071 return 0;
1072}
1073EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1074
313a3dc7
CO		 1075/*
1076 * Read or write a bunch of msrs. All parameters are kernel addresses.
1077 *
1078 * @return number of msrs set successfully.
1079 */
1080static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1081 struct kvm_msr_entry *entries,
1082 int (*do_msr)(struct kvm_vcpu *vcpu,
1083 unsigned index, u64 *data))
1084{
1085 int i;
1086
1087 vcpu_load(vcpu);
1088
3200f405 1089 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1090 for (i = 0; i < msrs->nmsrs; ++i)
1091 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1092 break;
3200f405 1093 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1094
1095 vcpu_put(vcpu);
1096
1097 return i;
1098}
1099
1100/*
1101 * Read or write a bunch of msrs. Parameters are user addresses.
1102 *
1103 * @return number of msrs set successfully.
1104 */
1105static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1106 int (*do_msr)(struct kvm_vcpu *vcpu,
1107 unsigned index, u64 *data),
1108 int writeback)
1109{
1110 struct kvm_msrs msrs;
1111 struct kvm_msr_entry *entries;
1112 int r, n;
1113 unsigned size;
1114
1115 r = -EFAULT;
1116 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1117 goto out;
1118
1119 r = -E2BIG;
1120 if (msrs.nmsrs >= MAX_IO_MSRS)
1121 goto out;
1122
1123 r = -ENOMEM;
1124 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1125 entries = vmalloc(size);
1126 if (!entries)
1127 goto out;
1128
1129 r = -EFAULT;
1130 if (copy_from_user(entries, user_msrs->entries, size))
1131 goto out_free;
1132
1133 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1134 if (r < 0)
1135 goto out_free;
1136
1137 r = -EFAULT;
1138 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1139 goto out_free;
1140
1141 r = n;
1142
1143out_free:
1144 vfree(entries);
1145out:
1146 return r;
1147}
1148
018d00d2
ZX		 1149int kvm_dev_ioctl_check_extension(long ext)
1150{
1151 int r;
1152
1153 switch (ext) {
1154 case KVM_CAP_IRQCHIP:
1155 case KVM_CAP_HLT:
1156 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1157 case KVM_CAP_SET_TSS_ADDR:
07716717 1158 case KVM_CAP_EXT_CPUID:
c8076604 1159 case KVM_CAP_CLOCKSOURCE:
7837699f 1160 case KVM_CAP_PIT:
a28e4f5a 1161 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1162 case KVM_CAP_MP_STATE:
ed848624 1163 case KVM_CAP_SYNC_MMU:
52d939a0 1164 case KVM_CAP_REINJECT_CONTROL:
4925663a 1165 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1166 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1167 case KVM_CAP_IRQFD:
c5ff41ce 1168 case KVM_CAP_PIT2:
018d00d2
ZX		 1169 r = 1;
1170 break;
542472b5
LV		 1171 case KVM_CAP_COALESCED_MMIO:
1172 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1173 break;
774ead3a
AK		 1174 case KVM_CAP_VAPIC:
1175 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1176 break;
f725230a
AK		 1177 case KVM_CAP_NR_VCPUS:
1178 r = KVM_MAX_VCPUS;
1179 break;
a988b910
AK		 1180 case KVM_CAP_NR_MEMSLOTS:
1181 r = KVM_MEMORY_SLOTS;
1182 break;
2f333bcb
MT		 1183 case KVM_CAP_PV_MMU:
1184 r = !tdp_enabled;
1185 break;
62c476c7 1186 case KVM_CAP_IOMMU:
19de40a8 1187 r = iommu_found();
62c476c7 1188 break;
890ca9ae
HY		 1189 case KVM_CAP_MCE:
1190 r = KVM_MAX_MCE_BANKS;
1191 break;
018d00d2
ZX		 1192 default:
1193 r = 0;
1194 break;
1195 }
1196 return r;
1197
1198}
1199
043405e1
CO		 1200long kvm_arch_dev_ioctl(struct file *filp,
1201 unsigned int ioctl, unsigned long arg)
1202{
1203 void __user *argp = (void __user *)arg;
1204 long r;
1205
1206 switch (ioctl) {
1207 case KVM_GET_MSR_INDEX_LIST: {
1208 struct kvm_msr_list __user *user_msr_list = argp;
1209 struct kvm_msr_list msr_list;
1210 unsigned n;
1211
1212 r = -EFAULT;
1213 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1214 goto out;
1215 n = msr_list.nmsrs;
1216 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1217 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1218 goto out;
1219 r = -E2BIG;
e125e7b6 1220 if (n < msr_list.nmsrs)
043405e1
CO		 1221 goto out;
1222 r = -EFAULT;
1223 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1224 num_msrs_to_save * sizeof(u32)))
1225 goto out;
e125e7b6 1226 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1227 &emulated_msrs,
1228 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1229 goto out;
1230 r = 0;
1231 break;
1232 }
674eea0f
AK		 1233 case KVM_GET_SUPPORTED_CPUID: {
1234 struct kvm_cpuid2 __user *cpuid_arg = argp;
1235 struct kvm_cpuid2 cpuid;
1236
1237 r = -EFAULT;
1238 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1239 goto out;
1240 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1241 cpuid_arg->entries);
674eea0f
AK		 1242 if (r)
1243 goto out;
1244
1245 r = -EFAULT;
1246 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1247 goto out;
1248 r = 0;
1249 break;
1250 }
890ca9ae
HY		 1251 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1252 u64 mce_cap;
1253
1254 mce_cap = KVM_MCE_CAP_SUPPORTED;
1255 r = -EFAULT;
1256 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1257 goto out;
1258 r = 0;
1259 break;
1260 }
043405e1
CO		 1261 default:
1262 r = -EINVAL;
1263 }
1264out:
1265 return r;
1266}
1267
313a3dc7
CO		 1268void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1269{
1270 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1271 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1272}
1273
1274void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1275{
1276 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1277 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1278}
1279
07716717 1280static int is_efer_nx(void)
313a3dc7 1281{
e286e86e 1282 unsigned long long efer = 0;
313a3dc7 1283
e286e86e 1284 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1285 return efer & EFER_NX;
1286}
1287
1288static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1289{
1290 int i;
1291 struct kvm_cpuid_entry2 *e, *entry;
1292
313a3dc7 1293 entry = NULL;
ad312c7c
ZX		 1294 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1295 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1296 if (e->function == 0x80000001) {
1297 entry = e;
1298 break;
1299 }
1300 }
07716717 1301 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1302 entry->edx &= ~(1 << 20);
1303 printk(KERN_INFO "kvm: guest NX capability removed\n");
1304 }
1305}
1306
07716717 1307/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1308static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1309 struct kvm_cpuid *cpuid,
1310 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1311{
1312 int r, i;
1313 struct kvm_cpuid_entry *cpuid_entries;
1314
1315 r = -E2BIG;
1316 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1317 goto out;
1318 r = -ENOMEM;
1319 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1320 if (!cpuid_entries)
1321 goto out;
1322 r = -EFAULT;
1323 if (copy_from_user(cpuid_entries, entries,
1324 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1325 goto out_free;
1326 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1327 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1328 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1329 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1330 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1331 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1332 vcpu->arch.cpuid_entries[i].index = 0;
1333 vcpu->arch.cpuid_entries[i].flags = 0;
1334 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1335 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1336 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1337 }
1338 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1339 cpuid_fix_nx_cap(vcpu);
1340 r = 0;
1341
1342out_free:
1343 vfree(cpuid_entries);
1344out:
1345 return r;
1346}
1347
1348static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1349 struct kvm_cpuid2 *cpuid,
1350 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1351{
1352 int r;
1353
1354 r = -E2BIG;
1355 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1356 goto out;
1357 r = -EFAULT;
ad312c7c 1358 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1359 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1360 goto out;
ad312c7c 1361 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1362 return 0;
1363
1364out:
1365 return r;
1366}
1367
07716717 1368static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1369 struct kvm_cpuid2 *cpuid,
1370 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1371{
1372 int r;
1373
1374 r = -E2BIG;
ad312c7c 1375 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1376 goto out;
1377 r = -EFAULT;
ad312c7c 1378 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1379 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1380 goto out;
1381 return 0;
1382
1383out:
ad312c7c 1384 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1385 return r;
1386}
1387
07716717 1388static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1389 u32 index)
07716717
DK		 1390{
1391 entry->function = function;
1392 entry->index = index;
1393 cpuid_count(entry->function, entry->index,
19355475 1394 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1395 entry->flags = 0;
1396}
1397
7faa4ee1
AK		 1398#define F(x) bit(X86_FEATURE_##x)
1399
07716717
DK		 1400static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1401 u32 index, int *nent, int maxnent)
1402{
7faa4ee1 1403 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1404#ifdef CONFIG_X86_64
7faa4ee1
AK		 1405 unsigned f_lm = F(LM);
1406#else
1407 unsigned f_lm = 0;
07716717 1408#endif
7faa4ee1
AK		 1409
1410 /* cpuid 1.edx */
1411 const u32 kvm_supported_word0_x86_features =
1412 F(FPU) | F(VME) | F(DE) | F(PSE) |
1413 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1414 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1415 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1416 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1417 0 /* Reserved, DS, ACPI */ | F(MMX) |
1418 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1419 0 /* HTT, TM, Reserved, PBE */;
1420 /* cpuid 0x80000001.edx */
1421 const u32 kvm_supported_word1_x86_features =
1422 F(FPU) | F(VME) | F(DE) | F(PSE) |
1423 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1424 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1425 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1426 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1427 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1428 F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
1429 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1430 /* cpuid 1.ecx */
1431 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1432 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1433 0 /* DS-CPL, VMX, SMX, EST */ |
1434 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1435 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1436 0 /* Reserved, DCA */ | F(XMM4_1) |
1437 F(XMM4_2) | 0 /* x2APIC */ | F(MOVBE) | F(POPCNT) |
1438 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1439 /* cpuid 0x80000001.ecx */
07716717 1440 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1441 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1442 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1443 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1444 0 /* SKINIT */ | 0 /* WDT */;
07716717 1445
19355475 1446 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1447 get_cpu();
1448 do_cpuid_1_ent(entry, function, index);
1449 ++*nent;
1450
1451 switch (function) {
1452 case 0:
1453 entry->eax = min(entry->eax, (u32)0xb);
1454 break;
1455 case 1:
1456 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1457 entry->ecx &= kvm_supported_word4_x86_features;
07716717
DK		 1458 break;
1459 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1460 * may return different values. This forces us to get_cpu() before
1461 * issuing the first command, and also to emulate this annoying behavior
1462 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1463 case 2: {
1464 int t, times = entry->eax & 0xff;
1465
1466 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1467 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1468 for (t = 1; t < times && *nent < maxnent; ++t) {
1469 do_cpuid_1_ent(&entry[t], function, 0);
1470 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1471 ++*nent;
1472 }
1473 break;
1474 }
1475 /* function 4 and 0xb have additional index. */
1476 case 4: {
14af3f3c 1477 int i, cache_type;
07716717
DK		 1478
1479 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1480 /* read more entries until cache_type is zero */
14af3f3c
HH		 1481 for (i = 1; *nent < maxnent; ++i) {
1482 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1483 if (!cache_type)
1484 break;
14af3f3c
HH		 1485 do_cpuid_1_ent(&entry[i], function, i);
1486 entry[i].flags |=
07716717
DK		 1487 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1488 ++*nent;
1489 }
1490 break;
1491 }
1492 case 0xb: {
14af3f3c 1493 int i, level_type;
07716717
DK		 1494
1495 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1496 /* read more entries until level_type is zero */
14af3f3c 1497 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1498 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1499 if (!level_type)
1500 break;
14af3f3c
HH		 1501 do_cpuid_1_ent(&entry[i], function, i);
1502 entry[i].flags |=
07716717
DK		 1503 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1504 ++*nent;
1505 }
1506 break;
1507 }
1508 case 0x80000000:
1509 entry->eax = min(entry->eax, 0x8000001a);
1510 break;
1511 case 0x80000001:
1512 entry->edx &= kvm_supported_word1_x86_features;
1513 entry->ecx &= kvm_supported_word6_x86_features;
1514 break;
1515 }
1516 put_cpu();
1517}
1518
7faa4ee1
AK		 1519#undef F
1520
674eea0f 1521static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1522 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1523{
1524 struct kvm_cpuid_entry2 *cpuid_entries;
1525 int limit, nent = 0, r = -E2BIG;
1526 u32 func;
1527
1528 if (cpuid->nent < 1)
1529 goto out;
1530 r = -ENOMEM;
1531 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1532 if (!cpuid_entries)
1533 goto out;
1534
1535 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1536 limit = cpuid_entries[0].eax;
1537 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1538 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1539 &nent, cpuid->nent);
07716717
DK		 1540 r = -E2BIG;
1541 if (nent >= cpuid->nent)
1542 goto out_free;
1543
1544 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1545 limit = cpuid_entries[nent - 1].eax;
1546 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1547 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1548 &nent, cpuid->nent);
cb007648
MM		 1549 r = -E2BIG;
1550 if (nent >= cpuid->nent)
1551 goto out_free;
1552
07716717
DK		 1553 r = -EFAULT;
1554 if (copy_to_user(entries, cpuid_entries,
19355475 1555 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1556 goto out_free;
1557 cpuid->nent = nent;
1558 r = 0;
1559
1560out_free:
1561 vfree(cpuid_entries);
1562out:
1563 return r;
1564}
1565
313a3dc7
CO		 1566static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1567 struct kvm_lapic_state *s)
1568{
1569 vcpu_load(vcpu);
ad312c7c 1570 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1571 vcpu_put(vcpu);
1572
1573 return 0;
1574}
1575
1576static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1577 struct kvm_lapic_state *s)
1578{
1579 vcpu_load(vcpu);
ad312c7c 1580 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1581 kvm_apic_post_state_restore(vcpu);
1582 vcpu_put(vcpu);
1583
1584 return 0;
1585}
1586
f77bc6a4
ZX		 1587static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1588 struct kvm_interrupt *irq)
1589{
1590 if (irq->irq < 0 || irq->irq >= 256)
1591 return -EINVAL;
1592 if (irqchip_in_kernel(vcpu->kvm))
1593 return -ENXIO;
1594 vcpu_load(vcpu);
1595
66fd3f7f 1596 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1597
1598 vcpu_put(vcpu);
1599
1600 return 0;
1601}
1602
c4abb7c9
JK		 1603static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1604{
1605 vcpu_load(vcpu);
1606 kvm_inject_nmi(vcpu);
1607 vcpu_put(vcpu);
1608
1609 return 0;
1610}
1611
b209749f
AK		 1612static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1613 struct kvm_tpr_access_ctl *tac)
1614{
1615 if (tac->flags)
1616 return -EINVAL;
1617 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1618 return 0;
1619}
1620
890ca9ae
HY		 1621static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1622 u64 mcg_cap)
1623{
1624 int r;
1625 unsigned bank_num = mcg_cap & 0xff, bank;
1626
1627 r = -EINVAL;
1628 if (!bank_num)
1629 goto out;
1630 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1631 goto out;
1632 r = 0;
1633 vcpu->arch.mcg_cap = mcg_cap;
1634 /* Init IA32_MCG_CTL to all 1s */
1635 if (mcg_cap & MCG_CTL_P)
1636 vcpu->arch.mcg_ctl = ~(u64)0;
1637 /* Init IA32_MCi_CTL to all 1s */
1638 for (bank = 0; bank < bank_num; bank++)
1639 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1640out:
1641 return r;
1642}
1643
1644static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1645 struct kvm_x86_mce *mce)
1646{
1647 u64 mcg_cap = vcpu->arch.mcg_cap;
1648 unsigned bank_num = mcg_cap & 0xff;
1649 u64 *banks = vcpu->arch.mce_banks;
1650
1651 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1652 return -EINVAL;
1653 /*
1654 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1655 * reporting is disabled
1656 */
1657 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1658 vcpu->arch.mcg_ctl != ~(u64)0)
1659 return 0;
1660 banks += 4 * mce->bank;
1661 /*
1662 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1663 * reporting is disabled for the bank
1664 */
1665 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1666 return 0;
1667 if (mce->status & MCI_STATUS_UC) {
1668 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1669 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1670 printk(KERN_DEBUG "kvm: set_mce: "
1671 "injects mce exception while "
1672 "previous one is in progress!\n");
1673 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1674 return 0;
1675 }
1676 if (banks[1] & MCI_STATUS_VAL)
1677 mce->status |= MCI_STATUS_OVER;
1678 banks[2] = mce->addr;
1679 banks[3] = mce->misc;
1680 vcpu->arch.mcg_status = mce->mcg_status;
1681 banks[1] = mce->status;
1682 kvm_queue_exception(vcpu, MC_VECTOR);
1683 } else if (!(banks[1] & MCI_STATUS_VAL)
1684 || !(banks[1] & MCI_STATUS_UC)) {
1685 if (banks[1] & MCI_STATUS_VAL)
1686 mce->status |= MCI_STATUS_OVER;
1687 banks[2] = mce->addr;
1688 banks[3] = mce->misc;
1689 banks[1] = mce->status;
1690 } else
1691 banks[1] |= MCI_STATUS_OVER;
1692 return 0;
1693}
1694
313a3dc7
CO		 1695long kvm_arch_vcpu_ioctl(struct file *filp,
1696 unsigned int ioctl, unsigned long arg)
1697{
1698 struct kvm_vcpu *vcpu = filp->private_data;
1699 void __user *argp = (void __user *)arg;
1700 int r;
b772ff36 1701 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1702
1703 switch (ioctl) {
1704 case KVM_GET_LAPIC: {
b772ff36 1705 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1706
b772ff36
DH		 1707 r = -ENOMEM;
1708 if (!lapic)
1709 goto out;
1710 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1711 if (r)
1712 goto out;
1713 r = -EFAULT;
b772ff36 1714 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1715 goto out;
1716 r = 0;
1717 break;
1718 }
1719 case KVM_SET_LAPIC: {
b772ff36
DH		 1720 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1721 r = -ENOMEM;
1722 if (!lapic)
1723 goto out;
313a3dc7 1724 r = -EFAULT;
b772ff36 1725 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1726 goto out;
b772ff36 1727 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1728 if (r)
1729 goto out;
1730 r = 0;
1731 break;
1732 }
f77bc6a4
ZX		 1733 case KVM_INTERRUPT: {
1734 struct kvm_interrupt irq;
1735
1736 r = -EFAULT;
1737 if (copy_from_user(&irq, argp, sizeof irq))
1738 goto out;
1739 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1740 if (r)
1741 goto out;
1742 r = 0;
1743 break;
1744 }
c4abb7c9
JK		 1745 case KVM_NMI: {
1746 r = kvm_vcpu_ioctl_nmi(vcpu);
1747 if (r)
1748 goto out;
1749 r = 0;
1750 break;
1751 }
313a3dc7
CO		 1752 case KVM_SET_CPUID: {
1753 struct kvm_cpuid __user *cpuid_arg = argp;
1754 struct kvm_cpuid cpuid;
1755
1756 r = -EFAULT;
1757 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1758 goto out;
1759 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1760 if (r)
1761 goto out;
1762 break;
1763 }
07716717
DK		 1764 case KVM_SET_CPUID2: {
1765 struct kvm_cpuid2 __user *cpuid_arg = argp;
1766 struct kvm_cpuid2 cpuid;
1767
1768 r = -EFAULT;
1769 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1770 goto out;
1771 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1772 cpuid_arg->entries);
07716717
DK		 1773 if (r)
1774 goto out;
1775 break;
1776 }
1777 case KVM_GET_CPUID2: {
1778 struct kvm_cpuid2 __user *cpuid_arg = argp;
1779 struct kvm_cpuid2 cpuid;
1780
1781 r = -EFAULT;
1782 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1783 goto out;
1784 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1785 cpuid_arg->entries);
07716717
DK		 1786 if (r)
1787 goto out;
1788 r = -EFAULT;
1789 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1790 goto out;
1791 r = 0;
1792 break;
1793 }
313a3dc7
CO		 1794 case KVM_GET_MSRS:
1795 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1796 break;
1797 case KVM_SET_MSRS:
1798 r = msr_io(vcpu, argp, do_set_msr, 0);
1799 break;
b209749f
AK		 1800 case KVM_TPR_ACCESS_REPORTING: {
1801 struct kvm_tpr_access_ctl tac;
1802
1803 r = -EFAULT;
1804 if (copy_from_user(&tac, argp, sizeof tac))
1805 goto out;
1806 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1807 if (r)
1808 goto out;
1809 r = -EFAULT;
1810 if (copy_to_user(argp, &tac, sizeof tac))
1811 goto out;
1812 r = 0;
1813 break;
1814 };
b93463aa
AK		 1815 case KVM_SET_VAPIC_ADDR: {
1816 struct kvm_vapic_addr va;
1817
1818 r = -EINVAL;
1819 if (!irqchip_in_kernel(vcpu->kvm))
1820 goto out;
1821 r = -EFAULT;
1822 if (copy_from_user(&va, argp, sizeof va))
1823 goto out;
1824 r = 0;
1825 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1826 break;
1827 }
890ca9ae
HY		 1828 case KVM_X86_SETUP_MCE: {
1829 u64 mcg_cap;
1830
1831 r = -EFAULT;
1832 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1833 goto out;
1834 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1835 break;
1836 }
1837 case KVM_X86_SET_MCE: {
1838 struct kvm_x86_mce mce;
1839
1840 r = -EFAULT;
1841 if (copy_from_user(&mce, argp, sizeof mce))
1842 goto out;
1843 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1844 break;
1845 }
313a3dc7
CO		 1846 default:
1847 r = -EINVAL;
1848 }
1849out:
7a6ce84c 1850 kfree(lapic);
313a3dc7
CO		 1851 return r;
1852}
1853
1fe779f8
CO		 1854static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1855{
1856 int ret;
1857
1858 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1859 return -1;
1860 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1861 return ret;
1862}
1863
1864static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1865 u32 kvm_nr_mmu_pages)
1866{
1867 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1868 return -EINVAL;
1869
72dc67a6 1870 down_write(&kvm->slots_lock);
7c8a83b7 1871 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1872
1873 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1874 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1875
7c8a83b7 1876 spin_unlock(&kvm->mmu_lock);
72dc67a6 1877 up_write(&kvm->slots_lock);
1fe779f8
CO		 1878 return 0;
1879}
1880
1881static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1882{
f05e70ac 1883 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1884}
1885
e9f85cde
ZX		 1886gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1887{
1888 int i;
1889 struct kvm_mem_alias *alias;
1890
d69fb81f
ZX		 1891 for (i = 0; i < kvm->arch.naliases; ++i) {
1892 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1893 if (gfn >= alias->base_gfn
1894 && gfn < alias->base_gfn + alias->npages)
1895 return alias->target_gfn + gfn - alias->base_gfn;
1896 }
1897 return gfn;
1898}
1899
1fe779f8
CO		 1900/*
1901 * Set a new alias region. Aliases map a portion of physical memory into
1902 * another portion. This is useful for memory windows, for example the PC
1903 * VGA region.
1904 */
1905static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1906 struct kvm_memory_alias *alias)
1907{
1908 int r, n;
1909 struct kvm_mem_alias *p;
1910
1911 r = -EINVAL;
1912 /* General sanity checks */
1913 if (alias->memory_size & (PAGE_SIZE - 1))
1914 goto out;
1915 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1916 goto out;
1917 if (alias->slot >= KVM_ALIAS_SLOTS)
1918 goto out;
1919 if (alias->guest_phys_addr + alias->memory_size
1920 < alias->guest_phys_addr)
1921 goto out;
1922 if (alias->target_phys_addr + alias->memory_size
1923 < alias->target_phys_addr)
1924 goto out;
1925
72dc67a6 1926 down_write(&kvm->slots_lock);
a1708ce8 1927 spin_lock(&kvm->mmu_lock);
1fe779f8 1928
d69fb81f 1929 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1930 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1931 p->npages = alias->memory_size >> PAGE_SHIFT;
1932 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1933
1934 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1935 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1936 break;
d69fb81f 1937 kvm->arch.naliases = n;
1fe779f8 1938
a1708ce8 1939 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1940 kvm_mmu_zap_all(kvm);
1941
72dc67a6 1942 up_write(&kvm->slots_lock);
1fe779f8
CO		 1943
1944 return 0;
1945
1946out:
1947 return r;
1948}
1949
1950static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1951{
1952 int r;
1953
1954 r = 0;
1955 switch (chip->chip_id) {
1956 case KVM_IRQCHIP_PIC_MASTER:
1957 memcpy(&chip->chip.pic,
1958 &pic_irqchip(kvm)->pics[0],
1959 sizeof(struct kvm_pic_state));
1960 break;
1961 case KVM_IRQCHIP_PIC_SLAVE:
1962 memcpy(&chip->chip.pic,
1963 &pic_irqchip(kvm)->pics[1],
1964 sizeof(struct kvm_pic_state));
1965 break;
1966 case KVM_IRQCHIP_IOAPIC:
1967 memcpy(&chip->chip.ioapic,
1968 ioapic_irqchip(kvm),
1969 sizeof(struct kvm_ioapic_state));
1970 break;
1971 default:
1972 r = -EINVAL;
1973 break;
1974 }
1975 return r;
1976}
1977
1978static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1979{
1980 int r;
1981
1982 r = 0;
1983 switch (chip->chip_id) {
1984 case KVM_IRQCHIP_PIC_MASTER:
1985 memcpy(&pic_irqchip(kvm)->pics[0],
1986 &chip->chip.pic,
1987 sizeof(struct kvm_pic_state));
1988 break;
1989 case KVM_IRQCHIP_PIC_SLAVE:
1990 memcpy(&pic_irqchip(kvm)->pics[1],
1991 &chip->chip.pic,
1992 sizeof(struct kvm_pic_state));
1993 break;
1994 case KVM_IRQCHIP_IOAPIC:
1995 memcpy(ioapic_irqchip(kvm),
1996 &chip->chip.ioapic,
1997 sizeof(struct kvm_ioapic_state));
1998 break;
1999 default:
2000 r = -EINVAL;
2001 break;
2002 }
2003 kvm_pic_update_irq(pic_irqchip(kvm));
2004 return r;
2005}
2006
e0f63cb9
SY		 2007static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2008{
2009 int r = 0;
2010
2011 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
2012 return r;
2013}
2014
2015static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2016{
2017 int r = 0;
2018
2019 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2020 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
2021 return r;
2022}
2023
52d939a0
MT		 2024static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2025 struct kvm_reinject_control *control)
2026{
2027 if (!kvm->arch.vpit)
2028 return -ENXIO;
2029 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
2030 return 0;
2031}
2032
5bb064dc
ZX		 2033/*
2034 * Get (and clear) the dirty memory log for a memory slot.
2035 */
2036int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2037 struct kvm_dirty_log *log)
2038{
2039 int r;
2040 int n;
2041 struct kvm_memory_slot *memslot;
2042 int is_dirty = 0;
2043
72dc67a6 2044 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2045
2046 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2047 if (r)
2048 goto out;
2049
2050 /* If nothing is dirty, don't bother messing with page tables. */
2051 if (is_dirty) {
7c8a83b7 2052 spin_lock(&kvm->mmu_lock);
5bb064dc 2053 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2054 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2055 kvm_flush_remote_tlbs(kvm);
2056 memslot = &kvm->memslots[log->slot];
2057 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2058 memset(memslot->dirty_bitmap, 0, n);
2059 }
2060 r = 0;
2061out:
72dc67a6 2062 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2063 return r;
2064}
2065
1fe779f8
CO		 2066long kvm_arch_vm_ioctl(struct file *filp,
2067 unsigned int ioctl, unsigned long arg)
2068{
2069 struct kvm *kvm = filp->private_data;
2070 void __user *argp = (void __user *)arg;
2071 int r = -EINVAL;
f0d66275
DH		 2072 /*
2073 * This union makes it completely explicit to gcc-3.x
2074 * that these two variables' stack usage should be
2075 * combined, not added together.
2076 */
2077 union {
2078 struct kvm_pit_state ps;
2079 struct kvm_memory_alias alias;
c5ff41ce 2080 struct kvm_pit_config pit_config;
f0d66275 2081 } u;
1fe779f8
CO		 2082
2083 switch (ioctl) {
2084 case KVM_SET_TSS_ADDR:
2085 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2086 if (r < 0)
2087 goto out;
2088 break;
2089 case KVM_SET_MEMORY_REGION: {
2090 struct kvm_memory_region kvm_mem;
2091 struct kvm_userspace_memory_region kvm_userspace_mem;
2092
2093 r = -EFAULT;
2094 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2095 goto out;
2096 kvm_userspace_mem.slot = kvm_mem.slot;
2097 kvm_userspace_mem.flags = kvm_mem.flags;
2098 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2099 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2100 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2101 if (r)
2102 goto out;
2103 break;
2104 }
2105 case KVM_SET_NR_MMU_PAGES:
2106 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2107 if (r)
2108 goto out;
2109 break;
2110 case KVM_GET_NR_MMU_PAGES:
2111 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2112 break;
f0d66275 2113 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2114 r = -EFAULT;
f0d66275 2115 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2116 goto out;
f0d66275 2117 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2118 if (r)
2119 goto out;
2120 break;
1fe779f8
CO		 2121 case KVM_CREATE_IRQCHIP:
2122 r = -ENOMEM;
d7deeeb0
ZX		 2123 kvm->arch.vpic = kvm_create_pic(kvm);
2124 if (kvm->arch.vpic) {
1fe779f8
CO		 2125 r = kvm_ioapic_init(kvm);
2126 if (r) {
d7deeeb0
ZX		 2127 kfree(kvm->arch.vpic);
2128 kvm->arch.vpic = NULL;
1fe779f8
CO		 2129 goto out;
2130 }
2131 } else
2132 goto out;
399ec807
AK		 2133 r = kvm_setup_default_irq_routing(kvm);
2134 if (r) {
2135 kfree(kvm->arch.vpic);
2136 kfree(kvm->arch.vioapic);
2137 goto out;
2138 }
1fe779f8 2139 break;
7837699f 2140 case KVM_CREATE_PIT:
c5ff41ce
JK		 2141 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2142 goto create_pit;
2143 case KVM_CREATE_PIT2:
2144 r = -EFAULT;
2145 if (copy_from_user(&u.pit_config, argp,
2146 sizeof(struct kvm_pit_config)))
2147 goto out;
2148 create_pit:
269e05e4
AK		 2149 mutex_lock(&kvm->lock);
2150 r = -EEXIST;
2151 if (kvm->arch.vpit)
2152 goto create_pit_unlock;
7837699f 2153 r = -ENOMEM;
c5ff41ce 2154 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2155 if (kvm->arch.vpit)
2156 r = 0;
269e05e4
AK		 2157 create_pit_unlock:
2158 mutex_unlock(&kvm->lock);
7837699f 2159 break;
4925663a 2160 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2161 case KVM_IRQ_LINE: {
2162 struct kvm_irq_level irq_event;
2163
2164 r = -EFAULT;
2165 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2166 goto out;
2167 if (irqchip_in_kernel(kvm)) {
4925663a 2168 __s32 status;
fa40a821 2169 mutex_lock(&kvm->irq_lock);
4925663a
GN		 2170 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2171 irq_event.irq, irq_event.level);
fa40a821 2172 mutex_unlock(&kvm->irq_lock);
4925663a
GN		 2173 if (ioctl == KVM_IRQ_LINE_STATUS) {
2174 irq_event.status = status;
2175 if (copy_to_user(argp, &irq_event,
2176 sizeof irq_event))
2177 goto out;
2178 }
1fe779f8
CO		 2179 r = 0;
2180 }
2181 break;
2182 }
2183 case KVM_GET_IRQCHIP: {
2184 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2185 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2186
f0d66275
DH		 2187 r = -ENOMEM;
2188 if (!chip)
1fe779f8 2189 goto out;
f0d66275
DH		 2190 r = -EFAULT;
2191 if (copy_from_user(chip, argp, sizeof *chip))
2192 goto get_irqchip_out;
1fe779f8
CO		 2193 r = -ENXIO;
2194 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2195 goto get_irqchip_out;
2196 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2197 if (r)
f0d66275 2198 goto get_irqchip_out;
1fe779f8 2199 r = -EFAULT;
f0d66275
DH		 2200 if (copy_to_user(argp, chip, sizeof *chip))
2201 goto get_irqchip_out;
1fe779f8 2202 r = 0;
f0d66275
DH		 2203 get_irqchip_out:
2204 kfree(chip);
2205 if (r)
2206 goto out;
1fe779f8
CO		 2207 break;
2208 }
2209 case KVM_SET_IRQCHIP: {
2210 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2211 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2212
f0d66275
DH		 2213 r = -ENOMEM;
2214 if (!chip)
1fe779f8 2215 goto out;
f0d66275
DH		 2216 r = -EFAULT;
2217 if (copy_from_user(chip, argp, sizeof *chip))
2218 goto set_irqchip_out;
1fe779f8
CO		 2219 r = -ENXIO;
2220 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2221 goto set_irqchip_out;
2222 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2223 if (r)
f0d66275 2224 goto set_irqchip_out;
1fe779f8 2225 r = 0;
f0d66275
DH		 2226 set_irqchip_out:
2227 kfree(chip);
2228 if (r)
2229 goto out;
1fe779f8
CO		 2230 break;
2231 }
e0f63cb9 2232 case KVM_GET_PIT: {
e0f63cb9 2233 r = -EFAULT;
f0d66275 2234 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2235 goto out;
2236 r = -ENXIO;
2237 if (!kvm->arch.vpit)
2238 goto out;
f0d66275 2239 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2240 if (r)
2241 goto out;
2242 r = -EFAULT;
f0d66275 2243 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2244 goto out;
2245 r = 0;
2246 break;
2247 }
2248 case KVM_SET_PIT: {
e0f63cb9 2249 r = -EFAULT;
f0d66275 2250 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2251 goto out;
2252 r = -ENXIO;
2253 if (!kvm->arch.vpit)
2254 goto out;
f0d66275 2255 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2256 if (r)
2257 goto out;
2258 r = 0;
2259 break;
2260 }
52d939a0
MT		 2261 case KVM_REINJECT_CONTROL: {
2262 struct kvm_reinject_control control;
2263 r = -EFAULT;
2264 if (copy_from_user(&control, argp, sizeof(control)))
2265 goto out;
2266 r = kvm_vm_ioctl_reinject(kvm, &control);
2267 if (r)
2268 goto out;
2269 r = 0;
2270 break;
2271 }
1fe779f8
CO		 2272 default:
2273 ;
2274 }
2275out:
2276 return r;
2277}
2278
a16b043c 2279static void kvm_init_msr_list(void)
043405e1
CO		 2280{
2281 u32 dummy[2];
2282 unsigned i, j;
2283
2284 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2285 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2286 continue;
2287 if (j < i)
2288 msrs_to_save[j] = msrs_to_save[i];
2289 j++;
2290 }
2291 num_msrs_to_save = j;
2292}
2293
bbd9b64e
CO		 2294/*
2295 * Only apic need an MMIO device hook, so shortcut now..
2296 */
2297static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2298 gpa_t addr, int len,
2299 int is_write)
bbd9b64e
CO		 2300{
2301 struct kvm_io_device *dev;
2302
ad312c7c
ZX		 2303 if (vcpu->arch.apic) {
2304 dev = &vcpu->arch.apic->dev;
d76685c4 2305 if (kvm_iodevice_in_range(dev, addr, len, is_write))
bbd9b64e
CO		 2306 return dev;
2307 }
2308 return NULL;
2309}
2310
2311
2312static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2313 gpa_t addr, int len,
2314 int is_write)
bbd9b64e
CO		 2315{
2316 struct kvm_io_device *dev;
2317
92760499 2318 dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
bbd9b64e 2319 if (dev == NULL)
92760499
LV		 2320 dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
2321 is_write);
bbd9b64e
CO		 2322 return dev;
2323}
2324
cded19f3
HE		 2325static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2326 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2327{
2328 void *data = val;
10589a46 2329 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2330
2331 while (bytes) {
ad312c7c 2332 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2333 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2334 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2335 int ret;
2336
10589a46
MT		 2337 if (gpa == UNMAPPED_GVA) {
2338 r = X86EMUL_PROPAGATE_FAULT;
2339 goto out;
2340 }
77c2002e 2341 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2342 if (ret < 0) {
2343 r = X86EMUL_UNHANDLEABLE;
2344 goto out;
2345 }
bbd9b64e 2346
77c2002e
IE		 2347 bytes -= toread;
2348 data += toread;
2349 addr += toread;
bbd9b64e 2350 }
10589a46 2351out:
10589a46 2352 return r;
bbd9b64e 2353}
77c2002e 2354
cded19f3
HE		 2355static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2356 struct kvm_vcpu *vcpu)
77c2002e
IE		 2357{
2358 void *data = val;
2359 int r = X86EMUL_CONTINUE;
2360
2361 while (bytes) {
2362 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2363 unsigned offset = addr & (PAGE_SIZE-1);
2364 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2365 int ret;
2366
2367 if (gpa == UNMAPPED_GVA) {
2368 r = X86EMUL_PROPAGATE_FAULT;
2369 goto out;
2370 }
2371 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2372 if (ret < 0) {
2373 r = X86EMUL_UNHANDLEABLE;
2374 goto out;
2375 }
2376
2377 bytes -= towrite;
2378 data += towrite;
2379 addr += towrite;
2380 }
2381out:
2382 return r;
2383}
2384
bbd9b64e 2385
bbd9b64e
CO		 2386static int emulator_read_emulated(unsigned long addr,
2387 void *val,
2388 unsigned int bytes,
2389 struct kvm_vcpu *vcpu)
2390{
2391 struct kvm_io_device *mmio_dev;
2392 gpa_t gpa;
2393
2394 if (vcpu->mmio_read_completed) {
2395 memcpy(val, vcpu->mmio_data, bytes);
2396 vcpu->mmio_read_completed = 0;
2397 return X86EMUL_CONTINUE;
2398 }
2399
ad312c7c 2400 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2401
2402 /* For APIC access vmexit */
2403 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2404 goto mmio;
2405
77c2002e
IE		 2406 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2407 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2408 return X86EMUL_CONTINUE;
2409 if (gpa == UNMAPPED_GVA)
2410 return X86EMUL_PROPAGATE_FAULT;
2411
2412mmio:
2413 /*
2414 * Is this MMIO handled locally?
2415 */
10589a46 2416 mutex_lock(&vcpu->kvm->lock);
92760499 2417 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
fa40a821 2418 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2419 if (mmio_dev) {
2420 kvm_iodevice_read(mmio_dev, gpa, bytes, val);
2421 return X86EMUL_CONTINUE;
2422 }
2423
2424 vcpu->mmio_needed = 1;
2425 vcpu->mmio_phys_addr = gpa;
2426 vcpu->mmio_size = bytes;
2427 vcpu->mmio_is_write = 0;
2428
2429 return X86EMUL_UNHANDLEABLE;
2430}
2431
3200f405 2432int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2433 const void *val, int bytes)
bbd9b64e
CO		 2434{
2435 int ret;
2436
2437 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2438 if (ret < 0)
bbd9b64e 2439 return 0;
ad218f85 2440 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2441 return 1;
2442}
2443
2444static int emulator_write_emulated_onepage(unsigned long addr,
2445 const void *val,
2446 unsigned int bytes,
2447 struct kvm_vcpu *vcpu)
2448{
2449 struct kvm_io_device *mmio_dev;
10589a46
MT		 2450 gpa_t gpa;
2451
10589a46 2452 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2453
2454 if (gpa == UNMAPPED_GVA) {
c3c91fee 2455 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2456 return X86EMUL_PROPAGATE_FAULT;
2457 }
2458
2459 /* For APIC access vmexit */
2460 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2461 goto mmio;
2462
2463 if (emulator_write_phys(vcpu, gpa, val, bytes))
2464 return X86EMUL_CONTINUE;
2465
2466mmio:
2467 /*
2468 * Is this MMIO handled locally?
2469 */
10589a46 2470 mutex_lock(&vcpu->kvm->lock);
92760499 2471 mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
fa40a821 2472 mutex_unlock(&vcpu->kvm->lock);
bbd9b64e
CO		 2473 if (mmio_dev) {
2474 kvm_iodevice_write(mmio_dev, gpa, bytes, val);
2475 return X86EMUL_CONTINUE;
2476 }
2477
2478 vcpu->mmio_needed = 1;
2479 vcpu->mmio_phys_addr = gpa;
2480 vcpu->mmio_size = bytes;
2481 vcpu->mmio_is_write = 1;
2482 memcpy(vcpu->mmio_data, val, bytes);
2483
2484 return X86EMUL_CONTINUE;
2485}
2486
2487int emulator_write_emulated(unsigned long addr,
2488 const void *val,
2489 unsigned int bytes,
2490 struct kvm_vcpu *vcpu)
2491{
2492 /* Crossing a page boundary? */
2493 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2494 int rc, now;
2495
2496 now = -addr & ~PAGE_MASK;
2497 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2498 if (rc != X86EMUL_CONTINUE)
2499 return rc;
2500 addr += now;
2501 val += now;
2502 bytes -= now;
2503 }
2504 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2505}
2506EXPORT_SYMBOL_GPL(emulator_write_emulated);
2507
2508static int emulator_cmpxchg_emulated(unsigned long addr,
2509 const void *old,
2510 const void *new,
2511 unsigned int bytes,
2512 struct kvm_vcpu *vcpu)
2513{
2514 static int reported;
2515
2516 if (!reported) {
2517 reported = 1;
2518 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2519 }
2bacc55c
MT		 2520#ifndef CONFIG_X86_64
2521 /* guests cmpxchg8b have to be emulated atomically */
2522 if (bytes == 8) {
10589a46 2523 gpa_t gpa;
2bacc55c 2524 struct page *page;
c0b49b0d 2525 char *kaddr;
2bacc55c
MT		 2526 u64 val;
2527
10589a46
MT		 2528 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2529
2bacc55c
MT		 2530 if (gpa == UNMAPPED_GVA ||
2531 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2532 goto emul_write;
2533
2534 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2535 goto emul_write;
2536
2537 val = *(u64 *)new;
72dc67a6 2538
2bacc55c 2539 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2540
c0b49b0d
AM		 2541 kaddr = kmap_atomic(page, KM_USER0);
2542 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2543 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2544 kvm_release_page_dirty(page);
2545 }
3200f405 2546emul_write:
2bacc55c
MT		 2547#endif
2548
bbd9b64e
CO		 2549 return emulator_write_emulated(addr, new, bytes, vcpu);
2550}
2551
2552static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2553{
2554 return kvm_x86_ops->get_segment_base(vcpu, seg);
2555}
2556
2557int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2558{
a7052897 2559 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2560 return X86EMUL_CONTINUE;
2561}
2562
2563int emulate_clts(struct kvm_vcpu *vcpu)
2564{
54e445ca 2565 KVMTRACE_0D(CLTS, vcpu, handler);
ad312c7c 2566 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2567 return X86EMUL_CONTINUE;
2568}
2569
2570int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2571{
2572 struct kvm_vcpu *vcpu = ctxt->vcpu;
2573
2574 switch (dr) {
2575 case 0 ... 3:
2576 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2577 return X86EMUL_CONTINUE;
2578 default:
b8688d51 2579 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2580 return X86EMUL_UNHANDLEABLE;
2581 }
2582}
2583
2584int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2585{
2586 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2587 int exception;
2588
2589 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2590 if (exception) {
2591 /* FIXME: better handling */
2592 return X86EMUL_UNHANDLEABLE;
2593 }
2594 return X86EMUL_CONTINUE;
2595}
2596
2597void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2598{
bbd9b64e 2599 u8 opcodes[4];
5fdbf976 2600 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2601 unsigned long rip_linear;
2602
f76c710d 2603 if (!printk_ratelimit())
bbd9b64e
CO		 2604 return;
2605
25be4608
GC		 2606 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2607
77c2002e 2608 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2609
2610 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2611 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2612}
2613EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2614
14af3f3c 2615static struct x86_emulate_ops emulate_ops = {
77c2002e 2616 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2617 .read_emulated = emulator_read_emulated,
2618 .write_emulated = emulator_write_emulated,
2619 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2620};
2621
5fdbf976
MT		 2622static void cache_all_regs(struct kvm_vcpu *vcpu)
2623{
2624 kvm_register_read(vcpu, VCPU_REGS_RAX);
2625 kvm_register_read(vcpu, VCPU_REGS_RSP);
2626 kvm_register_read(vcpu, VCPU_REGS_RIP);
2627 vcpu->arch.regs_dirty = ~0;
2628}
2629
bbd9b64e
CO		 2630int emulate_instruction(struct kvm_vcpu *vcpu,
2631 struct kvm_run *run,
2632 unsigned long cr2,
2633 u16 error_code,
571008da 2634 int emulation_type)
bbd9b64e 2635{
310b5d30 2636 int r, shadow_mask;
571008da 2637 struct decode_cache *c;
bbd9b64e 2638
26eef70c 2639 kvm_clear_exception_queue(vcpu);
ad312c7c 2640 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2641 /*
2642 * TODO: fix x86_emulate.c to use guest_read/write_register
2643 * instead of direct ->regs accesses, can save hundred cycles
2644 * on Intel for instructions that don't read/change RSP, for
2645 * for example.
2646 */
2647 cache_all_regs(vcpu);
bbd9b64e
CO		 2648
2649 vcpu->mmio_is_write = 0;
ad312c7c 2650 vcpu->arch.pio.string = 0;
bbd9b64e 2651
571008da 2652 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2653 int cs_db, cs_l;
2654 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2655
ad312c7c
ZX		 2656 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2657 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2658 vcpu->arch.emulate_ctxt.mode =
2659 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2660 ? X86EMUL_MODE_REAL : cs_l
2661 ? X86EMUL_MODE_PROT64 : cs_db
2662 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2663
ad312c7c 2664 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da
SY		 2665
2666 /* Reject the instructions other than VMCALL/VMMCALL when
2667 * try to emulate invalid opcode */
2668 c = &vcpu->arch.emulate_ctxt.decode;
2669 if ((emulation_type & EMULTYPE_TRAP_UD) &&
2670 (!(c->twobyte && c->b == 0x01 &&
2671 (c->modrm_reg == 0 || c->modrm_reg == 3) &&
2672 c->modrm_mod == 3 && c->modrm_rm == 1)))
2673 return EMULATE_FAIL;
2674
f2b5756b 2675 ++vcpu->stat.insn_emulation;
bbd9b64e 2676 if (r) {
f2b5756b 2677 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2678 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2679 return EMULATE_DONE;
2680 return EMULATE_FAIL;
2681 }
2682 }
2683
ba8afb6b
GN		 2684 if (emulation_type & EMULTYPE_SKIP) {
2685 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2686 return EMULATE_DONE;
2687 }
2688
ad312c7c 2689 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2690 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2691
2692 if (r == 0)
2693 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2694
ad312c7c 2695 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2696 return EMULATE_DO_MMIO;
2697
2698 if ((r || vcpu->mmio_is_write) && run) {
2699 run->exit_reason = KVM_EXIT_MMIO;
2700 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2701 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2702 run->mmio.len = vcpu->mmio_size;
2703 run->mmio.is_write = vcpu->mmio_is_write;
2704 }
2705
2706 if (r) {
2707 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2708 return EMULATE_DONE;
2709 if (!vcpu->mmio_needed) {
2710 kvm_report_emulation_failure(vcpu, "mmio");
2711 return EMULATE_FAIL;
2712 }
2713 return EMULATE_DO_MMIO;
2714 }
2715
ad312c7c 2716 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2717
2718 if (vcpu->mmio_is_write) {
2719 vcpu->mmio_needed = 0;
2720 return EMULATE_DO_MMIO;
2721 }
2722
2723 return EMULATE_DONE;
2724}
2725EXPORT_SYMBOL_GPL(emulate_instruction);
2726
de7d789a
CO		 2727static int pio_copy_data(struct kvm_vcpu *vcpu)
2728{
ad312c7c 2729 void *p = vcpu->arch.pio_data;
0f346074 2730 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2731 unsigned bytes;
0f346074 2732 int ret;
de7d789a 2733
ad312c7c
ZX		 2734 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2735 if (vcpu->arch.pio.in)
0f346074 2736 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2737 else
0f346074
IE		 2738 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2739 return ret;
de7d789a
CO		 2740}
2741
2742int complete_pio(struct kvm_vcpu *vcpu)
2743{
ad312c7c 2744 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2745 long delta;
2746 int r;
5fdbf976 2747 unsigned long val;
de7d789a
CO		 2748
2749 if (!io->string) {
5fdbf976
MT		 2750 if (io->in) {
2751 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2752 memcpy(&val, vcpu->arch.pio_data, io->size);
2753 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2754 }
de7d789a
CO		 2755 } else {
2756 if (io->in) {
2757 r = pio_copy_data(vcpu);
5fdbf976 2758 if (r)
de7d789a 2759 return r;
de7d789a
CO		 2760 }
2761
2762 delta = 1;
2763 if (io->rep) {
2764 delta *= io->cur_count;
2765 /*
2766 * The size of the register should really depend on
2767 * current address size.
2768 */
5fdbf976
MT		 2769 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2770 val -= delta;
2771 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2772 }
2773 if (io->down)
2774 delta = -delta;
2775 delta *= io->size;
5fdbf976
MT		 2776 if (io->in) {
2777 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2778 val += delta;
2779 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2780 } else {
2781 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2782 val += delta;
2783 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2784 }
de7d789a
CO		 2785 }
2786
de7d789a
CO		 2787 io->count -= io->cur_count;
2788 io->cur_count = 0;
2789
2790 return 0;
2791}
2792
2793static void kernel_pio(struct kvm_io_device *pio_dev,
2794 struct kvm_vcpu *vcpu,
2795 void *pd)
2796{
2797 /* TODO: String I/O for in kernel device */
2798
ad312c7c
ZX		 2799 if (vcpu->arch.pio.in)
2800 kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
2801 vcpu->arch.pio.size,
de7d789a
CO		 2802 pd);
2803 else
ad312c7c
ZX		 2804 kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
2805 vcpu->arch.pio.size,
de7d789a 2806 pd);
de7d789a
CO		 2807}
2808
2809static void pio_string_write(struct kvm_io_device *pio_dev,
2810 struct kvm_vcpu *vcpu)
2811{
ad312c7c
ZX		 2812 struct kvm_pio_request *io = &vcpu->arch.pio;
2813 void *pd = vcpu->arch.pio_data;
de7d789a
CO		 2814 int i;
2815
de7d789a
CO		 2816 for (i = 0; i < io->cur_count; i++) {
2817 kvm_iodevice_write(pio_dev, io->port,
2818 io->size,
2819 pd);
2820 pd += io->size;
2821 }
de7d789a
CO		 2822}
2823
2824static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
92760499
LV		 2825 gpa_t addr, int len,
2826 int is_write)
de7d789a 2827{
92760499 2828 return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
de7d789a
CO		 2829}
2830
2831int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2832 int size, unsigned port)
2833{
2834 struct kvm_io_device *pio_dev;
5fdbf976 2835 unsigned long val;
de7d789a
CO		 2836
2837 vcpu->run->exit_reason = KVM_EXIT_IO;
2838 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2839 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2840 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2841 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2842 vcpu->run->io.port = vcpu->arch.pio.port = port;
2843 vcpu->arch.pio.in = in;
2844 vcpu->arch.pio.string = 0;
2845 vcpu->arch.pio.down = 0;
ad312c7c 2846 vcpu->arch.pio.rep = 0;
de7d789a 2847
2714d1d3
FEL		 2848 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2849 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2850 handler);
2851 else
2852 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2853 handler);
2854
5fdbf976
MT		 2855 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2856 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2857
fa40a821 2858 mutex_lock(&vcpu->kvm->lock);
92760499 2859 pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
fa40a821 2860 mutex_unlock(&vcpu->kvm->lock);
de7d789a 2861 if (pio_dev) {
ad312c7c 2862 kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
de7d789a
CO		 2863 complete_pio(vcpu);
2864 return 1;
2865 }
2866 return 0;
2867}
2868EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2869
2870int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2871 int size, unsigned long count, int down,
2872 gva_t address, int rep, unsigned port)
2873{
2874 unsigned now, in_page;
0f346074 2875 int ret = 0;
de7d789a
CO		 2876 struct kvm_io_device *pio_dev;
2877
2878 vcpu->run->exit_reason = KVM_EXIT_IO;
2879 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2880 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2881 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2882 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2883 vcpu->run->io.port = vcpu->arch.pio.port = port;
2884 vcpu->arch.pio.in = in;
2885 vcpu->arch.pio.string = 1;
2886 vcpu->arch.pio.down = down;
ad312c7c 2887 vcpu->arch.pio.rep = rep;
de7d789a 2888
2714d1d3
FEL		 2889 if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
2890 KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
2891 handler);
2892 else
2893 KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
2894 handler);
2895
de7d789a
CO		 2896 if (!count) {
2897 kvm_x86_ops->skip_emulated_instruction(vcpu);
2898 return 1;
2899 }
2900
2901 if (!down)
2902 in_page = PAGE_SIZE - offset_in_page(address);
2903 else
2904 in_page = offset_in_page(address) + size;
2905 now = min(count, (unsigned long)in_page / size);
0f346074 2906 if (!now)
de7d789a 2907 now = 1;
de7d789a
CO		 2908 if (down) {
2909 /*
2910 * String I/O in reverse. Yuck. Kill the guest, fix later.
2911 */
2912 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2913 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2914 return 1;
2915 }
2916 vcpu->run->io.count = now;
ad312c7c 2917 vcpu->arch.pio.cur_count = now;
de7d789a 2918
ad312c7c 2919 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2920 kvm_x86_ops->skip_emulated_instruction(vcpu);
2921
0f346074 2922 vcpu->arch.pio.guest_gva = address;
de7d789a 2923
fa40a821 2924 mutex_lock(&vcpu->kvm->lock);
92760499
LV		 2925 pio_dev = vcpu_find_pio_dev(vcpu, port,
2926 vcpu->arch.pio.cur_count,
2927 !vcpu->arch.pio.in);
fa40a821
MT		 2928 mutex_unlock(&vcpu->kvm->lock);
2929
ad312c7c 2930 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2931 /* string PIO write */
2932 ret = pio_copy_data(vcpu);
0f346074
IE		 2933 if (ret == X86EMUL_PROPAGATE_FAULT) {
2934 kvm_inject_gp(vcpu, 0);
2935 return 1;
2936 }
2937 if (ret == 0 && pio_dev) {
de7d789a
CO		 2938 pio_string_write(pio_dev, vcpu);
2939 complete_pio(vcpu);
ad312c7c 2940 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2941 ret = 1;
2942 }
2943 } else if (pio_dev)
2944 pr_unimpl(vcpu, "no string pio read support yet, "
2945 "port %x size %d count %ld\n",
2946 port, size, count);
2947
2948 return ret;
2949}
2950EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2951
c8076604
GH		 2952static void bounce_off(void *info)
2953{
2954 /* nothing */
2955}
2956
2957static unsigned int ref_freq;
2958static unsigned long tsc_khz_ref;
2959
2960static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
2961 void *data)
2962{
2963 struct cpufreq_freqs *freq = data;
2964 struct kvm *kvm;
2965 struct kvm_vcpu *vcpu;
2966 int i, send_ipi = 0;
2967
2968 if (!ref_freq)
2969 ref_freq = freq->old;
2970
2971 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
2972 return 0;
2973 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
2974 return 0;
2975 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
2976
2977 spin_lock(&kvm_lock);
2978 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 2979 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 2980 if (vcpu->cpu != freq->cpu)
2981 continue;
2982 if (!kvm_request_guest_time_update(vcpu))
2983 continue;
2984 if (vcpu->cpu != smp_processor_id())
2985 send_ipi++;
2986 }
2987 }
2988 spin_unlock(&kvm_lock);
2989
2990 if (freq->old < freq->new && send_ipi) {
2991 /*
2992 * We upscale the frequency. Must make the guest
2993 * doesn't see old kvmclock values while running with
2994 * the new frequency, otherwise we risk the guest sees
2995 * time go backwards.
2996 *
2997 * In case we update the frequency for another cpu
2998 * (which might be in guest context) send an interrupt
2999 * to kick the cpu out of guest context. Next time
3000 * guest context is entered kvmclock will be updated,
3001 * so the guest will not see stale values.
3002 */
3003 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3004 }
3005 return 0;
3006}
3007
3008static struct notifier_block kvmclock_cpufreq_notifier_block = {
3009 .notifier_call = kvmclock_cpufreq_notifier
3010};
3011
f8c16bba 3012int kvm_arch_init(void *opaque)
043405e1 3013{
c8076604 3014 int r, cpu;
f8c16bba
ZX		 3015 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3016
f8c16bba
ZX		 3017 if (kvm_x86_ops) {
3018 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3019 r = -EEXIST;
3020 goto out;
f8c16bba
ZX		 3021 }
3022
3023 if (!ops->cpu_has_kvm_support()) {
3024 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3025 r = -EOPNOTSUPP;
3026 goto out;
f8c16bba
ZX		 3027 }
3028 if (ops->disabled_by_bios()) {
3029 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3030 r = -EOPNOTSUPP;
3031 goto out;
f8c16bba
ZX		 3032 }
3033
97db56ce
AK		 3034 r = kvm_mmu_module_init();
3035 if (r)
3036 goto out;
3037
3038 kvm_init_msr_list();
3039
f8c16bba 3040 kvm_x86_ops = ops;
56c6d28a 3041 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3042 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3043 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3044 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604
GH		 3045
3046 for_each_possible_cpu(cpu)
3047 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3048 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3049 tsc_khz_ref = tsc_khz;
3050 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3051 CPUFREQ_TRANSITION_NOTIFIER);
3052 }
3053
f8c16bba 3054 return 0;
56c6d28a
ZX		 3055
3056out:
56c6d28a 3057 return r;
043405e1 3058}
8776e519 3059
f8c16bba
ZX		 3060void kvm_arch_exit(void)
3061{
888d256e
JK		 3062 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3063 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3064 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3065 kvm_x86_ops = NULL;
56c6d28a
ZX		 3066 kvm_mmu_module_exit();
3067}
f8c16bba 3068
8776e519
HB		 3069int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3070{
3071 ++vcpu->stat.halt_exits;
2714d1d3 3072 KVMTRACE_0D(HLT, vcpu, handler);
8776e519 3073 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3074 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3075 return 1;
3076 } else {
3077 vcpu->run->exit_reason = KVM_EXIT_HLT;
3078 return 0;
3079 }
3080}
3081EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3082
2f333bcb
MT		 3083static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3084 unsigned long a1)
3085{
3086 if (is_long_mode(vcpu))
3087 return a0;
3088 else
3089 return a0 | ((gpa_t)a1 << 32);
3090}
3091
8776e519
HB		 3092int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3093{
3094 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3095 int r = 1;
8776e519 3096
5fdbf976
MT		 3097 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3098 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3099 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3100 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3101 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3102
2714d1d3
FEL		 3103 KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
3104
8776e519
HB		 3105 if (!is_long_mode(vcpu)) {
3106 nr &= 0xFFFFFFFF;
3107 a0 &= 0xFFFFFFFF;
3108 a1 &= 0xFFFFFFFF;
3109 a2 &= 0xFFFFFFFF;
3110 a3 &= 0xFFFFFFFF;
3111 }
3112
3113 switch (nr) {
b93463aa
AK		 3114 case KVM_HC_VAPIC_POLL_IRQ:
3115 ret = 0;
3116 break;
2f333bcb
MT		 3117 case KVM_HC_MMU_OP:
3118 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3119 break;
8776e519
HB		 3120 default:
3121 ret = -KVM_ENOSYS;
3122 break;
3123 }
5fdbf976 3124 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3125 ++vcpu->stat.hypercalls;
2f333bcb 3126 return r;
8776e519
HB		 3127}
3128EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3129
3130int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3131{
3132 char instruction[3];
3133 int ret = 0;
5fdbf976 3134 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3135
8776e519
HB		 3136
3137 /*
3138 * Blow out the MMU to ensure that no other VCPU has an active mapping
3139 * to ensure that the updated hypercall appears atomically across all
3140 * VCPUs.
3141 */
3142 kvm_mmu_zap_all(vcpu->kvm);
3143
8776e519 3144 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3145 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3146 != X86EMUL_CONTINUE)
3147 ret = -EFAULT;
3148
8776e519
HB		 3149 return ret;
3150}
3151
3152static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3153{
3154 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3155}
3156
3157void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3158{
3159 struct descriptor_table dt = { limit, base };
3160
3161 kvm_x86_ops->set_gdt(vcpu, &dt);
3162}
3163
3164void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3165{
3166 struct descriptor_table dt = { limit, base };
3167
3168 kvm_x86_ops->set_idt(vcpu, &dt);
3169}
3170
3171void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3172 unsigned long *rflags)
3173{
2d3ad1f4 3174 kvm_lmsw(vcpu, msw);
8776e519
HB		 3175 *rflags = kvm_x86_ops->get_rflags(vcpu);
3176}
3177
3178unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3179{
54e445ca
JR		 3180 unsigned long value;
3181
8776e519
HB		 3182 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3183 switch (cr) {
3184 case 0:
54e445ca
JR		 3185 value = vcpu->arch.cr0;
3186 break;
8776e519 3187 case 2:
54e445ca
JR		 3188 value = vcpu->arch.cr2;
3189 break;
8776e519 3190 case 3:
54e445ca
JR		 3191 value = vcpu->arch.cr3;
3192 break;
8776e519 3193 case 4:
54e445ca
JR		 3194 value = vcpu->arch.cr4;
3195 break;
152ff9be 3196 case 8:
54e445ca
JR		 3197 value = kvm_get_cr8(vcpu);
3198 break;
8776e519 3199 default:
b8688d51 3200 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3201 return 0;
3202 }
54e445ca
JR		 3203 KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
3204 (u32)((u64)value >> 32), handler);
3205
3206 return value;
8776e519
HB		 3207}
3208
3209void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3210 unsigned long *rflags)
3211{
54e445ca
JR		 3212 KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
3213 (u32)((u64)val >> 32), handler);
3214
8776e519
HB		 3215 switch (cr) {
3216 case 0:
2d3ad1f4 3217 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 3218 *rflags = kvm_x86_ops->get_rflags(vcpu);
3219 break;
3220 case 2:
ad312c7c 3221 vcpu->arch.cr2 = val;
8776e519
HB		 3222 break;
3223 case 3:
2d3ad1f4 3224 kvm_set_cr3(vcpu, val);
8776e519
HB		 3225 break;
3226 case 4:
2d3ad1f4 3227 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3228 break;
152ff9be 3229 case 8:
2d3ad1f4 3230 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3231 break;
8776e519 3232 default:
b8688d51 3233 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3234 }
3235}
3236
07716717
DK		 3237static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3238{
ad312c7c
ZX		 3239 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3240 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3241
3242 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3243 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3244 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3245 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3246 if (ej->function == e->function) {
3247 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3248 return j;
3249 }
3250 }
3251 return 0; /* silence gcc, even though control never reaches here */
3252}
3253
3254/* find an entry with matching function, matching index (if needed), and that
3255 * should be read next (if it's stateful) */
3256static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3257 u32 function, u32 index)
3258{
3259 if (e->function != function)
3260 return 0;
3261 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3262 return 0;
3263 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3264 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3265 return 0;
3266 return 1;
3267}
3268
d8017474
AG		 3269struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3270 u32 function, u32 index)
8776e519
HB		 3271{
3272 int i;
d8017474 3273 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3274
ad312c7c 3275 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3276 struct kvm_cpuid_entry2 *e;
3277
ad312c7c 3278 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3279 if (is_matching_cpuid_entry(e, function, index)) {
3280 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3281 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3282 best = e;
3283 break;
3284 }
3285 /*
3286 * Both basic or both extended?
3287 */
3288 if (((e->function ^ function) & 0x80000000) == 0)
3289 if (!best || e->function > best->function)
3290 best = e;
3291 }
d8017474
AG		 3292 return best;
3293}
3294
82725b20
DE		 3295int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3296{
3297 struct kvm_cpuid_entry2 *best;
3298
3299 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3300 if (best)
3301 return best->eax & 0xff;
3302 return 36;
3303}
3304
d8017474
AG		 3305void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3306{
3307 u32 function, index;
3308 struct kvm_cpuid_entry2 *best;
3309
3310 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3311 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3312 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3313 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3314 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3315 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3316 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3317 if (best) {
5fdbf976
MT		 3318 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3319 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3320 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3321 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3322 }
8776e519 3323 kvm_x86_ops->skip_emulated_instruction(vcpu);
2714d1d3 3324 KVMTRACE_5D(CPUID, vcpu, function,
5fdbf976
MT		 3325 (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
3326 (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
3327 (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
3328 (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
8776e519
HB		 3329}
3330EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3331
b6c7a5dc
HB		 3332/*
3333 * Check if userspace requested an interrupt window, and that the
3334 * interrupt window is open.
3335 *
3336 * No need to exit to userspace if we already have an interrupt queued.
3337 */
3338static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3339 struct kvm_run *kvm_run)
3340{
8061823a 3341 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
b6c7a5dc 3342 kvm_run->request_interrupt_window &&
5df56646 3343 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3344}
3345
3346static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3347 struct kvm_run *kvm_run)
3348{
3349 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3350 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3351 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3352 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3353 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3354 else
b6c7a5dc 3355 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3356 kvm_arch_interrupt_allowed(vcpu) &&
3357 !kvm_cpu_has_interrupt(vcpu) &&
3358 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3359}
3360
b93463aa
AK		 3361static void vapic_enter(struct kvm_vcpu *vcpu)
3362{
3363 struct kvm_lapic *apic = vcpu->arch.apic;
3364 struct page *page;
3365
3366 if (!apic || !apic->vapic_addr)
3367 return;
3368
3369 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3370
3371 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3372}
3373
3374static void vapic_exit(struct kvm_vcpu *vcpu)
3375{
3376 struct kvm_lapic *apic = vcpu->arch.apic;
3377
3378 if (!apic || !apic->vapic_addr)
3379 return;
3380
f8b78fa3 3381 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3382 kvm_release_page_dirty(apic->vapic_page);
3383 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3384 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3385}
3386
95ba8273
GN		 3387static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3388{
3389 int max_irr, tpr;
3390
3391 if (!kvm_x86_ops->update_cr8_intercept)
3392 return;
3393
8db3baa2
GN		 3394 if (!vcpu->arch.apic->vapic_addr)
3395 max_irr = kvm_lapic_find_highest_irr(vcpu);
3396 else
3397 max_irr = -1;
95ba8273
GN		 3398
3399 if (max_irr != -1)
3400 max_irr >>= 4;
3401
3402 tpr = kvm_lapic_get_cr8(vcpu);
3403
3404 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3405}
3406
6a8b1d13 3407static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
95ba8273
GN		 3408{
3409 /* try to reinject previous events if any */
3410 if (vcpu->arch.nmi_injected) {
3411 kvm_x86_ops->set_nmi(vcpu);
3412 return;
3413 }
3414
3415 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3416 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3417 return;
3418 }
3419
3420 /* try to inject new event if pending */
3421 if (vcpu->arch.nmi_pending) {
3422 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3423 vcpu->arch.nmi_pending = false;
3424 vcpu->arch.nmi_injected = true;
3425 kvm_x86_ops->set_nmi(vcpu);
3426 }
3427 } else if (kvm_cpu_has_interrupt(vcpu)) {
3428 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3429 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3430 false);
3431 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3432 }
3433 }
3434}
3435
d7690175 3436static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3437{
3438 int r;
6a8b1d13
GN		 3439 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3440 kvm_run->request_interrupt_window;
b6c7a5dc 3441
2e53d63a
MT		 3442 if (vcpu->requests)
3443 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3444 kvm_mmu_unload(vcpu);
3445
b6c7a5dc
HB		 3446 r = kvm_mmu_reload(vcpu);
3447 if (unlikely(r))
3448 goto out;
3449
2f52d58c
AK		 3450 if (vcpu->requests) {
3451 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3452 __kvm_migrate_timers(vcpu);
c8076604
GH		 3453 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3454 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3455 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3456 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3457 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3458 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3459 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3460 &vcpu->requests)) {
3461 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3462 r = 0;
3463 goto out;
3464 }
71c4dfaf
JR		 3465 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3466 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3467 r = 0;
3468 goto out;
3469 }
2f52d58c 3470 }
b93463aa 3471
b6c7a5dc
HB		 3472 preempt_disable();
3473
3474 kvm_x86_ops->prepare_guest_switch(vcpu);
3475 kvm_load_guest_fpu(vcpu);
3476
3477 local_irq_disable();
3478
32f88400
MT		 3479 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3480 smp_mb__after_clear_bit();
3481
d7690175 3482 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3483 local_irq_enable();
3484 preempt_enable();
3485 r = 1;
3486 goto out;
3487 }
3488
ad312c7c 3489 if (vcpu->arch.exception.pending)
298101da 3490 __queue_exception(vcpu);
eb9774f0 3491 else
95ba8273 3492 inject_pending_irq(vcpu, kvm_run);
b6c7a5dc 3493
6a8b1d13
GN		 3494 /* enable NMI/IRQ window open exits if needed */
3495 if (vcpu->arch.nmi_pending)
3496 kvm_x86_ops->enable_nmi_window(vcpu);
3497 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3498 kvm_x86_ops->enable_irq_window(vcpu);
3499
95ba8273 3500 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3501 update_cr8_intercept(vcpu);
3502 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3503 }
b93463aa 3504
3200f405
MT		 3505 up_read(&vcpu->kvm->slots_lock);
3506
b6c7a5dc
HB		 3507 kvm_guest_enter();
3508
42dbaa5a
JK		 3509 get_debugreg(vcpu->arch.host_dr6, 6);
3510 get_debugreg(vcpu->arch.host_dr7, 7);
3511 if (unlikely(vcpu->arch.switch_db_regs)) {
3512 get_debugreg(vcpu->arch.host_db[0], 0);
3513 get_debugreg(vcpu->arch.host_db[1], 1);
3514 get_debugreg(vcpu->arch.host_db[2], 2);
3515 get_debugreg(vcpu->arch.host_db[3], 3);
3516
3517 set_debugreg(0, 7);
3518 set_debugreg(vcpu->arch.eff_db[0], 0);
3519 set_debugreg(vcpu->arch.eff_db[1], 1);
3520 set_debugreg(vcpu->arch.eff_db[2], 2);
3521 set_debugreg(vcpu->arch.eff_db[3], 3);
3522 }
b6c7a5dc 3523
2714d1d3 3524 KVMTRACE_0D(VMENTRY, vcpu, entryexit);
b6c7a5dc
HB		 3525 kvm_x86_ops->run(vcpu, kvm_run);
3526
42dbaa5a
JK		 3527 if (unlikely(vcpu->arch.switch_db_regs)) {
3528 set_debugreg(0, 7);
3529 set_debugreg(vcpu->arch.host_db[0], 0);
3530 set_debugreg(vcpu->arch.host_db[1], 1);
3531 set_debugreg(vcpu->arch.host_db[2], 2);
3532 set_debugreg(vcpu->arch.host_db[3], 3);
3533 }
3534 set_debugreg(vcpu->arch.host_dr6, 6);
3535 set_debugreg(vcpu->arch.host_dr7, 7);
3536
32f88400 3537 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3538 local_irq_enable();
3539
3540 ++vcpu->stat.exits;
3541
3542 /*
3543 * We must have an instruction between local_irq_enable() and
3544 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3545 * the interrupt shadow. The stat.exits increment will do nicely.
3546 * But we need to prevent reordering, hence this barrier():
3547 */
3548 barrier();
3549
3550 kvm_guest_exit();
3551
3552 preempt_enable();
3553
3200f405
MT		 3554 down_read(&vcpu->kvm->slots_lock);
3555
b6c7a5dc
HB		 3556 /*
3557 * Profile KVM exit RIPs:
3558 */
3559 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3560 unsigned long rip = kvm_rip_read(vcpu);
3561 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3562 }
3563
298101da 3564
b93463aa
AK		 3565 kvm_lapic_sync_from_vapic(vcpu);
3566
b6c7a5dc 3567 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3568out:
3569 return r;
3570}
b6c7a5dc 3571
09cec754 3572
d7690175
MT		 3573static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3574{
3575 int r;
3576
3577 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3578 pr_debug("vcpu %d received sipi with vector # %x\n",
3579 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3580 kvm_lapic_reset(vcpu);
5f179287 3581 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3582 if (r)
3583 return r;
3584 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3585 }
3586
d7690175
MT		 3587 down_read(&vcpu->kvm->slots_lock);
3588 vapic_enter(vcpu);
3589
3590 r = 1;
3591 while (r > 0) {
af2152f5 3592 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3593 r = vcpu_enter_guest(vcpu, kvm_run);
3594 else {
3595 up_read(&vcpu->kvm->slots_lock);
3596 kvm_vcpu_block(vcpu);
3597 down_read(&vcpu->kvm->slots_lock);
3598 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3599 {
3600 switch(vcpu->arch.mp_state) {
3601 case KVM_MP_STATE_HALTED:
d7690175 3602 vcpu->arch.mp_state =
09cec754
GN		 3603 KVM_MP_STATE_RUNNABLE;
3604 case KVM_MP_STATE_RUNNABLE:
3605 break;
3606 case KVM_MP_STATE_SIPI_RECEIVED:
3607 default:
3608 r = -EINTR;
3609 break;
3610 }
3611 }
d7690175
MT		 3612 }
3613
09cec754
GN		 3614 if (r <= 0)
3615 break;
3616
3617 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3618 if (kvm_cpu_has_pending_timer(vcpu))
3619 kvm_inject_pending_timer_irqs(vcpu);
3620
3621 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3622 r = -EINTR;
3623 kvm_run->exit_reason = KVM_EXIT_INTR;
3624 ++vcpu->stat.request_irq_exits;
3625 }
3626 if (signal_pending(current)) {
3627 r = -EINTR;
3628 kvm_run->exit_reason = KVM_EXIT_INTR;
3629 ++vcpu->stat.signal_exits;
3630 }
3631 if (need_resched()) {
3632 up_read(&vcpu->kvm->slots_lock);
3633 kvm_resched(vcpu);
3634 down_read(&vcpu->kvm->slots_lock);
d7690175 3635 }
b6c7a5dc
HB		 3636 }
3637
d7690175 3638 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3639 post_kvm_run_save(vcpu, kvm_run);
3640
b93463aa
AK		 3641 vapic_exit(vcpu);
3642
b6c7a5dc
HB		 3643 return r;
3644}
3645
3646int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3647{
3648 int r;
3649 sigset_t sigsaved;
3650
3651 vcpu_load(vcpu);
3652
ac9f6dc0
AK		 3653 if (vcpu->sigset_active)
3654 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3655
a4535290 3656 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3657 kvm_vcpu_block(vcpu);
d7690175 3658 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3659 r = -EAGAIN;
3660 goto out;
b6c7a5dc
HB		 3661 }
3662
b6c7a5dc
HB		 3663 /* re-sync apic's tpr */
3664 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3665 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3666
ad312c7c 3667 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3668 r = complete_pio(vcpu);
3669 if (r)
3670 goto out;
3671 }
3672#if CONFIG_HAS_IOMEM
3673 if (vcpu->mmio_needed) {
3674 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3675 vcpu->mmio_read_completed = 1;
3676 vcpu->mmio_needed = 0;
3200f405
MT		 3677
3678 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3679 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3680 vcpu->arch.mmio_fault_cr2, 0,
3681 EMULTYPE_NO_DECODE);
3200f405 3682 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3683 if (r == EMULATE_DO_MMIO) {
3684 /*
3685 * Read-modify-write. Back to userspace.
3686 */
3687 r = 0;
3688 goto out;
3689 }
3690 }
3691#endif
5fdbf976
MT		 3692 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3693 kvm_register_write(vcpu, VCPU_REGS_RAX,
3694 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3695
3696 r = __vcpu_run(vcpu, kvm_run);
3697
3698out:
3699 if (vcpu->sigset_active)
3700 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3701
3702 vcpu_put(vcpu);
3703 return r;
3704}
3705
3706int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3707{
3708 vcpu_load(vcpu);
3709
5fdbf976
MT		 3710 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3711 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3712 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3713 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3714 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3715 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3716 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3717 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3718#ifdef CONFIG_X86_64
5fdbf976
MT		 3719 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3720 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3721 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3722 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3723 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3724 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3725 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3726 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3727#endif
3728
5fdbf976 3729 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3730 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3731
3732 /*
3733 * Don't leak debug flags in case they were set for guest debugging
3734 */
d0bfb940 3735 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3736 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3737
3738 vcpu_put(vcpu);
3739
3740 return 0;
3741}
3742
3743int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3744{
3745 vcpu_load(vcpu);
3746
5fdbf976
MT		 3747 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3748 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3749 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3750 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3751 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3752 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3753 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3754 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3755#ifdef CONFIG_X86_64
5fdbf976
MT		 3756 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3757 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3758 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3759 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3760 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3761 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3762 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3763 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3764
b6c7a5dc
HB		 3765#endif
3766
5fdbf976 3767 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3768 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3769
b6c7a5dc 3770
b4f14abd
JK		 3771 vcpu->arch.exception.pending = false;
3772
b6c7a5dc
HB		 3773 vcpu_put(vcpu);
3774
3775 return 0;
3776}
3777
3e6e0aab
GT		 3778void kvm_get_segment(struct kvm_vcpu *vcpu,
3779 struct kvm_segment *var, int seg)
b6c7a5dc 3780{
14af3f3c 3781 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3782}
3783
3784void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3785{
3786 struct kvm_segment cs;
3787
3e6e0aab 3788 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3789 *db = cs.db;
3790 *l = cs.l;
3791}
3792EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3793
3794int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3795 struct kvm_sregs *sregs)
3796{
3797 struct descriptor_table dt;
b6c7a5dc
HB		 3798
3799 vcpu_load(vcpu);
3800
3e6e0aab
GT		 3801 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3802 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3803 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3804 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3805 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3806 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3807
3e6e0aab
GT		 3808 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3809 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3810
3811 kvm_x86_ops->get_idt(vcpu, &dt);
3812 sregs->idt.limit = dt.limit;
3813 sregs->idt.base = dt.base;
3814 kvm_x86_ops->get_gdt(vcpu, &dt);
3815 sregs->gdt.limit = dt.limit;
3816 sregs->gdt.base = dt.base;
3817
3818 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3819 sregs->cr0 = vcpu->arch.cr0;
3820 sregs->cr2 = vcpu->arch.cr2;
3821 sregs->cr3 = vcpu->arch.cr3;
3822 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3823 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3824 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3825 sregs->apic_base = kvm_get_apic_base(vcpu);
3826
923c61bb 3827 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3828
36752c9b 3829 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3830 set_bit(vcpu->arch.interrupt.nr,
3831 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3832
b6c7a5dc
HB		 3833 vcpu_put(vcpu);
3834
3835 return 0;
3836}
3837
62d9f0db
MT		 3838int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3839 struct kvm_mp_state *mp_state)
3840{
3841 vcpu_load(vcpu);
3842 mp_state->mp_state = vcpu->arch.mp_state;
3843 vcpu_put(vcpu);
3844 return 0;
3845}
3846
3847int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3848 struct kvm_mp_state *mp_state)
3849{
3850 vcpu_load(vcpu);
3851 vcpu->arch.mp_state = mp_state->mp_state;
3852 vcpu_put(vcpu);
3853 return 0;
3854}
3855
3e6e0aab 3856static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3857 struct kvm_segment *var, int seg)
3858{
14af3f3c 3859 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3860}
3861
37817f29
IE		 3862static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3863 struct kvm_segment *kvm_desct)
3864{
3865 kvm_desct->base = seg_desc->base0;
3866 kvm_desct->base |= seg_desc->base1 << 16;
3867 kvm_desct->base |= seg_desc->base2 << 24;
3868 kvm_desct->limit = seg_desc->limit0;
3869 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3870 if (seg_desc->g) {
3871 kvm_desct->limit <<= 12;
3872 kvm_desct->limit |= 0xfff;
3873 }
37817f29
IE		 3874 kvm_desct->selector = selector;
3875 kvm_desct->type = seg_desc->type;
3876 kvm_desct->present = seg_desc->p;
3877 kvm_desct->dpl = seg_desc->dpl;
3878 kvm_desct->db = seg_desc->d;
3879 kvm_desct->s = seg_desc->s;
3880 kvm_desct->l = seg_desc->l;
3881 kvm_desct->g = seg_desc->g;
3882 kvm_desct->avl = seg_desc->avl;
3883 if (!selector)
3884 kvm_desct->unusable = 1;
3885 else
3886 kvm_desct->unusable = 0;
3887 kvm_desct->padding = 0;
3888}
3889
b8222ad2
AS		 3890static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3891 u16 selector,
3892 struct descriptor_table *dtable)
37817f29
IE		 3893{
3894 if (selector & 1 << 2) {
3895 struct kvm_segment kvm_seg;
3896
3e6e0aab 3897 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3898
3899 if (kvm_seg.unusable)
3900 dtable->limit = 0;
3901 else
3902 dtable->limit = kvm_seg.limit;
3903 dtable->base = kvm_seg.base;
3904 }
3905 else
3906 kvm_x86_ops->get_gdt(vcpu, dtable);
3907}
3908
3909/* allowed just for 8 bytes segments */
3910static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3911 struct desc_struct *seg_desc)
3912{
98899aa0 3913 gpa_t gpa;
37817f29
IE		 3914 struct descriptor_table dtable;
3915 u16 index = selector >> 3;
3916
b8222ad2 3917 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3918
3919 if (dtable.limit < index * 8 + 7) {
3920 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3921 return 1;
3922 }
98899aa0
MT		 3923 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3924 gpa += index * 8;
3925 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3926}
3927
3928/* allowed just for 8 bytes segments */
3929static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3930 struct desc_struct *seg_desc)
3931{
98899aa0 3932 gpa_t gpa;
37817f29
IE		 3933 struct descriptor_table dtable;
3934 u16 index = selector >> 3;
3935
b8222ad2 3936 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3937
3938 if (dtable.limit < index * 8 + 7)
3939 return 1;
98899aa0
MT		 3940 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3941 gpa += index * 8;
3942 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3943}
3944
3945static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3946 struct desc_struct *seg_desc)
3947{
3948 u32 base_addr;
3949
3950 base_addr = seg_desc->base0;
3951 base_addr |= (seg_desc->base1 << 16);
3952 base_addr |= (seg_desc->base2 << 24);
3953
98899aa0 3954 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3955}
3956
37817f29
IE		 3957static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3958{
3959 struct kvm_segment kvm_seg;
3960
3e6e0aab 3961 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3962 return kvm_seg.selector;
3963}
3964
3965static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3966 u16 selector,
3967 struct kvm_segment *kvm_seg)
3968{
3969 struct desc_struct seg_desc;
3970
3971 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3972 return 1;
3973 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3974 return 0;
3975}
3976
2259e3a7 3977static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3978{
3979 struct kvm_segment segvar = {
3980 .base = selector << 4,
3981 .limit = 0xffff,
3982 .selector = selector,
3983 .type = 3,
3984 .present = 1,
3985 .dpl = 3,
3986 .db = 0,
3987 .s = 1,
3988 .l = 0,
3989 .g = 0,
3990 .avl = 0,
3991 .unusable = 0,
3992 };
3993 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
3994 return 0;
3995}
3996
3e6e0aab
GT		 3997int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3998 int type_bits, int seg)
37817f29
IE		 3999{
4000 struct kvm_segment kvm_seg;
4001
f4bbd9aa
AK		 4002 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4003 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4004 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4005 return 1;
4006 kvm_seg.type |= type_bits;
4007
4008 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4009 seg != VCPU_SREG_LDTR)
4010 if (!kvm_seg.s)
4011 kvm_seg.unusable = 1;
4012
3e6e0aab 4013 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4014 return 0;
4015}
4016
4017static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4018 struct tss_segment_32 *tss)
4019{
4020 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4021 tss->eip = kvm_rip_read(vcpu);
37817f29 4022 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4023 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4024 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4025 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4026 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4027 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4028 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4029 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4030 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4031 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4032 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4033 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4034 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4035 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4036 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4037 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4038}
4039
4040static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4041 struct tss_segment_32 *tss)
4042{
4043 kvm_set_cr3(vcpu, tss->cr3);
4044
5fdbf976 4045 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 4046 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4047
5fdbf976
MT		 4048 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4049 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4050 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4051 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4052 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4053 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4054 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4055 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4056
3e6e0aab 4057 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4058 return 1;
4059
3e6e0aab 4060 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4061 return 1;
4062
3e6e0aab 4063 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4064 return 1;
4065
3e6e0aab 4066 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4067 return 1;
4068
3e6e0aab 4069 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4070 return 1;
4071
3e6e0aab 4072 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4073 return 1;
4074
3e6e0aab 4075 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4076 return 1;
4077 return 0;
4078}
4079
4080static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4081 struct tss_segment_16 *tss)
4082{
5fdbf976 4083 tss->ip = kvm_rip_read(vcpu);
37817f29 4084 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4085 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4086 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4087 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4088 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4089 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4090 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4091 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4092 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4093
4094 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4095 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4096 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4097 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4098 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4099 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4100}
4101
4102static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4103 struct tss_segment_16 *tss)
4104{
5fdbf976 4105 kvm_rip_write(vcpu, tss->ip);
37817f29 4106 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4107 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4108 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4109 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4110 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4111 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4112 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4113 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4114 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4115
3e6e0aab 4116 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4117 return 1;
4118
3e6e0aab 4119 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4120 return 1;
4121
3e6e0aab 4122 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4123 return 1;
4124
3e6e0aab 4125 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4126 return 1;
4127
3e6e0aab 4128 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4129 return 1;
4130 return 0;
4131}
4132
8b2cf73c 4133static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4134 u16 old_tss_sel, u32 old_tss_base,
4135 struct desc_struct *nseg_desc)
37817f29
IE		 4136{
4137 struct tss_segment_16 tss_segment_16;
4138 int ret = 0;
4139
34198bf8
MT		 4140 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4141 sizeof tss_segment_16))
37817f29
IE		 4142 goto out;
4143
4144 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4145
34198bf8
MT		 4146 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4147 sizeof tss_segment_16))
37817f29 4148 goto out;
34198bf8
MT		 4149
4150 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4151 &tss_segment_16, sizeof tss_segment_16))
4152 goto out;
4153
b237ac37
GN		 4154 if (old_tss_sel != 0xffff) {
4155 tss_segment_16.prev_task_link = old_tss_sel;
4156
4157 if (kvm_write_guest(vcpu->kvm,
4158 get_tss_base_addr(vcpu, nseg_desc),
4159 &tss_segment_16.prev_task_link,
4160 sizeof tss_segment_16.prev_task_link))
4161 goto out;
4162 }
4163
37817f29
IE		 4164 if (load_state_from_tss16(vcpu, &tss_segment_16))
4165 goto out;
4166
4167 ret = 1;
4168out:
4169 return ret;
4170}
4171
8b2cf73c 4172static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4173 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4174 struct desc_struct *nseg_desc)
4175{
4176 struct tss_segment_32 tss_segment_32;
4177 int ret = 0;
4178
34198bf8
MT		 4179 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4180 sizeof tss_segment_32))
37817f29
IE		 4181 goto out;
4182
4183 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4184
34198bf8
MT		 4185 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4186 sizeof tss_segment_32))
4187 goto out;
4188
4189 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4190 &tss_segment_32, sizeof tss_segment_32))
37817f29 4191 goto out;
34198bf8 4192
b237ac37
GN		 4193 if (old_tss_sel != 0xffff) {
4194 tss_segment_32.prev_task_link = old_tss_sel;
4195
4196 if (kvm_write_guest(vcpu->kvm,
4197 get_tss_base_addr(vcpu, nseg_desc),
4198 &tss_segment_32.prev_task_link,
4199 sizeof tss_segment_32.prev_task_link))
4200 goto out;
4201 }
4202
37817f29
IE		 4203 if (load_state_from_tss32(vcpu, &tss_segment_32))
4204 goto out;
4205
4206 ret = 1;
4207out:
4208 return ret;
4209}
4210
4211int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4212{
4213 struct kvm_segment tr_seg;
4214 struct desc_struct cseg_desc;
4215 struct desc_struct nseg_desc;
4216 int ret = 0;
34198bf8
MT		 4217 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4218 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4219
34198bf8 4220 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4221
34198bf8
MT		 4222 /* FIXME: Handle errors. Failure to read either TSS or their
4223 * descriptors should generate a pagefault.
4224 */
37817f29
IE		 4225 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4226 goto out;
4227
34198bf8 4228 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4229 goto out;
4230
37817f29
IE		 4231 if (reason != TASK_SWITCH_IRET) {
4232 int cpl;
4233
4234 cpl = kvm_x86_ops->get_cpl(vcpu);
4235 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4236 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4237 return 1;
4238 }
4239 }
4240
4241 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
4242 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4243 return 1;
4244 }
4245
4246 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4247 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4248 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4249 }
4250
4251 if (reason == TASK_SWITCH_IRET) {
4252 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4253 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4254 }
4255
64a7ec06
GN		 4256 /* set back link to prev task only if NT bit is set in eflags
4257 note that old_tss_sel is not used afetr this point */
4258 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4259 old_tss_sel = 0xffff;
37817f29 4260
b237ac37
GN		 4261 /* set back link to prev task only if NT bit is set in eflags
4262 note that old_tss_sel is not used afetr this point */
4263 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4264 old_tss_sel = 0xffff;
4265
37817f29 4266 if (nseg_desc.type & 8)
b237ac37
GN		 4267 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4268 old_tss_base, &nseg_desc);
37817f29 4269 else
b237ac37
GN		 4270 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4271 old_tss_base, &nseg_desc);
37817f29
IE		 4272
4273 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4274 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4275 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4276 }
4277
4278 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4279 nseg_desc.type |= (1 << 1);
37817f29
IE		 4280 save_guest_segment_descriptor(vcpu, tss_selector,
4281 &nseg_desc);
4282 }
4283
4284 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4285 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4286 tr_seg.type = 11;
3e6e0aab 4287 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4288out:
37817f29
IE		 4289 return ret;
4290}
4291EXPORT_SYMBOL_GPL(kvm_task_switch);
4292
b6c7a5dc
HB		 4293int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4294 struct kvm_sregs *sregs)
4295{
4296 int mmu_reset_needed = 0;
923c61bb 4297 int pending_vec, max_bits;
b6c7a5dc
HB		 4298 struct descriptor_table dt;
4299
4300 vcpu_load(vcpu);
4301
4302 dt.limit = sregs->idt.limit;
4303 dt.base = sregs->idt.base;
4304 kvm_x86_ops->set_idt(vcpu, &dt);
4305 dt.limit = sregs->gdt.limit;
4306 dt.base = sregs->gdt.base;
4307 kvm_x86_ops->set_gdt(vcpu, &dt);
4308
ad312c7c
ZX		 4309 vcpu->arch.cr2 = sregs->cr2;
4310 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
59839dff
MT		 4311
4312 down_read(&vcpu->kvm->slots_lock);
4313 if (gfn_to_memslot(vcpu->kvm, sregs->cr3 >> PAGE_SHIFT))
4314 vcpu->arch.cr3 = sregs->cr3;
4315 else
4316 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
4317 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc 4318
2d3ad1f4 4319 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4320
ad312c7c 4321 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4322 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4323 kvm_set_apic_base(vcpu, sregs->apic_base);
4324
4325 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4326
ad312c7c 4327 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4328 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4329 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4330
ad312c7c 4331 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4332 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4333 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4334 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4335
4336 if (mmu_reset_needed)
4337 kvm_mmu_reset_context(vcpu);
4338
923c61bb
GN		 4339 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4340 pending_vec = find_first_bit(
4341 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4342 if (pending_vec < max_bits) {
66fd3f7f 4343 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4344 pr_debug("Set back pending irq %d\n", pending_vec);
4345 if (irqchip_in_kernel(vcpu->kvm))
4346 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4347 }
4348
3e6e0aab
GT		 4349 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4350 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4351 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4352 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4353 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4354 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4355
3e6e0aab
GT		 4356 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4357 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4358
9c3e4aab 4359 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4360 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4361 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4362 !(vcpu->arch.cr0 & X86_CR0_PE))
4363 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4364
b6c7a5dc
HB		 4365 vcpu_put(vcpu);
4366
4367 return 0;
4368}
4369
d0bfb940
JK		 4370int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4371 struct kvm_guest_debug *dbg)
b6c7a5dc 4372{
ae675ef0 4373 int i, r;
b6c7a5dc
HB		 4374
4375 vcpu_load(vcpu);
4376
ae675ef0
JK		 4377 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4378 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4379 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4380 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4381 vcpu->arch.switch_db_regs =
4382 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4383 } else {
4384 for (i = 0; i < KVM_NR_DB_REGS; i++)
4385 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4386 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4387 }
4388
b6c7a5dc
HB		 4389 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4390
d0bfb940
JK		 4391 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4392 kvm_queue_exception(vcpu, DB_VECTOR);
4393 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4394 kvm_queue_exception(vcpu, BP_VECTOR);
4395
b6c7a5dc
HB		 4396 vcpu_put(vcpu);
4397
4398 return r;
4399}
4400
d0752060
HB		 4401/*
4402 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4403 * we have asm/x86/processor.h
4404 */
4405struct fxsave {
4406 u16 cwd;
4407 u16 swd;
4408 u16 twd;
4409 u16 fop;
4410 u64 rip;
4411 u64 rdp;
4412 u32 mxcsr;
4413 u32 mxcsr_mask;
4414 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4415#ifdef CONFIG_X86_64
4416 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4417#else
4418 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4419#endif
4420};
4421
8b006791
ZX		 4422/*
4423 * Translate a guest virtual address to a guest physical address.
4424 */
4425int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4426 struct kvm_translation *tr)
4427{
4428 unsigned long vaddr = tr->linear_address;
4429 gpa_t gpa;
4430
4431 vcpu_load(vcpu);
72dc67a6 4432 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4433 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4434 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4435 tr->physical_address = gpa;
4436 tr->valid = gpa != UNMAPPED_GVA;
4437 tr->writeable = 1;
4438 tr->usermode = 0;
8b006791
ZX		 4439 vcpu_put(vcpu);
4440
4441 return 0;
4442}
4443
d0752060
HB		 4444int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4445{
ad312c7c 4446 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4447
4448 vcpu_load(vcpu);
4449
4450 memcpy(fpu->fpr, fxsave->st_space, 128);
4451 fpu->fcw = fxsave->cwd;
4452 fpu->fsw = fxsave->swd;
4453 fpu->ftwx = fxsave->twd;
4454 fpu->last_opcode = fxsave->fop;
4455 fpu->last_ip = fxsave->rip;
4456 fpu->last_dp = fxsave->rdp;
4457 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4458
4459 vcpu_put(vcpu);
4460
4461 return 0;
4462}
4463
4464int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4465{
ad312c7c 4466 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4467
4468 vcpu_load(vcpu);
4469
4470 memcpy(fxsave->st_space, fpu->fpr, 128);
4471 fxsave->cwd = fpu->fcw;
4472 fxsave->swd = fpu->fsw;
4473 fxsave->twd = fpu->ftwx;
4474 fxsave->fop = fpu->last_opcode;
4475 fxsave->rip = fpu->last_ip;
4476 fxsave->rdp = fpu->last_dp;
4477 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4478
4479 vcpu_put(vcpu);
4480
4481 return 0;
4482}
4483
4484void fx_init(struct kvm_vcpu *vcpu)
4485{
4486 unsigned after_mxcsr_mask;
4487
bc1a34f1
AA		 4488 /*
4489 * Touch the fpu the first time in non atomic context as if
4490 * this is the first fpu instruction the exception handler
4491 * will fire before the instruction returns and it'll have to
4492 * allocate ram with GFP_KERNEL.
4493 */
4494 if (!used_math())
d6e88aec 4495 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4496
d0752060
HB		 4497 /* Initialize guest FPU by resetting ours and saving into guest's */
4498 preempt_disable();
d6e88aec
AK		 4499 kvm_fx_save(&vcpu->arch.host_fx_image);
4500 kvm_fx_finit();
4501 kvm_fx_save(&vcpu->arch.guest_fx_image);
4502 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4503 preempt_enable();
4504
ad312c7c 4505 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4506 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4507 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4508 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4509 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4510}
4511EXPORT_SYMBOL_GPL(fx_init);
4512
4513void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4514{
4515 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4516 return;
4517
4518 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4519 kvm_fx_save(&vcpu->arch.host_fx_image);
4520 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4521}
4522EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4523
4524void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4525{
4526 if (!vcpu->guest_fpu_loaded)
4527 return;
4528
4529 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4530 kvm_fx_save(&vcpu->arch.guest_fx_image);
4531 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4532 ++vcpu->stat.fpu_reload;
d0752060
HB		 4533}
4534EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4535
4536void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4537{
7f1ea208
JR		 4538 if (vcpu->arch.time_page) {
4539 kvm_release_page_dirty(vcpu->arch.time_page);
4540 vcpu->arch.time_page = NULL;
4541 }
4542
e9b11c17
ZX		 4543 kvm_x86_ops->vcpu_free(vcpu);
4544}
4545
4546struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4547 unsigned int id)
4548{
26e5215f
AK		 4549 return kvm_x86_ops->vcpu_create(kvm, id);
4550}
e9b11c17 4551
26e5215f
AK		 4552int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4553{
4554 int r;
e9b11c17
ZX		 4555
4556 /* We do fxsave: this must be aligned. */
ad312c7c 4557 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4558
0bed3b56 4559 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4560 vcpu_load(vcpu);
4561 r = kvm_arch_vcpu_reset(vcpu);
4562 if (r == 0)
4563 r = kvm_mmu_setup(vcpu);
4564 vcpu_put(vcpu);
4565 if (r < 0)
4566 goto free_vcpu;
4567
26e5215f 4568 return 0;
e9b11c17
ZX		 4569free_vcpu:
4570 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4571 return r;
e9b11c17
ZX		 4572}
4573
d40ccc62 4574void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4575{
4576 vcpu_load(vcpu);
4577 kvm_mmu_unload(vcpu);
4578 vcpu_put(vcpu);
4579
4580 kvm_x86_ops->vcpu_free(vcpu);
4581}
4582
4583int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4584{
448fa4a9
JK		 4585 vcpu->arch.nmi_pending = false;
4586 vcpu->arch.nmi_injected = false;
4587
42dbaa5a
JK		 4588 vcpu->arch.switch_db_regs = 0;
4589 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4590 vcpu->arch.dr6 = DR6_FIXED_1;
4591 vcpu->arch.dr7 = DR7_FIXED_1;
4592
e9b11c17
ZX		 4593 return kvm_x86_ops->vcpu_reset(vcpu);
4594}
4595
4596void kvm_arch_hardware_enable(void *garbage)
4597{
4598 kvm_x86_ops->hardware_enable(garbage);
4599}
4600
4601void kvm_arch_hardware_disable(void *garbage)
4602{
4603 kvm_x86_ops->hardware_disable(garbage);
4604}
4605
4606int kvm_arch_hardware_setup(void)
4607{
4608 return kvm_x86_ops->hardware_setup();
4609}
4610
4611void kvm_arch_hardware_unsetup(void)
4612{
4613 kvm_x86_ops->hardware_unsetup();
4614}
4615
4616void kvm_arch_check_processor_compat(void *rtn)
4617{
4618 kvm_x86_ops->check_processor_compatibility(rtn);
4619}
4620
4621int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4622{
4623 struct page *page;
4624 struct kvm *kvm;
4625 int r;
4626
4627 BUG_ON(vcpu->kvm == NULL);
4628 kvm = vcpu->kvm;
4629
ad312c7c 4630 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 4631 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 4632 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4633 else
a4535290 4634 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4635
4636 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4637 if (!page) {
4638 r = -ENOMEM;
4639 goto fail;
4640 }
ad312c7c 4641 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4642
4643 r = kvm_mmu_create(vcpu);
4644 if (r < 0)
4645 goto fail_free_pio_data;
4646
4647 if (irqchip_in_kernel(kvm)) {
4648 r = kvm_create_lapic(vcpu);
4649 if (r < 0)
4650 goto fail_mmu_destroy;
4651 }
4652
890ca9ae
HY		 4653 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4654 GFP_KERNEL);
4655 if (!vcpu->arch.mce_banks) {
4656 r = -ENOMEM;
4657 goto fail_mmu_destroy;
4658 }
4659 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4660
e9b11c17
ZX		 4661 return 0;
4662
4663fail_mmu_destroy:
4664 kvm_mmu_destroy(vcpu);
4665fail_free_pio_data:
ad312c7c 4666 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4667fail:
4668 return r;
4669}
4670
4671void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4672{
4673 kvm_free_lapic(vcpu);
3200f405 4674 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4675 kvm_mmu_destroy(vcpu);
3200f405 4676 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4677 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4678}
d19a9cd2
ZX		 4679
4680struct kvm *kvm_arch_create_vm(void)
4681{
4682 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4683
4684 if (!kvm)
4685 return ERR_PTR(-ENOMEM);
4686
f05e70ac 4687 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4688 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4689
5550af4d
SY		 4690 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4691 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4692
53f658b3
MT		 4693 rdtscll(kvm->arch.vm_init_tsc);
4694
d19a9cd2
ZX		 4695 return kvm;
4696}
4697
4698static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4699{
4700 vcpu_load(vcpu);
4701 kvm_mmu_unload(vcpu);
4702 vcpu_put(vcpu);
4703}
4704
4705static void kvm_free_vcpus(struct kvm *kvm)
4706{
4707 unsigned int i;
988a2cae 4708 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 4709
4710 /*
4711 * Unpin any mmu pages first.
4712 */
988a2cae
GN		 4713 kvm_for_each_vcpu(i, vcpu, kvm)
4714 kvm_unload_vcpu_mmu(vcpu);
4715 kvm_for_each_vcpu(i, vcpu, kvm)
4716 kvm_arch_vcpu_free(vcpu);
4717
4718 mutex_lock(&kvm->lock);
4719 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4720 kvm->vcpus[i] = NULL;
d19a9cd2 4721
988a2cae
GN		 4722 atomic_set(&kvm->online_vcpus, 0);
4723 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 4724}
4725
ad8ba2cd
SY		 4726void kvm_arch_sync_events(struct kvm *kvm)
4727{
ba4cef31 4728 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4729}
4730
d19a9cd2
ZX		 4731void kvm_arch_destroy_vm(struct kvm *kvm)
4732{
6eb55818 4733 kvm_iommu_unmap_guest(kvm);
7837699f 4734 kvm_free_pit(kvm);
d7deeeb0
ZX		 4735 kfree(kvm->arch.vpic);
4736 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4737 kvm_free_vcpus(kvm);
4738 kvm_free_physmem(kvm);
3d45830c
AK		 4739 if (kvm->arch.apic_access_page)
4740 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4741 if (kvm->arch.ept_identity_pagetable)
4742 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4743 kfree(kvm);
4744}
0de10343
ZX		 4745
4746int kvm_arch_set_memory_region(struct kvm *kvm,
4747 struct kvm_userspace_memory_region *mem,
4748 struct kvm_memory_slot old,
4749 int user_alloc)
4750{
4751 int npages = mem->memory_size >> PAGE_SHIFT;
4752 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4753
4754 /*To keep backward compatibility with older userspace,
4755 *x86 needs to hanlde !user_alloc case.
4756 */
4757 if (!user_alloc) {
4758 if (npages && !old.rmap) {
604b38ac
AA		 4759 unsigned long userspace_addr;
4760
72dc67a6 4761 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4762 userspace_addr = do_mmap(NULL, 0,
4763 npages * PAGE_SIZE,
4764 PROT_READ | PROT_WRITE,
acee3c04 4765 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4766 0);
72dc67a6 4767 up_write(&current->mm->mmap_sem);
0de10343 4768
604b38ac
AA		 4769 if (IS_ERR((void *)userspace_addr))
4770 return PTR_ERR((void *)userspace_addr);
4771
4772 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4773 spin_lock(&kvm->mmu_lock);
4774 memslot->userspace_addr = userspace_addr;
4775 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4776 } else {
4777 if (!old.user_alloc && old.rmap) {
4778 int ret;
4779
72dc67a6 4780 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4781 ret = do_munmap(current->mm, old.userspace_addr,
4782 old.npages * PAGE_SIZE);
72dc67a6 4783 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4784 if (ret < 0)
4785 printk(KERN_WARNING
4786 "kvm_vm_ioctl_set_memory_region: "
4787 "failed to munmap memory\n");
4788 }
4789 }
4790 }
4791
7c8a83b7 4792 spin_lock(&kvm->mmu_lock);
f05e70ac 4793 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4794 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4795 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4796 }
4797
4798 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4799 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4800 kvm_flush_remote_tlbs(kvm);
4801
4802 return 0;
4803}
1d737c8a 4804
34d4cb8f
MT		 4805void kvm_arch_flush_shadow(struct kvm *kvm)
4806{
4807 kvm_mmu_zap_all(kvm);
8986ecc0 4808 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4809}
4810
1d737c8a
ZX		 4811int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4812{
a4535290 4813 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4814 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4815 || vcpu->arch.nmi_pending;
1d737c8a 4816}
5736199a 4817
5736199a
ZX		 4818void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4819{
32f88400
MT		 4820 int me;
4821 int cpu = vcpu->cpu;
5736199a
ZX		 4822
4823 if (waitqueue_active(&vcpu->wq)) {
4824 wake_up_interruptible(&vcpu->wq);
4825 ++vcpu->stat.halt_wakeup;
4826 }
32f88400
MT		 4827
4828 me = get_cpu();
4829 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4830 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4831 smp_send_reschedule(cpu);
e9571ed5 4832 put_cpu();
5736199a 4833}
78646121
GN		 4834
4835int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4836{
4837 return kvm_x86_ops->interrupt_allowed(vcpu);
4838}
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git