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KVM: Trace apic registers using their symbolic names
[thirdparty/kernel/stable.git] / arch / x86 / kvm / x86.c
CommitLineData
043405e1
CO		 1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
4d5c5d0f
BAY		 7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008
043405e1
CO		 9 *
10 * Authors:
11 * Avi Kivity <avi@qumranet.com>
12 * Yaniv Kamay <yaniv@qumranet.com>
4d5c5d0f
BAY		 13 * Amit Shah <amit.shah@qumranet.com>
14 * Ben-Ami Yassour <benami@il.ibm.com>
043405e1
CO		 15 *
16 * This work is licensed under the terms of the GNU GPL, version 2. See
17 * the COPYING file in the top-level directory.
18 *
19 */
20
edf88417 21#include <linux/kvm_host.h>
313a3dc7 22#include "irq.h"
1d737c8a 23#include "mmu.h"
7837699f 24#include "i8254.h"
37817f29 25#include "tss.h"
5fdbf976 26#include "kvm_cache_regs.h"
26eef70c 27#include "x86.h"
313a3dc7 28
18068523 29#include <linux/clocksource.h>
4d5c5d0f 30#include <linux/interrupt.h>
313a3dc7
CO		 31#include <linux/kvm.h>
32#include <linux/fs.h>
33#include <linux/vmalloc.h>
5fb76f9b 34#include <linux/module.h>
0de10343 35#include <linux/mman.h>
2bacc55c 36#include <linux/highmem.h>
19de40a8 37#include <linux/iommu.h>
62c476c7 38#include <linux/intel-iommu.h>
c8076604 39#include <linux/cpufreq.h>
aec51dc4
AK		 40#include <trace/events/kvm.h>
41#undef TRACE_INCLUDE_FILE
229456fc
MT		 42#define CREATE_TRACE_POINTS
43#include "trace.h"
043405e1
CO		 44
45#include <asm/uaccess.h>
d825ed0a 46#include <asm/msr.h>
a5f61300 47#include <asm/desc.h>
0bed3b56 48#include <asm/mtrr.h>
890ca9ae 49#include <asm/mce.h>
043405e1 50
313a3dc7 51#define MAX_IO_MSRS 256
a03490ed
CO		 52#define CR0_RESERVED_BITS \
53 (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
54 | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
55 | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
56#define CR4_RESERVED_BITS \
57 (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
58 | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
59 | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
60 | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
61
62#define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
890ca9ae
HY		 63
64#define KVM_MAX_MCE_BANKS 32
65#define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
66
50a37eb4
JR		 67/* EFER defaults:
68 * - enable syscall per default because its emulated by KVM
69 * - enable LME and LMA per default on 64 bit KVM
70 */
71#ifdef CONFIG_X86_64
72static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
73#else
74static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
75#endif
313a3dc7 76
ba1389b7
AK		 77#define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
78#define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
417bc304 79
674eea0f
AK		 80static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
81 struct kvm_cpuid_entry2 __user *entries);
d8017474
AG		 82struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
83 u32 function, u32 index);
674eea0f 84
97896d04 85struct kvm_x86_ops *kvm_x86_ops;
5fdbf976 86EXPORT_SYMBOL_GPL(kvm_x86_ops);
97896d04 87
ed85c068
AP		 88int ignore_msrs = 0;
89module_param_named(ignore_msrs, ignore_msrs, bool, S_IRUGO | S_IWUSR);
90
417bc304 91struct kvm_stats_debugfs_item debugfs_entries[] = {
ba1389b7
AK		 92 { "pf_fixed", VCPU_STAT(pf_fixed) },
93 { "pf_guest", VCPU_STAT(pf_guest) },
94 { "tlb_flush", VCPU_STAT(tlb_flush) },
95 { "invlpg", VCPU_STAT(invlpg) },
96 { "exits", VCPU_STAT(exits) },
97 { "io_exits", VCPU_STAT(io_exits) },
98 { "mmio_exits", VCPU_STAT(mmio_exits) },
99 { "signal_exits", VCPU_STAT(signal_exits) },
100 { "irq_window", VCPU_STAT(irq_window_exits) },
f08864b4 101 { "nmi_window", VCPU_STAT(nmi_window_exits) },
ba1389b7
AK		 102 { "halt_exits", VCPU_STAT(halt_exits) },
103 { "halt_wakeup", VCPU_STAT(halt_wakeup) },
f11c3a8d 104 { "hypercalls", VCPU_STAT(hypercalls) },
ba1389b7
AK		 105 { "request_irq", VCPU_STAT(request_irq_exits) },
106 { "irq_exits", VCPU_STAT(irq_exits) },
107 { "host_state_reload", VCPU_STAT(host_state_reload) },
108 { "efer_reload", VCPU_STAT(efer_reload) },
109 { "fpu_reload", VCPU_STAT(fpu_reload) },
110 { "insn_emulation", VCPU_STAT(insn_emulation) },
111 { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
fa89a817 112 { "irq_injections", VCPU_STAT(irq_injections) },
c4abb7c9 113 { "nmi_injections", VCPU_STAT(nmi_injections) },
4cee5764
AK		 114 { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
115 { "mmu_pte_write", VM_STAT(mmu_pte_write) },
116 { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
117 { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
118 { "mmu_flooded", VM_STAT(mmu_flooded) },
119 { "mmu_recycled", VM_STAT(mmu_recycled) },
dfc5aa00 120 { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
4731d4c7 121 { "mmu_unsync", VM_STAT(mmu_unsync) },
0f74a24c 122 { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
05da4558 123 { "largepages", VM_STAT(lpages) },
417bc304
HB		 124 { NULL }
125};
126
5fb76f9b
CO		 127unsigned long segment_base(u16 selector)
128{
129 struct descriptor_table gdt;
a5f61300 130 struct desc_struct *d;
5fb76f9b
CO		 131 unsigned long table_base;
132 unsigned long v;
133
134 if (selector == 0)
135 return 0;
136
137 asm("sgdt %0" : "=m"(gdt));
138 table_base = gdt.base;
139
140 if (selector & 4) { /* from ldt */
141 u16 ldt_selector;
142
143 asm("sldt %0" : "=g"(ldt_selector));
144 table_base = segment_base(ldt_selector);
145 }
a5f61300
AK		 146 d = (struct desc_struct *)(table_base + (selector & ~7));
147 v = d->base0 | ((unsigned long)d->base1 << 16) |
148 ((unsigned long)d->base2 << 24);
5fb76f9b 149#ifdef CONFIG_X86_64
a5f61300
AK		 150 if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
151 v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
5fb76f9b
CO		 152#endif
153 return v;
154}
155EXPORT_SYMBOL_GPL(segment_base);
156
6866b83e
CO		 157u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
158{
159 if (irqchip_in_kernel(vcpu->kvm))
ad312c7c 160 return vcpu->arch.apic_base;
6866b83e 161 else
ad312c7c 162 return vcpu->arch.apic_base;
6866b83e
CO		 163}
164EXPORT_SYMBOL_GPL(kvm_get_apic_base);
165
166void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
167{
168 /* TODO: reserve bits check */
169 if (irqchip_in_kernel(vcpu->kvm))
170 kvm_lapic_set_base(vcpu, data);
171 else
ad312c7c 172 vcpu->arch.apic_base = data;
6866b83e
CO		 173}
174EXPORT_SYMBOL_GPL(kvm_set_apic_base);
175
298101da
AK		 176void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
177{
ad312c7c
ZX		 178 WARN_ON(vcpu->arch.exception.pending);
179 vcpu->arch.exception.pending = true;
180 vcpu->arch.exception.has_error_code = false;
181 vcpu->arch.exception.nr = nr;
298101da
AK		 182}
183EXPORT_SYMBOL_GPL(kvm_queue_exception);
184
c3c91fee
AK		 185void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
186 u32 error_code)
187{
188 ++vcpu->stat.pf_guest;
d8017474 189
71c4dfaf 190 if (vcpu->arch.exception.pending) {
6edf14d8
GN		 191 switch(vcpu->arch.exception.nr) {
192 case DF_VECTOR:
71c4dfaf
JR		 193 /* triple fault -> shutdown */
194 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
6edf14d8
GN		 195 return;
196 case PF_VECTOR:
197 vcpu->arch.exception.nr = DF_VECTOR;
198 vcpu->arch.exception.error_code = 0;
199 return;
200 default:
201 /* replace previous exception with a new one in a hope
202 that instruction re-execution will regenerate lost
203 exception */
204 vcpu->arch.exception.pending = false;
205 break;
71c4dfaf 206 }
c3c91fee 207 }
ad312c7c 208 vcpu->arch.cr2 = addr;
c3c91fee
AK		 209 kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
210}
211
3419ffc8
SY		 212void kvm_inject_nmi(struct kvm_vcpu *vcpu)
213{
214 vcpu->arch.nmi_pending = 1;
215}
216EXPORT_SYMBOL_GPL(kvm_inject_nmi);
217
298101da
AK		 218void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
219{
ad312c7c
ZX		 220 WARN_ON(vcpu->arch.exception.pending);
221 vcpu->arch.exception.pending = true;
222 vcpu->arch.exception.has_error_code = true;
223 vcpu->arch.exception.nr = nr;
224 vcpu->arch.exception.error_code = error_code;
298101da
AK		 225}
226EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
227
228static void __queue_exception(struct kvm_vcpu *vcpu)
229{
ad312c7c
ZX		 230 kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
231 vcpu->arch.exception.has_error_code,
232 vcpu->arch.exception.error_code);
298101da
AK		 233}
234
a03490ed
CO		 235/*
236 * Load the pae pdptrs. Return true is they are all valid.
237 */
238int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
239{
240 gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
241 unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
242 int i;
243 int ret;
ad312c7c 244 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
a03490ed 245
a03490ed
CO		 246 ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
247 offset * sizeof(u64), sizeof(pdpte));
248 if (ret < 0) {
249 ret = 0;
250 goto out;
251 }
252 for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
43a3795a 253 if (is_present_gpte(pdpte[i]) &&
20c466b5 254 (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
a03490ed
CO		 255 ret = 0;
256 goto out;
257 }
258 }
259 ret = 1;
260
ad312c7c 261 memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
6de4f3ad
AK		 262 __set_bit(VCPU_EXREG_PDPTR,
263 (unsigned long *)&vcpu->arch.regs_avail);
264 __set_bit(VCPU_EXREG_PDPTR,
265 (unsigned long *)&vcpu->arch.regs_dirty);
a03490ed 266out:
a03490ed
CO		 267
268 return ret;
269}
cc4b6871 270EXPORT_SYMBOL_GPL(load_pdptrs);
a03490ed 271
d835dfec
AK		 272static bool pdptrs_changed(struct kvm_vcpu *vcpu)
273{
ad312c7c 274 u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
d835dfec
AK		 275 bool changed = true;
276 int r;
277
278 if (is_long_mode(vcpu) || !is_pae(vcpu))
279 return false;
280
6de4f3ad
AK		 281 if (!test_bit(VCPU_EXREG_PDPTR,
282 (unsigned long *)&vcpu->arch.regs_avail))
283 return true;
284
ad312c7c 285 r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
d835dfec
AK		 286 if (r < 0)
287 goto out;
ad312c7c 288 changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
d835dfec 289out:
d835dfec
AK		 290
291 return changed;
292}
293
2d3ad1f4 294void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
a03490ed
CO		 295{
296 if (cr0 & CR0_RESERVED_BITS) {
297 printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
ad312c7c 298 cr0, vcpu->arch.cr0);
c1a5d4f9 299 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 300 return;
301 }
302
303 if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
304 printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
c1a5d4f9 305 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 306 return;
307 }
308
309 if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
310 printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
311 "and a clear PE flag\n");
c1a5d4f9 312 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 313 return;
314 }
315
316 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
317#ifdef CONFIG_X86_64
ad312c7c 318 if ((vcpu->arch.shadow_efer & EFER_LME)) {
a03490ed
CO		 319 int cs_db, cs_l;
320
321 if (!is_pae(vcpu)) {
322 printk(KERN_DEBUG "set_cr0: #GP, start paging "
323 "in long mode while PAE is disabled\n");
c1a5d4f9 324 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 325 return;
326 }
327 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
328 if (cs_l) {
329 printk(KERN_DEBUG "set_cr0: #GP, start paging "
330 "in long mode while CS.L == 1\n");
c1a5d4f9 331 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 332 return;
333
334 }
335 } else
336#endif
ad312c7c 337 if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed
CO		 338 printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
339 "reserved bits\n");
c1a5d4f9 340 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 341 return;
342 }
343
344 }
345
346 kvm_x86_ops->set_cr0(vcpu, cr0);
ad312c7c 347 vcpu->arch.cr0 = cr0;
a03490ed 348
a03490ed 349 kvm_mmu_reset_context(vcpu);
a03490ed
CO		 350 return;
351}
2d3ad1f4 352EXPORT_SYMBOL_GPL(kvm_set_cr0);
a03490ed 353
2d3ad1f4 354void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
a03490ed 355{
2d3ad1f4 356 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
a03490ed 357}
2d3ad1f4 358EXPORT_SYMBOL_GPL(kvm_lmsw);
a03490ed 359
2d3ad1f4 360void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
a03490ed 361{
a2edf57f
AK		 362 unsigned long old_cr4 = vcpu->arch.cr4;
363 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
364
a03490ed
CO		 365 if (cr4 & CR4_RESERVED_BITS) {
366 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
c1a5d4f9 367 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 368 return;
369 }
370
371 if (is_long_mode(vcpu)) {
372 if (!(cr4 & X86_CR4_PAE)) {
373 printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
374 "in long mode\n");
c1a5d4f9 375 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 376 return;
377 }
a2edf57f
AK		 378 } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
379 && ((cr4 ^ old_cr4) & pdptr_bits)
ad312c7c 380 && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
a03490ed 381 printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
c1a5d4f9 382 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 383 return;
384 }
385
386 if (cr4 & X86_CR4_VMXE) {
387 printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
c1a5d4f9 388 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 389 return;
390 }
391 kvm_x86_ops->set_cr4(vcpu, cr4);
ad312c7c 392 vcpu->arch.cr4 = cr4;
5a41accd 393 vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
a03490ed 394 kvm_mmu_reset_context(vcpu);
a03490ed 395}
2d3ad1f4 396EXPORT_SYMBOL_GPL(kvm_set_cr4);
a03490ed 397
2d3ad1f4 398void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
a03490ed 399{
ad312c7c 400 if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
0ba73cda 401 kvm_mmu_sync_roots(vcpu);
d835dfec
AK		 402 kvm_mmu_flush_tlb(vcpu);
403 return;
404 }
405
a03490ed
CO		 406 if (is_long_mode(vcpu)) {
407 if (cr3 & CR3_L_MODE_RESERVED_BITS) {
408 printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
c1a5d4f9 409 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 410 return;
411 }
412 } else {
413 if (is_pae(vcpu)) {
414 if (cr3 & CR3_PAE_RESERVED_BITS) {
415 printk(KERN_DEBUG
416 "set_cr3: #GP, reserved bits\n");
c1a5d4f9 417 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 418 return;
419 }
420 if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
421 printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
422 "reserved bits\n");
c1a5d4f9 423 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 424 return;
425 }
426 }
427 /*
428 * We don't check reserved bits in nonpae mode, because
429 * this isn't enforced, and VMware depends on this.
430 */
431 }
432
a03490ed
CO		 433 /*
434 * Does the new cr3 value map to physical memory? (Note, we
435 * catch an invalid cr3 even in real-mode, because it would
436 * cause trouble later on when we turn on paging anyway.)
437 *
438 * A real CPU would silently accept an invalid cr3 and would
439 * attempt to use it - with largely undefined (and often hard
440 * to debug) behavior on the guest side.
441 */
442 if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
c1a5d4f9 443 kvm_inject_gp(vcpu, 0);
a03490ed 444 else {
ad312c7c
ZX		 445 vcpu->arch.cr3 = cr3;
446 vcpu->arch.mmu.new_cr3(vcpu);
a03490ed 447 }
a03490ed 448}
2d3ad1f4 449EXPORT_SYMBOL_GPL(kvm_set_cr3);
a03490ed 450
2d3ad1f4 451void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
a03490ed
CO		 452{
453 if (cr8 & CR8_RESERVED_BITS) {
454 printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
c1a5d4f9 455 kvm_inject_gp(vcpu, 0);
a03490ed
CO		 456 return;
457 }
458 if (irqchip_in_kernel(vcpu->kvm))
459 kvm_lapic_set_tpr(vcpu, cr8);
460 else
ad312c7c 461 vcpu->arch.cr8 = cr8;
a03490ed 462}
2d3ad1f4 463EXPORT_SYMBOL_GPL(kvm_set_cr8);
a03490ed 464
2d3ad1f4 465unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
a03490ed
CO		 466{
467 if (irqchip_in_kernel(vcpu->kvm))
468 return kvm_lapic_get_cr8(vcpu);
469 else
ad312c7c 470 return vcpu->arch.cr8;
a03490ed 471}
2d3ad1f4 472EXPORT_SYMBOL_GPL(kvm_get_cr8);
a03490ed 473
d8017474
AG		 474static inline u32 bit(int bitno)
475{
476 return 1 << (bitno & 31);
477}
478
043405e1
CO		 479/*
480 * List of msr numbers which we expose to userspace through KVM_GET_MSRS
481 * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
482 *
483 * This list is modified at module load time to reflect the
484 * capabilities of the host cpu.
485 */
486static u32 msrs_to_save[] = {
487 MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
488 MSR_K6_STAR,
489#ifdef CONFIG_X86_64
490 MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
491#endif
af24a4e4 492 MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
b286d5d8 493 MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
043405e1
CO		 494};
495
496static unsigned num_msrs_to_save;
497
498static u32 emulated_msrs[] = {
499 MSR_IA32_MISC_ENABLE,
500};
501
15c4a640
CO		 502static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
503{
f2b4b7dd 504 if (efer & efer_reserved_bits) {
15c4a640
CO		 505 printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
506 efer);
c1a5d4f9 507 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 508 return;
509 }
510
511 if (is_paging(vcpu)
ad312c7c 512 && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
15c4a640 513 printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
c1a5d4f9 514 kvm_inject_gp(vcpu, 0);
15c4a640
CO		 515 return;
516 }
517
1b2fd70c
AG		 518 if (efer & EFER_FFXSR) {
519 struct kvm_cpuid_entry2 *feat;
520
521 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
522 if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
523 printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
524 kvm_inject_gp(vcpu, 0);
525 return;
526 }
527 }
528
d8017474
AG		 529 if (efer & EFER_SVME) {
530 struct kvm_cpuid_entry2 *feat;
531
532 feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
533 if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
534 printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
535 kvm_inject_gp(vcpu, 0);
536 return;
537 }
538 }
539
15c4a640
CO		 540 kvm_x86_ops->set_efer(vcpu, efer);
541
542 efer &= ~EFER_LMA;
ad312c7c 543 efer |= vcpu->arch.shadow_efer & EFER_LMA;
15c4a640 544
ad312c7c 545 vcpu->arch.shadow_efer = efer;
9645bb56
AK		 546
547 vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
548 kvm_mmu_reset_context(vcpu);
15c4a640
CO		 549}
550
f2b4b7dd
JR		 551void kvm_enable_efer_bits(u64 mask)
552{
553 efer_reserved_bits &= ~mask;
554}
555EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
556
557
15c4a640
CO		 558/*
559 * Writes msr value into into the appropriate "register".
560 * Returns 0 on success, non-0 otherwise.
561 * Assumes vcpu_load() was already called.
562 */
563int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
564{
565 return kvm_x86_ops->set_msr(vcpu, msr_index, data);
566}
567
313a3dc7
CO		 568/*
569 * Adapt set_msr() to msr_io()'s calling convention
570 */
571static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
572{
573 return kvm_set_msr(vcpu, index, *data);
574}
575
18068523
GOC		 576static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
577{
578 static int version;
50d0a0f9
GH		 579 struct pvclock_wall_clock wc;
580 struct timespec now, sys, boot;
18068523
GOC		 581
582 if (!wall_clock)
583 return;
584
585 version++;
586
18068523
GOC		 587 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
588
50d0a0f9
GH		 589 /*
590 * The guest calculates current wall clock time by adding
591 * system time (updated by kvm_write_guest_time below) to the
592 * wall clock specified here. guest system time equals host
593 * system time for us, thus we must fill in host boot time here.
594 */
595 now = current_kernel_time();
596 ktime_get_ts(&sys);
597 boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
598
599 wc.sec = boot.tv_sec;
600 wc.nsec = boot.tv_nsec;
601 wc.version = version;
18068523
GOC		 602
603 kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
604
605 version++;
606 kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
18068523
GOC		 607}
608
50d0a0f9
GH		 609static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
610{
611 uint32_t quotient, remainder;
612
613 /* Don't try to replace with do_div(), this one calculates
614 * "(dividend << 32) / divisor" */
615 __asm__ ( "divl %4"
616 : "=a" (quotient), "=d" (remainder)
617 : "0" (0), "1" (dividend), "r" (divisor) );
618 return quotient;
619}
620
621static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
622{
623 uint64_t nsecs = 1000000000LL;
624 int32_t shift = 0;
625 uint64_t tps64;
626 uint32_t tps32;
627
628 tps64 = tsc_khz * 1000LL;
629 while (tps64 > nsecs*2) {
630 tps64 >>= 1;
631 shift--;
632 }
633
634 tps32 = (uint32_t)tps64;
635 while (tps32 <= (uint32_t)nsecs) {
636 tps32 <<= 1;
637 shift++;
638 }
639
640 hv_clock->tsc_shift = shift;
641 hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
642
643 pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
80a914dc 644 __func__, tsc_khz, hv_clock->tsc_shift,
50d0a0f9
GH		 645 hv_clock->tsc_to_system_mul);
646}
647
c8076604
GH		 648static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
649
18068523
GOC		 650static void kvm_write_guest_time(struct kvm_vcpu *v)
651{
652 struct timespec ts;
653 unsigned long flags;
654 struct kvm_vcpu_arch *vcpu = &v->arch;
655 void *shared_kaddr;
463656c0 656 unsigned long this_tsc_khz;
18068523
GOC		 657
658 if ((!vcpu->time_page))
659 return;
660
463656c0
AK		 661 this_tsc_khz = get_cpu_var(cpu_tsc_khz);
662 if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
663 kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
664 vcpu->hv_clock_tsc_khz = this_tsc_khz;
50d0a0f9 665 }
463656c0 666 put_cpu_var(cpu_tsc_khz);
50d0a0f9 667
18068523
GOC		 668 /* Keep irq disabled to prevent changes to the clock */
669 local_irq_save(flags);
af24a4e4 670 kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
18068523
GOC		 671 ktime_get_ts(&ts);
672 local_irq_restore(flags);
673
674 /* With all the info we got, fill in the values */
675
676 vcpu->hv_clock.system_time = ts.tv_nsec +
677 (NSEC_PER_SEC * (u64)ts.tv_sec);
678 /*
679 * The interface expects us to write an even number signaling that the
680 * update is finished. Since the guest won't see the intermediate
50d0a0f9 681 * state, we just increase by 2 at the end.
18068523 682 */
50d0a0f9 683 vcpu->hv_clock.version += 2;
18068523
GOC		 684
685 shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
686
687 memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
50d0a0f9 688 sizeof(vcpu->hv_clock));
18068523
GOC		 689
690 kunmap_atomic(shared_kaddr, KM_USER0);
691
692 mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
693}
694
c8076604
GH		 695static int kvm_request_guest_time_update(struct kvm_vcpu *v)
696{
697 struct kvm_vcpu_arch *vcpu = &v->arch;
698
699 if (!vcpu->time_page)
700 return 0;
701 set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
702 return 1;
703}
704
9ba075a6
AK		 705static bool msr_mtrr_valid(unsigned msr)
706{
707 switch (msr) {
708 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
709 case MSR_MTRRfix64K_00000:
710 case MSR_MTRRfix16K_80000:
711 case MSR_MTRRfix16K_A0000:
712 case MSR_MTRRfix4K_C0000:
713 case MSR_MTRRfix4K_C8000:
714 case MSR_MTRRfix4K_D0000:
715 case MSR_MTRRfix4K_D8000:
716 case MSR_MTRRfix4K_E0000:
717 case MSR_MTRRfix4K_E8000:
718 case MSR_MTRRfix4K_F0000:
719 case MSR_MTRRfix4K_F8000:
720 case MSR_MTRRdefType:
721 case MSR_IA32_CR_PAT:
722 return true;
723 case 0x2f8:
724 return true;
725 }
726 return false;
727}
728
d6289b93
MT		 729static bool valid_pat_type(unsigned t)
730{
731 return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
732}
733
734static bool valid_mtrr_type(unsigned t)
735{
736 return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
737}
738
739static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
740{
741 int i;
742
743 if (!msr_mtrr_valid(msr))
744 return false;
745
746 if (msr == MSR_IA32_CR_PAT) {
747 for (i = 0; i < 8; i++)
748 if (!valid_pat_type((data >> (i * 8)) & 0xff))
749 return false;
750 return true;
751 } else if (msr == MSR_MTRRdefType) {
752 if (data & ~0xcff)
753 return false;
754 return valid_mtrr_type(data & 0xff);
755 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
756 for (i = 0; i < 8 ; i++)
757 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
758 return false;
759 return true;
760 }
761
762 /* variable MTRRs */
763 return valid_mtrr_type(data & 0xff);
764}
765
9ba075a6
AK		 766static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
767{
0bed3b56
SY		 768 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
769
d6289b93 770 if (!mtrr_valid(vcpu, msr, data))
9ba075a6
AK		 771 return 1;
772
0bed3b56
SY		 773 if (msr == MSR_MTRRdefType) {
774 vcpu->arch.mtrr_state.def_type = data;
775 vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
776 } else if (msr == MSR_MTRRfix64K_00000)
777 p[0] = data;
778 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
779 p[1 + msr - MSR_MTRRfix16K_80000] = data;
780 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
781 p[3 + msr - MSR_MTRRfix4K_C0000] = data;
782 else if (msr == MSR_IA32_CR_PAT)
783 vcpu->arch.pat = data;
784 else { /* Variable MTRRs */
785 int idx, is_mtrr_mask;
786 u64 *pt;
787
788 idx = (msr - 0x200) / 2;
789 is_mtrr_mask = msr - 0x200 - 2 * idx;
790 if (!is_mtrr_mask)
791 pt =
792 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
793 else
794 pt =
795 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
796 *pt = data;
797 }
798
799 kvm_mmu_reset_context(vcpu);
9ba075a6
AK		 800 return 0;
801}
15c4a640 802
890ca9ae 803static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
15c4a640 804{
890ca9ae
HY		 805 u64 mcg_cap = vcpu->arch.mcg_cap;
806 unsigned bank_num = mcg_cap & 0xff;
807
15c4a640 808 switch (msr) {
15c4a640 809 case MSR_IA32_MCG_STATUS:
890ca9ae 810 vcpu->arch.mcg_status = data;
15c4a640 811 break;
c7ac679c 812 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 813 if (!(mcg_cap & MCG_CTL_P))
814 return 1;
815 if (data != 0 && data != ~(u64)0)
816 return -1;
817 vcpu->arch.mcg_ctl = data;
818 break;
819 default:
820 if (msr >= MSR_IA32_MC0_CTL &&
821 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
822 u32 offset = msr - MSR_IA32_MC0_CTL;
823 /* only 0 or all 1s can be written to IA32_MCi_CTL */
824 if ((offset & 0x3) == 0 &&
825 data != 0 && data != ~(u64)0)
826 return -1;
827 vcpu->arch.mce_banks[offset] = data;
828 break;
829 }
830 return 1;
831 }
832 return 0;
833}
834
835int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
836{
837 switch (msr) {
838 case MSR_EFER:
839 set_efer(vcpu, data);
c7ac679c 840 break;
8f1589d9
AP		 841 case MSR_K7_HWCR:
842 data &= ~(u64)0x40; /* ignore flush filter disable */
843 if (data != 0) {
844 pr_unimpl(vcpu, "unimplemented HWCR wrmsr: 0x%llx\n",
845 data);
846 return 1;
847 }
848 break;
c323c0e5
AP		 849 case MSR_AMD64_NB_CFG:
850 break;
b5e2fec0
AG		 851 case MSR_IA32_DEBUGCTLMSR:
852 if (!data) {
853 /* We support the non-activated case already */
854 break;
855 } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
856 /* Values other than LBR and BTF are vendor-specific,
857 thus reserved and should throw a #GP */
858 return 1;
859 }
860 pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
861 __func__, data);
862 break;
15c4a640
CO		 863 case MSR_IA32_UCODE_REV:
864 case MSR_IA32_UCODE_WRITE:
61a6bd67 865 case MSR_VM_HSAVE_PA:
15c4a640 866 break;
9ba075a6
AK		 867 case 0x200 ... 0x2ff:
868 return set_msr_mtrr(vcpu, msr, data);
15c4a640
CO		 869 case MSR_IA32_APICBASE:
870 kvm_set_apic_base(vcpu, data);
871 break;
872 case MSR_IA32_MISC_ENABLE:
ad312c7c 873 vcpu->arch.ia32_misc_enable_msr = data;
15c4a640 874 break;
18068523
GOC		 875 case MSR_KVM_WALL_CLOCK:
876 vcpu->kvm->arch.wall_clock = data;
877 kvm_write_wall_clock(vcpu->kvm, data);
878 break;
879 case MSR_KVM_SYSTEM_TIME: {
880 if (vcpu->arch.time_page) {
881 kvm_release_page_dirty(vcpu->arch.time_page);
882 vcpu->arch.time_page = NULL;
883 }
884
885 vcpu->arch.time = data;
886
887 /* we verify if the enable bit is set... */
888 if (!(data & 1))
889 break;
890
891 /* ...but clean it before doing the actual write */
892 vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
893
18068523
GOC		 894 vcpu->arch.time_page =
895 gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
18068523
GOC		 896
897 if (is_error_page(vcpu->arch.time_page)) {
898 kvm_release_page_clean(vcpu->arch.time_page);
899 vcpu->arch.time_page = NULL;
900 }
901
c8076604 902 kvm_request_guest_time_update(vcpu);
18068523
GOC		 903 break;
904 }
890ca9ae
HY		 905 case MSR_IA32_MCG_CTL:
906 case MSR_IA32_MCG_STATUS:
907 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
908 return set_msr_mce(vcpu, msr, data);
71db6023
AP		 909
910 /* Performance counters are not protected by a CPUID bit,
911 * so we should check all of them in the generic path for the sake of
912 * cross vendor migration.
913 * Writing a zero into the event select MSRs disables them,
914 * which we perfectly emulate ;-). Any other value should be at least
915 * reported, some guests depend on them.
916 */
917 case MSR_P6_EVNTSEL0:
918 case MSR_P6_EVNTSEL1:
919 case MSR_K7_EVNTSEL0:
920 case MSR_K7_EVNTSEL1:
921 case MSR_K7_EVNTSEL2:
922 case MSR_K7_EVNTSEL3:
923 if (data != 0)
924 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
925 "0x%x data 0x%llx\n", msr, data);
926 break;
927 /* at least RHEL 4 unconditionally writes to the perfctr registers,
928 * so we ignore writes to make it happy.
929 */
930 case MSR_P6_PERFCTR0:
931 case MSR_P6_PERFCTR1:
932 case MSR_K7_PERFCTR0:
933 case MSR_K7_PERFCTR1:
934 case MSR_K7_PERFCTR2:
935 case MSR_K7_PERFCTR3:
936 pr_unimpl(vcpu, "unimplemented perfctr wrmsr: "
937 "0x%x data 0x%llx\n", msr, data);
938 break;
15c4a640 939 default:
ed85c068
AP		 940 if (!ignore_msrs) {
941 pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n",
942 msr, data);
943 return 1;
944 } else {
945 pr_unimpl(vcpu, "ignored wrmsr: 0x%x data %llx\n",
946 msr, data);
947 break;
948 }
15c4a640
CO		 949 }
950 return 0;
951}
952EXPORT_SYMBOL_GPL(kvm_set_msr_common);
953
954
955/*
956 * Reads an msr value (of 'msr_index') into 'pdata'.
957 * Returns 0 on success, non-0 otherwise.
958 * Assumes vcpu_load() was already called.
959 */
960int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
961{
962 return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
963}
964
9ba075a6
AK		 965static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
966{
0bed3b56
SY		 967 u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
968
9ba075a6
AK		 969 if (!msr_mtrr_valid(msr))
970 return 1;
971
0bed3b56
SY		 972 if (msr == MSR_MTRRdefType)
973 *pdata = vcpu->arch.mtrr_state.def_type +
974 (vcpu->arch.mtrr_state.enabled << 10);
975 else if (msr == MSR_MTRRfix64K_00000)
976 *pdata = p[0];
977 else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
978 *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
979 else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
980 *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
981 else if (msr == MSR_IA32_CR_PAT)
982 *pdata = vcpu->arch.pat;
983 else { /* Variable MTRRs */
984 int idx, is_mtrr_mask;
985 u64 *pt;
986
987 idx = (msr - 0x200) / 2;
988 is_mtrr_mask = msr - 0x200 - 2 * idx;
989 if (!is_mtrr_mask)
990 pt =
991 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
992 else
993 pt =
994 (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
995 *pdata = *pt;
996 }
997
9ba075a6
AK		 998 return 0;
999}
1000
890ca9ae 1001static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
15c4a640
CO		 1002{
1003 u64 data;
890ca9ae
HY		 1004 u64 mcg_cap = vcpu->arch.mcg_cap;
1005 unsigned bank_num = mcg_cap & 0xff;
15c4a640
CO		 1006
1007 switch (msr) {
15c4a640
CO		 1008 case MSR_IA32_P5_MC_ADDR:
1009 case MSR_IA32_P5_MC_TYPE:
890ca9ae
HY		 1010 data = 0;
1011 break;
15c4a640 1012 case MSR_IA32_MCG_CAP:
890ca9ae
HY		 1013 data = vcpu->arch.mcg_cap;
1014 break;
c7ac679c 1015 case MSR_IA32_MCG_CTL:
890ca9ae
HY		 1016 if (!(mcg_cap & MCG_CTL_P))
1017 return 1;
1018 data = vcpu->arch.mcg_ctl;
1019 break;
1020 case MSR_IA32_MCG_STATUS:
1021 data = vcpu->arch.mcg_status;
1022 break;
1023 default:
1024 if (msr >= MSR_IA32_MC0_CTL &&
1025 msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
1026 u32 offset = msr - MSR_IA32_MC0_CTL;
1027 data = vcpu->arch.mce_banks[offset];
1028 break;
1029 }
1030 return 1;
1031 }
1032 *pdata = data;
1033 return 0;
1034}
1035
1036int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
1037{
1038 u64 data;
1039
1040 switch (msr) {
890ca9ae 1041 case MSR_IA32_PLATFORM_ID:
15c4a640 1042 case MSR_IA32_UCODE_REV:
15c4a640 1043 case MSR_IA32_EBL_CR_POWERON:
b5e2fec0
AG		 1044 case MSR_IA32_DEBUGCTLMSR:
1045 case MSR_IA32_LASTBRANCHFROMIP:
1046 case MSR_IA32_LASTBRANCHTOIP:
1047 case MSR_IA32_LASTINTFROMIP:
1048 case MSR_IA32_LASTINTTOIP:
60af2ecd
JSR		 1049 case MSR_K8_SYSCFG:
1050 case MSR_K7_HWCR:
61a6bd67 1051 case MSR_VM_HSAVE_PA:
7fe29e0f
AS		 1052 case MSR_P6_EVNTSEL0:
1053 case MSR_P6_EVNTSEL1:
9e699624 1054 case MSR_K7_EVNTSEL0:
1fdbd48c 1055 case MSR_K8_INT_PENDING_MSG:
c323c0e5 1056 case MSR_AMD64_NB_CFG:
15c4a640
CO		 1057 data = 0;
1058 break;
9ba075a6
AK		 1059 case MSR_MTRRcap:
1060 data = 0x500 | KVM_NR_VAR_MTRR;
1061 break;
1062 case 0x200 ... 0x2ff:
1063 return get_msr_mtrr(vcpu, msr, pdata);
15c4a640
CO		 1064 case 0xcd: /* fsb frequency */
1065 data = 3;
1066 break;
1067 case MSR_IA32_APICBASE:
1068 data = kvm_get_apic_base(vcpu);
1069 break;
1070 case MSR_IA32_MISC_ENABLE:
ad312c7c 1071 data = vcpu->arch.ia32_misc_enable_msr;
15c4a640 1072 break;
847f0ad8
AG		 1073 case MSR_IA32_PERF_STATUS:
1074 /* TSC increment by tick */
1075 data = 1000ULL;
1076 /* CPU multiplier */
1077 data |= (((uint64_t)4ULL) << 40);
1078 break;
15c4a640 1079 case MSR_EFER:
ad312c7c 1080 data = vcpu->arch.shadow_efer;
15c4a640 1081 break;
18068523
GOC		 1082 case MSR_KVM_WALL_CLOCK:
1083 data = vcpu->kvm->arch.wall_clock;
1084 break;
1085 case MSR_KVM_SYSTEM_TIME:
1086 data = vcpu->arch.time;
1087 break;
890ca9ae
HY		 1088 case MSR_IA32_P5_MC_ADDR:
1089 case MSR_IA32_P5_MC_TYPE:
1090 case MSR_IA32_MCG_CAP:
1091 case MSR_IA32_MCG_CTL:
1092 case MSR_IA32_MCG_STATUS:
1093 case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
1094 return get_msr_mce(vcpu, msr, pdata);
15c4a640 1095 default:
ed85c068
AP		 1096 if (!ignore_msrs) {
1097 pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
1098 return 1;
1099 } else {
1100 pr_unimpl(vcpu, "ignored rdmsr: 0x%x\n", msr);
1101 data = 0;
1102 }
1103 break;
15c4a640
CO		 1104 }
1105 *pdata = data;
1106 return 0;
1107}
1108EXPORT_SYMBOL_GPL(kvm_get_msr_common);
1109
313a3dc7
CO		 1110/*
1111 * Read or write a bunch of msrs. All parameters are kernel addresses.
1112 *
1113 * @return number of msrs set successfully.
1114 */
1115static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
1116 struct kvm_msr_entry *entries,
1117 int (*do_msr)(struct kvm_vcpu *vcpu,
1118 unsigned index, u64 *data))
1119{
1120 int i;
1121
1122 vcpu_load(vcpu);
1123
3200f405 1124 down_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1125 for (i = 0; i < msrs->nmsrs; ++i)
1126 if (do_msr(vcpu, entries[i].index, &entries[i].data))
1127 break;
3200f405 1128 up_read(&vcpu->kvm->slots_lock);
313a3dc7
CO		 1129
1130 vcpu_put(vcpu);
1131
1132 return i;
1133}
1134
1135/*
1136 * Read or write a bunch of msrs. Parameters are user addresses.
1137 *
1138 * @return number of msrs set successfully.
1139 */
1140static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
1141 int (*do_msr)(struct kvm_vcpu *vcpu,
1142 unsigned index, u64 *data),
1143 int writeback)
1144{
1145 struct kvm_msrs msrs;
1146 struct kvm_msr_entry *entries;
1147 int r, n;
1148 unsigned size;
1149
1150 r = -EFAULT;
1151 if (copy_from_user(&msrs, user_msrs, sizeof msrs))
1152 goto out;
1153
1154 r = -E2BIG;
1155 if (msrs.nmsrs >= MAX_IO_MSRS)
1156 goto out;
1157
1158 r = -ENOMEM;
1159 size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
1160 entries = vmalloc(size);
1161 if (!entries)
1162 goto out;
1163
1164 r = -EFAULT;
1165 if (copy_from_user(entries, user_msrs->entries, size))
1166 goto out_free;
1167
1168 r = n = __msr_io(vcpu, &msrs, entries, do_msr);
1169 if (r < 0)
1170 goto out_free;
1171
1172 r = -EFAULT;
1173 if (writeback && copy_to_user(user_msrs->entries, entries, size))
1174 goto out_free;
1175
1176 r = n;
1177
1178out_free:
1179 vfree(entries);
1180out:
1181 return r;
1182}
1183
018d00d2
ZX		 1184int kvm_dev_ioctl_check_extension(long ext)
1185{
1186 int r;
1187
1188 switch (ext) {
1189 case KVM_CAP_IRQCHIP:
1190 case KVM_CAP_HLT:
1191 case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
018d00d2 1192 case KVM_CAP_SET_TSS_ADDR:
07716717 1193 case KVM_CAP_EXT_CPUID:
c8076604 1194 case KVM_CAP_CLOCKSOURCE:
7837699f 1195 case KVM_CAP_PIT:
a28e4f5a 1196 case KVM_CAP_NOP_IO_DELAY:
62d9f0db 1197 case KVM_CAP_MP_STATE:
ed848624 1198 case KVM_CAP_SYNC_MMU:
52d939a0 1199 case KVM_CAP_REINJECT_CONTROL:
4925663a 1200 case KVM_CAP_IRQ_INJECT_STATUS:
e56d532f 1201 case KVM_CAP_ASSIGN_DEV_IRQ:
721eecbf 1202 case KVM_CAP_IRQFD:
c5ff41ce 1203 case KVM_CAP_PIT2:
018d00d2
ZX		 1204 r = 1;
1205 break;
542472b5
LV		 1206 case KVM_CAP_COALESCED_MMIO:
1207 r = KVM_COALESCED_MMIO_PAGE_OFFSET;
1208 break;
774ead3a
AK		 1209 case KVM_CAP_VAPIC:
1210 r = !kvm_x86_ops->cpu_has_accelerated_tpr();
1211 break;
f725230a
AK		 1212 case KVM_CAP_NR_VCPUS:
1213 r = KVM_MAX_VCPUS;
1214 break;
a988b910
AK		 1215 case KVM_CAP_NR_MEMSLOTS:
1216 r = KVM_MEMORY_SLOTS;
1217 break;
2f333bcb
MT		 1218 case KVM_CAP_PV_MMU:
1219 r = !tdp_enabled;
1220 break;
62c476c7 1221 case KVM_CAP_IOMMU:
19de40a8 1222 r = iommu_found();
62c476c7 1223 break;
890ca9ae
HY		 1224 case KVM_CAP_MCE:
1225 r = KVM_MAX_MCE_BANKS;
1226 break;
018d00d2
ZX		 1227 default:
1228 r = 0;
1229 break;
1230 }
1231 return r;
1232
1233}
1234
043405e1
CO		 1235long kvm_arch_dev_ioctl(struct file *filp,
1236 unsigned int ioctl, unsigned long arg)
1237{
1238 void __user *argp = (void __user *)arg;
1239 long r;
1240
1241 switch (ioctl) {
1242 case KVM_GET_MSR_INDEX_LIST: {
1243 struct kvm_msr_list __user *user_msr_list = argp;
1244 struct kvm_msr_list msr_list;
1245 unsigned n;
1246
1247 r = -EFAULT;
1248 if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
1249 goto out;
1250 n = msr_list.nmsrs;
1251 msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
1252 if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
1253 goto out;
1254 r = -E2BIG;
e125e7b6 1255 if (n < msr_list.nmsrs)
043405e1
CO		 1256 goto out;
1257 r = -EFAULT;
1258 if (copy_to_user(user_msr_list->indices, &msrs_to_save,
1259 num_msrs_to_save * sizeof(u32)))
1260 goto out;
e125e7b6 1261 if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
043405e1
CO		 1262 &emulated_msrs,
1263 ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
1264 goto out;
1265 r = 0;
1266 break;
1267 }
674eea0f
AK		 1268 case KVM_GET_SUPPORTED_CPUID: {
1269 struct kvm_cpuid2 __user *cpuid_arg = argp;
1270 struct kvm_cpuid2 cpuid;
1271
1272 r = -EFAULT;
1273 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1274 goto out;
1275 r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
19355475 1276 cpuid_arg->entries);
674eea0f
AK		 1277 if (r)
1278 goto out;
1279
1280 r = -EFAULT;
1281 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1282 goto out;
1283 r = 0;
1284 break;
1285 }
890ca9ae
HY		 1286 case KVM_X86_GET_MCE_CAP_SUPPORTED: {
1287 u64 mce_cap;
1288
1289 mce_cap = KVM_MCE_CAP_SUPPORTED;
1290 r = -EFAULT;
1291 if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
1292 goto out;
1293 r = 0;
1294 break;
1295 }
043405e1
CO		 1296 default:
1297 r = -EINVAL;
1298 }
1299out:
1300 return r;
1301}
1302
313a3dc7
CO		 1303void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1304{
1305 kvm_x86_ops->vcpu_load(vcpu, cpu);
c8076604 1306 kvm_request_guest_time_update(vcpu);
313a3dc7
CO		 1307}
1308
1309void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
1310{
1311 kvm_x86_ops->vcpu_put(vcpu);
9327fd11 1312 kvm_put_guest_fpu(vcpu);
313a3dc7
CO		 1313}
1314
07716717 1315static int is_efer_nx(void)
313a3dc7 1316{
e286e86e 1317 unsigned long long efer = 0;
313a3dc7 1318
e286e86e 1319 rdmsrl_safe(MSR_EFER, &efer);
07716717
DK		 1320 return efer & EFER_NX;
1321}
1322
1323static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
1324{
1325 int i;
1326 struct kvm_cpuid_entry2 *e, *entry;
1327
313a3dc7 1328 entry = NULL;
ad312c7c
ZX		 1329 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
1330 e = &vcpu->arch.cpuid_entries[i];
313a3dc7
CO		 1331 if (e->function == 0x80000001) {
1332 entry = e;
1333 break;
1334 }
1335 }
07716717 1336 if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
313a3dc7
CO		 1337 entry->edx &= ~(1 << 20);
1338 printk(KERN_INFO "kvm: guest NX capability removed\n");
1339 }
1340}
1341
07716717 1342/* when an old userspace process fills a new kernel module */
313a3dc7
CO		 1343static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
1344 struct kvm_cpuid *cpuid,
1345 struct kvm_cpuid_entry __user *entries)
07716717
DK		 1346{
1347 int r, i;
1348 struct kvm_cpuid_entry *cpuid_entries;
1349
1350 r = -E2BIG;
1351 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1352 goto out;
1353 r = -ENOMEM;
1354 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
1355 if (!cpuid_entries)
1356 goto out;
1357 r = -EFAULT;
1358 if (copy_from_user(cpuid_entries, entries,
1359 cpuid->nent * sizeof(struct kvm_cpuid_entry)))
1360 goto out_free;
1361 for (i = 0; i < cpuid->nent; i++) {
ad312c7c
ZX		 1362 vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
1363 vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
1364 vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
1365 vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
1366 vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
1367 vcpu->arch.cpuid_entries[i].index = 0;
1368 vcpu->arch.cpuid_entries[i].flags = 0;
1369 vcpu->arch.cpuid_entries[i].padding[0] = 0;
1370 vcpu->arch.cpuid_entries[i].padding[1] = 0;
1371 vcpu->arch.cpuid_entries[i].padding[2] = 0;
1372 }
1373 vcpu->arch.cpuid_nent = cpuid->nent;
07716717
DK		 1374 cpuid_fix_nx_cap(vcpu);
1375 r = 0;
1376
1377out_free:
1378 vfree(cpuid_entries);
1379out:
1380 return r;
1381}
1382
1383static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1384 struct kvm_cpuid2 *cpuid,
1385 struct kvm_cpuid_entry2 __user *entries)
313a3dc7
CO		 1386{
1387 int r;
1388
1389 r = -E2BIG;
1390 if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
1391 goto out;
1392 r = -EFAULT;
ad312c7c 1393 if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
07716717 1394 cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
313a3dc7 1395 goto out;
ad312c7c 1396 vcpu->arch.cpuid_nent = cpuid->nent;
313a3dc7
CO		 1397 return 0;
1398
1399out:
1400 return r;
1401}
1402
07716717 1403static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
19355475
AS		 1404 struct kvm_cpuid2 *cpuid,
1405 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1406{
1407 int r;
1408
1409 r = -E2BIG;
ad312c7c 1410 if (cpuid->nent < vcpu->arch.cpuid_nent)
07716717
DK		 1411 goto out;
1412 r = -EFAULT;
ad312c7c 1413 if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
19355475 1414 vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1415 goto out;
1416 return 0;
1417
1418out:
ad312c7c 1419 cpuid->nent = vcpu->arch.cpuid_nent;
07716717
DK		 1420 return r;
1421}
1422
07716717 1423static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
19355475 1424 u32 index)
07716717
DK		 1425{
1426 entry->function = function;
1427 entry->index = index;
1428 cpuid_count(entry->function, entry->index,
19355475 1429 &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
07716717
DK		 1430 entry->flags = 0;
1431}
1432
7faa4ee1
AK		 1433#define F(x) bit(X86_FEATURE_##x)
1434
07716717
DK		 1435static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
1436 u32 index, int *nent, int maxnent)
1437{
7faa4ee1 1438 unsigned f_nx = is_efer_nx() ? F(NX) : 0;
07716717 1439#ifdef CONFIG_X86_64
7faa4ee1
AK		 1440 unsigned f_lm = F(LM);
1441#else
1442 unsigned f_lm = 0;
07716717 1443#endif
7faa4ee1
AK		 1444
1445 /* cpuid 1.edx */
1446 const u32 kvm_supported_word0_x86_features =
1447 F(FPU) | F(VME) | F(DE) | F(PSE) |
1448 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1449 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
1450 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1451 F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
1452 0 /* Reserved, DS, ACPI */ | F(MMX) |
1453 F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
1454 0 /* HTT, TM, Reserved, PBE */;
1455 /* cpuid 0x80000001.edx */
1456 const u32 kvm_supported_word1_x86_features =
1457 F(FPU) | F(VME) | F(DE) | F(PSE) |
1458 F(TSC) | F(MSR) | F(PAE) | F(MCE) |
1459 F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
1460 F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
1461 F(PAT) | F(PSE36) | 0 /* Reserved */ |
1462 f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
1463 F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
1464 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
1465 /* cpuid 1.ecx */
1466 const u32 kvm_supported_word4_x86_features =
d149c731
AK		 1467 F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
1468 0 /* DS-CPL, VMX, SMX, EST */ |
1469 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
1470 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
1471 0 /* Reserved, DCA */ | F(XMM4_1) |
1472 F(XMM4_2) | 0 /* x2APIC */ | F(MOVBE) | F(POPCNT) |
1473 0 /* Reserved, XSAVE, OSXSAVE */;
7faa4ee1 1474 /* cpuid 0x80000001.ecx */
07716717 1475 const u32 kvm_supported_word6_x86_features =
7faa4ee1
AK		 1476 F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
1477 F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
1478 F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
1479 0 /* SKINIT */ | 0 /* WDT */;
07716717 1480
19355475 1481 /* all calls to cpuid_count() should be made on the same cpu */
07716717
DK		 1482 get_cpu();
1483 do_cpuid_1_ent(entry, function, index);
1484 ++*nent;
1485
1486 switch (function) {
1487 case 0:
1488 entry->eax = min(entry->eax, (u32)0xb);
1489 break;
1490 case 1:
1491 entry->edx &= kvm_supported_word0_x86_features;
7faa4ee1 1492 entry->ecx &= kvm_supported_word4_x86_features;
07716717
DK		 1493 break;
1494 /* function 2 entries are STATEFUL. That is, repeated cpuid commands
1495 * may return different values. This forces us to get_cpu() before
1496 * issuing the first command, and also to emulate this annoying behavior
1497 * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
1498 case 2: {
1499 int t, times = entry->eax & 0xff;
1500
1501 entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
0fdf8e59 1502 entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
07716717
DK		 1503 for (t = 1; t < times && *nent < maxnent; ++t) {
1504 do_cpuid_1_ent(&entry[t], function, 0);
1505 entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
1506 ++*nent;
1507 }
1508 break;
1509 }
1510 /* function 4 and 0xb have additional index. */
1511 case 4: {
14af3f3c 1512 int i, cache_type;
07716717
DK		 1513
1514 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1515 /* read more entries until cache_type is zero */
14af3f3c
HH		 1516 for (i = 1; *nent < maxnent; ++i) {
1517 cache_type = entry[i - 1].eax & 0x1f;
07716717
DK		 1518 if (!cache_type)
1519 break;
14af3f3c
HH		 1520 do_cpuid_1_ent(&entry[i], function, i);
1521 entry[i].flags |=
07716717
DK		 1522 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1523 ++*nent;
1524 }
1525 break;
1526 }
1527 case 0xb: {
14af3f3c 1528 int i, level_type;
07716717
DK		 1529
1530 entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1531 /* read more entries until level_type is zero */
14af3f3c 1532 for (i = 1; *nent < maxnent; ++i) {
0853d2c1 1533 level_type = entry[i - 1].ecx & 0xff00;
07716717
DK		 1534 if (!level_type)
1535 break;
14af3f3c
HH		 1536 do_cpuid_1_ent(&entry[i], function, i);
1537 entry[i].flags |=
07716717
DK		 1538 KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
1539 ++*nent;
1540 }
1541 break;
1542 }
1543 case 0x80000000:
1544 entry->eax = min(entry->eax, 0x8000001a);
1545 break;
1546 case 0x80000001:
1547 entry->edx &= kvm_supported_word1_x86_features;
1548 entry->ecx &= kvm_supported_word6_x86_features;
1549 break;
1550 }
1551 put_cpu();
1552}
1553
7faa4ee1
AK		 1554#undef F
1555
674eea0f 1556static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
19355475 1557 struct kvm_cpuid_entry2 __user *entries)
07716717
DK		 1558{
1559 struct kvm_cpuid_entry2 *cpuid_entries;
1560 int limit, nent = 0, r = -E2BIG;
1561 u32 func;
1562
1563 if (cpuid->nent < 1)
1564 goto out;
1565 r = -ENOMEM;
1566 cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
1567 if (!cpuid_entries)
1568 goto out;
1569
1570 do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
1571 limit = cpuid_entries[0].eax;
1572 for (func = 1; func <= limit && nent < cpuid->nent; ++func)
1573 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1574 &nent, cpuid->nent);
07716717
DK		 1575 r = -E2BIG;
1576 if (nent >= cpuid->nent)
1577 goto out_free;
1578
1579 do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
1580 limit = cpuid_entries[nent - 1].eax;
1581 for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
1582 do_cpuid_ent(&cpuid_entries[nent], func, 0,
19355475 1583 &nent, cpuid->nent);
cb007648
MM		 1584 r = -E2BIG;
1585 if (nent >= cpuid->nent)
1586 goto out_free;
1587
07716717
DK		 1588 r = -EFAULT;
1589 if (copy_to_user(entries, cpuid_entries,
19355475 1590 nent * sizeof(struct kvm_cpuid_entry2)))
07716717
DK		 1591 goto out_free;
1592 cpuid->nent = nent;
1593 r = 0;
1594
1595out_free:
1596 vfree(cpuid_entries);
1597out:
1598 return r;
1599}
1600
313a3dc7
CO		 1601static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
1602 struct kvm_lapic_state *s)
1603{
1604 vcpu_load(vcpu);
ad312c7c 1605 memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
313a3dc7
CO		 1606 vcpu_put(vcpu);
1607
1608 return 0;
1609}
1610
1611static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
1612 struct kvm_lapic_state *s)
1613{
1614 vcpu_load(vcpu);
ad312c7c 1615 memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
313a3dc7
CO		 1616 kvm_apic_post_state_restore(vcpu);
1617 vcpu_put(vcpu);
1618
1619 return 0;
1620}
1621
f77bc6a4
ZX		 1622static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
1623 struct kvm_interrupt *irq)
1624{
1625 if (irq->irq < 0 || irq->irq >= 256)
1626 return -EINVAL;
1627 if (irqchip_in_kernel(vcpu->kvm))
1628 return -ENXIO;
1629 vcpu_load(vcpu);
1630
66fd3f7f 1631 kvm_queue_interrupt(vcpu, irq->irq, false);
f77bc6a4
ZX		 1632
1633 vcpu_put(vcpu);
1634
1635 return 0;
1636}
1637
c4abb7c9
JK		 1638static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
1639{
1640 vcpu_load(vcpu);
1641 kvm_inject_nmi(vcpu);
1642 vcpu_put(vcpu);
1643
1644 return 0;
1645}
1646
b209749f
AK		 1647static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
1648 struct kvm_tpr_access_ctl *tac)
1649{
1650 if (tac->flags)
1651 return -EINVAL;
1652 vcpu->arch.tpr_access_reporting = !!tac->enabled;
1653 return 0;
1654}
1655
890ca9ae
HY		 1656static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
1657 u64 mcg_cap)
1658{
1659 int r;
1660 unsigned bank_num = mcg_cap & 0xff, bank;
1661
1662 r = -EINVAL;
1663 if (!bank_num)
1664 goto out;
1665 if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
1666 goto out;
1667 r = 0;
1668 vcpu->arch.mcg_cap = mcg_cap;
1669 /* Init IA32_MCG_CTL to all 1s */
1670 if (mcg_cap & MCG_CTL_P)
1671 vcpu->arch.mcg_ctl = ~(u64)0;
1672 /* Init IA32_MCi_CTL to all 1s */
1673 for (bank = 0; bank < bank_num; bank++)
1674 vcpu->arch.mce_banks[bank*4] = ~(u64)0;
1675out:
1676 return r;
1677}
1678
1679static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
1680 struct kvm_x86_mce *mce)
1681{
1682 u64 mcg_cap = vcpu->arch.mcg_cap;
1683 unsigned bank_num = mcg_cap & 0xff;
1684 u64 *banks = vcpu->arch.mce_banks;
1685
1686 if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
1687 return -EINVAL;
1688 /*
1689 * if IA32_MCG_CTL is not all 1s, the uncorrected error
1690 * reporting is disabled
1691 */
1692 if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
1693 vcpu->arch.mcg_ctl != ~(u64)0)
1694 return 0;
1695 banks += 4 * mce->bank;
1696 /*
1697 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1698 * reporting is disabled for the bank
1699 */
1700 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1701 return 0;
1702 if (mce->status & MCI_STATUS_UC) {
1703 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1704 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1705 printk(KERN_DEBUG "kvm: set_mce: "
1706 "injects mce exception while "
1707 "previous one is in progress!\n");
1708 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1709 return 0;
1710 }
1711 if (banks[1] & MCI_STATUS_VAL)
1712 mce->status |= MCI_STATUS_OVER;
1713 banks[2] = mce->addr;
1714 banks[3] = mce->misc;
1715 vcpu->arch.mcg_status = mce->mcg_status;
1716 banks[1] = mce->status;
1717 kvm_queue_exception(vcpu, MC_VECTOR);
1718 } else if (!(banks[1] & MCI_STATUS_VAL)
1719 || !(banks[1] & MCI_STATUS_UC)) {
1720 if (banks[1] & MCI_STATUS_VAL)
1721 mce->status |= MCI_STATUS_OVER;
1722 banks[2] = mce->addr;
1723 banks[3] = mce->misc;
1724 banks[1] = mce->status;
1725 } else
1726 banks[1] |= MCI_STATUS_OVER;
1727 return 0;
1728}
1729
313a3dc7
CO		 1730long kvm_arch_vcpu_ioctl(struct file *filp,
1731 unsigned int ioctl, unsigned long arg)
1732{
1733 struct kvm_vcpu *vcpu = filp->private_data;
1734 void __user *argp = (void __user *)arg;
1735 int r;
b772ff36 1736 struct kvm_lapic_state *lapic = NULL;
313a3dc7
CO		 1737
1738 switch (ioctl) {
1739 case KVM_GET_LAPIC: {
b772ff36 1740 lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
313a3dc7 1741
b772ff36
DH		 1742 r = -ENOMEM;
1743 if (!lapic)
1744 goto out;
1745 r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
313a3dc7
CO		 1746 if (r)
1747 goto out;
1748 r = -EFAULT;
b772ff36 1749 if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
313a3dc7
CO		 1750 goto out;
1751 r = 0;
1752 break;
1753 }
1754 case KVM_SET_LAPIC: {
b772ff36
DH		 1755 lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
1756 r = -ENOMEM;
1757 if (!lapic)
1758 goto out;
313a3dc7 1759 r = -EFAULT;
b772ff36 1760 if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
313a3dc7 1761 goto out;
b772ff36 1762 r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
313a3dc7
CO		 1763 if (r)
1764 goto out;
1765 r = 0;
1766 break;
1767 }
f77bc6a4
ZX		 1768 case KVM_INTERRUPT: {
1769 struct kvm_interrupt irq;
1770
1771 r = -EFAULT;
1772 if (copy_from_user(&irq, argp, sizeof irq))
1773 goto out;
1774 r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
1775 if (r)
1776 goto out;
1777 r = 0;
1778 break;
1779 }
c4abb7c9
JK		 1780 case KVM_NMI: {
1781 r = kvm_vcpu_ioctl_nmi(vcpu);
1782 if (r)
1783 goto out;
1784 r = 0;
1785 break;
1786 }
313a3dc7
CO		 1787 case KVM_SET_CPUID: {
1788 struct kvm_cpuid __user *cpuid_arg = argp;
1789 struct kvm_cpuid cpuid;
1790
1791 r = -EFAULT;
1792 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1793 goto out;
1794 r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
1795 if (r)
1796 goto out;
1797 break;
1798 }
07716717
DK		 1799 case KVM_SET_CPUID2: {
1800 struct kvm_cpuid2 __user *cpuid_arg = argp;
1801 struct kvm_cpuid2 cpuid;
1802
1803 r = -EFAULT;
1804 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1805 goto out;
1806 r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
19355475 1807 cpuid_arg->entries);
07716717
DK		 1808 if (r)
1809 goto out;
1810 break;
1811 }
1812 case KVM_GET_CPUID2: {
1813 struct kvm_cpuid2 __user *cpuid_arg = argp;
1814 struct kvm_cpuid2 cpuid;
1815
1816 r = -EFAULT;
1817 if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
1818 goto out;
1819 r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
19355475 1820 cpuid_arg->entries);
07716717
DK		 1821 if (r)
1822 goto out;
1823 r = -EFAULT;
1824 if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
1825 goto out;
1826 r = 0;
1827 break;
1828 }
313a3dc7
CO		 1829 case KVM_GET_MSRS:
1830 r = msr_io(vcpu, argp, kvm_get_msr, 1);
1831 break;
1832 case KVM_SET_MSRS:
1833 r = msr_io(vcpu, argp, do_set_msr, 0);
1834 break;
b209749f
AK		 1835 case KVM_TPR_ACCESS_REPORTING: {
1836 struct kvm_tpr_access_ctl tac;
1837
1838 r = -EFAULT;
1839 if (copy_from_user(&tac, argp, sizeof tac))
1840 goto out;
1841 r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
1842 if (r)
1843 goto out;
1844 r = -EFAULT;
1845 if (copy_to_user(argp, &tac, sizeof tac))
1846 goto out;
1847 r = 0;
1848 break;
1849 };
b93463aa
AK		 1850 case KVM_SET_VAPIC_ADDR: {
1851 struct kvm_vapic_addr va;
1852
1853 r = -EINVAL;
1854 if (!irqchip_in_kernel(vcpu->kvm))
1855 goto out;
1856 r = -EFAULT;
1857 if (copy_from_user(&va, argp, sizeof va))
1858 goto out;
1859 r = 0;
1860 kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
1861 break;
1862 }
890ca9ae
HY		 1863 case KVM_X86_SETUP_MCE: {
1864 u64 mcg_cap;
1865
1866 r = -EFAULT;
1867 if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
1868 goto out;
1869 r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
1870 break;
1871 }
1872 case KVM_X86_SET_MCE: {
1873 struct kvm_x86_mce mce;
1874
1875 r = -EFAULT;
1876 if (copy_from_user(&mce, argp, sizeof mce))
1877 goto out;
1878 r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
1879 break;
1880 }
313a3dc7
CO		 1881 default:
1882 r = -EINVAL;
1883 }
1884out:
7a6ce84c 1885 kfree(lapic);
313a3dc7
CO		 1886 return r;
1887}
1888
1fe779f8
CO		 1889static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
1890{
1891 int ret;
1892
1893 if (addr > (unsigned int)(-3 * PAGE_SIZE))
1894 return -1;
1895 ret = kvm_x86_ops->set_tss_addr(kvm, addr);
1896 return ret;
1897}
1898
1899static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
1900 u32 kvm_nr_mmu_pages)
1901{
1902 if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
1903 return -EINVAL;
1904
72dc67a6 1905 down_write(&kvm->slots_lock);
7c8a83b7 1906 spin_lock(&kvm->mmu_lock);
1fe779f8
CO		 1907
1908 kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
f05e70ac 1909 kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
1fe779f8 1910
7c8a83b7 1911 spin_unlock(&kvm->mmu_lock);
72dc67a6 1912 up_write(&kvm->slots_lock);
1fe779f8
CO		 1913 return 0;
1914}
1915
1916static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
1917{
f05e70ac 1918 return kvm->arch.n_alloc_mmu_pages;
1fe779f8
CO		 1919}
1920
e9f85cde
ZX		 1921gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
1922{
1923 int i;
1924 struct kvm_mem_alias *alias;
1925
d69fb81f
ZX		 1926 for (i = 0; i < kvm->arch.naliases; ++i) {
1927 alias = &kvm->arch.aliases[i];
e9f85cde
ZX		 1928 if (gfn >= alias->base_gfn
1929 && gfn < alias->base_gfn + alias->npages)
1930 return alias->target_gfn + gfn - alias->base_gfn;
1931 }
1932 return gfn;
1933}
1934
1fe779f8
CO		 1935/*
1936 * Set a new alias region. Aliases map a portion of physical memory into
1937 * another portion. This is useful for memory windows, for example the PC
1938 * VGA region.
1939 */
1940static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
1941 struct kvm_memory_alias *alias)
1942{
1943 int r, n;
1944 struct kvm_mem_alias *p;
1945
1946 r = -EINVAL;
1947 /* General sanity checks */
1948 if (alias->memory_size & (PAGE_SIZE - 1))
1949 goto out;
1950 if (alias->guest_phys_addr & (PAGE_SIZE - 1))
1951 goto out;
1952 if (alias->slot >= KVM_ALIAS_SLOTS)
1953 goto out;
1954 if (alias->guest_phys_addr + alias->memory_size
1955 < alias->guest_phys_addr)
1956 goto out;
1957 if (alias->target_phys_addr + alias->memory_size
1958 < alias->target_phys_addr)
1959 goto out;
1960
72dc67a6 1961 down_write(&kvm->slots_lock);
a1708ce8 1962 spin_lock(&kvm->mmu_lock);
1fe779f8 1963
d69fb81f 1964 p = &kvm->arch.aliases[alias->slot];
1fe779f8
CO		 1965 p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
1966 p->npages = alias->memory_size >> PAGE_SHIFT;
1967 p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
1968
1969 for (n = KVM_ALIAS_SLOTS; n > 0; --n)
d69fb81f 1970 if (kvm->arch.aliases[n - 1].npages)
1fe779f8 1971 break;
d69fb81f 1972 kvm->arch.naliases = n;
1fe779f8 1973
a1708ce8 1974 spin_unlock(&kvm->mmu_lock);
1fe779f8
CO		 1975 kvm_mmu_zap_all(kvm);
1976
72dc67a6 1977 up_write(&kvm->slots_lock);
1fe779f8
CO		 1978
1979 return 0;
1980
1981out:
1982 return r;
1983}
1984
1985static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
1986{
1987 int r;
1988
1989 r = 0;
1990 switch (chip->chip_id) {
1991 case KVM_IRQCHIP_PIC_MASTER:
1992 memcpy(&chip->chip.pic,
1993 &pic_irqchip(kvm)->pics[0],
1994 sizeof(struct kvm_pic_state));
1995 break;
1996 case KVM_IRQCHIP_PIC_SLAVE:
1997 memcpy(&chip->chip.pic,
1998 &pic_irqchip(kvm)->pics[1],
1999 sizeof(struct kvm_pic_state));
2000 break;
2001 case KVM_IRQCHIP_IOAPIC:
2002 memcpy(&chip->chip.ioapic,
2003 ioapic_irqchip(kvm),
2004 sizeof(struct kvm_ioapic_state));
2005 break;
2006 default:
2007 r = -EINVAL;
2008 break;
2009 }
2010 return r;
2011}
2012
2013static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
2014{
2015 int r;
2016
2017 r = 0;
2018 switch (chip->chip_id) {
2019 case KVM_IRQCHIP_PIC_MASTER:
894a9c55 2020 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2021 memcpy(&pic_irqchip(kvm)->pics[0],
2022 &chip->chip.pic,
2023 sizeof(struct kvm_pic_state));
894a9c55 2024 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2025 break;
2026 case KVM_IRQCHIP_PIC_SLAVE:
894a9c55 2027 spin_lock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2028 memcpy(&pic_irqchip(kvm)->pics[1],
2029 &chip->chip.pic,
2030 sizeof(struct kvm_pic_state));
894a9c55 2031 spin_unlock(&pic_irqchip(kvm)->lock);
1fe779f8
CO		 2032 break;
2033 case KVM_IRQCHIP_IOAPIC:
894a9c55 2034 mutex_lock(&kvm->irq_lock);
1fe779f8
CO		 2035 memcpy(ioapic_irqchip(kvm),
2036 &chip->chip.ioapic,
2037 sizeof(struct kvm_ioapic_state));
894a9c55 2038 mutex_unlock(&kvm->irq_lock);
1fe779f8
CO		 2039 break;
2040 default:
2041 r = -EINVAL;
2042 break;
2043 }
2044 kvm_pic_update_irq(pic_irqchip(kvm));
2045 return r;
2046}
2047
e0f63cb9
SY		 2048static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2049{
2050 int r = 0;
2051
894a9c55 2052 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9 2053 memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
894a9c55 2054 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2055 return r;
2056}
2057
2058static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
2059{
2060 int r = 0;
2061
894a9c55 2062 mutex_lock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2063 memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
2064 kvm_pit_load_count(kvm, 0, ps->channels[0].count);
894a9c55 2065 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
e0f63cb9
SY		 2066 return r;
2067}
2068
52d939a0
MT		 2069static int kvm_vm_ioctl_reinject(struct kvm *kvm,
2070 struct kvm_reinject_control *control)
2071{
2072 if (!kvm->arch.vpit)
2073 return -ENXIO;
894a9c55 2074 mutex_lock(&kvm->arch.vpit->pit_state.lock);
52d939a0 2075 kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
894a9c55 2076 mutex_unlock(&kvm->arch.vpit->pit_state.lock);
52d939a0
MT		 2077 return 0;
2078}
2079
5bb064dc
ZX		 2080/*
2081 * Get (and clear) the dirty memory log for a memory slot.
2082 */
2083int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
2084 struct kvm_dirty_log *log)
2085{
2086 int r;
2087 int n;
2088 struct kvm_memory_slot *memslot;
2089 int is_dirty = 0;
2090
72dc67a6 2091 down_write(&kvm->slots_lock);
5bb064dc
ZX		 2092
2093 r = kvm_get_dirty_log(kvm, log, &is_dirty);
2094 if (r)
2095 goto out;
2096
2097 /* If nothing is dirty, don't bother messing with page tables. */
2098 if (is_dirty) {
7c8a83b7 2099 spin_lock(&kvm->mmu_lock);
5bb064dc 2100 kvm_mmu_slot_remove_write_access(kvm, log->slot);
7c8a83b7 2101 spin_unlock(&kvm->mmu_lock);
5bb064dc
ZX		 2102 kvm_flush_remote_tlbs(kvm);
2103 memslot = &kvm->memslots[log->slot];
2104 n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
2105 memset(memslot->dirty_bitmap, 0, n);
2106 }
2107 r = 0;
2108out:
72dc67a6 2109 up_write(&kvm->slots_lock);
5bb064dc
ZX		 2110 return r;
2111}
2112
1fe779f8
CO		 2113long kvm_arch_vm_ioctl(struct file *filp,
2114 unsigned int ioctl, unsigned long arg)
2115{
2116 struct kvm *kvm = filp->private_data;
2117 void __user *argp = (void __user *)arg;
2118 int r = -EINVAL;
f0d66275
DH		 2119 /*
2120 * This union makes it completely explicit to gcc-3.x
2121 * that these two variables' stack usage should be
2122 * combined, not added together.
2123 */
2124 union {
2125 struct kvm_pit_state ps;
2126 struct kvm_memory_alias alias;
c5ff41ce 2127 struct kvm_pit_config pit_config;
f0d66275 2128 } u;
1fe779f8
CO		 2129
2130 switch (ioctl) {
2131 case KVM_SET_TSS_ADDR:
2132 r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
2133 if (r < 0)
2134 goto out;
2135 break;
2136 case KVM_SET_MEMORY_REGION: {
2137 struct kvm_memory_region kvm_mem;
2138 struct kvm_userspace_memory_region kvm_userspace_mem;
2139
2140 r = -EFAULT;
2141 if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
2142 goto out;
2143 kvm_userspace_mem.slot = kvm_mem.slot;
2144 kvm_userspace_mem.flags = kvm_mem.flags;
2145 kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
2146 kvm_userspace_mem.memory_size = kvm_mem.memory_size;
2147 r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
2148 if (r)
2149 goto out;
2150 break;
2151 }
2152 case KVM_SET_NR_MMU_PAGES:
2153 r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
2154 if (r)
2155 goto out;
2156 break;
2157 case KVM_GET_NR_MMU_PAGES:
2158 r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
2159 break;
f0d66275 2160 case KVM_SET_MEMORY_ALIAS:
1fe779f8 2161 r = -EFAULT;
f0d66275 2162 if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
1fe779f8 2163 goto out;
f0d66275 2164 r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
1fe779f8
CO		 2165 if (r)
2166 goto out;
2167 break;
1fe779f8
CO		 2168 case KVM_CREATE_IRQCHIP:
2169 r = -ENOMEM;
d7deeeb0
ZX		 2170 kvm->arch.vpic = kvm_create_pic(kvm);
2171 if (kvm->arch.vpic) {
1fe779f8
CO		 2172 r = kvm_ioapic_init(kvm);
2173 if (r) {
d7deeeb0
ZX		 2174 kfree(kvm->arch.vpic);
2175 kvm->arch.vpic = NULL;
1fe779f8
CO		 2176 goto out;
2177 }
2178 } else
2179 goto out;
399ec807
AK		 2180 r = kvm_setup_default_irq_routing(kvm);
2181 if (r) {
2182 kfree(kvm->arch.vpic);
2183 kfree(kvm->arch.vioapic);
2184 goto out;
2185 }
1fe779f8 2186 break;
7837699f 2187 case KVM_CREATE_PIT:
c5ff41ce
JK		 2188 u.pit_config.flags = KVM_PIT_SPEAKER_DUMMY;
2189 goto create_pit;
2190 case KVM_CREATE_PIT2:
2191 r = -EFAULT;
2192 if (copy_from_user(&u.pit_config, argp,
2193 sizeof(struct kvm_pit_config)))
2194 goto out;
2195 create_pit:
108b5669 2196 down_write(&kvm->slots_lock);
269e05e4
AK		 2197 r = -EEXIST;
2198 if (kvm->arch.vpit)
2199 goto create_pit_unlock;
7837699f 2200 r = -ENOMEM;
c5ff41ce 2201 kvm->arch.vpit = kvm_create_pit(kvm, u.pit_config.flags);
7837699f
SY		 2202 if (kvm->arch.vpit)
2203 r = 0;
269e05e4 2204 create_pit_unlock:
108b5669 2205 up_write(&kvm->slots_lock);
7837699f 2206 break;
4925663a 2207 case KVM_IRQ_LINE_STATUS:
1fe779f8
CO		 2208 case KVM_IRQ_LINE: {
2209 struct kvm_irq_level irq_event;
2210
2211 r = -EFAULT;
2212 if (copy_from_user(&irq_event, argp, sizeof irq_event))
2213 goto out;
2214 if (irqchip_in_kernel(kvm)) {
4925663a 2215 __s32 status;
fa40a821 2216 mutex_lock(&kvm->irq_lock);
4925663a
GN		 2217 status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
2218 irq_event.irq, irq_event.level);
fa40a821 2219 mutex_unlock(&kvm->irq_lock);
4925663a
GN		 2220 if (ioctl == KVM_IRQ_LINE_STATUS) {
2221 irq_event.status = status;
2222 if (copy_to_user(argp, &irq_event,
2223 sizeof irq_event))
2224 goto out;
2225 }
1fe779f8
CO		 2226 r = 0;
2227 }
2228 break;
2229 }
2230 case KVM_GET_IRQCHIP: {
2231 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2232 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2233
f0d66275
DH		 2234 r = -ENOMEM;
2235 if (!chip)
1fe779f8 2236 goto out;
f0d66275
DH		 2237 r = -EFAULT;
2238 if (copy_from_user(chip, argp, sizeof *chip))
2239 goto get_irqchip_out;
1fe779f8
CO		 2240 r = -ENXIO;
2241 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2242 goto get_irqchip_out;
2243 r = kvm_vm_ioctl_get_irqchip(kvm, chip);
1fe779f8 2244 if (r)
f0d66275 2245 goto get_irqchip_out;
1fe779f8 2246 r = -EFAULT;
f0d66275
DH		 2247 if (copy_to_user(argp, chip, sizeof *chip))
2248 goto get_irqchip_out;
1fe779f8 2249 r = 0;
f0d66275
DH		 2250 get_irqchip_out:
2251 kfree(chip);
2252 if (r)
2253 goto out;
1fe779f8
CO		 2254 break;
2255 }
2256 case KVM_SET_IRQCHIP: {
2257 /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
f0d66275 2258 struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
1fe779f8 2259
f0d66275
DH		 2260 r = -ENOMEM;
2261 if (!chip)
1fe779f8 2262 goto out;
f0d66275
DH		 2263 r = -EFAULT;
2264 if (copy_from_user(chip, argp, sizeof *chip))
2265 goto set_irqchip_out;
1fe779f8
CO		 2266 r = -ENXIO;
2267 if (!irqchip_in_kernel(kvm))
f0d66275
DH		 2268 goto set_irqchip_out;
2269 r = kvm_vm_ioctl_set_irqchip(kvm, chip);
1fe779f8 2270 if (r)
f0d66275 2271 goto set_irqchip_out;
1fe779f8 2272 r = 0;
f0d66275
DH		 2273 set_irqchip_out:
2274 kfree(chip);
2275 if (r)
2276 goto out;
1fe779f8
CO		 2277 break;
2278 }
e0f63cb9 2279 case KVM_GET_PIT: {
e0f63cb9 2280 r = -EFAULT;
f0d66275 2281 if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2282 goto out;
2283 r = -ENXIO;
2284 if (!kvm->arch.vpit)
2285 goto out;
f0d66275 2286 r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
e0f63cb9
SY		 2287 if (r)
2288 goto out;
2289 r = -EFAULT;
f0d66275 2290 if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
e0f63cb9
SY		 2291 goto out;
2292 r = 0;
2293 break;
2294 }
2295 case KVM_SET_PIT: {
e0f63cb9 2296 r = -EFAULT;
f0d66275 2297 if (copy_from_user(&u.ps, argp, sizeof u.ps))
e0f63cb9
SY		 2298 goto out;
2299 r = -ENXIO;
2300 if (!kvm->arch.vpit)
2301 goto out;
f0d66275 2302 r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
e0f63cb9
SY		 2303 if (r)
2304 goto out;
2305 r = 0;
2306 break;
2307 }
52d939a0
MT		 2308 case KVM_REINJECT_CONTROL: {
2309 struct kvm_reinject_control control;
2310 r = -EFAULT;
2311 if (copy_from_user(&control, argp, sizeof(control)))
2312 goto out;
2313 r = kvm_vm_ioctl_reinject(kvm, &control);
2314 if (r)
2315 goto out;
2316 r = 0;
2317 break;
2318 }
1fe779f8
CO		 2319 default:
2320 ;
2321 }
2322out:
2323 return r;
2324}
2325
a16b043c 2326static void kvm_init_msr_list(void)
043405e1
CO		 2327{
2328 u32 dummy[2];
2329 unsigned i, j;
2330
2331 for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
2332 if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
2333 continue;
2334 if (j < i)
2335 msrs_to_save[j] = msrs_to_save[i];
2336 j++;
2337 }
2338 num_msrs_to_save = j;
2339}
2340
bda9020e
MT		 2341static int vcpu_mmio_write(struct kvm_vcpu *vcpu, gpa_t addr, int len,
2342 const void *v)
bbd9b64e 2343{
bda9020e
MT		 2344 if (vcpu->arch.apic &&
2345 !kvm_iodevice_write(&vcpu->arch.apic->dev, addr, len, v))
2346 return 0;
bbd9b64e 2347
bda9020e 2348 return kvm_io_bus_write(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2349}
2350
bda9020e 2351static int vcpu_mmio_read(struct kvm_vcpu *vcpu, gpa_t addr, int len, void *v)
bbd9b64e 2352{
bda9020e
MT		 2353 if (vcpu->arch.apic &&
2354 !kvm_iodevice_read(&vcpu->arch.apic->dev, addr, len, v))
2355 return 0;
bbd9b64e 2356
bda9020e 2357 return kvm_io_bus_read(&vcpu->kvm->mmio_bus, addr, len, v);
bbd9b64e
CO		 2358}
2359
cded19f3
HE		 2360static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
2361 struct kvm_vcpu *vcpu)
bbd9b64e
CO		 2362{
2363 void *data = val;
10589a46 2364 int r = X86EMUL_CONTINUE;
bbd9b64e
CO		 2365
2366 while (bytes) {
ad312c7c 2367 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e 2368 unsigned offset = addr & (PAGE_SIZE-1);
77c2002e 2369 unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
bbd9b64e
CO		 2370 int ret;
2371
10589a46
MT		 2372 if (gpa == UNMAPPED_GVA) {
2373 r = X86EMUL_PROPAGATE_FAULT;
2374 goto out;
2375 }
77c2002e 2376 ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
10589a46
MT		 2377 if (ret < 0) {
2378 r = X86EMUL_UNHANDLEABLE;
2379 goto out;
2380 }
bbd9b64e 2381
77c2002e
IE		 2382 bytes -= toread;
2383 data += toread;
2384 addr += toread;
bbd9b64e 2385 }
10589a46 2386out:
10589a46 2387 return r;
bbd9b64e 2388}
77c2002e 2389
cded19f3
HE		 2390static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
2391 struct kvm_vcpu *vcpu)
77c2002e
IE		 2392{
2393 void *data = val;
2394 int r = X86EMUL_CONTINUE;
2395
2396 while (bytes) {
2397 gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2398 unsigned offset = addr & (PAGE_SIZE-1);
2399 unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
2400 int ret;
2401
2402 if (gpa == UNMAPPED_GVA) {
2403 r = X86EMUL_PROPAGATE_FAULT;
2404 goto out;
2405 }
2406 ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
2407 if (ret < 0) {
2408 r = X86EMUL_UNHANDLEABLE;
2409 goto out;
2410 }
2411
2412 bytes -= towrite;
2413 data += towrite;
2414 addr += towrite;
2415 }
2416out:
2417 return r;
2418}
2419
bbd9b64e 2420
bbd9b64e
CO		 2421static int emulator_read_emulated(unsigned long addr,
2422 void *val,
2423 unsigned int bytes,
2424 struct kvm_vcpu *vcpu)
2425{
bbd9b64e
CO		 2426 gpa_t gpa;
2427
2428 if (vcpu->mmio_read_completed) {
2429 memcpy(val, vcpu->mmio_data, bytes);
aec51dc4
AK		 2430 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes,
2431 vcpu->mmio_phys_addr, *(u64 *)val);
bbd9b64e
CO		 2432 vcpu->mmio_read_completed = 0;
2433 return X86EMUL_CONTINUE;
2434 }
2435
ad312c7c 2436 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2437
2438 /* For APIC access vmexit */
2439 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2440 goto mmio;
2441
77c2002e
IE		 2442 if (kvm_read_guest_virt(addr, val, bytes, vcpu)
2443 == X86EMUL_CONTINUE)
bbd9b64e
CO		 2444 return X86EMUL_CONTINUE;
2445 if (gpa == UNMAPPED_GVA)
2446 return X86EMUL_PROPAGATE_FAULT;
2447
2448mmio:
2449 /*
2450 * Is this MMIO handled locally?
2451 */
aec51dc4
AK		 2452 if (!vcpu_mmio_read(vcpu, gpa, bytes, val)) {
2453 trace_kvm_mmio(KVM_TRACE_MMIO_READ, bytes, gpa, *(u64 *)val);
bbd9b64e 2454 return X86EMUL_CONTINUE;
aec51dc4
AK		 2455 }
2456
2457 trace_kvm_mmio(KVM_TRACE_MMIO_READ_UNSATISFIED, bytes, gpa, 0);
bbd9b64e
CO		 2458
2459 vcpu->mmio_needed = 1;
2460 vcpu->mmio_phys_addr = gpa;
2461 vcpu->mmio_size = bytes;
2462 vcpu->mmio_is_write = 0;
2463
2464 return X86EMUL_UNHANDLEABLE;
2465}
2466
3200f405 2467int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
9f811285 2468 const void *val, int bytes)
bbd9b64e
CO		 2469{
2470 int ret;
2471
2472 ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
9f811285 2473 if (ret < 0)
bbd9b64e 2474 return 0;
ad218f85 2475 kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
bbd9b64e
CO		 2476 return 1;
2477}
2478
2479static int emulator_write_emulated_onepage(unsigned long addr,
2480 const void *val,
2481 unsigned int bytes,
2482 struct kvm_vcpu *vcpu)
2483{
10589a46
MT		 2484 gpa_t gpa;
2485
10589a46 2486 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
bbd9b64e
CO		 2487
2488 if (gpa == UNMAPPED_GVA) {
c3c91fee 2489 kvm_inject_page_fault(vcpu, addr, 2);
bbd9b64e
CO		 2490 return X86EMUL_PROPAGATE_FAULT;
2491 }
2492
2493 /* For APIC access vmexit */
2494 if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2495 goto mmio;
2496
2497 if (emulator_write_phys(vcpu, gpa, val, bytes))
2498 return X86EMUL_CONTINUE;
2499
2500mmio:
aec51dc4 2501 trace_kvm_mmio(KVM_TRACE_MMIO_WRITE, bytes, gpa, *(u64 *)val);
bbd9b64e
CO		 2502 /*
2503 * Is this MMIO handled locally?
2504 */
bda9020e 2505 if (!vcpu_mmio_write(vcpu, gpa, bytes, val))
bbd9b64e 2506 return X86EMUL_CONTINUE;
bbd9b64e
CO		 2507
2508 vcpu->mmio_needed = 1;
2509 vcpu->mmio_phys_addr = gpa;
2510 vcpu->mmio_size = bytes;
2511 vcpu->mmio_is_write = 1;
2512 memcpy(vcpu->mmio_data, val, bytes);
2513
2514 return X86EMUL_CONTINUE;
2515}
2516
2517int emulator_write_emulated(unsigned long addr,
2518 const void *val,
2519 unsigned int bytes,
2520 struct kvm_vcpu *vcpu)
2521{
2522 /* Crossing a page boundary? */
2523 if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
2524 int rc, now;
2525
2526 now = -addr & ~PAGE_MASK;
2527 rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
2528 if (rc != X86EMUL_CONTINUE)
2529 return rc;
2530 addr += now;
2531 val += now;
2532 bytes -= now;
2533 }
2534 return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
2535}
2536EXPORT_SYMBOL_GPL(emulator_write_emulated);
2537
2538static int emulator_cmpxchg_emulated(unsigned long addr,
2539 const void *old,
2540 const void *new,
2541 unsigned int bytes,
2542 struct kvm_vcpu *vcpu)
2543{
2544 static int reported;
2545
2546 if (!reported) {
2547 reported = 1;
2548 printk(KERN_WARNING "kvm: emulating exchange as write\n");
2549 }
2bacc55c
MT		 2550#ifndef CONFIG_X86_64
2551 /* guests cmpxchg8b have to be emulated atomically */
2552 if (bytes == 8) {
10589a46 2553 gpa_t gpa;
2bacc55c 2554 struct page *page;
c0b49b0d 2555 char *kaddr;
2bacc55c
MT		 2556 u64 val;
2557
10589a46
MT		 2558 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
2559
2bacc55c
MT		 2560 if (gpa == UNMAPPED_GVA ||
2561 (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
2562 goto emul_write;
2563
2564 if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
2565 goto emul_write;
2566
2567 val = *(u64 *)new;
72dc67a6 2568
2bacc55c 2569 page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
72dc67a6 2570
c0b49b0d
AM		 2571 kaddr = kmap_atomic(page, KM_USER0);
2572 set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
2573 kunmap_atomic(kaddr, KM_USER0);
2bacc55c
MT		 2574 kvm_release_page_dirty(page);
2575 }
3200f405 2576emul_write:
2bacc55c
MT		 2577#endif
2578
bbd9b64e
CO		 2579 return emulator_write_emulated(addr, new, bytes, vcpu);
2580}
2581
2582static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
2583{
2584 return kvm_x86_ops->get_segment_base(vcpu, seg);
2585}
2586
2587int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
2588{
a7052897 2589 kvm_mmu_invlpg(vcpu, address);
bbd9b64e
CO		 2590 return X86EMUL_CONTINUE;
2591}
2592
2593int emulate_clts(struct kvm_vcpu *vcpu)
2594{
ad312c7c 2595 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
bbd9b64e
CO		 2596 return X86EMUL_CONTINUE;
2597}
2598
2599int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
2600{
2601 struct kvm_vcpu *vcpu = ctxt->vcpu;
2602
2603 switch (dr) {
2604 case 0 ... 3:
2605 *dest = kvm_x86_ops->get_dr(vcpu, dr);
2606 return X86EMUL_CONTINUE;
2607 default:
b8688d51 2608 pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
bbd9b64e
CO		 2609 return X86EMUL_UNHANDLEABLE;
2610 }
2611}
2612
2613int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
2614{
2615 unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
2616 int exception;
2617
2618 kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
2619 if (exception) {
2620 /* FIXME: better handling */
2621 return X86EMUL_UNHANDLEABLE;
2622 }
2623 return X86EMUL_CONTINUE;
2624}
2625
2626void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
2627{
bbd9b64e 2628 u8 opcodes[4];
5fdbf976 2629 unsigned long rip = kvm_rip_read(vcpu);
bbd9b64e
CO		 2630 unsigned long rip_linear;
2631
f76c710d 2632 if (!printk_ratelimit())
bbd9b64e
CO		 2633 return;
2634
25be4608
GC		 2635 rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
2636
77c2002e 2637 kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
bbd9b64e
CO		 2638
2639 printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
2640 context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
bbd9b64e
CO		 2641}
2642EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
2643
14af3f3c 2644static struct x86_emulate_ops emulate_ops = {
77c2002e 2645 .read_std = kvm_read_guest_virt,
bbd9b64e
CO		 2646 .read_emulated = emulator_read_emulated,
2647 .write_emulated = emulator_write_emulated,
2648 .cmpxchg_emulated = emulator_cmpxchg_emulated,
2649};
2650
5fdbf976
MT		 2651static void cache_all_regs(struct kvm_vcpu *vcpu)
2652{
2653 kvm_register_read(vcpu, VCPU_REGS_RAX);
2654 kvm_register_read(vcpu, VCPU_REGS_RSP);
2655 kvm_register_read(vcpu, VCPU_REGS_RIP);
2656 vcpu->arch.regs_dirty = ~0;
2657}
2658
bbd9b64e
CO		 2659int emulate_instruction(struct kvm_vcpu *vcpu,
2660 struct kvm_run *run,
2661 unsigned long cr2,
2662 u16 error_code,
571008da 2663 int emulation_type)
bbd9b64e 2664{
310b5d30 2665 int r, shadow_mask;
571008da 2666 struct decode_cache *c;
bbd9b64e 2667
26eef70c 2668 kvm_clear_exception_queue(vcpu);
ad312c7c 2669 vcpu->arch.mmio_fault_cr2 = cr2;
5fdbf976
MT		 2670 /*
2671 * TODO: fix x86_emulate.c to use guest_read/write_register
2672 * instead of direct ->regs accesses, can save hundred cycles
2673 * on Intel for instructions that don't read/change RSP, for
2674 * for example.
2675 */
2676 cache_all_regs(vcpu);
bbd9b64e
CO		 2677
2678 vcpu->mmio_is_write = 0;
ad312c7c 2679 vcpu->arch.pio.string = 0;
bbd9b64e 2680
571008da 2681 if (!(emulation_type & EMULTYPE_NO_DECODE)) {
bbd9b64e
CO		 2682 int cs_db, cs_l;
2683 kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
2684
ad312c7c
ZX		 2685 vcpu->arch.emulate_ctxt.vcpu = vcpu;
2686 vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
2687 vcpu->arch.emulate_ctxt.mode =
2688 (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
bbd9b64e
CO		 2689 ? X86EMUL_MODE_REAL : cs_l
2690 ? X86EMUL_MODE_PROT64 : cs_db
2691 ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
2692
ad312c7c 2693 r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
571008da 2694
0cb5762e
AP		 2695 /* Only allow emulation of specific instructions on #UD
2696 * (namely VMMCALL, sysenter, sysexit, syscall)*/
571008da 2697 c = &vcpu->arch.emulate_ctxt.decode;
0cb5762e
AP		 2698 if (emulation_type & EMULTYPE_TRAP_UD) {
2699 if (!c->twobyte)
2700 return EMULATE_FAIL;
2701 switch (c->b) {
2702 case 0x01: /* VMMCALL */
2703 if (c->modrm_mod != 3 || c->modrm_rm != 1)
2704 return EMULATE_FAIL;
2705 break;
2706 case 0x34: /* sysenter */
2707 case 0x35: /* sysexit */
2708 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2709 return EMULATE_FAIL;
2710 break;
2711 case 0x05: /* syscall */
2712 if (c->modrm_mod != 0 || c->modrm_rm != 0)
2713 return EMULATE_FAIL;
2714 break;
2715 default:
2716 return EMULATE_FAIL;
2717 }
2718
2719 if (!(c->modrm_reg == 0 || c->modrm_reg == 3))
2720 return EMULATE_FAIL;
2721 }
571008da 2722
f2b5756b 2723 ++vcpu->stat.insn_emulation;
bbd9b64e 2724 if (r) {
f2b5756b 2725 ++vcpu->stat.insn_emulation_fail;
bbd9b64e
CO		 2726 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2727 return EMULATE_DONE;
2728 return EMULATE_FAIL;
2729 }
2730 }
2731
ba8afb6b
GN		 2732 if (emulation_type & EMULTYPE_SKIP) {
2733 kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
2734 return EMULATE_DONE;
2735 }
2736
ad312c7c 2737 r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
310b5d30
GC		 2738 shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
2739
2740 if (r == 0)
2741 kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
bbd9b64e 2742
ad312c7c 2743 if (vcpu->arch.pio.string)
bbd9b64e
CO		 2744 return EMULATE_DO_MMIO;
2745
2746 if ((r || vcpu->mmio_is_write) && run) {
2747 run->exit_reason = KVM_EXIT_MMIO;
2748 run->mmio.phys_addr = vcpu->mmio_phys_addr;
2749 memcpy(run->mmio.data, vcpu->mmio_data, 8);
2750 run->mmio.len = vcpu->mmio_size;
2751 run->mmio.is_write = vcpu->mmio_is_write;
2752 }
2753
2754 if (r) {
2755 if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
2756 return EMULATE_DONE;
2757 if (!vcpu->mmio_needed) {
2758 kvm_report_emulation_failure(vcpu, "mmio");
2759 return EMULATE_FAIL;
2760 }
2761 return EMULATE_DO_MMIO;
2762 }
2763
ad312c7c 2764 kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
bbd9b64e
CO		 2765
2766 if (vcpu->mmio_is_write) {
2767 vcpu->mmio_needed = 0;
2768 return EMULATE_DO_MMIO;
2769 }
2770
2771 return EMULATE_DONE;
2772}
2773EXPORT_SYMBOL_GPL(emulate_instruction);
2774
de7d789a
CO		 2775static int pio_copy_data(struct kvm_vcpu *vcpu)
2776{
ad312c7c 2777 void *p = vcpu->arch.pio_data;
0f346074 2778 gva_t q = vcpu->arch.pio.guest_gva;
de7d789a 2779 unsigned bytes;
0f346074 2780 int ret;
de7d789a 2781
ad312c7c
ZX		 2782 bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
2783 if (vcpu->arch.pio.in)
0f346074 2784 ret = kvm_write_guest_virt(q, p, bytes, vcpu);
de7d789a 2785 else
0f346074
IE		 2786 ret = kvm_read_guest_virt(q, p, bytes, vcpu);
2787 return ret;
de7d789a
CO		 2788}
2789
2790int complete_pio(struct kvm_vcpu *vcpu)
2791{
ad312c7c 2792 struct kvm_pio_request *io = &vcpu->arch.pio;
de7d789a
CO		 2793 long delta;
2794 int r;
5fdbf976 2795 unsigned long val;
de7d789a
CO		 2796
2797 if (!io->string) {
5fdbf976
MT		 2798 if (io->in) {
2799 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2800 memcpy(&val, vcpu->arch.pio_data, io->size);
2801 kvm_register_write(vcpu, VCPU_REGS_RAX, val);
2802 }
de7d789a
CO		 2803 } else {
2804 if (io->in) {
2805 r = pio_copy_data(vcpu);
5fdbf976 2806 if (r)
de7d789a 2807 return r;
de7d789a
CO		 2808 }
2809
2810 delta = 1;
2811 if (io->rep) {
2812 delta *= io->cur_count;
2813 /*
2814 * The size of the register should really depend on
2815 * current address size.
2816 */
5fdbf976
MT		 2817 val = kvm_register_read(vcpu, VCPU_REGS_RCX);
2818 val -= delta;
2819 kvm_register_write(vcpu, VCPU_REGS_RCX, val);
de7d789a
CO		 2820 }
2821 if (io->down)
2822 delta = -delta;
2823 delta *= io->size;
5fdbf976
MT		 2824 if (io->in) {
2825 val = kvm_register_read(vcpu, VCPU_REGS_RDI);
2826 val += delta;
2827 kvm_register_write(vcpu, VCPU_REGS_RDI, val);
2828 } else {
2829 val = kvm_register_read(vcpu, VCPU_REGS_RSI);
2830 val += delta;
2831 kvm_register_write(vcpu, VCPU_REGS_RSI, val);
2832 }
de7d789a
CO		 2833 }
2834
de7d789a
CO		 2835 io->count -= io->cur_count;
2836 io->cur_count = 0;
2837
2838 return 0;
2839}
2840
bda9020e 2841static int kernel_pio(struct kvm_vcpu *vcpu, void *pd)
de7d789a
CO		 2842{
2843 /* TODO: String I/O for in kernel device */
bda9020e 2844 int r;
de7d789a 2845
ad312c7c 2846 if (vcpu->arch.pio.in)
bda9020e
MT		 2847 r = kvm_io_bus_read(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2848 vcpu->arch.pio.size, pd);
de7d789a 2849 else
bda9020e
MT		 2850 r = kvm_io_bus_write(&vcpu->kvm->pio_bus, vcpu->arch.pio.port,
2851 vcpu->arch.pio.size, pd);
2852 return r;
de7d789a
CO		 2853}
2854
bda9020e 2855static int pio_string_write(struct kvm_vcpu *vcpu)
de7d789a 2856{
ad312c7c
ZX		 2857 struct kvm_pio_request *io = &vcpu->arch.pio;
2858 void *pd = vcpu->arch.pio_data;
bda9020e 2859 int i, r = 0;
de7d789a 2860
de7d789a 2861 for (i = 0; i < io->cur_count; i++) {
bda9020e
MT		 2862 if (kvm_io_bus_write(&vcpu->kvm->pio_bus,
2863 io->port, io->size, pd)) {
2864 r = -EOPNOTSUPP;
2865 break;
2866 }
de7d789a
CO		 2867 pd += io->size;
2868 }
bda9020e 2869 return r;
de7d789a
CO		 2870}
2871
2872int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2873 int size, unsigned port)
2874{
5fdbf976 2875 unsigned long val;
de7d789a
CO		 2876
2877 vcpu->run->exit_reason = KVM_EXIT_IO;
2878 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2879 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2880 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2881 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
2882 vcpu->run->io.port = vcpu->arch.pio.port = port;
2883 vcpu->arch.pio.in = in;
2884 vcpu->arch.pio.string = 0;
2885 vcpu->arch.pio.down = 0;
ad312c7c 2886 vcpu->arch.pio.rep = 0;
de7d789a 2887
229456fc
MT		 2888 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2889 size, 1);
2714d1d3 2890
5fdbf976
MT		 2891 val = kvm_register_read(vcpu, VCPU_REGS_RAX);
2892 memcpy(vcpu->arch.pio_data, &val, 4);
de7d789a 2893
bda9020e 2894 if (!kernel_pio(vcpu, vcpu->arch.pio_data)) {
de7d789a
CO		 2895 complete_pio(vcpu);
2896 return 1;
2897 }
2898 return 0;
2899}
2900EXPORT_SYMBOL_GPL(kvm_emulate_pio);
2901
2902int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
2903 int size, unsigned long count, int down,
2904 gva_t address, int rep, unsigned port)
2905{
2906 unsigned now, in_page;
0f346074 2907 int ret = 0;
de7d789a
CO		 2908
2909 vcpu->run->exit_reason = KVM_EXIT_IO;
2910 vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
ad312c7c 2911 vcpu->run->io.size = vcpu->arch.pio.size = size;
de7d789a 2912 vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
ad312c7c
ZX		 2913 vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
2914 vcpu->run->io.port = vcpu->arch.pio.port = port;
2915 vcpu->arch.pio.in = in;
2916 vcpu->arch.pio.string = 1;
2917 vcpu->arch.pio.down = down;
ad312c7c 2918 vcpu->arch.pio.rep = rep;
de7d789a 2919
229456fc
MT		 2920 trace_kvm_pio(vcpu->run->io.direction == KVM_EXIT_IO_OUT, port,
2921 size, count);
2714d1d3 2922
de7d789a
CO		 2923 if (!count) {
2924 kvm_x86_ops->skip_emulated_instruction(vcpu);
2925 return 1;
2926 }
2927
2928 if (!down)
2929 in_page = PAGE_SIZE - offset_in_page(address);
2930 else
2931 in_page = offset_in_page(address) + size;
2932 now = min(count, (unsigned long)in_page / size);
0f346074 2933 if (!now)
de7d789a 2934 now = 1;
de7d789a
CO		 2935 if (down) {
2936 /*
2937 * String I/O in reverse. Yuck. Kill the guest, fix later.
2938 */
2939 pr_unimpl(vcpu, "guest string pio down\n");
c1a5d4f9 2940 kvm_inject_gp(vcpu, 0);
de7d789a
CO		 2941 return 1;
2942 }
2943 vcpu->run->io.count = now;
ad312c7c 2944 vcpu->arch.pio.cur_count = now;
de7d789a 2945
ad312c7c 2946 if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
de7d789a
CO		 2947 kvm_x86_ops->skip_emulated_instruction(vcpu);
2948
0f346074 2949 vcpu->arch.pio.guest_gva = address;
de7d789a 2950
ad312c7c 2951 if (!vcpu->arch.pio.in) {
de7d789a
CO		 2952 /* string PIO write */
2953 ret = pio_copy_data(vcpu);
0f346074
IE		 2954 if (ret == X86EMUL_PROPAGATE_FAULT) {
2955 kvm_inject_gp(vcpu, 0);
2956 return 1;
2957 }
bda9020e 2958 if (ret == 0 && !pio_string_write(vcpu)) {
de7d789a 2959 complete_pio(vcpu);
ad312c7c 2960 if (vcpu->arch.pio.count == 0)
de7d789a
CO		 2961 ret = 1;
2962 }
bda9020e
MT		 2963 }
2964 /* no string PIO read support yet */
de7d789a
CO		 2965
2966 return ret;
2967}
2968EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
2969
c8076604
GH		 2970static void bounce_off(void *info)
2971{
2972 /* nothing */
2973}
2974
2975static unsigned int ref_freq;
2976static unsigned long tsc_khz_ref;
2977
2978static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
2979 void *data)
2980{
2981 struct cpufreq_freqs *freq = data;
2982 struct kvm *kvm;
2983 struct kvm_vcpu *vcpu;
2984 int i, send_ipi = 0;
2985
2986 if (!ref_freq)
2987 ref_freq = freq->old;
2988
2989 if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
2990 return 0;
2991 if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
2992 return 0;
2993 per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
2994
2995 spin_lock(&kvm_lock);
2996 list_for_each_entry(kvm, &vm_list, vm_list) {
988a2cae 2997 kvm_for_each_vcpu(i, vcpu, kvm) {
c8076604
GH		 2998 if (vcpu->cpu != freq->cpu)
2999 continue;
3000 if (!kvm_request_guest_time_update(vcpu))
3001 continue;
3002 if (vcpu->cpu != smp_processor_id())
3003 send_ipi++;
3004 }
3005 }
3006 spin_unlock(&kvm_lock);
3007
3008 if (freq->old < freq->new && send_ipi) {
3009 /*
3010 * We upscale the frequency. Must make the guest
3011 * doesn't see old kvmclock values while running with
3012 * the new frequency, otherwise we risk the guest sees
3013 * time go backwards.
3014 *
3015 * In case we update the frequency for another cpu
3016 * (which might be in guest context) send an interrupt
3017 * to kick the cpu out of guest context. Next time
3018 * guest context is entered kvmclock will be updated,
3019 * so the guest will not see stale values.
3020 */
3021 smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
3022 }
3023 return 0;
3024}
3025
3026static struct notifier_block kvmclock_cpufreq_notifier_block = {
3027 .notifier_call = kvmclock_cpufreq_notifier
3028};
3029
f8c16bba 3030int kvm_arch_init(void *opaque)
043405e1 3031{
c8076604 3032 int r, cpu;
f8c16bba
ZX		 3033 struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
3034
f8c16bba
ZX		 3035 if (kvm_x86_ops) {
3036 printk(KERN_ERR "kvm: already loaded the other module\n");
56c6d28a
ZX		 3037 r = -EEXIST;
3038 goto out;
f8c16bba
ZX		 3039 }
3040
3041 if (!ops->cpu_has_kvm_support()) {
3042 printk(KERN_ERR "kvm: no hardware support\n");
56c6d28a
ZX		 3043 r = -EOPNOTSUPP;
3044 goto out;
f8c16bba
ZX		 3045 }
3046 if (ops->disabled_by_bios()) {
3047 printk(KERN_ERR "kvm: disabled by bios\n");
56c6d28a
ZX		 3048 r = -EOPNOTSUPP;
3049 goto out;
f8c16bba
ZX		 3050 }
3051
97db56ce
AK		 3052 r = kvm_mmu_module_init();
3053 if (r)
3054 goto out;
3055
3056 kvm_init_msr_list();
3057
f8c16bba 3058 kvm_x86_ops = ops;
56c6d28a 3059 kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
7b52345e
SY		 3060 kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
3061 kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
4b12f0de 3062 PT_DIRTY_MASK, PT64_NX_MASK, 0);
c8076604
GH		 3063
3064 for_each_possible_cpu(cpu)
3065 per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
3066 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
3067 tsc_khz_ref = tsc_khz;
3068 cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
3069 CPUFREQ_TRANSITION_NOTIFIER);
3070 }
3071
f8c16bba 3072 return 0;
56c6d28a
ZX		 3073
3074out:
56c6d28a 3075 return r;
043405e1 3076}
8776e519 3077
f8c16bba
ZX		 3078void kvm_arch_exit(void)
3079{
888d256e
JK		 3080 if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
3081 cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
3082 CPUFREQ_TRANSITION_NOTIFIER);
f8c16bba 3083 kvm_x86_ops = NULL;
56c6d28a
ZX		 3084 kvm_mmu_module_exit();
3085}
f8c16bba 3086
8776e519
HB		 3087int kvm_emulate_halt(struct kvm_vcpu *vcpu)
3088{
3089 ++vcpu->stat.halt_exits;
3090 if (irqchip_in_kernel(vcpu->kvm)) {
a4535290 3091 vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
8776e519
HB		 3092 return 1;
3093 } else {
3094 vcpu->run->exit_reason = KVM_EXIT_HLT;
3095 return 0;
3096 }
3097}
3098EXPORT_SYMBOL_GPL(kvm_emulate_halt);
3099
2f333bcb
MT		 3100static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
3101 unsigned long a1)
3102{
3103 if (is_long_mode(vcpu))
3104 return a0;
3105 else
3106 return a0 | ((gpa_t)a1 << 32);
3107}
3108
8776e519
HB		 3109int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
3110{
3111 unsigned long nr, a0, a1, a2, a3, ret;
2f333bcb 3112 int r = 1;
8776e519 3113
5fdbf976
MT		 3114 nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
3115 a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
3116 a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
3117 a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
3118 a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
8776e519 3119
229456fc 3120 trace_kvm_hypercall(nr, a0, a1, a2, a3);
2714d1d3 3121
8776e519
HB		 3122 if (!is_long_mode(vcpu)) {
3123 nr &= 0xFFFFFFFF;
3124 a0 &= 0xFFFFFFFF;
3125 a1 &= 0xFFFFFFFF;
3126 a2 &= 0xFFFFFFFF;
3127 a3 &= 0xFFFFFFFF;
3128 }
3129
3130 switch (nr) {
b93463aa
AK		 3131 case KVM_HC_VAPIC_POLL_IRQ:
3132 ret = 0;
3133 break;
2f333bcb
MT		 3134 case KVM_HC_MMU_OP:
3135 r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
3136 break;
8776e519
HB		 3137 default:
3138 ret = -KVM_ENOSYS;
3139 break;
3140 }
5fdbf976 3141 kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
f11c3a8d 3142 ++vcpu->stat.hypercalls;
2f333bcb 3143 return r;
8776e519
HB		 3144}
3145EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
3146
3147int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
3148{
3149 char instruction[3];
3150 int ret = 0;
5fdbf976 3151 unsigned long rip = kvm_rip_read(vcpu);
8776e519 3152
8776e519
HB		 3153
3154 /*
3155 * Blow out the MMU to ensure that no other VCPU has an active mapping
3156 * to ensure that the updated hypercall appears atomically across all
3157 * VCPUs.
3158 */
3159 kvm_mmu_zap_all(vcpu->kvm);
3160
8776e519 3161 kvm_x86_ops->patch_hypercall(vcpu, instruction);
5fdbf976 3162 if (emulator_write_emulated(rip, instruction, 3, vcpu)
8776e519
HB		 3163 != X86EMUL_CONTINUE)
3164 ret = -EFAULT;
3165
8776e519
HB		 3166 return ret;
3167}
3168
3169static u64 mk_cr_64(u64 curr_cr, u32 new_val)
3170{
3171 return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
3172}
3173
3174void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3175{
3176 struct descriptor_table dt = { limit, base };
3177
3178 kvm_x86_ops->set_gdt(vcpu, &dt);
3179}
3180
3181void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
3182{
3183 struct descriptor_table dt = { limit, base };
3184
3185 kvm_x86_ops->set_idt(vcpu, &dt);
3186}
3187
3188void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
3189 unsigned long *rflags)
3190{
2d3ad1f4 3191 kvm_lmsw(vcpu, msw);
8776e519
HB		 3192 *rflags = kvm_x86_ops->get_rflags(vcpu);
3193}
3194
3195unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3196{
54e445ca
JR		 3197 unsigned long value;
3198
8776e519
HB		 3199 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3200 switch (cr) {
3201 case 0:
54e445ca
JR		 3202 value = vcpu->arch.cr0;
3203 break;
8776e519 3204 case 2:
54e445ca
JR		 3205 value = vcpu->arch.cr2;
3206 break;
8776e519 3207 case 3:
54e445ca
JR		 3208 value = vcpu->arch.cr3;
3209 break;
8776e519 3210 case 4:
54e445ca
JR		 3211 value = vcpu->arch.cr4;
3212 break;
152ff9be 3213 case 8:
54e445ca
JR		 3214 value = kvm_get_cr8(vcpu);
3215 break;
8776e519 3216 default:
b8688d51 3217 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3218 return 0;
3219 }
54e445ca
JR		 3220
3221 return value;
8776e519
HB		 3222}
3223
3224void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
3225 unsigned long *rflags)
3226{
3227 switch (cr) {
3228 case 0:
2d3ad1f4 3229 kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
8776e519
HB		 3230 *rflags = kvm_x86_ops->get_rflags(vcpu);
3231 break;
3232 case 2:
ad312c7c 3233 vcpu->arch.cr2 = val;
8776e519
HB		 3234 break;
3235 case 3:
2d3ad1f4 3236 kvm_set_cr3(vcpu, val);
8776e519
HB		 3237 break;
3238 case 4:
2d3ad1f4 3239 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
8776e519 3240 break;
152ff9be 3241 case 8:
2d3ad1f4 3242 kvm_set_cr8(vcpu, val & 0xfUL);
152ff9be 3243 break;
8776e519 3244 default:
b8688d51 3245 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
8776e519
HB		 3246 }
3247}
3248
07716717
DK		 3249static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
3250{
ad312c7c
ZX		 3251 struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
3252 int j, nent = vcpu->arch.cpuid_nent;
07716717
DK		 3253
3254 e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
3255 /* when no next entry is found, the current entry[i] is reselected */
0fdf8e59 3256 for (j = i + 1; ; j = (j + 1) % nent) {
ad312c7c 3257 struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
07716717
DK		 3258 if (ej->function == e->function) {
3259 ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
3260 return j;
3261 }
3262 }
3263 return 0; /* silence gcc, even though control never reaches here */
3264}
3265
3266/* find an entry with matching function, matching index (if needed), and that
3267 * should be read next (if it's stateful) */
3268static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
3269 u32 function, u32 index)
3270{
3271 if (e->function != function)
3272 return 0;
3273 if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
3274 return 0;
3275 if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
19355475 3276 !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
07716717
DK		 3277 return 0;
3278 return 1;
3279}
3280
d8017474
AG		 3281struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
3282 u32 function, u32 index)
8776e519
HB		 3283{
3284 int i;
d8017474 3285 struct kvm_cpuid_entry2 *best = NULL;
8776e519 3286
ad312c7c 3287 for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
d8017474
AG		 3288 struct kvm_cpuid_entry2 *e;
3289
ad312c7c 3290 e = &vcpu->arch.cpuid_entries[i];
07716717
DK		 3291 if (is_matching_cpuid_entry(e, function, index)) {
3292 if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
3293 move_to_next_stateful_cpuid_entry(vcpu, i);
8776e519
HB		 3294 best = e;
3295 break;
3296 }
3297 /*
3298 * Both basic or both extended?
3299 */
3300 if (((e->function ^ function) & 0x80000000) == 0)
3301 if (!best || e->function > best->function)
3302 best = e;
3303 }
d8017474
AG		 3304 return best;
3305}
3306
82725b20
DE		 3307int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
3308{
3309 struct kvm_cpuid_entry2 *best;
3310
3311 best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
3312 if (best)
3313 return best->eax & 0xff;
3314 return 36;
3315}
3316
d8017474
AG		 3317void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
3318{
3319 u32 function, index;
3320 struct kvm_cpuid_entry2 *best;
3321
3322 function = kvm_register_read(vcpu, VCPU_REGS_RAX);
3323 index = kvm_register_read(vcpu, VCPU_REGS_RCX);
3324 kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
3325 kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
3326 kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
3327 kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
3328 best = kvm_find_cpuid_entry(vcpu, function, index);
8776e519 3329 if (best) {
5fdbf976
MT		 3330 kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
3331 kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
3332 kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
3333 kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
8776e519 3334 }
8776e519 3335 kvm_x86_ops->skip_emulated_instruction(vcpu);
229456fc
MT		 3336 trace_kvm_cpuid(function,
3337 kvm_register_read(vcpu, VCPU_REGS_RAX),
3338 kvm_register_read(vcpu, VCPU_REGS_RBX),
3339 kvm_register_read(vcpu, VCPU_REGS_RCX),
3340 kvm_register_read(vcpu, VCPU_REGS_RDX));
8776e519
HB		 3341}
3342EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
d0752060 3343
b6c7a5dc
HB		 3344/*
3345 * Check if userspace requested an interrupt window, and that the
3346 * interrupt window is open.
3347 *
3348 * No need to exit to userspace if we already have an interrupt queued.
3349 */
3350static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
3351 struct kvm_run *kvm_run)
3352{
8061823a 3353 return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
b6c7a5dc 3354 kvm_run->request_interrupt_window &&
5df56646 3355 kvm_arch_interrupt_allowed(vcpu));
b6c7a5dc
HB		 3356}
3357
3358static void post_kvm_run_save(struct kvm_vcpu *vcpu,
3359 struct kvm_run *kvm_run)
3360{
3361 kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
2d3ad1f4 3362 kvm_run->cr8 = kvm_get_cr8(vcpu);
b6c7a5dc 3363 kvm_run->apic_base = kvm_get_apic_base(vcpu);
4531220b 3364 if (irqchip_in_kernel(vcpu->kvm))
b6c7a5dc 3365 kvm_run->ready_for_interrupt_injection = 1;
4531220b 3366 else
b6c7a5dc 3367 kvm_run->ready_for_interrupt_injection =
fa9726b0
GN		 3368 kvm_arch_interrupt_allowed(vcpu) &&
3369 !kvm_cpu_has_interrupt(vcpu) &&
3370 !kvm_event_needs_reinjection(vcpu);
b6c7a5dc
HB		 3371}
3372
b93463aa
AK		 3373static void vapic_enter(struct kvm_vcpu *vcpu)
3374{
3375 struct kvm_lapic *apic = vcpu->arch.apic;
3376 struct page *page;
3377
3378 if (!apic || !apic->vapic_addr)
3379 return;
3380
3381 page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
72dc67a6
IE		 3382
3383 vcpu->arch.apic->vapic_page = page;
b93463aa
AK		 3384}
3385
3386static void vapic_exit(struct kvm_vcpu *vcpu)
3387{
3388 struct kvm_lapic *apic = vcpu->arch.apic;
3389
3390 if (!apic || !apic->vapic_addr)
3391 return;
3392
f8b78fa3 3393 down_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3394 kvm_release_page_dirty(apic->vapic_page);
3395 mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
f8b78fa3 3396 up_read(&vcpu->kvm->slots_lock);
b93463aa
AK		 3397}
3398
95ba8273
GN		 3399static void update_cr8_intercept(struct kvm_vcpu *vcpu)
3400{
3401 int max_irr, tpr;
3402
3403 if (!kvm_x86_ops->update_cr8_intercept)
3404 return;
3405
8db3baa2
GN		 3406 if (!vcpu->arch.apic->vapic_addr)
3407 max_irr = kvm_lapic_find_highest_irr(vcpu);
3408 else
3409 max_irr = -1;
95ba8273
GN		 3410
3411 if (max_irr != -1)
3412 max_irr >>= 4;
3413
3414 tpr = kvm_lapic_get_cr8(vcpu);
3415
3416 kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
3417}
3418
6a8b1d13 3419static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
95ba8273
GN		 3420{
3421 /* try to reinject previous events if any */
3422 if (vcpu->arch.nmi_injected) {
3423 kvm_x86_ops->set_nmi(vcpu);
3424 return;
3425 }
3426
3427 if (vcpu->arch.interrupt.pending) {
66fd3f7f 3428 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3429 return;
3430 }
3431
3432 /* try to inject new event if pending */
3433 if (vcpu->arch.nmi_pending) {
3434 if (kvm_x86_ops->nmi_allowed(vcpu)) {
3435 vcpu->arch.nmi_pending = false;
3436 vcpu->arch.nmi_injected = true;
3437 kvm_x86_ops->set_nmi(vcpu);
3438 }
3439 } else if (kvm_cpu_has_interrupt(vcpu)) {
3440 if (kvm_x86_ops->interrupt_allowed(vcpu)) {
66fd3f7f
GN		 3441 kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
3442 false);
3443 kvm_x86_ops->set_irq(vcpu);
95ba8273
GN		 3444 }
3445 }
3446}
3447
d7690175 3448static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
b6c7a5dc
HB		 3449{
3450 int r;
6a8b1d13
GN		 3451 bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
3452 kvm_run->request_interrupt_window;
b6c7a5dc 3453
2e53d63a
MT		 3454 if (vcpu->requests)
3455 if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
3456 kvm_mmu_unload(vcpu);
3457
b6c7a5dc
HB		 3458 r = kvm_mmu_reload(vcpu);
3459 if (unlikely(r))
3460 goto out;
3461
2f52d58c
AK		 3462 if (vcpu->requests) {
3463 if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
2f599714 3464 __kvm_migrate_timers(vcpu);
c8076604
GH		 3465 if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
3466 kvm_write_guest_time(vcpu);
4731d4c7
MT		 3467 if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
3468 kvm_mmu_sync_roots(vcpu);
d4acf7e7
MT		 3469 if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
3470 kvm_x86_ops->tlb_flush(vcpu);
b93463aa
AK		 3471 if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
3472 &vcpu->requests)) {
3473 kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
3474 r = 0;
3475 goto out;
3476 }
71c4dfaf
JR		 3477 if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
3478 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
3479 r = 0;
3480 goto out;
3481 }
2f52d58c 3482 }
b93463aa 3483
b6c7a5dc
HB		 3484 preempt_disable();
3485
3486 kvm_x86_ops->prepare_guest_switch(vcpu);
3487 kvm_load_guest_fpu(vcpu);
3488
3489 local_irq_disable();
3490
32f88400
MT		 3491 clear_bit(KVM_REQ_KICK, &vcpu->requests);
3492 smp_mb__after_clear_bit();
3493
d7690175 3494 if (vcpu->requests || need_resched() || signal_pending(current)) {
6c142801
AK		 3495 local_irq_enable();
3496 preempt_enable();
3497 r = 1;
3498 goto out;
3499 }
3500
ad312c7c 3501 if (vcpu->arch.exception.pending)
298101da 3502 __queue_exception(vcpu);
eb9774f0 3503 else
95ba8273 3504 inject_pending_irq(vcpu, kvm_run);
b6c7a5dc 3505
6a8b1d13
GN		 3506 /* enable NMI/IRQ window open exits if needed */
3507 if (vcpu->arch.nmi_pending)
3508 kvm_x86_ops->enable_nmi_window(vcpu);
3509 else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
3510 kvm_x86_ops->enable_irq_window(vcpu);
3511
95ba8273 3512 if (kvm_lapic_enabled(vcpu)) {
8db3baa2
GN		 3513 update_cr8_intercept(vcpu);
3514 kvm_lapic_sync_to_vapic(vcpu);
95ba8273 3515 }
b93463aa 3516
3200f405
MT		 3517 up_read(&vcpu->kvm->slots_lock);
3518
b6c7a5dc
HB		 3519 kvm_guest_enter();
3520
42dbaa5a
JK		 3521 get_debugreg(vcpu->arch.host_dr6, 6);
3522 get_debugreg(vcpu->arch.host_dr7, 7);
3523 if (unlikely(vcpu->arch.switch_db_regs)) {
3524 get_debugreg(vcpu->arch.host_db[0], 0);
3525 get_debugreg(vcpu->arch.host_db[1], 1);
3526 get_debugreg(vcpu->arch.host_db[2], 2);
3527 get_debugreg(vcpu->arch.host_db[3], 3);
3528
3529 set_debugreg(0, 7);
3530 set_debugreg(vcpu->arch.eff_db[0], 0);
3531 set_debugreg(vcpu->arch.eff_db[1], 1);
3532 set_debugreg(vcpu->arch.eff_db[2], 2);
3533 set_debugreg(vcpu->arch.eff_db[3], 3);
3534 }
b6c7a5dc 3535
229456fc 3536 trace_kvm_entry(vcpu->vcpu_id);
b6c7a5dc
HB		 3537 kvm_x86_ops->run(vcpu, kvm_run);
3538
42dbaa5a
JK		 3539 if (unlikely(vcpu->arch.switch_db_regs)) {
3540 set_debugreg(0, 7);
3541 set_debugreg(vcpu->arch.host_db[0], 0);
3542 set_debugreg(vcpu->arch.host_db[1], 1);
3543 set_debugreg(vcpu->arch.host_db[2], 2);
3544 set_debugreg(vcpu->arch.host_db[3], 3);
3545 }
3546 set_debugreg(vcpu->arch.host_dr6, 6);
3547 set_debugreg(vcpu->arch.host_dr7, 7);
3548
32f88400 3549 set_bit(KVM_REQ_KICK, &vcpu->requests);
b6c7a5dc
HB		 3550 local_irq_enable();
3551
3552 ++vcpu->stat.exits;
3553
3554 /*
3555 * We must have an instruction between local_irq_enable() and
3556 * kvm_guest_exit(), so the timer interrupt isn't delayed by
3557 * the interrupt shadow. The stat.exits increment will do nicely.
3558 * But we need to prevent reordering, hence this barrier():
3559 */
3560 barrier();
3561
3562 kvm_guest_exit();
3563
3564 preempt_enable();
3565
3200f405
MT		 3566 down_read(&vcpu->kvm->slots_lock);
3567
b6c7a5dc
HB		 3568 /*
3569 * Profile KVM exit RIPs:
3570 */
3571 if (unlikely(prof_on == KVM_PROFILING)) {
5fdbf976
MT		 3572 unsigned long rip = kvm_rip_read(vcpu);
3573 profile_hit(KVM_PROFILING, (void *)rip);
b6c7a5dc
HB		 3574 }
3575
298101da 3576
b93463aa
AK		 3577 kvm_lapic_sync_from_vapic(vcpu);
3578
b6c7a5dc 3579 r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
d7690175
MT		 3580out:
3581 return r;
3582}
b6c7a5dc 3583
09cec754 3584
d7690175
MT		 3585static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3586{
3587 int r;
3588
3589 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
1b10bf31
JK		 3590 pr_debug("vcpu %d received sipi with vector # %x\n",
3591 vcpu->vcpu_id, vcpu->arch.sipi_vector);
d7690175 3592 kvm_lapic_reset(vcpu);
5f179287 3593 r = kvm_arch_vcpu_reset(vcpu);
d7690175
MT		 3594 if (r)
3595 return r;
3596 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
b6c7a5dc
HB		 3597 }
3598
d7690175
MT		 3599 down_read(&vcpu->kvm->slots_lock);
3600 vapic_enter(vcpu);
3601
3602 r = 1;
3603 while (r > 0) {
af2152f5 3604 if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
d7690175
MT		 3605 r = vcpu_enter_guest(vcpu, kvm_run);
3606 else {
3607 up_read(&vcpu->kvm->slots_lock);
3608 kvm_vcpu_block(vcpu);
3609 down_read(&vcpu->kvm->slots_lock);
3610 if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
09cec754
GN		 3611 {
3612 switch(vcpu->arch.mp_state) {
3613 case KVM_MP_STATE_HALTED:
d7690175 3614 vcpu->arch.mp_state =
09cec754
GN		 3615 KVM_MP_STATE_RUNNABLE;
3616 case KVM_MP_STATE_RUNNABLE:
3617 break;
3618 case KVM_MP_STATE_SIPI_RECEIVED:
3619 default:
3620 r = -EINTR;
3621 break;
3622 }
3623 }
d7690175
MT		 3624 }
3625
09cec754
GN		 3626 if (r <= 0)
3627 break;
3628
3629 clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
3630 if (kvm_cpu_has_pending_timer(vcpu))
3631 kvm_inject_pending_timer_irqs(vcpu);
3632
3633 if (dm_request_for_irq_injection(vcpu, kvm_run)) {
3634 r = -EINTR;
3635 kvm_run->exit_reason = KVM_EXIT_INTR;
3636 ++vcpu->stat.request_irq_exits;
3637 }
3638 if (signal_pending(current)) {
3639 r = -EINTR;
3640 kvm_run->exit_reason = KVM_EXIT_INTR;
3641 ++vcpu->stat.signal_exits;
3642 }
3643 if (need_resched()) {
3644 up_read(&vcpu->kvm->slots_lock);
3645 kvm_resched(vcpu);
3646 down_read(&vcpu->kvm->slots_lock);
d7690175 3647 }
b6c7a5dc
HB		 3648 }
3649
d7690175 3650 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3651 post_kvm_run_save(vcpu, kvm_run);
3652
b93463aa
AK		 3653 vapic_exit(vcpu);
3654
b6c7a5dc
HB		 3655 return r;
3656}
3657
3658int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
3659{
3660 int r;
3661 sigset_t sigsaved;
3662
3663 vcpu_load(vcpu);
3664
ac9f6dc0
AK		 3665 if (vcpu->sigset_active)
3666 sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
3667
a4535290 3668 if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
b6c7a5dc 3669 kvm_vcpu_block(vcpu);
d7690175 3670 clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
ac9f6dc0
AK		 3671 r = -EAGAIN;
3672 goto out;
b6c7a5dc
HB		 3673 }
3674
b6c7a5dc
HB		 3675 /* re-sync apic's tpr */
3676 if (!irqchip_in_kernel(vcpu->kvm))
2d3ad1f4 3677 kvm_set_cr8(vcpu, kvm_run->cr8);
b6c7a5dc 3678
ad312c7c 3679 if (vcpu->arch.pio.cur_count) {
b6c7a5dc
HB		 3680 r = complete_pio(vcpu);
3681 if (r)
3682 goto out;
3683 }
3684#if CONFIG_HAS_IOMEM
3685 if (vcpu->mmio_needed) {
3686 memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
3687 vcpu->mmio_read_completed = 1;
3688 vcpu->mmio_needed = 0;
3200f405
MT		 3689
3690 down_read(&vcpu->kvm->slots_lock);
b6c7a5dc 3691 r = emulate_instruction(vcpu, kvm_run,
571008da
SY		 3692 vcpu->arch.mmio_fault_cr2, 0,
3693 EMULTYPE_NO_DECODE);
3200f405 3694 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc
HB		 3695 if (r == EMULATE_DO_MMIO) {
3696 /*
3697 * Read-modify-write. Back to userspace.
3698 */
3699 r = 0;
3700 goto out;
3701 }
3702 }
3703#endif
5fdbf976
MT		 3704 if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
3705 kvm_register_write(vcpu, VCPU_REGS_RAX,
3706 kvm_run->hypercall.ret);
b6c7a5dc
HB		 3707
3708 r = __vcpu_run(vcpu, kvm_run);
3709
3710out:
3711 if (vcpu->sigset_active)
3712 sigprocmask(SIG_SETMASK, &sigsaved, NULL);
3713
3714 vcpu_put(vcpu);
3715 return r;
3716}
3717
3718int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3719{
3720 vcpu_load(vcpu);
3721
5fdbf976
MT		 3722 regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
3723 regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
3724 regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
3725 regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
3726 regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
3727 regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
3728 regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
3729 regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
b6c7a5dc 3730#ifdef CONFIG_X86_64
5fdbf976
MT		 3731 regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
3732 regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
3733 regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
3734 regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
3735 regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
3736 regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
3737 regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
3738 regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
b6c7a5dc
HB		 3739#endif
3740
5fdbf976 3741 regs->rip = kvm_rip_read(vcpu);
b6c7a5dc
HB		 3742 regs->rflags = kvm_x86_ops->get_rflags(vcpu);
3743
3744 /*
3745 * Don't leak debug flags in case they were set for guest debugging
3746 */
d0bfb940 3747 if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
b6c7a5dc
HB		 3748 regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
3749
3750 vcpu_put(vcpu);
3751
3752 return 0;
3753}
3754
3755int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
3756{
3757 vcpu_load(vcpu);
3758
5fdbf976
MT		 3759 kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
3760 kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
3761 kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
3762 kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
3763 kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
3764 kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
3765 kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
3766 kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
b6c7a5dc 3767#ifdef CONFIG_X86_64
5fdbf976
MT		 3768 kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
3769 kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
3770 kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
3771 kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
3772 kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
3773 kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
3774 kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
3775 kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
3776
b6c7a5dc
HB		 3777#endif
3778
5fdbf976 3779 kvm_rip_write(vcpu, regs->rip);
b6c7a5dc
HB		 3780 kvm_x86_ops->set_rflags(vcpu, regs->rflags);
3781
b6c7a5dc 3782
b4f14abd
JK		 3783 vcpu->arch.exception.pending = false;
3784
b6c7a5dc
HB		 3785 vcpu_put(vcpu);
3786
3787 return 0;
3788}
3789
3e6e0aab
GT		 3790void kvm_get_segment(struct kvm_vcpu *vcpu,
3791 struct kvm_segment *var, int seg)
b6c7a5dc 3792{
14af3f3c 3793 kvm_x86_ops->get_segment(vcpu, var, seg);
b6c7a5dc
HB		 3794}
3795
3796void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
3797{
3798 struct kvm_segment cs;
3799
3e6e0aab 3800 kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
b6c7a5dc
HB		 3801 *db = cs.db;
3802 *l = cs.l;
3803}
3804EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
3805
3806int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
3807 struct kvm_sregs *sregs)
3808{
3809 struct descriptor_table dt;
b6c7a5dc
HB		 3810
3811 vcpu_load(vcpu);
3812
3e6e0aab
GT		 3813 kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
3814 kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
3815 kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
3816 kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
3817 kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
3818 kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 3819
3e6e0aab
GT		 3820 kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
3821 kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc
HB		 3822
3823 kvm_x86_ops->get_idt(vcpu, &dt);
3824 sregs->idt.limit = dt.limit;
3825 sregs->idt.base = dt.base;
3826 kvm_x86_ops->get_gdt(vcpu, &dt);
3827 sregs->gdt.limit = dt.limit;
3828 sregs->gdt.base = dt.base;
3829
3830 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
ad312c7c
ZX		 3831 sregs->cr0 = vcpu->arch.cr0;
3832 sregs->cr2 = vcpu->arch.cr2;
3833 sregs->cr3 = vcpu->arch.cr3;
3834 sregs->cr4 = vcpu->arch.cr4;
2d3ad1f4 3835 sregs->cr8 = kvm_get_cr8(vcpu);
ad312c7c 3836 sregs->efer = vcpu->arch.shadow_efer;
b6c7a5dc
HB		 3837 sregs->apic_base = kvm_get_apic_base(vcpu);
3838
923c61bb 3839 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
b6c7a5dc 3840
36752c9b 3841 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
14d0bc1f
GN		 3842 set_bit(vcpu->arch.interrupt.nr,
3843 (unsigned long *)sregs->interrupt_bitmap);
16d7a191 3844
b6c7a5dc
HB		 3845 vcpu_put(vcpu);
3846
3847 return 0;
3848}
3849
62d9f0db
MT		 3850int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
3851 struct kvm_mp_state *mp_state)
3852{
3853 vcpu_load(vcpu);
3854 mp_state->mp_state = vcpu->arch.mp_state;
3855 vcpu_put(vcpu);
3856 return 0;
3857}
3858
3859int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
3860 struct kvm_mp_state *mp_state)
3861{
3862 vcpu_load(vcpu);
3863 vcpu->arch.mp_state = mp_state->mp_state;
3864 vcpu_put(vcpu);
3865 return 0;
3866}
3867
3e6e0aab 3868static void kvm_set_segment(struct kvm_vcpu *vcpu,
b6c7a5dc
HB		 3869 struct kvm_segment *var, int seg)
3870{
14af3f3c 3871 kvm_x86_ops->set_segment(vcpu, var, seg);
b6c7a5dc
HB		 3872}
3873
37817f29
IE		 3874static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
3875 struct kvm_segment *kvm_desct)
3876{
3877 kvm_desct->base = seg_desc->base0;
3878 kvm_desct->base |= seg_desc->base1 << 16;
3879 kvm_desct->base |= seg_desc->base2 << 24;
3880 kvm_desct->limit = seg_desc->limit0;
3881 kvm_desct->limit |= seg_desc->limit << 16;
c93cd3a5
MT		 3882 if (seg_desc->g) {
3883 kvm_desct->limit <<= 12;
3884 kvm_desct->limit |= 0xfff;
3885 }
37817f29
IE		 3886 kvm_desct->selector = selector;
3887 kvm_desct->type = seg_desc->type;
3888 kvm_desct->present = seg_desc->p;
3889 kvm_desct->dpl = seg_desc->dpl;
3890 kvm_desct->db = seg_desc->d;
3891 kvm_desct->s = seg_desc->s;
3892 kvm_desct->l = seg_desc->l;
3893 kvm_desct->g = seg_desc->g;
3894 kvm_desct->avl = seg_desc->avl;
3895 if (!selector)
3896 kvm_desct->unusable = 1;
3897 else
3898 kvm_desct->unusable = 0;
3899 kvm_desct->padding = 0;
3900}
3901
b8222ad2
AS		 3902static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
3903 u16 selector,
3904 struct descriptor_table *dtable)
37817f29
IE		 3905{
3906 if (selector & 1 << 2) {
3907 struct kvm_segment kvm_seg;
3908
3e6e0aab 3909 kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
37817f29
IE		 3910
3911 if (kvm_seg.unusable)
3912 dtable->limit = 0;
3913 else
3914 dtable->limit = kvm_seg.limit;
3915 dtable->base = kvm_seg.base;
3916 }
3917 else
3918 kvm_x86_ops->get_gdt(vcpu, dtable);
3919}
3920
3921/* allowed just for 8 bytes segments */
3922static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3923 struct desc_struct *seg_desc)
3924{
98899aa0 3925 gpa_t gpa;
37817f29
IE		 3926 struct descriptor_table dtable;
3927 u16 index = selector >> 3;
3928
b8222ad2 3929 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3930
3931 if (dtable.limit < index * 8 + 7) {
3932 kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
3933 return 1;
3934 }
98899aa0
MT		 3935 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3936 gpa += index * 8;
3937 return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3938}
3939
3940/* allowed just for 8 bytes segments */
3941static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
3942 struct desc_struct *seg_desc)
3943{
98899aa0 3944 gpa_t gpa;
37817f29
IE		 3945 struct descriptor_table dtable;
3946 u16 index = selector >> 3;
3947
b8222ad2 3948 get_segment_descriptor_dtable(vcpu, selector, &dtable);
37817f29
IE		 3949
3950 if (dtable.limit < index * 8 + 7)
3951 return 1;
98899aa0
MT		 3952 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
3953 gpa += index * 8;
3954 return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
37817f29
IE		 3955}
3956
3957static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
3958 struct desc_struct *seg_desc)
3959{
3960 u32 base_addr;
3961
3962 base_addr = seg_desc->base0;
3963 base_addr |= (seg_desc->base1 << 16);
3964 base_addr |= (seg_desc->base2 << 24);
3965
98899aa0 3966 return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
37817f29
IE		 3967}
3968
37817f29
IE		 3969static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
3970{
3971 struct kvm_segment kvm_seg;
3972
3e6e0aab 3973 kvm_get_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 3974 return kvm_seg.selector;
3975}
3976
3977static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
3978 u16 selector,
3979 struct kvm_segment *kvm_seg)
3980{
3981 struct desc_struct seg_desc;
3982
3983 if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
3984 return 1;
3985 seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
3986 return 0;
3987}
3988
2259e3a7 3989static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
f4bbd9aa
AK		 3990{
3991 struct kvm_segment segvar = {
3992 .base = selector << 4,
3993 .limit = 0xffff,
3994 .selector = selector,
3995 .type = 3,
3996 .present = 1,
3997 .dpl = 3,
3998 .db = 0,
3999 .s = 1,
4000 .l = 0,
4001 .g = 0,
4002 .avl = 0,
4003 .unusable = 0,
4004 };
4005 kvm_x86_ops->set_segment(vcpu, &segvar, seg);
4006 return 0;
4007}
4008
3e6e0aab
GT		 4009int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
4010 int type_bits, int seg)
37817f29
IE		 4011{
4012 struct kvm_segment kvm_seg;
4013
f4bbd9aa
AK		 4014 if (!(vcpu->arch.cr0 & X86_CR0_PE))
4015 return kvm_load_realmode_segment(vcpu, selector, seg);
37817f29
IE		 4016 if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
4017 return 1;
4018 kvm_seg.type |= type_bits;
4019
4020 if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
4021 seg != VCPU_SREG_LDTR)
4022 if (!kvm_seg.s)
4023 kvm_seg.unusable = 1;
4024
3e6e0aab 4025 kvm_set_segment(vcpu, &kvm_seg, seg);
37817f29
IE		 4026 return 0;
4027}
4028
4029static void save_state_to_tss32(struct kvm_vcpu *vcpu,
4030 struct tss_segment_32 *tss)
4031{
4032 tss->cr3 = vcpu->arch.cr3;
5fdbf976 4033 tss->eip = kvm_rip_read(vcpu);
37817f29 4034 tss->eflags = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4035 tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4036 tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4037 tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4038 tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4039 tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4040 tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4041 tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
4042 tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4043 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4044 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4045 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4046 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4047 tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
4048 tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
4049 tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
37817f29
IE		 4050}
4051
4052static int load_state_from_tss32(struct kvm_vcpu *vcpu,
4053 struct tss_segment_32 *tss)
4054{
4055 kvm_set_cr3(vcpu, tss->cr3);
4056
5fdbf976 4057 kvm_rip_write(vcpu, tss->eip);
37817f29
IE		 4058 kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
4059
5fdbf976
MT		 4060 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
4061 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
4062 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
4063 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
4064 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
4065 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
4066 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
4067 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
37817f29 4068
3e6e0aab 4069 if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
37817f29
IE		 4070 return 1;
4071
3e6e0aab 4072 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4073 return 1;
4074
3e6e0aab 4075 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4076 return 1;
4077
3e6e0aab 4078 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4079 return 1;
4080
3e6e0aab 4081 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4082 return 1;
4083
3e6e0aab 4084 if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
37817f29
IE		 4085 return 1;
4086
3e6e0aab 4087 if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
37817f29
IE		 4088 return 1;
4089 return 0;
4090}
4091
4092static void save_state_to_tss16(struct kvm_vcpu *vcpu,
4093 struct tss_segment_16 *tss)
4094{
5fdbf976 4095 tss->ip = kvm_rip_read(vcpu);
37817f29 4096 tss->flag = kvm_x86_ops->get_rflags(vcpu);
5fdbf976
MT		 4097 tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
4098 tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
4099 tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
4100 tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
4101 tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
4102 tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
4103 tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
4104 tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
37817f29
IE		 4105
4106 tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
4107 tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
4108 tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
4109 tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
4110 tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
4111 tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
4112}
4113
4114static int load_state_from_tss16(struct kvm_vcpu *vcpu,
4115 struct tss_segment_16 *tss)
4116{
5fdbf976 4117 kvm_rip_write(vcpu, tss->ip);
37817f29 4118 kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
5fdbf976
MT		 4119 kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
4120 kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
4121 kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
4122 kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
4123 kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
4124 kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
4125 kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
4126 kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
37817f29 4127
3e6e0aab 4128 if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
37817f29
IE		 4129 return 1;
4130
3e6e0aab 4131 if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
37817f29
IE		 4132 return 1;
4133
3e6e0aab 4134 if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
37817f29
IE		 4135 return 1;
4136
3e6e0aab 4137 if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
37817f29
IE		 4138 return 1;
4139
3e6e0aab 4140 if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
37817f29
IE		 4141 return 1;
4142 return 0;
4143}
4144
8b2cf73c 4145static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37
GN		 4146 u16 old_tss_sel, u32 old_tss_base,
4147 struct desc_struct *nseg_desc)
37817f29
IE		 4148{
4149 struct tss_segment_16 tss_segment_16;
4150 int ret = 0;
4151
34198bf8
MT		 4152 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4153 sizeof tss_segment_16))
37817f29
IE		 4154 goto out;
4155
4156 save_state_to_tss16(vcpu, &tss_segment_16);
37817f29 4157
34198bf8
MT		 4158 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
4159 sizeof tss_segment_16))
37817f29 4160 goto out;
34198bf8
MT		 4161
4162 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4163 &tss_segment_16, sizeof tss_segment_16))
4164 goto out;
4165
b237ac37
GN		 4166 if (old_tss_sel != 0xffff) {
4167 tss_segment_16.prev_task_link = old_tss_sel;
4168
4169 if (kvm_write_guest(vcpu->kvm,
4170 get_tss_base_addr(vcpu, nseg_desc),
4171 &tss_segment_16.prev_task_link,
4172 sizeof tss_segment_16.prev_task_link))
4173 goto out;
4174 }
4175
37817f29
IE		 4176 if (load_state_from_tss16(vcpu, &tss_segment_16))
4177 goto out;
4178
4179 ret = 1;
4180out:
4181 return ret;
4182}
4183
8b2cf73c 4184static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
b237ac37 4185 u16 old_tss_sel, u32 old_tss_base,
37817f29
IE		 4186 struct desc_struct *nseg_desc)
4187{
4188 struct tss_segment_32 tss_segment_32;
4189 int ret = 0;
4190
34198bf8
MT		 4191 if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4192 sizeof tss_segment_32))
37817f29
IE		 4193 goto out;
4194
4195 save_state_to_tss32(vcpu, &tss_segment_32);
37817f29 4196
34198bf8
MT		 4197 if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
4198 sizeof tss_segment_32))
4199 goto out;
4200
4201 if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
4202 &tss_segment_32, sizeof tss_segment_32))
37817f29 4203 goto out;
34198bf8 4204
b237ac37
GN		 4205 if (old_tss_sel != 0xffff) {
4206 tss_segment_32.prev_task_link = old_tss_sel;
4207
4208 if (kvm_write_guest(vcpu->kvm,
4209 get_tss_base_addr(vcpu, nseg_desc),
4210 &tss_segment_32.prev_task_link,
4211 sizeof tss_segment_32.prev_task_link))
4212 goto out;
4213 }
4214
37817f29
IE		 4215 if (load_state_from_tss32(vcpu, &tss_segment_32))
4216 goto out;
4217
4218 ret = 1;
4219out:
4220 return ret;
4221}
4222
4223int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
4224{
4225 struct kvm_segment tr_seg;
4226 struct desc_struct cseg_desc;
4227 struct desc_struct nseg_desc;
4228 int ret = 0;
34198bf8
MT		 4229 u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
4230 u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
37817f29 4231
34198bf8 4232 old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
37817f29 4233
34198bf8
MT		 4234 /* FIXME: Handle errors. Failure to read either TSS or their
4235 * descriptors should generate a pagefault.
4236 */
37817f29
IE		 4237 if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
4238 goto out;
4239
34198bf8 4240 if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
37817f29
IE		 4241 goto out;
4242
37817f29
IE		 4243 if (reason != TASK_SWITCH_IRET) {
4244 int cpl;
4245
4246 cpl = kvm_x86_ops->get_cpl(vcpu);
4247 if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
4248 kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
4249 return 1;
4250 }
4251 }
4252
4253 if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
4254 kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
4255 return 1;
4256 }
4257
4258 if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
3fe913e7 4259 cseg_desc.type &= ~(1 << 1); //clear the B flag
34198bf8 4260 save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
37817f29
IE		 4261 }
4262
4263 if (reason == TASK_SWITCH_IRET) {
4264 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4265 kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
4266 }
4267
64a7ec06
GN		 4268 /* set back link to prev task only if NT bit is set in eflags
4269 note that old_tss_sel is not used afetr this point */
4270 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4271 old_tss_sel = 0xffff;
37817f29 4272
b237ac37
GN		 4273 /* set back link to prev task only if NT bit is set in eflags
4274 note that old_tss_sel is not used afetr this point */
4275 if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
4276 old_tss_sel = 0xffff;
4277
37817f29 4278 if (nseg_desc.type & 8)
b237ac37
GN		 4279 ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
4280 old_tss_base, &nseg_desc);
37817f29 4281 else
b237ac37
GN		 4282 ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
4283 old_tss_base, &nseg_desc);
37817f29
IE		 4284
4285 if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
4286 u32 eflags = kvm_x86_ops->get_rflags(vcpu);
4287 kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
4288 }
4289
4290 if (reason != TASK_SWITCH_IRET) {
3fe913e7 4291 nseg_desc.type |= (1 << 1);
37817f29
IE		 4292 save_guest_segment_descriptor(vcpu, tss_selector,
4293 &nseg_desc);
4294 }
4295
4296 kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
4297 seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
4298 tr_seg.type = 11;
3e6e0aab 4299 kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
37817f29 4300out:
37817f29
IE		 4301 return ret;
4302}
4303EXPORT_SYMBOL_GPL(kvm_task_switch);
4304
b6c7a5dc
HB		 4305int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
4306 struct kvm_sregs *sregs)
4307{
4308 int mmu_reset_needed = 0;
923c61bb 4309 int pending_vec, max_bits;
b6c7a5dc
HB		 4310 struct descriptor_table dt;
4311
4312 vcpu_load(vcpu);
4313
4314 dt.limit = sregs->idt.limit;
4315 dt.base = sregs->idt.base;
4316 kvm_x86_ops->set_idt(vcpu, &dt);
4317 dt.limit = sregs->gdt.limit;
4318 dt.base = sregs->gdt.base;
4319 kvm_x86_ops->set_gdt(vcpu, &dt);
4320
ad312c7c
ZX		 4321 vcpu->arch.cr2 = sregs->cr2;
4322 mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
59839dff
MT		 4323
4324 down_read(&vcpu->kvm->slots_lock);
4325 if (gfn_to_memslot(vcpu->kvm, sregs->cr3 >> PAGE_SHIFT))
4326 vcpu->arch.cr3 = sregs->cr3;
4327 else
4328 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
4329 up_read(&vcpu->kvm->slots_lock);
b6c7a5dc 4330
2d3ad1f4 4331 kvm_set_cr8(vcpu, sregs->cr8);
b6c7a5dc 4332
ad312c7c 4333 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
b6c7a5dc 4334 kvm_x86_ops->set_efer(vcpu, sregs->efer);
b6c7a5dc
HB		 4335 kvm_set_apic_base(vcpu, sregs->apic_base);
4336
4337 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4338
ad312c7c 4339 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
b6c7a5dc 4340 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
d7306163 4341 vcpu->arch.cr0 = sregs->cr0;
b6c7a5dc 4342
ad312c7c 4343 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
b6c7a5dc
HB		 4344 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4345 if (!is_long_mode(vcpu) && is_pae(vcpu))
ad312c7c 4346 load_pdptrs(vcpu, vcpu->arch.cr3);
b6c7a5dc
HB		 4347
4348 if (mmu_reset_needed)
4349 kvm_mmu_reset_context(vcpu);
4350
923c61bb
GN		 4351 max_bits = (sizeof sregs->interrupt_bitmap) << 3;
4352 pending_vec = find_first_bit(
4353 (const unsigned long *)sregs->interrupt_bitmap, max_bits);
4354 if (pending_vec < max_bits) {
66fd3f7f 4355 kvm_queue_interrupt(vcpu, pending_vec, false);
923c61bb
GN		 4356 pr_debug("Set back pending irq %d\n", pending_vec);
4357 if (irqchip_in_kernel(vcpu->kvm))
4358 kvm_pic_clear_isr_ack(vcpu->kvm);
b6c7a5dc
HB		 4359 }
4360
3e6e0aab
GT		 4361 kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
4362 kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
4363 kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
4364 kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
4365 kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
4366 kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
b6c7a5dc 4367
3e6e0aab
GT		 4368 kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
4369 kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
b6c7a5dc 4370
9c3e4aab 4371 /* Older userspace won't unhalt the vcpu on reset. */
c5af89b6 4372 if (kvm_vcpu_is_bsp(vcpu) && kvm_rip_read(vcpu) == 0xfff0 &&
9c3e4aab
MT		 4373 sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
4374 !(vcpu->arch.cr0 & X86_CR0_PE))
4375 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
4376
b6c7a5dc
HB		 4377 vcpu_put(vcpu);
4378
4379 return 0;
4380}
4381
d0bfb940
JK		 4382int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
4383 struct kvm_guest_debug *dbg)
b6c7a5dc 4384{
ae675ef0 4385 int i, r;
b6c7a5dc
HB		 4386
4387 vcpu_load(vcpu);
4388
ae675ef0
JK		 4389 if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
4390 (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
4391 for (i = 0; i < KVM_NR_DB_REGS; ++i)
4392 vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
4393 vcpu->arch.switch_db_regs =
4394 (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
4395 } else {
4396 for (i = 0; i < KVM_NR_DB_REGS; i++)
4397 vcpu->arch.eff_db[i] = vcpu->arch.db[i];
4398 vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
4399 }
4400
b6c7a5dc
HB		 4401 r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
4402
d0bfb940
JK		 4403 if (dbg->control & KVM_GUESTDBG_INJECT_DB)
4404 kvm_queue_exception(vcpu, DB_VECTOR);
4405 else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
4406 kvm_queue_exception(vcpu, BP_VECTOR);
4407
b6c7a5dc
HB		 4408 vcpu_put(vcpu);
4409
4410 return r;
4411}
4412
d0752060
HB		 4413/*
4414 * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
4415 * we have asm/x86/processor.h
4416 */
4417struct fxsave {
4418 u16 cwd;
4419 u16 swd;
4420 u16 twd;
4421 u16 fop;
4422 u64 rip;
4423 u64 rdp;
4424 u32 mxcsr;
4425 u32 mxcsr_mask;
4426 u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
4427#ifdef CONFIG_X86_64
4428 u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
4429#else
4430 u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
4431#endif
4432};
4433
8b006791
ZX		 4434/*
4435 * Translate a guest virtual address to a guest physical address.
4436 */
4437int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
4438 struct kvm_translation *tr)
4439{
4440 unsigned long vaddr = tr->linear_address;
4441 gpa_t gpa;
4442
4443 vcpu_load(vcpu);
72dc67a6 4444 down_read(&vcpu->kvm->slots_lock);
ad312c7c 4445 gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
72dc67a6 4446 up_read(&vcpu->kvm->slots_lock);
8b006791
ZX		 4447 tr->physical_address = gpa;
4448 tr->valid = gpa != UNMAPPED_GVA;
4449 tr->writeable = 1;
4450 tr->usermode = 0;
8b006791
ZX		 4451 vcpu_put(vcpu);
4452
4453 return 0;
4454}
4455
d0752060
HB		 4456int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4457{
ad312c7c 4458 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4459
4460 vcpu_load(vcpu);
4461
4462 memcpy(fpu->fpr, fxsave->st_space, 128);
4463 fpu->fcw = fxsave->cwd;
4464 fpu->fsw = fxsave->swd;
4465 fpu->ftwx = fxsave->twd;
4466 fpu->last_opcode = fxsave->fop;
4467 fpu->last_ip = fxsave->rip;
4468 fpu->last_dp = fxsave->rdp;
4469 memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
4470
4471 vcpu_put(vcpu);
4472
4473 return 0;
4474}
4475
4476int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
4477{
ad312c7c 4478 struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
d0752060
HB		 4479
4480 vcpu_load(vcpu);
4481
4482 memcpy(fxsave->st_space, fpu->fpr, 128);
4483 fxsave->cwd = fpu->fcw;
4484 fxsave->swd = fpu->fsw;
4485 fxsave->twd = fpu->ftwx;
4486 fxsave->fop = fpu->last_opcode;
4487 fxsave->rip = fpu->last_ip;
4488 fxsave->rdp = fpu->last_dp;
4489 memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
4490
4491 vcpu_put(vcpu);
4492
4493 return 0;
4494}
4495
4496void fx_init(struct kvm_vcpu *vcpu)
4497{
4498 unsigned after_mxcsr_mask;
4499
bc1a34f1
AA		 4500 /*
4501 * Touch the fpu the first time in non atomic context as if
4502 * this is the first fpu instruction the exception handler
4503 * will fire before the instruction returns and it'll have to
4504 * allocate ram with GFP_KERNEL.
4505 */
4506 if (!used_math())
d6e88aec 4507 kvm_fx_save(&vcpu->arch.host_fx_image);
bc1a34f1 4508
d0752060
HB		 4509 /* Initialize guest FPU by resetting ours and saving into guest's */
4510 preempt_disable();
d6e88aec
AK		 4511 kvm_fx_save(&vcpu->arch.host_fx_image);
4512 kvm_fx_finit();
4513 kvm_fx_save(&vcpu->arch.guest_fx_image);
4514 kvm_fx_restore(&vcpu->arch.host_fx_image);
d0752060
HB		 4515 preempt_enable();
4516
ad312c7c 4517 vcpu->arch.cr0 |= X86_CR0_ET;
d0752060 4518 after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
ad312c7c
ZX		 4519 vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
4520 memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
d0752060
HB		 4521 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
4522}
4523EXPORT_SYMBOL_GPL(fx_init);
4524
4525void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
4526{
4527 if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
4528 return;
4529
4530 vcpu->guest_fpu_loaded = 1;
d6e88aec
AK		 4531 kvm_fx_save(&vcpu->arch.host_fx_image);
4532 kvm_fx_restore(&vcpu->arch.guest_fx_image);
d0752060
HB		 4533}
4534EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
4535
4536void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
4537{
4538 if (!vcpu->guest_fpu_loaded)
4539 return;
4540
4541 vcpu->guest_fpu_loaded = 0;
d6e88aec
AK		 4542 kvm_fx_save(&vcpu->arch.guest_fx_image);
4543 kvm_fx_restore(&vcpu->arch.host_fx_image);
f096ed85 4544 ++vcpu->stat.fpu_reload;
d0752060
HB		 4545}
4546EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
e9b11c17
ZX		 4547
4548void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
4549{
7f1ea208
JR		 4550 if (vcpu->arch.time_page) {
4551 kvm_release_page_dirty(vcpu->arch.time_page);
4552 vcpu->arch.time_page = NULL;
4553 }
4554
e9b11c17
ZX		 4555 kvm_x86_ops->vcpu_free(vcpu);
4556}
4557
4558struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
4559 unsigned int id)
4560{
26e5215f
AK		 4561 return kvm_x86_ops->vcpu_create(kvm, id);
4562}
e9b11c17 4563
26e5215f
AK		 4564int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
4565{
4566 int r;
e9b11c17
ZX		 4567
4568 /* We do fxsave: this must be aligned. */
ad312c7c 4569 BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
e9b11c17 4570
0bed3b56 4571 vcpu->arch.mtrr_state.have_fixed = 1;
e9b11c17
ZX		 4572 vcpu_load(vcpu);
4573 r = kvm_arch_vcpu_reset(vcpu);
4574 if (r == 0)
4575 r = kvm_mmu_setup(vcpu);
4576 vcpu_put(vcpu);
4577 if (r < 0)
4578 goto free_vcpu;
4579
26e5215f 4580 return 0;
e9b11c17
ZX		 4581free_vcpu:
4582 kvm_x86_ops->vcpu_free(vcpu);
26e5215f 4583 return r;
e9b11c17
ZX		 4584}
4585
d40ccc62 4586void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
e9b11c17
ZX		 4587{
4588 vcpu_load(vcpu);
4589 kvm_mmu_unload(vcpu);
4590 vcpu_put(vcpu);
4591
4592 kvm_x86_ops->vcpu_free(vcpu);
4593}
4594
4595int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
4596{
448fa4a9
JK		 4597 vcpu->arch.nmi_pending = false;
4598 vcpu->arch.nmi_injected = false;
4599
42dbaa5a
JK		 4600 vcpu->arch.switch_db_regs = 0;
4601 memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
4602 vcpu->arch.dr6 = DR6_FIXED_1;
4603 vcpu->arch.dr7 = DR7_FIXED_1;
4604
e9b11c17
ZX		 4605 return kvm_x86_ops->vcpu_reset(vcpu);
4606}
4607
4608void kvm_arch_hardware_enable(void *garbage)
4609{
4610 kvm_x86_ops->hardware_enable(garbage);
4611}
4612
4613void kvm_arch_hardware_disable(void *garbage)
4614{
4615 kvm_x86_ops->hardware_disable(garbage);
4616}
4617
4618int kvm_arch_hardware_setup(void)
4619{
4620 return kvm_x86_ops->hardware_setup();
4621}
4622
4623void kvm_arch_hardware_unsetup(void)
4624{
4625 kvm_x86_ops->hardware_unsetup();
4626}
4627
4628void kvm_arch_check_processor_compat(void *rtn)
4629{
4630 kvm_x86_ops->check_processor_compatibility(rtn);
4631}
4632
4633int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
4634{
4635 struct page *page;
4636 struct kvm *kvm;
4637 int r;
4638
4639 BUG_ON(vcpu->kvm == NULL);
4640 kvm = vcpu->kvm;
4641
ad312c7c 4642 vcpu->arch.mmu.root_hpa = INVALID_PAGE;
c5af89b6 4643 if (!irqchip_in_kernel(kvm) || kvm_vcpu_is_bsp(vcpu))
a4535290 4644 vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
e9b11c17 4645 else
a4535290 4646 vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
e9b11c17
ZX		 4647
4648 page = alloc_page(GFP_KERNEL | __GFP_ZERO);
4649 if (!page) {
4650 r = -ENOMEM;
4651 goto fail;
4652 }
ad312c7c 4653 vcpu->arch.pio_data = page_address(page);
e9b11c17
ZX		 4654
4655 r = kvm_mmu_create(vcpu);
4656 if (r < 0)
4657 goto fail_free_pio_data;
4658
4659 if (irqchip_in_kernel(kvm)) {
4660 r = kvm_create_lapic(vcpu);
4661 if (r < 0)
4662 goto fail_mmu_destroy;
4663 }
4664
890ca9ae
HY		 4665 vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
4666 GFP_KERNEL);
4667 if (!vcpu->arch.mce_banks) {
4668 r = -ENOMEM;
4669 goto fail_mmu_destroy;
4670 }
4671 vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
4672
e9b11c17
ZX		 4673 return 0;
4674
4675fail_mmu_destroy:
4676 kvm_mmu_destroy(vcpu);
4677fail_free_pio_data:
ad312c7c 4678 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17
ZX		 4679fail:
4680 return r;
4681}
4682
4683void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
4684{
4685 kvm_free_lapic(vcpu);
3200f405 4686 down_read(&vcpu->kvm->slots_lock);
e9b11c17 4687 kvm_mmu_destroy(vcpu);
3200f405 4688 up_read(&vcpu->kvm->slots_lock);
ad312c7c 4689 free_page((unsigned long)vcpu->arch.pio_data);
e9b11c17 4690}
d19a9cd2
ZX		 4691
4692struct kvm *kvm_arch_create_vm(void)
4693{
4694 struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
4695
4696 if (!kvm)
4697 return ERR_PTR(-ENOMEM);
4698
f05e70ac 4699 INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
4d5c5d0f 4700 INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
d19a9cd2 4701
5550af4d
SY		 4702 /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
4703 set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
4704
53f658b3
MT		 4705 rdtscll(kvm->arch.vm_init_tsc);
4706
d19a9cd2
ZX		 4707 return kvm;
4708}
4709
4710static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
4711{
4712 vcpu_load(vcpu);
4713 kvm_mmu_unload(vcpu);
4714 vcpu_put(vcpu);
4715}
4716
4717static void kvm_free_vcpus(struct kvm *kvm)
4718{
4719 unsigned int i;
988a2cae 4720 struct kvm_vcpu *vcpu;
d19a9cd2
ZX		 4721
4722 /*
4723 * Unpin any mmu pages first.
4724 */
988a2cae
GN		 4725 kvm_for_each_vcpu(i, vcpu, kvm)
4726 kvm_unload_vcpu_mmu(vcpu);
4727 kvm_for_each_vcpu(i, vcpu, kvm)
4728 kvm_arch_vcpu_free(vcpu);
4729
4730 mutex_lock(&kvm->lock);
4731 for (i = 0; i < atomic_read(&kvm->online_vcpus); i++)
4732 kvm->vcpus[i] = NULL;
d19a9cd2 4733
988a2cae
GN		 4734 atomic_set(&kvm->online_vcpus, 0);
4735 mutex_unlock(&kvm->lock);
d19a9cd2
ZX		 4736}
4737
ad8ba2cd
SY		 4738void kvm_arch_sync_events(struct kvm *kvm)
4739{
ba4cef31 4740 kvm_free_all_assigned_devices(kvm);
ad8ba2cd
SY		 4741}
4742
d19a9cd2
ZX		 4743void kvm_arch_destroy_vm(struct kvm *kvm)
4744{
6eb55818 4745 kvm_iommu_unmap_guest(kvm);
7837699f 4746 kvm_free_pit(kvm);
d7deeeb0
ZX		 4747 kfree(kvm->arch.vpic);
4748 kfree(kvm->arch.vioapic);
d19a9cd2
ZX		 4749 kvm_free_vcpus(kvm);
4750 kvm_free_physmem(kvm);
3d45830c
AK		 4751 if (kvm->arch.apic_access_page)
4752 put_page(kvm->arch.apic_access_page);
b7ebfb05
SY		 4753 if (kvm->arch.ept_identity_pagetable)
4754 put_page(kvm->arch.ept_identity_pagetable);
d19a9cd2
ZX		 4755 kfree(kvm);
4756}
0de10343
ZX		 4757
4758int kvm_arch_set_memory_region(struct kvm *kvm,
4759 struct kvm_userspace_memory_region *mem,
4760 struct kvm_memory_slot old,
4761 int user_alloc)
4762{
4763 int npages = mem->memory_size >> PAGE_SHIFT;
4764 struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
4765
4766 /*To keep backward compatibility with older userspace,
4767 *x86 needs to hanlde !user_alloc case.
4768 */
4769 if (!user_alloc) {
4770 if (npages && !old.rmap) {
604b38ac
AA		 4771 unsigned long userspace_addr;
4772
72dc67a6 4773 down_write(&current->mm->mmap_sem);
604b38ac
AA		 4774 userspace_addr = do_mmap(NULL, 0,
4775 npages * PAGE_SIZE,
4776 PROT_READ | PROT_WRITE,
acee3c04 4777 MAP_PRIVATE | MAP_ANONYMOUS,
604b38ac 4778 0);
72dc67a6 4779 up_write(&current->mm->mmap_sem);
0de10343 4780
604b38ac
AA		 4781 if (IS_ERR((void *)userspace_addr))
4782 return PTR_ERR((void *)userspace_addr);
4783
4784 /* set userspace_addr atomically for kvm_hva_to_rmapp */
4785 spin_lock(&kvm->mmu_lock);
4786 memslot->userspace_addr = userspace_addr;
4787 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4788 } else {
4789 if (!old.user_alloc && old.rmap) {
4790 int ret;
4791
72dc67a6 4792 down_write(&current->mm->mmap_sem);
0de10343
ZX		 4793 ret = do_munmap(current->mm, old.userspace_addr,
4794 old.npages * PAGE_SIZE);
72dc67a6 4795 up_write(&current->mm->mmap_sem);
0de10343
ZX		 4796 if (ret < 0)
4797 printk(KERN_WARNING
4798 "kvm_vm_ioctl_set_memory_region: "
4799 "failed to munmap memory\n");
4800 }
4801 }
4802 }
4803
7c8a83b7 4804 spin_lock(&kvm->mmu_lock);
f05e70ac 4805 if (!kvm->arch.n_requested_mmu_pages) {
0de10343
ZX		 4806 unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
4807 kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
4808 }
4809
4810 kvm_mmu_slot_remove_write_access(kvm, mem->slot);
7c8a83b7 4811 spin_unlock(&kvm->mmu_lock);
0de10343
ZX		 4812 kvm_flush_remote_tlbs(kvm);
4813
4814 return 0;
4815}
1d737c8a 4816
34d4cb8f
MT		 4817void kvm_arch_flush_shadow(struct kvm *kvm)
4818{
4819 kvm_mmu_zap_all(kvm);
8986ecc0 4820 kvm_reload_remote_mmus(kvm);
34d4cb8f
MT		 4821}
4822
1d737c8a
ZX		 4823int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
4824{
a4535290 4825 return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
0496fbb9
JK		 4826 || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
4827 || vcpu->arch.nmi_pending;
1d737c8a 4828}
5736199a 4829
5736199a
ZX		 4830void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
4831{
32f88400
MT		 4832 int me;
4833 int cpu = vcpu->cpu;
5736199a
ZX		 4834
4835 if (waitqueue_active(&vcpu->wq)) {
4836 wake_up_interruptible(&vcpu->wq);
4837 ++vcpu->stat.halt_wakeup;
4838 }
32f88400
MT		 4839
4840 me = get_cpu();
4841 if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
4842 if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
4843 smp_send_reschedule(cpu);
e9571ed5 4844 put_cpu();
5736199a 4845}
78646121
GN		 4846
4847int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
4848{
4849 return kvm_x86_ops->interrupt_allowed(vcpu);
4850}
229456fc
MT		 4851
4852EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_exit);
4853EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_inj_virq);
4854EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_page_fault);
4855EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_msr);
4856EXPORT_TRACEPOINT_SYMBOL_GPL(kvm_cr);
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git