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[thirdparty/linux.git] / arch / x86 / mm / pat / set_memory.c
CommitLineData
457c8996 1// SPDX-License-Identifier: GPL-2.0-only
9f4c815c
IM
2/*
3 * Copyright 2002 Andi Kleen, SuSE Labs.
1da177e4 4 * Thanks to Ben LaHaise for precious feedback.
9f4c815c 5 */
1da177e4 6#include <linux/highmem.h>
57c8a661 7#include <linux/memblock.h>
9f4c815c 8#include <linux/sched.h>
9f4c815c 9#include <linux/mm.h>
76ebd054 10#include <linux/interrupt.h>
ee7ae7a1
TG
11#include <linux/seq_file.h>
12#include <linux/debugfs.h>
e59a1bb2 13#include <linux/pfn.h>
8c4bfc6e 14#include <linux/percpu.h>
5a0e3ad6 15#include <linux/gfp.h>
5bd5a452 16#include <linux/pci.h>
d6472302 17#include <linux/vmalloc.h>
5bacdc09 18#include <linux/libnvdimm.h>
9f4c815c 19
66441bd3 20#include <asm/e820/api.h>
1da177e4
LT
21#include <asm/processor.h>
22#include <asm/tlbflush.h>
f8af095d 23#include <asm/sections.h>
93dbda7c 24#include <asm/setup.h>
7c0f6ba6 25#include <linux/uaccess.h>
9f4c815c 26#include <asm/pgalloc.h>
c31c7d48 27#include <asm/proto.h>
eb243d1d 28#include <asm/memtype.h>
d1163651 29#include <asm/set_memory.h>
1da177e4 30
f9b57cf8 31#include "../mm_internal.h"
935f5839 32
9df84993
IM
33/*
34 * The current flushing context - we pass it instead of 5 arguments:
35 */
72e458df 36struct cpa_data {
d75586ad 37 unsigned long *vaddr;
0fd64c23 38 pgd_t *pgd;
72e458df
TG
39 pgprot_t mask_set;
40 pgprot_t mask_clr;
74256377 41 unsigned long numpages;
98bfc9b0 42 unsigned long curpage;
c31c7d48 43 unsigned long pfn;
98bfc9b0
PZ
44 unsigned int flags;
45 unsigned int force_split : 1,
ab513018
RE
46 force_static_prot : 1,
47 force_flush_all : 1;
9ae28475 48 struct page **pages;
72e458df
TG
49};
50
4046460b 51enum cpa_warn {
f61c5ba2 52 CPA_CONFLICT,
4046460b
TG
53 CPA_PROTECT,
54 CPA_DETECT,
55};
56
57static const int cpa_warn_level = CPA_PROTECT;
58
ad5ca55f
SS
59/*
60 * Serialize cpa() (for !DEBUG_PAGEALLOC which uses large identity mappings)
61 * using cpa_lock. So that we don't allow any other cpu, with stale large tlb
62 * entries change the page attribute in parallel to some other cpu
63 * splitting a large page entry along with changing the attribute.
64 */
65static DEFINE_SPINLOCK(cpa_lock);
66
d75586ad
SL
67#define CPA_FLUSHTLB 1
68#define CPA_ARRAY 2
9ae28475 69#define CPA_PAGES_ARRAY 4
c40a56a7 70#define CPA_NO_CHECK_ALIAS 8 /* Do not search for aliases */
d75586ad 71
65280e61 72#ifdef CONFIG_PROC_FS
ce0c0e50
AK
73static unsigned long direct_pages_count[PG_LEVEL_NUM];
74
65280e61 75void update_page_count(int level, unsigned long pages)
ce0c0e50 76{
ce0c0e50 77 /* Protect against CPA */
a79e53d8 78 spin_lock(&pgd_lock);
ce0c0e50 79 direct_pages_count[level] += pages;
a79e53d8 80 spin_unlock(&pgd_lock);
65280e61
TG
81}
82
83static void split_page_count(int level)
84{
c9e0d391
DJ
85 if (direct_pages_count[level] == 0)
86 return;
87
65280e61
TG
88 direct_pages_count[level]--;
89 direct_pages_count[level - 1] += PTRS_PER_PTE;
90}
91
e1759c21 92void arch_report_meminfo(struct seq_file *m)
65280e61 93{
b9c3bfc2 94 seq_printf(m, "DirectMap4k: %8lu kB\n",
a06de630
HD
95 direct_pages_count[PG_LEVEL_4K] << 2);
96#if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
b9c3bfc2 97 seq_printf(m, "DirectMap2M: %8lu kB\n",
a06de630
HD
98 direct_pages_count[PG_LEVEL_2M] << 11);
99#else
b9c3bfc2 100 seq_printf(m, "DirectMap4M: %8lu kB\n",
a06de630
HD
101 direct_pages_count[PG_LEVEL_2M] << 12);
102#endif
a06de630 103 if (direct_gbpages)
b9c3bfc2 104 seq_printf(m, "DirectMap1G: %8lu kB\n",
a06de630 105 direct_pages_count[PG_LEVEL_1G] << 20);
ce0c0e50 106}
65280e61
TG
107#else
108static inline void split_page_count(int level) { }
109#endif
ce0c0e50 110
5c280cf6
TG
111#ifdef CONFIG_X86_CPA_STATISTICS
112
113static unsigned long cpa_1g_checked;
114static unsigned long cpa_1g_sameprot;
115static unsigned long cpa_1g_preserved;
116static unsigned long cpa_2m_checked;
117static unsigned long cpa_2m_sameprot;
118static unsigned long cpa_2m_preserved;
5c280cf6
TG
119static unsigned long cpa_4k_install;
120
121static inline void cpa_inc_1g_checked(void)
122{
123 cpa_1g_checked++;
124}
125
126static inline void cpa_inc_2m_checked(void)
127{
128 cpa_2m_checked++;
129}
130
5c280cf6
TG
131static inline void cpa_inc_4k_install(void)
132{
133 cpa_4k_install++;
134}
135
136static inline void cpa_inc_lp_sameprot(int level)
137{
138 if (level == PG_LEVEL_1G)
139 cpa_1g_sameprot++;
140 else
141 cpa_2m_sameprot++;
142}
143
144static inline void cpa_inc_lp_preserved(int level)
145{
146 if (level == PG_LEVEL_1G)
147 cpa_1g_preserved++;
148 else
149 cpa_2m_preserved++;
150}
151
152static int cpastats_show(struct seq_file *m, void *p)
153{
154 seq_printf(m, "1G pages checked: %16lu\n", cpa_1g_checked);
155 seq_printf(m, "1G pages sameprot: %16lu\n", cpa_1g_sameprot);
156 seq_printf(m, "1G pages preserved: %16lu\n", cpa_1g_preserved);
157 seq_printf(m, "2M pages checked: %16lu\n", cpa_2m_checked);
158 seq_printf(m, "2M pages sameprot: %16lu\n", cpa_2m_sameprot);
159 seq_printf(m, "2M pages preserved: %16lu\n", cpa_2m_preserved);
5c280cf6
TG
160 seq_printf(m, "4K pages set-checked: %16lu\n", cpa_4k_install);
161 return 0;
162}
163
164static int cpastats_open(struct inode *inode, struct file *file)
165{
166 return single_open(file, cpastats_show, NULL);
167}
168
169static const struct file_operations cpastats_fops = {
170 .open = cpastats_open,
171 .read = seq_read,
172 .llseek = seq_lseek,
173 .release = single_release,
174};
175
176static int __init cpa_stats_init(void)
177{
178 debugfs_create_file("cpa_stats", S_IRUSR, arch_debugfs_dir, NULL,
179 &cpastats_fops);
180 return 0;
181}
182late_initcall(cpa_stats_init);
183#else
184static inline void cpa_inc_1g_checked(void) { }
185static inline void cpa_inc_2m_checked(void) { }
5c280cf6
TG
186static inline void cpa_inc_4k_install(void) { }
187static inline void cpa_inc_lp_sameprot(int level) { }
188static inline void cpa_inc_lp_preserved(int level) { }
189#endif
190
191
58e65b51
DH
192static inline int
193within(unsigned long addr, unsigned long start, unsigned long end)
194{
195 return addr >= start && addr < end;
196}
197
198static inline int
199within_inclusive(unsigned long addr, unsigned long start, unsigned long end)
200{
201 return addr >= start && addr <= end;
202}
203
c31c7d48
TG
204#ifdef CONFIG_X86_64
205
206static inline unsigned long highmap_start_pfn(void)
207{
fc8d7826 208 return __pa_symbol(_text) >> PAGE_SHIFT;
c31c7d48
TG
209}
210
211static inline unsigned long highmap_end_pfn(void)
212{
4ff53087
TG
213 /* Do not reference physical address outside the kernel. */
214 return __pa_symbol(roundup(_brk_end, PMD_SIZE) - 1) >> PAGE_SHIFT;
c31c7d48
TG
215}
216
58e65b51 217static bool __cpa_pfn_in_highmap(unsigned long pfn)
687c4825 218{
58e65b51
DH
219 /*
220 * Kernel text has an alias mapping at a high address, known
221 * here as "highmap".
222 */
223 return within_inclusive(pfn, highmap_start_pfn(), highmap_end_pfn());
ed724be6
AV
224}
225
58e65b51
DH
226#else
227
228static bool __cpa_pfn_in_highmap(unsigned long pfn)
4ff53087 229{
58e65b51
DH
230 /* There is no highmap on 32-bit */
231 return false;
4ff53087
TG
232}
233
58e65b51
DH
234#endif
235
0521e8be
PZ
236/*
237 * See set_mce_nospec().
238 *
239 * Machine check recovery code needs to change cache mode of poisoned pages to
240 * UC to avoid speculative access logging another error. But passing the
241 * address of the 1:1 mapping to set_memory_uc() is a fine way to encourage a
242 * speculative access. So we cheat and flip the top bit of the address. This
243 * works fine for the code that updates the page tables. But at the end of the
244 * process we need to flush the TLB and cache and the non-canonical address
245 * causes a #GP fault when used by the INVLPG and CLFLUSH instructions.
246 *
247 * But in the common case we already have a canonical address. This code
248 * will fix the top bit if needed and is a no-op otherwise.
249 */
250static inline unsigned long fix_addr(unsigned long addr)
251{
252#ifdef CONFIG_X86_64
253 return (long)(addr << 1) >> 1;
254#else
255 return addr;
256#endif
257}
258
98bfc9b0 259static unsigned long __cpa_addr(struct cpa_data *cpa, unsigned long idx)
16ebf031
PZ
260{
261 if (cpa->flags & CPA_PAGES_ARRAY) {
262 struct page *page = cpa->pages[idx];
263
264 if (unlikely(PageHighMem(page)))
265 return 0;
266
267 return (unsigned long)page_address(page);
268 }
269
270 if (cpa->flags & CPA_ARRAY)
271 return cpa->vaddr[idx];
272
98bfc9b0 273 return *cpa->vaddr + idx * PAGE_SIZE;
16ebf031
PZ
274}
275
d7c8f21a
TG
276/*
277 * Flushing functions
278 */
cd8ddf1a 279
c38116bb 280static void clflush_cache_range_opt(void *vaddr, unsigned int size)
d7c8f21a 281{
1f1a89ac
CW
282 const unsigned long clflush_size = boot_cpu_data.x86_clflush_size;
283 void *p = (void *)((unsigned long)vaddr & ~(clflush_size - 1));
6c434d61 284 void *vend = vaddr + size;
1f1a89ac
CW
285
286 if (p >= vend)
287 return;
d7c8f21a 288
1f1a89ac 289 for (; p < vend; p += clflush_size)
6c434d61 290 clflushopt(p);
c38116bb 291}
4c61afcd 292
c38116bb
PZ
293/**
294 * clflush_cache_range - flush a cache range with clflush
295 * @vaddr: virtual start address
296 * @size: number of bytes to flush
297 *
298 * CLFLUSHOPT is an unordered instruction which needs fencing with MFENCE or
299 * SFENCE to avoid ordering issues.
300 */
301void clflush_cache_range(void *vaddr, unsigned int size)
302{
303 mb();
304 clflush_cache_range_opt(vaddr, size);
cd8ddf1a 305 mb();
d7c8f21a 306}
e517a5e9 307EXPORT_SYMBOL_GPL(clflush_cache_range);
d7c8f21a 308
5bacdc09 309#ifdef CONFIG_ARCH_HAS_PMEM_API
f2b61257
DW
310void arch_invalidate_pmem(void *addr, size_t size)
311{
312 clflush_cache_range(addr, size);
313}
314EXPORT_SYMBOL_GPL(arch_invalidate_pmem);
5bacdc09 315#endif
f2b61257 316
af1e6844 317static void __cpa_flush_all(void *arg)
d7c8f21a 318{
6bb8383b
AK
319 unsigned long cache = (unsigned long)arg;
320
d7c8f21a
TG
321 /*
322 * Flush all to work around Errata in early athlons regarding
323 * large page flushing.
324 */
325 __flush_tlb_all();
326
0b827537 327 if (cache && boot_cpu_data.x86 >= 4)
d7c8f21a
TG
328 wbinvd();
329}
330
6bb8383b 331static void cpa_flush_all(unsigned long cache)
d7c8f21a 332{
d2479a30 333 BUG_ON(irqs_disabled() && !early_boot_irqs_disabled);
d7c8f21a 334
15c8b6c1 335 on_each_cpu(__cpa_flush_all, (void *) cache, 1);
d7c8f21a
TG
336}
337
da9144c5 338static void __cpa_flush_tlb(void *data)
57a6a46a 339{
935f5839
PZ
340 struct cpa_data *cpa = data;
341 unsigned int i;
47e262ac 342
935f5839 343 for (i = 0; i < cpa->numpages; i++)
0521e8be 344 __flush_tlb_one_kernel(fix_addr(__cpa_addr(cpa, i)));
47e262ac
PZ
345}
346
fe0937b2 347static void cpa_flush(struct cpa_data *data, int cache)
47e262ac 348{
fe0937b2 349 struct cpa_data *cpa = data;
935f5839 350 unsigned int i;
47e262ac 351
fe0937b2 352 BUG_ON(irqs_disabled() && !early_boot_irqs_disabled);
721066df 353
fe0937b2
PZ
354 if (cache && !static_cpu_has(X86_FEATURE_CLFLUSH)) {
355 cpa_flush_all(cache);
6bb8383b 356 return;
4c61afcd 357 }
57a6a46a 358
ab513018 359 if (cpa->force_flush_all || cpa->numpages > tlb_single_page_flush_ceiling)
935f5839 360 flush_tlb_all();
ab513018
RE
361 else
362 on_each_cpu(__cpa_flush_tlb, cpa, 1);
721066df
PZ
363
364 if (!cache)
d75586ad
SL
365 return;
366
c38116bb 367 mb();
935f5839
PZ
368 for (i = 0; i < cpa->numpages; i++) {
369 unsigned long addr = __cpa_addr(cpa, i);
370 unsigned int level;
9ae28475 371
fe0937b2 372 pte_t *pte = lookup_address(addr, &level);
d75586ad
SL
373
374 /*
375 * Only flush present addresses:
376 */
377 if (pte && (pte_val(*pte) & _PAGE_PRESENT))
0521e8be 378 clflush_cache_range_opt((void *)fix_addr(addr), PAGE_SIZE);
d75586ad 379 }
c38116bb 380 mb();
d75586ad
SL
381}
382
91ee8f5c
TG
383static bool overlaps(unsigned long r1_start, unsigned long r1_end,
384 unsigned long r2_start, unsigned long r2_end)
385{
386 return (r1_start <= r2_end && r1_end >= r2_start) ||
387 (r2_start <= r1_end && r2_end >= r1_start);
388}
389
afd7969a 390#ifdef CONFIG_PCI_BIOS
ed724be6 391/*
afd7969a
TG
392 * The BIOS area between 640k and 1Mb needs to be executable for PCI BIOS
393 * based config access (CONFIG_PCI_GOBIOS) support.
ed724be6 394 */
afd7969a 395#define BIOS_PFN PFN_DOWN(BIOS_BEGIN)
91ee8f5c 396#define BIOS_PFN_END PFN_DOWN(BIOS_END - 1)
ed724be6 397
91ee8f5c 398static pgprotval_t protect_pci_bios(unsigned long spfn, unsigned long epfn)
afd7969a 399{
91ee8f5c 400 if (pcibios_enabled && overlaps(spfn, epfn, BIOS_PFN, BIOS_PFN_END))
afd7969a
TG
401 return _PAGE_NX;
402 return 0;
403}
404#else
91ee8f5c 405static pgprotval_t protect_pci_bios(unsigned long spfn, unsigned long epfn)
afd7969a
TG
406{
407 return 0;
408}
5bd5a452 409#endif
ed724be6 410
afd7969a
TG
411/*
412 * The .rodata section needs to be read-only. Using the pfn catches all
413 * aliases. This also includes __ro_after_init, so do not enforce until
414 * kernel_set_to_readonly is true.
415 */
91ee8f5c 416static pgprotval_t protect_rodata(unsigned long spfn, unsigned long epfn)
afd7969a 417{
91ee8f5c
TG
418 unsigned long epfn_ro, spfn_ro = PFN_DOWN(__pa_symbol(__start_rodata));
419
420 /*
421 * Note: __end_rodata is at page aligned and not inclusive, so
422 * subtract 1 to get the last enforced PFN in the rodata area.
423 */
424 epfn_ro = PFN_DOWN(__pa_symbol(__end_rodata)) - 1;
cc0f21bb 425
91ee8f5c 426 if (kernel_set_to_readonly && overlaps(spfn, epfn, spfn_ro, epfn_ro))
afd7969a
TG
427 return _PAGE_RW;
428 return 0;
429}
430
431/*
432 * Protect kernel text against becoming non executable by forbidding
433 * _PAGE_NX. This protects only the high kernel mapping (_text -> _etext)
434 * out of which the kernel actually executes. Do not protect the low
435 * mapping.
436 *
437 * This does not cover __inittext since that is gone after boot.
438 */
91ee8f5c 439static pgprotval_t protect_kernel_text(unsigned long start, unsigned long end)
afd7969a 440{
91ee8f5c
TG
441 unsigned long t_end = (unsigned long)_etext - 1;
442 unsigned long t_start = (unsigned long)_text;
443
444 if (overlaps(start, end, t_start, t_end))
afd7969a
TG
445 return _PAGE_NX;
446 return 0;
447}
ed724be6 448
9ccaf77c 449#if defined(CONFIG_X86_64)
afd7969a
TG
450/*
451 * Once the kernel maps the text as RO (kernel_set_to_readonly is set),
452 * kernel text mappings for the large page aligned text, rodata sections
453 * will be always read-only. For the kernel identity mappings covering the
454 * holes caused by this alignment can be anything that user asks.
455 *
456 * This will preserve the large page mappings for kernel text/data at no
457 * extra cost.
458 */
91ee8f5c
TG
459static pgprotval_t protect_kernel_text_ro(unsigned long start,
460 unsigned long end)
afd7969a 461{
91ee8f5c
TG
462 unsigned long t_end = (unsigned long)__end_rodata_hpage_align - 1;
463 unsigned long t_start = (unsigned long)_text;
afd7969a
TG
464 unsigned int level;
465
91ee8f5c 466 if (!kernel_set_to_readonly || !overlaps(start, end, t_start, t_end))
afd7969a 467 return 0;
74e08179 468 /*
afd7969a
TG
469 * Don't enforce the !RW mapping for the kernel text mapping, if
470 * the current mapping is already using small page mapping. No
471 * need to work hard to preserve large page mappings in this case.
74e08179 472 *
afd7969a
TG
473 * This also fixes the Linux Xen paravirt guest boot failure caused
474 * by unexpected read-only mappings for kernel identity
475 * mappings. In this paravirt guest case, the kernel text mapping
476 * and the kernel identity mapping share the same page-table pages,
477 * so the protections for kernel text and identity mappings have to
478 * be the same.
74e08179 479 */
91ee8f5c 480 if (lookup_address(start, &level) && (level != PG_LEVEL_4K))
afd7969a
TG
481 return _PAGE_RW;
482 return 0;
483}
484#else
91ee8f5c
TG
485static pgprotval_t protect_kernel_text_ro(unsigned long start,
486 unsigned long end)
afd7969a
TG
487{
488 return 0;
489}
74e08179
SS
490#endif
491
4046460b
TG
492static inline bool conflicts(pgprot_t prot, pgprotval_t val)
493{
494 return (pgprot_val(prot) & ~val) != pgprot_val(prot);
495}
496
497static inline void check_conflict(int warnlvl, pgprot_t prot, pgprotval_t val,
498 unsigned long start, unsigned long end,
499 unsigned long pfn, const char *txt)
500{
501 static const char *lvltxt[] = {
f61c5ba2 502 [CPA_CONFLICT] = "conflict",
4046460b
TG
503 [CPA_PROTECT] = "protect",
504 [CPA_DETECT] = "detect",
505 };
506
507 if (warnlvl > cpa_warn_level || !conflicts(prot, val))
508 return;
509
510 pr_warn("CPA %8s %10s: 0x%016lx - 0x%016lx PFN %lx req %016llx prevent %016llx\n",
511 lvltxt[warnlvl], txt, start, end, pfn, (unsigned long long)pgprot_val(prot),
512 (unsigned long long)val);
513}
514
afd7969a
TG
515/*
516 * Certain areas of memory on x86 require very specific protection flags,
517 * for example the BIOS area or kernel text. Callers don't always get this
518 * right (again, ioremap() on BIOS memory is not uncommon) so this function
519 * checks and fixes these known static required protection bits.
520 */
91ee8f5c 521static inline pgprot_t static_protections(pgprot_t prot, unsigned long start,
4046460b 522 unsigned long pfn, unsigned long npg,
7af01450 523 unsigned long lpsize, int warnlvl)
afd7969a 524{
4046460b 525 pgprotval_t forbidden, res;
91ee8f5c 526 unsigned long end;
afd7969a 527
69c31e69
TG
528 /*
529 * There is no point in checking RW/NX conflicts when the requested
530 * mapping is setting the page !PRESENT.
531 */
532 if (!(pgprot_val(prot) & _PAGE_PRESENT))
533 return prot;
534
afd7969a 535 /* Operate on the virtual address */
91ee8f5c 536 end = start + npg * PAGE_SIZE - 1;
4046460b
TG
537
538 res = protect_kernel_text(start, end);
539 check_conflict(warnlvl, prot, res, start, end, pfn, "Text NX");
540 forbidden = res;
541
7af01450
TG
542 /*
543 * Special case to preserve a large page. If the change spawns the
544 * full large page mapping then there is no point to split it
545 * up. Happens with ftrace and is going to be removed once ftrace
546 * switched to text_poke().
547 */
548 if (lpsize != (npg * PAGE_SIZE) || (start & (lpsize - 1))) {
549 res = protect_kernel_text_ro(start, end);
550 check_conflict(warnlvl, prot, res, start, end, pfn, "Text RO");
551 forbidden |= res;
552 }
afd7969a
TG
553
554 /* Check the PFN directly */
4046460b
TG
555 res = protect_pci_bios(pfn, pfn + npg - 1);
556 check_conflict(warnlvl, prot, res, start, end, pfn, "PCIBIOS NX");
557 forbidden |= res;
558
559 res = protect_rodata(pfn, pfn + npg - 1);
560 check_conflict(warnlvl, prot, res, start, end, pfn, "Rodata RO");
561 forbidden |= res;
687c4825 562
afd7969a 563 return __pgprot(pgprot_val(prot) & ~forbidden);
687c4825
IM
564}
565
426e34cc
MF
566/*
567 * Lookup the page table entry for a virtual address in a specific pgd.
568 * Return a pointer to the entry and the level of the mapping.
569 */
570pte_t *lookup_address_in_pgd(pgd_t *pgd, unsigned long address,
571 unsigned int *level)
9f4c815c 572{
45478336 573 p4d_t *p4d;
1da177e4
LT
574 pud_t *pud;
575 pmd_t *pmd;
9f4c815c 576
30551bb3
TG
577 *level = PG_LEVEL_NONE;
578
1da177e4
LT
579 if (pgd_none(*pgd))
580 return NULL;
9df84993 581
45478336
KS
582 p4d = p4d_offset(pgd, address);
583 if (p4d_none(*p4d))
584 return NULL;
585
586 *level = PG_LEVEL_512G;
587 if (p4d_large(*p4d) || !p4d_present(*p4d))
588 return (pte_t *)p4d;
589
590 pud = pud_offset(p4d, address);
1da177e4
LT
591 if (pud_none(*pud))
592 return NULL;
c2f71ee2
AK
593
594 *level = PG_LEVEL_1G;
595 if (pud_large(*pud) || !pud_present(*pud))
596 return (pte_t *)pud;
597
1da177e4
LT
598 pmd = pmd_offset(pud, address);
599 if (pmd_none(*pmd))
600 return NULL;
30551bb3
TG
601
602 *level = PG_LEVEL_2M;
9a14aefc 603 if (pmd_large(*pmd) || !pmd_present(*pmd))
1da177e4 604 return (pte_t *)pmd;
1da177e4 605
30551bb3 606 *level = PG_LEVEL_4K;
9df84993 607
9f4c815c
IM
608 return pte_offset_kernel(pmd, address);
609}
0fd64c23
BP
610
611/*
612 * Lookup the page table entry for a virtual address. Return a pointer
613 * to the entry and the level of the mapping.
614 *
615 * Note: We return pud and pmd either when the entry is marked large
616 * or when the present bit is not set. Otherwise we would return a
617 * pointer to a nonexisting mapping.
618 */
619pte_t *lookup_address(unsigned long address, unsigned int *level)
620{
8679de09 621 return lookup_address_in_pgd(pgd_offset_k(address), address, level);
0fd64c23 622}
75bb8835 623EXPORT_SYMBOL_GPL(lookup_address);
9f4c815c 624
13c72c06
SC
625/*
626 * Lookup the page table entry for a virtual address in a given mm. Return a
627 * pointer to the entry and the level of the mapping.
628 */
629pte_t *lookup_address_in_mm(struct mm_struct *mm, unsigned long address,
630 unsigned int *level)
631{
632 return lookup_address_in_pgd(pgd_offset(mm, address), address, level);
633}
634EXPORT_SYMBOL_GPL(lookup_address_in_mm);
635
0fd64c23
BP
636static pte_t *_lookup_address_cpa(struct cpa_data *cpa, unsigned long address,
637 unsigned int *level)
638{
8679de09 639 if (cpa->pgd)
426e34cc 640 return lookup_address_in_pgd(cpa->pgd + pgd_index(address),
0fd64c23
BP
641 address, level);
642
8679de09 643 return lookup_address(address, level);
0fd64c23
BP
644}
645
792230c3
JG
646/*
647 * Lookup the PMD entry for a virtual address. Return a pointer to the entry
648 * or NULL if not present.
649 */
650pmd_t *lookup_pmd_address(unsigned long address)
651{
652 pgd_t *pgd;
45478336 653 p4d_t *p4d;
792230c3
JG
654 pud_t *pud;
655
656 pgd = pgd_offset_k(address);
657 if (pgd_none(*pgd))
658 return NULL;
659
45478336
KS
660 p4d = p4d_offset(pgd, address);
661 if (p4d_none(*p4d) || p4d_large(*p4d) || !p4d_present(*p4d))
662 return NULL;
663
664 pud = pud_offset(p4d, address);
792230c3
JG
665 if (pud_none(*pud) || pud_large(*pud) || !pud_present(*pud))
666 return NULL;
667
668 return pmd_offset(pud, address);
669}
670
d7656534
DH
671/*
672 * This is necessary because __pa() does not work on some
673 * kinds of memory, like vmalloc() or the alloc_remap()
674 * areas on 32-bit NUMA systems. The percpu areas can
675 * end up in this kind of memory, for instance.
676 *
677 * This could be optimized, but it is only intended to be
678 * used at inititalization time, and keeping it
679 * unoptimized should increase the testing coverage for
680 * the more obscure platforms.
681 */
682phys_addr_t slow_virt_to_phys(void *__virt_addr)
683{
684 unsigned long virt_addr = (unsigned long)__virt_addr;
bf70e551
DC
685 phys_addr_t phys_addr;
686 unsigned long offset;
d7656534 687 enum pg_level level;
d7656534
DH
688 pte_t *pte;
689
690 pte = lookup_address(virt_addr, &level);
691 BUG_ON(!pte);
34437e67 692
bf70e551
DC
693 /*
694 * pXX_pfn() returns unsigned long, which must be cast to phys_addr_t
695 * before being left-shifted PAGE_SHIFT bits -- this trick is to
696 * make 32-PAE kernel work correctly.
697 */
34437e67
TK
698 switch (level) {
699 case PG_LEVEL_1G:
bf70e551 700 phys_addr = (phys_addr_t)pud_pfn(*(pud_t *)pte) << PAGE_SHIFT;
34437e67
TK
701 offset = virt_addr & ~PUD_PAGE_MASK;
702 break;
703 case PG_LEVEL_2M:
bf70e551 704 phys_addr = (phys_addr_t)pmd_pfn(*(pmd_t *)pte) << PAGE_SHIFT;
34437e67
TK
705 offset = virt_addr & ~PMD_PAGE_MASK;
706 break;
707 default:
bf70e551 708 phys_addr = (phys_addr_t)pte_pfn(*pte) << PAGE_SHIFT;
34437e67
TK
709 offset = virt_addr & ~PAGE_MASK;
710 }
711
712 return (phys_addr_t)(phys_addr | offset);
d7656534
DH
713}
714EXPORT_SYMBOL_GPL(slow_virt_to_phys);
715
9df84993
IM
716/*
717 * Set the new pmd in all the pgds we know about:
718 */
9a3dc780 719static void __set_pmd_pte(pte_t *kpte, unsigned long address, pte_t pte)
9f4c815c 720{
9f4c815c
IM
721 /* change init_mm */
722 set_pte_atomic(kpte, pte);
44af6c41 723#ifdef CONFIG_X86_32
e4b71dcf 724 if (!SHARED_KERNEL_PMD) {
44af6c41
IM
725 struct page *page;
726
e3ed910d 727 list_for_each_entry(page, &pgd_list, lru) {
44af6c41 728 pgd_t *pgd;
45478336 729 p4d_t *p4d;
44af6c41
IM
730 pud_t *pud;
731 pmd_t *pmd;
732
733 pgd = (pgd_t *)page_address(page) + pgd_index(address);
45478336
KS
734 p4d = p4d_offset(pgd, address);
735 pud = pud_offset(p4d, address);
44af6c41
IM
736 pmd = pmd_offset(pud, address);
737 set_pte_atomic((pte_t *)pmd, pte);
738 }
1da177e4 739 }
44af6c41 740#endif
1da177e4
LT
741}
742
d1440b23
DH
743static pgprot_t pgprot_clear_protnone_bits(pgprot_t prot)
744{
745 /*
746 * _PAGE_GLOBAL means "global page" for present PTEs.
747 * But, it is also used to indicate _PAGE_PROTNONE
748 * for non-present PTEs.
749 *
750 * This ensures that a _PAGE_GLOBAL PTE going from
751 * present to non-present is not confused as
752 * _PAGE_PROTNONE.
753 */
754 if (!(pgprot_val(prot) & _PAGE_PRESENT))
755 pgprot_val(prot) &= ~_PAGE_GLOBAL;
756
757 return prot;
758}
759
8679de09
TG
760static int __should_split_large_page(pte_t *kpte, unsigned long address,
761 struct cpa_data *cpa)
65e074df 762{
585948f4 763 unsigned long numpages, pmask, psize, lpaddr, pfn, old_pfn;
f61c5ba2 764 pgprot_t old_prot, new_prot, req_prot, chk_prot;
24c41220 765 pte_t new_pte, *tmp;
f3c4fbb6 766 enum pg_level level;
65e074df 767
65e074df
TG
768 /*
769 * Check for races, another CPU might have split this page
770 * up already:
771 */
82f0712c 772 tmp = _lookup_address_cpa(cpa, address, &level);
65e074df 773 if (tmp != kpte)
8679de09 774 return 1;
65e074df
TG
775
776 switch (level) {
777 case PG_LEVEL_2M:
3a19109e
TK
778 old_prot = pmd_pgprot(*(pmd_t *)kpte);
779 old_pfn = pmd_pfn(*(pmd_t *)kpte);
5c280cf6 780 cpa_inc_2m_checked();
3a19109e 781 break;
65e074df 782 case PG_LEVEL_1G:
3a19109e
TK
783 old_prot = pud_pgprot(*(pud_t *)kpte);
784 old_pfn = pud_pfn(*(pud_t *)kpte);
5c280cf6 785 cpa_inc_1g_checked();
f3c4fbb6 786 break;
65e074df 787 default:
8679de09 788 return -EINVAL;
65e074df
TG
789 }
790
3a19109e
TK
791 psize = page_level_size(level);
792 pmask = page_level_mask(level);
793
65e074df
TG
794 /*
795 * Calculate the number of pages, which fit into this large
796 * page starting at address:
797 */
8679de09
TG
798 lpaddr = (address + psize) & pmask;
799 numpages = (lpaddr - address) >> PAGE_SHIFT;
9b5cf48b
RW
800 if (numpages < cpa->numpages)
801 cpa->numpages = numpages;
65e074df
TG
802
803 /*
804 * We are safe now. Check whether the new pgprot is the same:
f5b2831d
JG
805 * Convert protection attributes to 4k-format, as cpa->mask* are set
806 * up accordingly.
65e074df 807 */
24c41220 808
606c7193 809 /* Clear PSE (aka _PAGE_PAT) and move PAT bit to correct position */
55696b1f 810 req_prot = pgprot_large_2_4k(old_prot);
65e074df 811
64edc8ed
MC
812 pgprot_val(req_prot) &= ~pgprot_val(cpa->mask_clr);
813 pgprot_val(req_prot) |= pgprot_val(cpa->mask_set);
c31c7d48 814
f5b2831d
JG
815 /*
816 * req_prot is in format of 4k pages. It must be converted to large
817 * page format: the caching mode includes the PAT bit located at
818 * different bit positions in the two formats.
819 */
820 req_prot = pgprot_4k_2_large(req_prot);
d1440b23 821 req_prot = pgprot_clear_protnone_bits(req_prot);
f76cfa3c 822 if (pgprot_val(req_prot) & _PAGE_PRESENT)
d1440b23 823 pgprot_val(req_prot) |= _PAGE_PSE;
a8aed3e0 824
c31c7d48 825 /*
8679de09
TG
826 * old_pfn points to the large page base pfn. So we need to add the
827 * offset of the virtual address:
c31c7d48 828 */
3a19109e 829 pfn = old_pfn + ((address & (psize - 1)) >> PAGE_SHIFT);
c31c7d48
TG
830 cpa->pfn = pfn;
831
8679de09
TG
832 /*
833 * Calculate the large page base address and the number of 4K pages
834 * in the large page
835 */
836 lpaddr = address & pmask;
837 numpages = psize >> PAGE_SHIFT;
65e074df 838
f61c5ba2
TG
839 /*
840 * Sanity check that the existing mapping is correct versus the static
841 * protections. static_protections() guards against !PRESENT, so no
842 * extra conditional required here.
843 */
844 chk_prot = static_protections(old_prot, lpaddr, old_pfn, numpages,
7af01450 845 psize, CPA_CONFLICT);
f61c5ba2
TG
846
847 if (WARN_ON_ONCE(pgprot_val(chk_prot) != pgprot_val(old_prot))) {
848 /*
849 * Split the large page and tell the split code to
850 * enforce static protections.
851 */
852 cpa->force_static_prot = 1;
853 return 1;
854 }
855
1c4b406e
TG
856 /*
857 * Optimization: If the requested pgprot is the same as the current
858 * pgprot, then the large page can be preserved and no updates are
859 * required independent of alignment and length of the requested
860 * range. The above already established that the current pgprot is
861 * correct, which in consequence makes the requested pgprot correct
862 * as well if it is the same. The static protection scan below will
863 * not come to a different conclusion.
864 */
865 if (pgprot_val(req_prot) == pgprot_val(old_prot)) {
866 cpa_inc_lp_sameprot(level);
867 return 0;
868 }
869
fac84939 870 /*
585948f4 871 * If the requested range does not cover the full page, split it up
9cc9f17a 872 */
585948f4
TG
873 if (address != lpaddr || cpa->numpages != numpages)
874 return 1;
9cc9f17a
TG
875
876 /*
585948f4
TG
877 * Check whether the requested pgprot is conflicting with a static
878 * protection requirement in the large page.
fac84939 879 */
585948f4 880 new_prot = static_protections(req_prot, lpaddr, old_pfn, numpages,
7af01450 881 psize, CPA_DETECT);
65e074df
TG
882
883 /*
585948f4
TG
884 * If there is a conflict, split the large page.
885 *
886 * There used to be a 4k wise evaluation trying really hard to
887 * preserve the large pages, but experimentation has shown, that this
888 * does not help at all. There might be corner cases which would
889 * preserve one large page occasionally, but it's really not worth the
890 * extra code and cycles for the common case.
65e074df 891 */
585948f4 892 if (pgprot_val(req_prot) != pgprot_val(new_prot))
8679de09
TG
893 return 1;
894
895 /* All checks passed. Update the large page mapping. */
896 new_pte = pfn_pte(old_pfn, new_prot);
897 __set_pmd_pte(kpte, address, new_pte);
898 cpa->flags |= CPA_FLUSHTLB;
5c280cf6 899 cpa_inc_lp_preserved(level);
8679de09
TG
900 return 0;
901}
902
903static int should_split_large_page(pte_t *kpte, unsigned long address,
904 struct cpa_data *cpa)
905{
906 int do_split;
907
908 if (cpa->force_split)
909 return 1;
65e074df 910
8679de09
TG
911 spin_lock(&pgd_lock);
912 do_split = __should_split_large_page(kpte, address, cpa);
a79e53d8 913 spin_unlock(&pgd_lock);
9df84993 914
beaff633 915 return do_split;
65e074df
TG
916}
917
f61c5ba2
TG
918static void split_set_pte(struct cpa_data *cpa, pte_t *pte, unsigned long pfn,
919 pgprot_t ref_prot, unsigned long address,
920 unsigned long size)
921{
922 unsigned int npg = PFN_DOWN(size);
923 pgprot_t prot;
924
925 /*
926 * If should_split_large_page() discovered an inconsistent mapping,
927 * remove the invalid protection in the split mapping.
928 */
929 if (!cpa->force_static_prot)
930 goto set;
931
7af01450
TG
932 /* Hand in lpsize = 0 to enforce the protection mechanism */
933 prot = static_protections(ref_prot, address, pfn, npg, 0, CPA_PROTECT);
f61c5ba2
TG
934
935 if (pgprot_val(prot) == pgprot_val(ref_prot))
936 goto set;
937
938 /*
939 * If this is splitting a PMD, fix it up. PUD splits cannot be
940 * fixed trivially as that would require to rescan the newly
941 * installed PMD mappings after returning from split_large_page()
942 * so an eventual further split can allocate the necessary PTE
943 * pages. Warn for now and revisit it in case this actually
944 * happens.
945 */
946 if (size == PAGE_SIZE)
947 ref_prot = prot;
948 else
949 pr_warn_once("CPA: Cannot fixup static protections for PUD split\n");
950set:
951 set_pte(pte, pfn_pte(pfn, ref_prot));
952}
953
5952886b 954static int
82f0712c
BP
955__split_large_page(struct cpa_data *cpa, pte_t *kpte, unsigned long address,
956 struct page *base)
bb5c2dbd 957{
f61c5ba2 958 unsigned long lpaddr, lpinc, ref_pfn, pfn, pfninc = 1;
5952886b 959 pte_t *pbase = (pte_t *)page_address(base);
9df84993 960 unsigned int i, level;
9df84993 961 pgprot_t ref_prot;
f61c5ba2 962 pte_t *tmp;
bb5c2dbd 963
a79e53d8 964 spin_lock(&pgd_lock);
bb5c2dbd
IM
965 /*
966 * Check for races, another CPU might have split this page
967 * up for us already:
968 */
82f0712c 969 tmp = _lookup_address_cpa(cpa, address, &level);
ae9aae9e
WC
970 if (tmp != kpte) {
971 spin_unlock(&pgd_lock);
972 return 1;
973 }
bb5c2dbd 974
6944a9c8 975 paravirt_alloc_pte(&init_mm, page_to_pfn(base));
f5b2831d 976
d551aaa2
TK
977 switch (level) {
978 case PG_LEVEL_2M:
979 ref_prot = pmd_pgprot(*(pmd_t *)kpte);
606c7193
DH
980 /*
981 * Clear PSE (aka _PAGE_PAT) and move
982 * PAT bit to correct position.
983 */
f5b2831d 984 ref_prot = pgprot_large_2_4k(ref_prot);
d551aaa2 985 ref_pfn = pmd_pfn(*(pmd_t *)kpte);
f61c5ba2
TG
986 lpaddr = address & PMD_MASK;
987 lpinc = PAGE_SIZE;
d551aaa2 988 break;
bb5c2dbd 989
d551aaa2
TK
990 case PG_LEVEL_1G:
991 ref_prot = pud_pgprot(*(pud_t *)kpte);
992 ref_pfn = pud_pfn(*(pud_t *)kpte);
f07333fd 993 pfninc = PMD_PAGE_SIZE >> PAGE_SHIFT;
f61c5ba2
TG
994 lpaddr = address & PUD_MASK;
995 lpinc = PMD_SIZE;
a8aed3e0 996 /*
d551aaa2 997 * Clear the PSE flags if the PRESENT flag is not set
a8aed3e0
AA
998 * otherwise pmd_present/pmd_huge will return true
999 * even on a non present pmd.
1000 */
d551aaa2 1001 if (!(pgprot_val(ref_prot) & _PAGE_PRESENT))
a8aed3e0 1002 pgprot_val(ref_prot) &= ~_PAGE_PSE;
d551aaa2
TK
1003 break;
1004
1005 default:
1006 spin_unlock(&pgd_lock);
1007 return 1;
f07333fd 1008 }
f07333fd 1009
d1440b23 1010 ref_prot = pgprot_clear_protnone_bits(ref_prot);
a8aed3e0 1011
63c1dcf4
TG
1012 /*
1013 * Get the target pfn from the original entry:
1014 */
d551aaa2 1015 pfn = ref_pfn;
f61c5ba2
TG
1016 for (i = 0; i < PTRS_PER_PTE; i++, pfn += pfninc, lpaddr += lpinc)
1017 split_set_pte(cpa, pbase + i, pfn, ref_prot, lpaddr, lpinc);
bb5c2dbd 1018
2c66e24d
SP
1019 if (virt_addr_valid(address)) {
1020 unsigned long pfn = PFN_DOWN(__pa(address));
1021
1022 if (pfn_range_is_mapped(pfn, pfn + 1))
1023 split_page_count(level);
1024 }
f361a450 1025
bb5c2dbd 1026 /*
07a66d7c 1027 * Install the new, split up pagetable.
4c881ca1 1028 *
07a66d7c
IM
1029 * We use the standard kernel pagetable protections for the new
1030 * pagetable protections, the actual ptes set above control the
1031 * primary protection behavior:
bb5c2dbd 1032 */
07a66d7c 1033 __set_pmd_pte(kpte, address, mk_pte(base, __pgprot(_KERNPG_TABLE)));
211b3d03
IM
1034
1035 /*
c0a759ab
PZ
1036 * Do a global flush tlb after splitting the large page
1037 * and before we do the actual change page attribute in the PTE.
211b3d03 1038 *
c0a759ab
PZ
1039 * Without this, we violate the TLB application note, that says:
1040 * "The TLBs may contain both ordinary and large-page
1041 * translations for a 4-KByte range of linear addresses. This
1042 * may occur if software modifies the paging structures so that
1043 * the page size used for the address range changes. If the two
1044 * translations differ with respect to page frame or attributes
1045 * (e.g., permissions), processor behavior is undefined and may
1046 * be implementation-specific."
1047 *
1048 * We do this global tlb flush inside the cpa_lock, so that we
1049 * don't allow any other cpu, with stale tlb entries change the
1050 * page attribute in parallel, that also falls into the
1051 * just split large page entry.
211b3d03 1052 */
c0a759ab 1053 flush_tlb_all();
ae9aae9e 1054 spin_unlock(&pgd_lock);
211b3d03 1055
ae9aae9e
WC
1056 return 0;
1057}
bb5c2dbd 1058
82f0712c
BP
1059static int split_large_page(struct cpa_data *cpa, pte_t *kpte,
1060 unsigned long address)
ae9aae9e 1061{
ae9aae9e
WC
1062 struct page *base;
1063
288cf3c6 1064 if (!debug_pagealloc_enabled())
ae9aae9e 1065 spin_unlock(&cpa_lock);
75f296d9 1066 base = alloc_pages(GFP_KERNEL, 0);
288cf3c6 1067 if (!debug_pagealloc_enabled())
ae9aae9e
WC
1068 spin_lock(&cpa_lock);
1069 if (!base)
1070 return -ENOMEM;
1071
82f0712c 1072 if (__split_large_page(cpa, kpte, address, base))
8311eb84 1073 __free_page(base);
bb5c2dbd 1074
bb5c2dbd
IM
1075 return 0;
1076}
1077
52a628fb
BP
1078static bool try_to_free_pte_page(pte_t *pte)
1079{
1080 int i;
1081
1082 for (i = 0; i < PTRS_PER_PTE; i++)
1083 if (!pte_none(pte[i]))
1084 return false;
1085
1086 free_page((unsigned long)pte);
1087 return true;
1088}
1089
1090static bool try_to_free_pmd_page(pmd_t *pmd)
1091{
1092 int i;
1093
1094 for (i = 0; i < PTRS_PER_PMD; i++)
1095 if (!pmd_none(pmd[i]))
1096 return false;
1097
1098 free_page((unsigned long)pmd);
1099 return true;
1100}
1101
1102static bool unmap_pte_range(pmd_t *pmd, unsigned long start, unsigned long end)
1103{
1104 pte_t *pte = pte_offset_kernel(pmd, start);
1105
1106 while (start < end) {
1107 set_pte(pte, __pte(0));
1108
1109 start += PAGE_SIZE;
1110 pte++;
1111 }
1112
1113 if (try_to_free_pte_page((pte_t *)pmd_page_vaddr(*pmd))) {
1114 pmd_clear(pmd);
1115 return true;
1116 }
1117 return false;
1118}
1119
1120static void __unmap_pmd_range(pud_t *pud, pmd_t *pmd,
1121 unsigned long start, unsigned long end)
1122{
1123 if (unmap_pte_range(pmd, start, end))
1124 if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud)))
1125 pud_clear(pud);
1126}
1127
1128static void unmap_pmd_range(pud_t *pud, unsigned long start, unsigned long end)
1129{
1130 pmd_t *pmd = pmd_offset(pud, start);
1131
1132 /*
1133 * Not on a 2MB page boundary?
1134 */
1135 if (start & (PMD_SIZE - 1)) {
1136 unsigned long next_page = (start + PMD_SIZE) & PMD_MASK;
1137 unsigned long pre_end = min_t(unsigned long, end, next_page);
1138
1139 __unmap_pmd_range(pud, pmd, start, pre_end);
1140
1141 start = pre_end;
1142 pmd++;
1143 }
1144
1145 /*
1146 * Try to unmap in 2M chunks.
1147 */
1148 while (end - start >= PMD_SIZE) {
1149 if (pmd_large(*pmd))
1150 pmd_clear(pmd);
1151 else
1152 __unmap_pmd_range(pud, pmd, start, start + PMD_SIZE);
1153
1154 start += PMD_SIZE;
1155 pmd++;
1156 }
1157
1158 /*
1159 * 4K leftovers?
1160 */
1161 if (start < end)
1162 return __unmap_pmd_range(pud, pmd, start, end);
1163
1164 /*
1165 * Try again to free the PMD page if haven't succeeded above.
1166 */
1167 if (!pud_none(*pud))
1168 if (try_to_free_pmd_page((pmd_t *)pud_page_vaddr(*pud)))
1169 pud_clear(pud);
1170}
0bb8aeee 1171
45478336 1172static void unmap_pud_range(p4d_t *p4d, unsigned long start, unsigned long end)
0bb8aeee 1173{
45478336 1174 pud_t *pud = pud_offset(p4d, start);
0bb8aeee
BP
1175
1176 /*
1177 * Not on a GB page boundary?
1178 */
1179 if (start & (PUD_SIZE - 1)) {
1180 unsigned long next_page = (start + PUD_SIZE) & PUD_MASK;
1181 unsigned long pre_end = min_t(unsigned long, end, next_page);
1182
1183 unmap_pmd_range(pud, start, pre_end);
1184
1185 start = pre_end;
1186 pud++;
1187 }
1188
1189 /*
1190 * Try to unmap in 1G chunks?
1191 */
1192 while (end - start >= PUD_SIZE) {
1193
1194 if (pud_large(*pud))
1195 pud_clear(pud);
1196 else
1197 unmap_pmd_range(pud, start, start + PUD_SIZE);
1198
1199 start += PUD_SIZE;
1200 pud++;
1201 }
1202
1203 /*
1204 * 2M leftovers?
1205 */
1206 if (start < end)
1207 unmap_pmd_range(pud, start, end);
1208
1209 /*
1210 * No need to try to free the PUD page because we'll free it in
1211 * populate_pgd's error path
1212 */
1213}
1214
f900a4b8
BP
1215static int alloc_pte_page(pmd_t *pmd)
1216{
75f296d9 1217 pte_t *pte = (pte_t *)get_zeroed_page(GFP_KERNEL);
f900a4b8
BP
1218 if (!pte)
1219 return -1;
1220
1221 set_pmd(pmd, __pmd(__pa(pte) | _KERNPG_TABLE));
1222 return 0;
1223}
1224
4b23538d
BP
1225static int alloc_pmd_page(pud_t *pud)
1226{
75f296d9 1227 pmd_t *pmd = (pmd_t *)get_zeroed_page(GFP_KERNEL);
4b23538d
BP
1228 if (!pmd)
1229 return -1;
1230
1231 set_pud(pud, __pud(__pa(pmd) | _KERNPG_TABLE));
1232 return 0;
1233}
1234
c6b6f363
BP
1235static void populate_pte(struct cpa_data *cpa,
1236 unsigned long start, unsigned long end,
1237 unsigned num_pages, pmd_t *pmd, pgprot_t pgprot)
1238{
1239 pte_t *pte;
1240
1241 pte = pte_offset_kernel(pmd, start);
1242
d1440b23 1243 pgprot = pgprot_clear_protnone_bits(pgprot);
c6b6f363 1244
c6b6f363 1245 while (num_pages-- && start < end) {
edc3b912 1246 set_pte(pte, pfn_pte(cpa->pfn, pgprot));
c6b6f363
BP
1247
1248 start += PAGE_SIZE;
edc3b912 1249 cpa->pfn++;
c6b6f363
BP
1250 pte++;
1251 }
1252}
f900a4b8 1253
e535ec08
MF
1254static long populate_pmd(struct cpa_data *cpa,
1255 unsigned long start, unsigned long end,
1256 unsigned num_pages, pud_t *pud, pgprot_t pgprot)
f900a4b8 1257{
e535ec08 1258 long cur_pages = 0;
f900a4b8 1259 pmd_t *pmd;
f5b2831d 1260 pgprot_t pmd_pgprot;
f900a4b8
BP
1261
1262 /*
1263 * Not on a 2M boundary?
1264 */
1265 if (start & (PMD_SIZE - 1)) {
1266 unsigned long pre_end = start + (num_pages << PAGE_SHIFT);
1267 unsigned long next_page = (start + PMD_SIZE) & PMD_MASK;
1268
1269 pre_end = min_t(unsigned long, pre_end, next_page);
1270 cur_pages = (pre_end - start) >> PAGE_SHIFT;
1271 cur_pages = min_t(unsigned int, num_pages, cur_pages);
1272
1273 /*
1274 * Need a PTE page?
1275 */
1276 pmd = pmd_offset(pud, start);
1277 if (pmd_none(*pmd))
1278 if (alloc_pte_page(pmd))
1279 return -1;
1280
1281 populate_pte(cpa, start, pre_end, cur_pages, pmd, pgprot);
1282
1283 start = pre_end;
1284 }
1285
1286 /*
1287 * We mapped them all?
1288 */
1289 if (num_pages == cur_pages)
1290 return cur_pages;
1291
f5b2831d
JG
1292 pmd_pgprot = pgprot_4k_2_large(pgprot);
1293
f900a4b8
BP
1294 while (end - start >= PMD_SIZE) {
1295
1296 /*
1297 * We cannot use a 1G page so allocate a PMD page if needed.
1298 */
1299 if (pud_none(*pud))
1300 if (alloc_pmd_page(pud))
1301 return -1;
1302
1303 pmd = pmd_offset(pud, start);
1304
958f79b9
AK
1305 set_pmd(pmd, pmd_mkhuge(pfn_pmd(cpa->pfn,
1306 canon_pgprot(pmd_pgprot))));
f900a4b8
BP
1307
1308 start += PMD_SIZE;
edc3b912 1309 cpa->pfn += PMD_SIZE >> PAGE_SHIFT;
f900a4b8
BP
1310 cur_pages += PMD_SIZE >> PAGE_SHIFT;
1311 }
1312
1313 /*
1314 * Map trailing 4K pages.
1315 */
1316 if (start < end) {
1317 pmd = pmd_offset(pud, start);
1318 if (pmd_none(*pmd))
1319 if (alloc_pte_page(pmd))
1320 return -1;
1321
1322 populate_pte(cpa, start, end, num_pages - cur_pages,
1323 pmd, pgprot);
1324 }
1325 return num_pages;
1326}
4b23538d 1327
45478336
KS
1328static int populate_pud(struct cpa_data *cpa, unsigned long start, p4d_t *p4d,
1329 pgprot_t pgprot)
4b23538d
BP
1330{
1331 pud_t *pud;
1332 unsigned long end;
e535ec08 1333 long cur_pages = 0;
f5b2831d 1334 pgprot_t pud_pgprot;
4b23538d
BP
1335
1336 end = start + (cpa->numpages << PAGE_SHIFT);
1337
1338 /*
1339 * Not on a Gb page boundary? => map everything up to it with
1340 * smaller pages.
1341 */
1342 if (start & (PUD_SIZE - 1)) {
1343 unsigned long pre_end;
1344 unsigned long next_page = (start + PUD_SIZE) & PUD_MASK;
1345
1346 pre_end = min_t(unsigned long, end, next_page);
1347 cur_pages = (pre_end - start) >> PAGE_SHIFT;
1348 cur_pages = min_t(int, (int)cpa->numpages, cur_pages);
1349
45478336 1350 pud = pud_offset(p4d, start);
4b23538d
BP
1351
1352 /*
1353 * Need a PMD page?
1354 */
1355 if (pud_none(*pud))
1356 if (alloc_pmd_page(pud))
1357 return -1;
1358
1359 cur_pages = populate_pmd(cpa, start, pre_end, cur_pages,
1360 pud, pgprot);
1361 if (cur_pages < 0)
1362 return cur_pages;
1363
1364 start = pre_end;
1365 }
1366
1367 /* We mapped them all? */
1368 if (cpa->numpages == cur_pages)
1369 return cur_pages;
1370
45478336 1371 pud = pud_offset(p4d, start);
f5b2831d 1372 pud_pgprot = pgprot_4k_2_large(pgprot);
4b23538d
BP
1373
1374 /*
1375 * Map everything starting from the Gb boundary, possibly with 1G pages
1376 */
b8291adc 1377 while (boot_cpu_has(X86_FEATURE_GBPAGES) && end - start >= PUD_SIZE) {
958f79b9
AK
1378 set_pud(pud, pud_mkhuge(pfn_pud(cpa->pfn,
1379 canon_pgprot(pud_pgprot))));
4b23538d
BP
1380
1381 start += PUD_SIZE;
edc3b912 1382 cpa->pfn += PUD_SIZE >> PAGE_SHIFT;
4b23538d
BP
1383 cur_pages += PUD_SIZE >> PAGE_SHIFT;
1384 pud++;
1385 }
1386
1387 /* Map trailing leftover */
1388 if (start < end) {
e535ec08 1389 long tmp;
4b23538d 1390
45478336 1391 pud = pud_offset(p4d, start);
4b23538d
BP
1392 if (pud_none(*pud))
1393 if (alloc_pmd_page(pud))
1394 return -1;
1395
1396 tmp = populate_pmd(cpa, start, end, cpa->numpages - cur_pages,
1397 pud, pgprot);
1398 if (tmp < 0)
1399 return cur_pages;
1400
1401 cur_pages += tmp;
1402 }
1403 return cur_pages;
1404}
f3f72966
BP
1405
1406/*
1407 * Restrictions for kernel page table do not necessarily apply when mapping in
1408 * an alternate PGD.
1409 */
1410static int populate_pgd(struct cpa_data *cpa, unsigned long addr)
1411{
1412 pgprot_t pgprot = __pgprot(_KERNPG_TABLE);
f3f72966 1413 pud_t *pud = NULL; /* shut up gcc */
45478336 1414 p4d_t *p4d;
42a54772 1415 pgd_t *pgd_entry;
e535ec08 1416 long ret;
f3f72966
BP
1417
1418 pgd_entry = cpa->pgd + pgd_index(addr);
1419
45478336 1420 if (pgd_none(*pgd_entry)) {
75f296d9 1421 p4d = (p4d_t *)get_zeroed_page(GFP_KERNEL);
45478336
KS
1422 if (!p4d)
1423 return -1;
1424
1425 set_pgd(pgd_entry, __pgd(__pa(p4d) | _KERNPG_TABLE));
1426 }
1427
f3f72966
BP
1428 /*
1429 * Allocate a PUD page and hand it down for mapping.
1430 */
45478336
KS
1431 p4d = p4d_offset(pgd_entry, addr);
1432 if (p4d_none(*p4d)) {
75f296d9 1433 pud = (pud_t *)get_zeroed_page(GFP_KERNEL);
f3f72966
BP
1434 if (!pud)
1435 return -1;
530dd8d4 1436
45478336 1437 set_p4d(p4d, __p4d(__pa(pud) | _KERNPG_TABLE));
f3f72966
BP
1438 }
1439
1440 pgprot_val(pgprot) &= ~pgprot_val(cpa->mask_clr);
1441 pgprot_val(pgprot) |= pgprot_val(cpa->mask_set);
1442
45478336 1443 ret = populate_pud(cpa, addr, p4d, pgprot);
0bb8aeee 1444 if (ret < 0) {
55920d31
AL
1445 /*
1446 * Leave the PUD page in place in case some other CPU or thread
1447 * already found it, but remove any useless entries we just
1448 * added to it.
1449 */
45478336 1450 unmap_pud_range(p4d, addr,
0bb8aeee 1451 addr + (cpa->numpages << PAGE_SHIFT));
f3f72966 1452 return ret;
0bb8aeee 1453 }
42a54772 1454
f3f72966
BP
1455 cpa->numpages = ret;
1456 return 0;
1457}
1458
a1e46212
SS
1459static int __cpa_process_fault(struct cpa_data *cpa, unsigned long vaddr,
1460 int primary)
1461{
7fc8442f
MF
1462 if (cpa->pgd) {
1463 /*
1464 * Right now, we only execute this code path when mapping
1465 * the EFI virtual memory map regions, no other users
1466 * provide a ->pgd value. This may change in the future.
1467 */
82f0712c 1468 return populate_pgd(cpa, vaddr);
7fc8442f 1469 }
82f0712c 1470
a1e46212
SS
1471 /*
1472 * Ignore all non primary paths.
1473 */
405e1133
JB
1474 if (!primary) {
1475 cpa->numpages = 1;
a1e46212 1476 return 0;
405e1133 1477 }
a1e46212
SS
1478
1479 /*
1480 * Ignore the NULL PTE for kernel identity mapping, as it is expected
1481 * to have holes.
1482 * Also set numpages to '1' indicating that we processed cpa req for
1483 * one virtual address page and its pfn. TBD: numpages can be set based
1484 * on the initial value and the level returned by lookup_address().
1485 */
1486 if (within(vaddr, PAGE_OFFSET,
1487 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT))) {
1488 cpa->numpages = 1;
1489 cpa->pfn = __pa(vaddr) >> PAGE_SHIFT;
1490 return 0;
58e65b51
DH
1491
1492 } else if (__cpa_pfn_in_highmap(cpa->pfn)) {
1493 /* Faults in the highmap are OK, so do not warn: */
1494 return -EFAULT;
a1e46212
SS
1495 } else {
1496 WARN(1, KERN_WARNING "CPA: called for zero pte. "
1497 "vaddr = %lx cpa->vaddr = %lx\n", vaddr,
1498 *cpa->vaddr);
1499
1500 return -EFAULT;
1501 }
1502}
1503
c31c7d48 1504static int __change_page_attr(struct cpa_data *cpa, int primary)
9f4c815c 1505{
d75586ad 1506 unsigned long address;
da7bfc50
HH
1507 int do_split, err;
1508 unsigned int level;
c31c7d48 1509 pte_t *kpte, old_pte;
1da177e4 1510
16ebf031 1511 address = __cpa_addr(cpa, cpa->curpage);
97f99fed 1512repeat:
82f0712c 1513 kpte = _lookup_address_cpa(cpa, address, &level);
1da177e4 1514 if (!kpte)
a1e46212 1515 return __cpa_process_fault(cpa, address, primary);
c31c7d48
TG
1516
1517 old_pte = *kpte;
dcb32d99 1518 if (pte_none(old_pte))
a1e46212 1519 return __cpa_process_fault(cpa, address, primary);
9f4c815c 1520
30551bb3 1521 if (level == PG_LEVEL_4K) {
c31c7d48 1522 pte_t new_pte;
626c2c9d 1523 pgprot_t new_prot = pte_pgprot(old_pte);
c31c7d48 1524 unsigned long pfn = pte_pfn(old_pte);
86f03989 1525
72e458df
TG
1526 pgprot_val(new_prot) &= ~pgprot_val(cpa->mask_clr);
1527 pgprot_val(new_prot) |= pgprot_val(cpa->mask_set);
86f03989 1528
5c280cf6 1529 cpa_inc_4k_install();
7af01450
TG
1530 /* Hand in lpsize = 0 to enforce the protection mechanism */
1531 new_prot = static_protections(new_prot, address, pfn, 1, 0,
4046460b 1532 CPA_PROTECT);
86f03989 1533
d1440b23 1534 new_prot = pgprot_clear_protnone_bits(new_prot);
a8aed3e0 1535
626c2c9d
AV
1536 /*
1537 * We need to keep the pfn from the existing PTE,
1538 * after all we're only going to change it's attributes
1539 * not the memory it points to
1540 */
1a54420a 1541 new_pte = pfn_pte(pfn, new_prot);
c31c7d48 1542 cpa->pfn = pfn;
f4ae5da0
TG
1543 /*
1544 * Do we really change anything ?
1545 */
1546 if (pte_val(old_pte) != pte_val(new_pte)) {
1547 set_pte_atomic(kpte, new_pte);
d75586ad 1548 cpa->flags |= CPA_FLUSHTLB;
f4ae5da0 1549 }
9b5cf48b 1550 cpa->numpages = 1;
65e074df 1551 return 0;
1da177e4 1552 }
65e074df
TG
1553
1554 /*
1555 * Check, whether we can keep the large page intact
1556 * and just change the pte:
1557 */
8679de09 1558 do_split = should_split_large_page(kpte, address, cpa);
65e074df
TG
1559 /*
1560 * When the range fits into the existing large page,
9b5cf48b 1561 * return. cp->numpages and cpa->tlbflush have been updated in
65e074df
TG
1562 * try_large_page:
1563 */
87f7f8fe
IM
1564 if (do_split <= 0)
1565 return do_split;
65e074df
TG
1566
1567 /*
1568 * We have to split the large page:
1569 */
82f0712c 1570 err = split_large_page(cpa, kpte, address);
c0a759ab 1571 if (!err)
87f7f8fe 1572 goto repeat;
beaff633 1573
87f7f8fe 1574 return err;
9f4c815c 1575}
1da177e4 1576
c31c7d48
TG
1577static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias);
1578
1579static int cpa_process_alias(struct cpa_data *cpa)
1da177e4 1580{
c31c7d48 1581 struct cpa_data alias_cpa;
992f4c1c 1582 unsigned long laddr = (unsigned long)__va(cpa->pfn << PAGE_SHIFT);
e933a73f 1583 unsigned long vaddr;
992f4c1c 1584 int ret;
44af6c41 1585
8eb5779f 1586 if (!pfn_range_is_mapped(cpa->pfn, cpa->pfn + 1))
c31c7d48 1587 return 0;
626c2c9d 1588
f34b439f
TG
1589 /*
1590 * No need to redo, when the primary call touched the direct
1591 * mapping already:
1592 */
16ebf031 1593 vaddr = __cpa_addr(cpa, cpa->curpage);
d75586ad 1594 if (!(within(vaddr, PAGE_OFFSET,
a1e46212 1595 PAGE_OFFSET + (max_pfn_mapped << PAGE_SHIFT)))) {
44af6c41 1596
f34b439f 1597 alias_cpa = *cpa;
992f4c1c 1598 alias_cpa.vaddr = &laddr;
9ae28475 1599 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
98bfc9b0 1600 alias_cpa.curpage = 0;
d75586ad 1601
ab513018
RE
1602 cpa->force_flush_all = 1;
1603
f34b439f 1604 ret = __change_page_attr_set_clr(&alias_cpa, 0);
992f4c1c
TH
1605 if (ret)
1606 return ret;
f34b439f 1607 }
44af6c41 1608
44af6c41 1609#ifdef CONFIG_X86_64
488fd995 1610 /*
992f4c1c
TH
1611 * If the primary call didn't touch the high mapping already
1612 * and the physical address is inside the kernel map, we need
0879750f 1613 * to touch the high mapped kernel as well:
488fd995 1614 */
992f4c1c 1615 if (!within(vaddr, (unsigned long)_text, _brk_end) &&
58e65b51 1616 __cpa_pfn_in_highmap(cpa->pfn)) {
992f4c1c
TH
1617 unsigned long temp_cpa_vaddr = (cpa->pfn << PAGE_SHIFT) +
1618 __START_KERNEL_map - phys_base;
1619 alias_cpa = *cpa;
1620 alias_cpa.vaddr = &temp_cpa_vaddr;
1621 alias_cpa.flags &= ~(CPA_PAGES_ARRAY | CPA_ARRAY);
98bfc9b0 1622 alias_cpa.curpage = 0;
c31c7d48 1623
ab513018 1624 cpa->force_flush_all = 1;
992f4c1c
TH
1625 /*
1626 * The high mapping range is imprecise, so ignore the
1627 * return value.
1628 */
1629 __change_page_attr_set_clr(&alias_cpa, 0);
1630 }
488fd995 1631#endif
992f4c1c
TH
1632
1633 return 0;
1da177e4
LT
1634}
1635
c31c7d48 1636static int __change_page_attr_set_clr(struct cpa_data *cpa, int checkalias)
ff31452b 1637{
e535ec08 1638 unsigned long numpages = cpa->numpages;
83b4e391
PZ
1639 unsigned long rempages = numpages;
1640 int ret = 0;
ff31452b 1641
83b4e391 1642 while (rempages) {
65e074df
TG
1643 /*
1644 * Store the remaining nr of pages for the large page
1645 * preservation check.
1646 */
83b4e391 1647 cpa->numpages = rempages;
d75586ad 1648 /* for array changes, we can't use large page */
9ae28475 1649 if (cpa->flags & (CPA_ARRAY | CPA_PAGES_ARRAY))
d75586ad 1650 cpa->numpages = 1;
c31c7d48 1651
288cf3c6 1652 if (!debug_pagealloc_enabled())
ad5ca55f 1653 spin_lock(&cpa_lock);
c31c7d48 1654 ret = __change_page_attr(cpa, checkalias);
288cf3c6 1655 if (!debug_pagealloc_enabled())
ad5ca55f 1656 spin_unlock(&cpa_lock);
ff31452b 1657 if (ret)
83b4e391 1658 goto out;
ff31452b 1659
c31c7d48
TG
1660 if (checkalias) {
1661 ret = cpa_process_alias(cpa);
1662 if (ret)
83b4e391 1663 goto out;
c31c7d48
TG
1664 }
1665
65e074df
TG
1666 /*
1667 * Adjust the number of pages with the result of the
1668 * CPA operation. Either a large page has been
1669 * preserved or a single page update happened.
1670 */
83b4e391
PZ
1671 BUG_ON(cpa->numpages > rempages || !cpa->numpages);
1672 rempages -= cpa->numpages;
98bfc9b0 1673 cpa->curpage += cpa->numpages;
65e074df 1674 }
83b4e391
PZ
1675
1676out:
1677 /* Restore the original numpages */
1678 cpa->numpages = numpages;
1679 return ret;
ff31452b
TG
1680}
1681
d75586ad 1682static int change_page_attr_set_clr(unsigned long *addr, int numpages,
c9caa02c 1683 pgprot_t mask_set, pgprot_t mask_clr,
9ae28475 1684 int force_split, int in_flag,
1685 struct page **pages)
ff31452b 1686{
72e458df 1687 struct cpa_data cpa;
cacf8906 1688 int ret, cache, checkalias;
331e4065 1689
82f0712c
BP
1690 memset(&cpa, 0, sizeof(cpa));
1691
331e4065 1692 /*
39114b7a
DH
1693 * Check, if we are requested to set a not supported
1694 * feature. Clearing non-supported features is OK.
331e4065
TG
1695 */
1696 mask_set = canon_pgprot(mask_set);
39114b7a 1697
c9caa02c 1698 if (!pgprot_val(mask_set) && !pgprot_val(mask_clr) && !force_split)
331e4065
TG
1699 return 0;
1700
69b1415e 1701 /* Ensure we are PAGE_SIZE aligned */
9ae28475 1702 if (in_flag & CPA_ARRAY) {
d75586ad
SL
1703 int i;
1704 for (i = 0; i < numpages; i++) {
1705 if (addr[i] & ~PAGE_MASK) {
1706 addr[i] &= PAGE_MASK;
1707 WARN_ON_ONCE(1);
1708 }
1709 }
9ae28475 1710 } else if (!(in_flag & CPA_PAGES_ARRAY)) {
1711 /*
1712 * in_flag of CPA_PAGES_ARRAY implies it is aligned.
a97673a1 1713 * No need to check in that case
9ae28475 1714 */
1715 if (*addr & ~PAGE_MASK) {
1716 *addr &= PAGE_MASK;
1717 /*
1718 * People should not be passing in unaligned addresses:
1719 */
1720 WARN_ON_ONCE(1);
1721 }
69b1415e
TG
1722 }
1723
5843d9a4
NP
1724 /* Must avoid aliasing mappings in the highmem code */
1725 kmap_flush_unused();
1726
db64fe02
NP
1727 vm_unmap_aliases();
1728
72e458df 1729 cpa.vaddr = addr;
9ae28475 1730 cpa.pages = pages;
72e458df
TG
1731 cpa.numpages = numpages;
1732 cpa.mask_set = mask_set;
1733 cpa.mask_clr = mask_clr;
d75586ad
SL
1734 cpa.flags = 0;
1735 cpa.curpage = 0;
c9caa02c 1736 cpa.force_split = force_split;
72e458df 1737
9ae28475 1738 if (in_flag & (CPA_ARRAY | CPA_PAGES_ARRAY))
1739 cpa.flags |= in_flag;
d75586ad 1740
af96e443
TG
1741 /* No alias checking for _NX bit modifications */
1742 checkalias = (pgprot_val(mask_set) | pgprot_val(mask_clr)) != _PAGE_NX;
c40a56a7
DH
1743 /* Has caller explicitly disabled alias checking? */
1744 if (in_flag & CPA_NO_CHECK_ALIAS)
1745 checkalias = 0;
af96e443
TG
1746
1747 ret = __change_page_attr_set_clr(&cpa, checkalias);
ff31452b 1748
f4ae5da0
TG
1749 /*
1750 * Check whether we really changed something:
1751 */
d75586ad 1752 if (!(cpa.flags & CPA_FLUSHTLB))
1ac2f7d5 1753 goto out;
cacf8906 1754
6bb8383b
AK
1755 /*
1756 * No need to flush, when we did not set any of the caching
1757 * attributes:
1758 */
c06814d8 1759 cache = !!pgprot2cachemode(mask_set);
6bb8383b 1760
57a6a46a 1761 /*
fce2ce95 1762 * On error; flush everything to be sure.
57a6a46a 1763 */
fce2ce95 1764 if (ret) {
6bb8383b 1765 cpa_flush_all(cache);
fce2ce95
PZ
1766 goto out;
1767 }
1768
fe0937b2 1769 cpa_flush(&cpa, cache);
76ebd054 1770out:
ff31452b
TG
1771 return ret;
1772}
1773
d75586ad
SL
1774static inline int change_page_attr_set(unsigned long *addr, int numpages,
1775 pgprot_t mask, int array)
75cbade8 1776{
d75586ad 1777 return change_page_attr_set_clr(addr, numpages, mask, __pgprot(0), 0,
9ae28475 1778 (array ? CPA_ARRAY : 0), NULL);
75cbade8
AV
1779}
1780
d75586ad
SL
1781static inline int change_page_attr_clear(unsigned long *addr, int numpages,
1782 pgprot_t mask, int array)
72932c7a 1783{
d75586ad 1784 return change_page_attr_set_clr(addr, numpages, __pgprot(0), mask, 0,
9ae28475 1785 (array ? CPA_ARRAY : 0), NULL);
72932c7a
TG
1786}
1787
0f350755 1788static inline int cpa_set_pages_array(struct page **pages, int numpages,
1789 pgprot_t mask)
1790{
1791 return change_page_attr_set_clr(NULL, numpages, mask, __pgprot(0), 0,
1792 CPA_PAGES_ARRAY, pages);
1793}
1794
1795static inline int cpa_clear_pages_array(struct page **pages, int numpages,
1796 pgprot_t mask)
1797{
1798 return change_page_attr_set_clr(NULL, numpages, __pgprot(0), mask, 0,
1799 CPA_PAGES_ARRAY, pages);
1800}
1801
30796e18
LG
1802/*
1803 * _set_memory_prot is an internal helper for callers that have been passed
1804 * a pgprot_t value from upper layers and a reservation has already been taken.
1805 * If you want to set the pgprot to a specific page protocol, use the
1806 * set_memory_xx() functions.
1807 */
1808int __set_memory_prot(unsigned long addr, int numpages, pgprot_t prot)
1809{
1810 return change_page_attr_set_clr(&addr, numpages, prot,
1811 __pgprot(~pgprot_val(prot)), 0, 0,
1812 NULL);
1813}
1814
1219333d 1815int _set_memory_uc(unsigned long addr, int numpages)
72932c7a 1816{
de33c442 1817 /*
c0d94aa5 1818 * for now UC MINUS. see comments in ioremap()
e4b6be33
LR
1819 * If you really need strong UC use ioremap_uc(), but note
1820 * that you cannot override IO areas with set_memory_*() as
1821 * these helpers cannot work with IO memory.
de33c442 1822 */
d75586ad 1823 return change_page_attr_set(&addr, numpages,
c06814d8
JG
1824 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS),
1825 0);
75cbade8 1826}
1219333d 1827
1828int set_memory_uc(unsigned long addr, int numpages)
1829{
9fa3ab39 1830 int ret;
1831
de33c442 1832 /*
c0d94aa5 1833 * for now UC MINUS. see comments in ioremap()
de33c442 1834 */
ecdd6ee7 1835 ret = memtype_reserve(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
e00c8cc9 1836 _PAGE_CACHE_MODE_UC_MINUS, NULL);
9fa3ab39 1837 if (ret)
1838 goto out_err;
1839
1840 ret = _set_memory_uc(addr, numpages);
1841 if (ret)
1842 goto out_free;
1843
1844 return 0;
1219333d 1845
9fa3ab39 1846out_free:
ecdd6ee7 1847 memtype_free(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
9fa3ab39 1848out_err:
1849 return ret;
1219333d 1850}
75cbade8
AV
1851EXPORT_SYMBOL(set_memory_uc);
1852
ef354af4 1853int _set_memory_wc(unsigned long addr, int numpages)
1854{
3869c4aa 1855 int ret;
bdc6340f 1856
3869c4aa 1857 ret = change_page_attr_set(&addr, numpages,
c06814d8
JG
1858 cachemode2pgprot(_PAGE_CACHE_MODE_UC_MINUS),
1859 0);
3869c4aa 1860 if (!ret) {
5fe26b7a
PZ
1861 ret = change_page_attr_set_clr(&addr, numpages,
1862 cachemode2pgprot(_PAGE_CACHE_MODE_WC),
bdc6340f
PV
1863 __pgprot(_PAGE_CACHE_MASK),
1864 0, 0, NULL);
3869c4aa 1865 }
1866 return ret;
ef354af4 1867}
1868
1869int set_memory_wc(unsigned long addr, int numpages)
1870{
9fa3ab39 1871 int ret;
1872
ecdd6ee7 1873 ret = memtype_reserve(__pa(addr), __pa(addr) + numpages * PAGE_SIZE,
e00c8cc9 1874 _PAGE_CACHE_MODE_WC, NULL);
9fa3ab39 1875 if (ret)
623dffb2 1876 return ret;
ef354af4 1877
9fa3ab39 1878 ret = _set_memory_wc(addr, numpages);
1879 if (ret)
ecdd6ee7 1880 memtype_free(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
9fa3ab39 1881
9fa3ab39 1882 return ret;
ef354af4 1883}
1884EXPORT_SYMBOL(set_memory_wc);
1885
623dffb2
TK
1886int _set_memory_wt(unsigned long addr, int numpages)
1887{
1888 return change_page_attr_set(&addr, numpages,
1889 cachemode2pgprot(_PAGE_CACHE_MODE_WT), 0);
1890}
1891
1219333d 1892int _set_memory_wb(unsigned long addr, int numpages)
75cbade8 1893{
c06814d8 1894 /* WB cache mode is hard wired to all cache attribute bits being 0 */
d75586ad
SL
1895 return change_page_attr_clear(&addr, numpages,
1896 __pgprot(_PAGE_CACHE_MASK), 0);
75cbade8 1897}
1219333d 1898
1899int set_memory_wb(unsigned long addr, int numpages)
1900{
9fa3ab39 1901 int ret;
1902
1903 ret = _set_memory_wb(addr, numpages);
1904 if (ret)
1905 return ret;
1906
ecdd6ee7 1907 memtype_free(__pa(addr), __pa(addr) + numpages * PAGE_SIZE);
9fa3ab39 1908 return 0;
1219333d 1909}
75cbade8
AV
1910EXPORT_SYMBOL(set_memory_wb);
1911
1912int set_memory_x(unsigned long addr, int numpages)
1913{
583140af
PA
1914 if (!(__supported_pte_mask & _PAGE_NX))
1915 return 0;
1916
d75586ad 1917 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_NX), 0);
75cbade8 1918}
75cbade8
AV
1919
1920int set_memory_nx(unsigned long addr, int numpages)
1921{
583140af
PA
1922 if (!(__supported_pte_mask & _PAGE_NX))
1923 return 0;
1924
d75586ad 1925 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_NX), 0);
75cbade8 1926}
75cbade8
AV
1927
1928int set_memory_ro(unsigned long addr, int numpages)
1929{
d75586ad 1930 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_RW), 0);
75cbade8 1931}
75cbade8
AV
1932
1933int set_memory_rw(unsigned long addr, int numpages)
1934{
d75586ad 1935 return change_page_attr_set(&addr, numpages, __pgprot(_PAGE_RW), 0);
75cbade8 1936}
f62d0f00
IM
1937
1938int set_memory_np(unsigned long addr, int numpages)
1939{
d75586ad 1940 return change_page_attr_clear(&addr, numpages, __pgprot(_PAGE_PRESENT), 0);
f62d0f00 1941}
75cbade8 1942
c40a56a7
DH
1943int set_memory_np_noalias(unsigned long addr, int numpages)
1944{
1945 int cpa_flags = CPA_NO_CHECK_ALIAS;
1946
1947 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
1948 __pgprot(_PAGE_PRESENT), 0,
1949 cpa_flags, NULL);
1950}
1951
c9caa02c
AK
1952int set_memory_4k(unsigned long addr, int numpages)
1953{
d75586ad 1954 return change_page_attr_set_clr(&addr, numpages, __pgprot(0),
9ae28475 1955 __pgprot(0), 1, 0, NULL);
c9caa02c
AK
1956}
1957
39114b7a
DH
1958int set_memory_nonglobal(unsigned long addr, int numpages)
1959{
1960 return change_page_attr_clear(&addr, numpages,
1961 __pgprot(_PAGE_GLOBAL), 0);
1962}
1963
eac7073a
DH
1964int set_memory_global(unsigned long addr, int numpages)
1965{
1966 return change_page_attr_set(&addr, numpages,
1967 __pgprot(_PAGE_GLOBAL), 0);
1968}
1969
77bd2342
TL
1970static int __set_memory_enc_dec(unsigned long addr, int numpages, bool enc)
1971{
1972 struct cpa_data cpa;
77bd2342
TL
1973 int ret;
1974
a72ec5a3
TL
1975 /* Nothing to do if memory encryption is not active */
1976 if (!mem_encrypt_active())
77bd2342
TL
1977 return 0;
1978
1979 /* Should not be working on unaligned addresses */
1980 if (WARN_ONCE(addr & ~PAGE_MASK, "misaligned address: %#lx\n", addr))
1981 addr &= PAGE_MASK;
1982
77bd2342
TL
1983 memset(&cpa, 0, sizeof(cpa));
1984 cpa.vaddr = &addr;
1985 cpa.numpages = numpages;
1986 cpa.mask_set = enc ? __pgprot(_PAGE_ENC) : __pgprot(0);
1987 cpa.mask_clr = enc ? __pgprot(0) : __pgprot(_PAGE_ENC);
1988 cpa.pgd = init_mm.pgd;
1989
1990 /* Must avoid aliasing mappings in the highmem code */
1991 kmap_flush_unused();
1992 vm_unmap_aliases();
1993
1994 /*
1995 * Before changing the encryption attribute, we need to flush caches.
1996 */
fe0937b2 1997 cpa_flush(&cpa, 1);
77bd2342
TL
1998
1999 ret = __change_page_attr_set_clr(&cpa, 1);
2000
2001 /*
fe0937b2
PZ
2002 * After changing the encryption attribute, we need to flush TLBs again
2003 * in case any speculative TLB caching occurred (but no need to flush
2004 * caches again). We could just use cpa_flush_all(), but in case TLB
2005 * flushing gets optimized in the cpa_flush() path use the same logic
2006 * as above.
77bd2342 2007 */
fe0937b2 2008 cpa_flush(&cpa, 0);
77bd2342
TL
2009
2010 return ret;
2011}
2012
2013int set_memory_encrypted(unsigned long addr, int numpages)
2014{
2015 return __set_memory_enc_dec(addr, numpages, true);
2016}
95cf9264 2017EXPORT_SYMBOL_GPL(set_memory_encrypted);
77bd2342
TL
2018
2019int set_memory_decrypted(unsigned long addr, int numpages)
2020{
2021 return __set_memory_enc_dec(addr, numpages, false);
2022}
95cf9264 2023EXPORT_SYMBOL_GPL(set_memory_decrypted);
77bd2342 2024
75cbade8
AV
2025int set_pages_uc(struct page *page, int numpages)
2026{
2027 unsigned long addr = (unsigned long)page_address(page);
75cbade8 2028
d7c8f21a 2029 return set_memory_uc(addr, numpages);
75cbade8
AV
2030}
2031EXPORT_SYMBOL(set_pages_uc);
2032
3c567356 2033static int _set_pages_array(struct page **pages, int numpages,
c06814d8 2034 enum page_cache_mode new_type)
0f350755 2035{
2036 unsigned long start;
2037 unsigned long end;
623dffb2 2038 enum page_cache_mode set_type;
0f350755 2039 int i;
2040 int free_idx;
4f646254 2041 int ret;
0f350755 2042
3c567356 2043 for (i = 0; i < numpages; i++) {
8523acfe
TH
2044 if (PageHighMem(pages[i]))
2045 continue;
2046 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
0f350755 2047 end = start + PAGE_SIZE;
ecdd6ee7 2048 if (memtype_reserve(start, end, new_type, NULL))
0f350755 2049 goto err_out;
2050 }
2051
623dffb2
TK
2052 /* If WC, set to UC- first and then WC */
2053 set_type = (new_type == _PAGE_CACHE_MODE_WC) ?
2054 _PAGE_CACHE_MODE_UC_MINUS : new_type;
2055
3c567356 2056 ret = cpa_set_pages_array(pages, numpages,
623dffb2 2057 cachemode2pgprot(set_type));
c06814d8 2058 if (!ret && new_type == _PAGE_CACHE_MODE_WC)
3c567356 2059 ret = change_page_attr_set_clr(NULL, numpages,
c06814d8
JG
2060 cachemode2pgprot(
2061 _PAGE_CACHE_MODE_WC),
4f646254
PN
2062 __pgprot(_PAGE_CACHE_MASK),
2063 0, CPA_PAGES_ARRAY, pages);
2064 if (ret)
2065 goto err_out;
2066 return 0; /* Success */
0f350755 2067err_out:
2068 free_idx = i;
2069 for (i = 0; i < free_idx; i++) {
8523acfe
TH
2070 if (PageHighMem(pages[i]))
2071 continue;
2072 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
0f350755 2073 end = start + PAGE_SIZE;
ecdd6ee7 2074 memtype_free(start, end);
0f350755 2075 }
2076 return -EINVAL;
2077}
4f646254 2078
3c567356 2079int set_pages_array_uc(struct page **pages, int numpages)
4f646254 2080{
3c567356 2081 return _set_pages_array(pages, numpages, _PAGE_CACHE_MODE_UC_MINUS);
4f646254 2082}
0f350755 2083EXPORT_SYMBOL(set_pages_array_uc);
2084
3c567356 2085int set_pages_array_wc(struct page **pages, int numpages)
4f646254 2086{
3c567356 2087 return _set_pages_array(pages, numpages, _PAGE_CACHE_MODE_WC);
4f646254
PN
2088}
2089EXPORT_SYMBOL(set_pages_array_wc);
2090
3c567356 2091int set_pages_array_wt(struct page **pages, int numpages)
623dffb2 2092{
3c567356 2093 return _set_pages_array(pages, numpages, _PAGE_CACHE_MODE_WT);
623dffb2
TK
2094}
2095EXPORT_SYMBOL_GPL(set_pages_array_wt);
2096
75cbade8
AV
2097int set_pages_wb(struct page *page, int numpages)
2098{
2099 unsigned long addr = (unsigned long)page_address(page);
75cbade8 2100
d7c8f21a 2101 return set_memory_wb(addr, numpages);
75cbade8
AV
2102}
2103EXPORT_SYMBOL(set_pages_wb);
2104
3c567356 2105int set_pages_array_wb(struct page **pages, int numpages)
0f350755 2106{
2107 int retval;
2108 unsigned long start;
2109 unsigned long end;
2110 int i;
2111
c06814d8 2112 /* WB cache mode is hard wired to all cache attribute bits being 0 */
3c567356 2113 retval = cpa_clear_pages_array(pages, numpages,
0f350755 2114 __pgprot(_PAGE_CACHE_MASK));
9fa3ab39 2115 if (retval)
2116 return retval;
0f350755 2117
3c567356 2118 for (i = 0; i < numpages; i++) {
8523acfe
TH
2119 if (PageHighMem(pages[i]))
2120 continue;
2121 start = page_to_pfn(pages[i]) << PAGE_SHIFT;
0f350755 2122 end = start + PAGE_SIZE;
ecdd6ee7 2123 memtype_free(start, end);
0f350755 2124 }
2125
9fa3ab39 2126 return 0;
0f350755 2127}
2128EXPORT_SYMBOL(set_pages_array_wb);
2129
75cbade8
AV
2130int set_pages_ro(struct page *page, int numpages)
2131{
2132 unsigned long addr = (unsigned long)page_address(page);
75cbade8 2133
d7c8f21a 2134 return set_memory_ro(addr, numpages);
75cbade8 2135}
75cbade8
AV
2136
2137int set_pages_rw(struct page *page, int numpages)
2138{
2139 unsigned long addr = (unsigned long)page_address(page);
e81d5dc4 2140
d7c8f21a 2141 return set_memory_rw(addr, numpages);
78c94aba
IM
2142}
2143
f62d0f00
IM
2144static int __set_pages_p(struct page *page, int numpages)
2145{
d75586ad
SL
2146 unsigned long tempaddr = (unsigned long) page_address(page);
2147 struct cpa_data cpa = { .vaddr = &tempaddr,
82f0712c 2148 .pgd = NULL,
72e458df
TG
2149 .numpages = numpages,
2150 .mask_set = __pgprot(_PAGE_PRESENT | _PAGE_RW),
d75586ad
SL
2151 .mask_clr = __pgprot(0),
2152 .flags = 0};
72932c7a 2153
55121b43
SS
2154 /*
2155 * No alias checking needed for setting present flag. otherwise,
2156 * we may need to break large pages for 64-bit kernel text
2157 * mappings (this adds to complexity if we want to do this from
2158 * atomic context especially). Let's keep it simple!
2159 */
2160 return __change_page_attr_set_clr(&cpa, 0);
f62d0f00
IM
2161}
2162
2163static int __set_pages_np(struct page *page, int numpages)
2164{
d75586ad
SL
2165 unsigned long tempaddr = (unsigned long) page_address(page);
2166 struct cpa_data cpa = { .vaddr = &tempaddr,
82f0712c 2167 .pgd = NULL,
72e458df
TG
2168 .numpages = numpages,
2169 .mask_set = __pgprot(0),
d75586ad
SL
2170 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
2171 .flags = 0};
72932c7a 2172
55121b43
SS
2173 /*
2174 * No alias checking needed for setting not present flag. otherwise,
2175 * we may need to break large pages for 64-bit kernel text
2176 * mappings (this adds to complexity if we want to do this from
2177 * atomic context especially). Let's keep it simple!
2178 */
2179 return __change_page_attr_set_clr(&cpa, 0);
f62d0f00
IM
2180}
2181
d253ca0c
RE
2182int set_direct_map_invalid_noflush(struct page *page)
2183{
2184 return __set_pages_np(page, 1);
2185}
2186
2187int set_direct_map_default_noflush(struct page *page)
2188{
2189 return __set_pages_p(page, 1);
2190}
2191
031bc574 2192void __kernel_map_pages(struct page *page, int numpages, int enable)
1da177e4
LT
2193{
2194 if (PageHighMem(page))
2195 return;
9f4c815c 2196 if (!enable) {
f9b8404c
IM
2197 debug_check_no_locks_freed(page_address(page),
2198 numpages * PAGE_SIZE);
9f4c815c 2199 }
de5097c2 2200
9f4c815c 2201 /*
f8d8406b 2202 * The return value is ignored as the calls cannot fail.
55121b43
SS
2203 * Large pages for identity mappings are not used at boot time
2204 * and hence no memory allocations during large page split.
1da177e4 2205 */
f62d0f00
IM
2206 if (enable)
2207 __set_pages_p(page, numpages);
2208 else
2209 __set_pages_np(page, numpages);
9f4c815c
IM
2210
2211 /*
e4b71dcf 2212 * We should perform an IPI and flush all tlbs,
f77084d9
SAS
2213 * but that can deadlock->flush only current cpu.
2214 * Preemption needs to be disabled around __flush_tlb_all() due to
2215 * CR3 reload in __native_flush_tlb().
1da177e4 2216 */
f77084d9 2217 preempt_disable();
1da177e4 2218 __flush_tlb_all();
f77084d9 2219 preempt_enable();
26564600
BO
2220
2221 arch_flush_lazy_mmu_mode();
ee7ae7a1
TG
2222}
2223
8a235efa 2224#ifdef CONFIG_HIBERNATION
8a235efa
RW
2225bool kernel_page_present(struct page *page)
2226{
2227 unsigned int level;
2228 pte_t *pte;
2229
2230 if (PageHighMem(page))
2231 return false;
2232
2233 pte = lookup_address((unsigned long)page_address(page), &level);
2234 return (pte_val(*pte) & _PAGE_PRESENT);
2235}
8a235efa
RW
2236#endif /* CONFIG_HIBERNATION */
2237
7e0dabd3
SPP
2238int __init kernel_map_pages_in_pgd(pgd_t *pgd, u64 pfn, unsigned long address,
2239 unsigned numpages, unsigned long page_flags)
82f0712c
BP
2240{
2241 int retval = -EINVAL;
2242
2243 struct cpa_data cpa = {
2244 .vaddr = &address,
2245 .pfn = pfn,
2246 .pgd = pgd,
2247 .numpages = numpages,
2248 .mask_set = __pgprot(0),
75fbef0a 2249 .mask_clr = __pgprot(~page_flags & (_PAGE_NX|_PAGE_RW)),
82f0712c
BP
2250 .flags = 0,
2251 };
2252
7e0dabd3
SPP
2253 WARN_ONCE(num_online_cpus() > 1, "Don't call after initializing SMP");
2254
82f0712c
BP
2255 if (!(__supported_pte_mask & _PAGE_NX))
2256 goto out;
2257
21729f81
TL
2258 if (!(page_flags & _PAGE_ENC))
2259 cpa.mask_clr = pgprot_encrypted(cpa.mask_clr);
2260
82f0712c
BP
2261 cpa.mask_set = __pgprot(_PAGE_PRESENT | page_flags);
2262
2263 retval = __change_page_attr_set_clr(&cpa, 0);
2264 __flush_tlb_all();
2265
2266out:
2267 return retval;
2268}
2269
7e0dabd3
SPP
2270/*
2271 * __flush_tlb_all() flushes mappings only on current CPU and hence this
2272 * function shouldn't be used in an SMP environment. Presently, it's used only
2273 * during boot (way before smp_init()) by EFI subsystem and hence is ok.
2274 */
2275int __init kernel_unmap_pages_in_pgd(pgd_t *pgd, unsigned long address,
2276 unsigned long numpages)
2277{
2278 int retval;
2279
2280 /*
2281 * The typical sequence for unmapping is to find a pte through
2282 * lookup_address_in_pgd() (ideally, it should never return NULL because
2283 * the address is already mapped) and change it's protections. As pfn is
2284 * the *target* of a mapping, it's not useful while unmapping.
2285 */
2286 struct cpa_data cpa = {
2287 .vaddr = &address,
2288 .pfn = 0,
2289 .pgd = pgd,
2290 .numpages = numpages,
2291 .mask_set = __pgprot(0),
2292 .mask_clr = __pgprot(_PAGE_PRESENT | _PAGE_RW),
2293 .flags = 0,
2294 };
2295
2296 WARN_ONCE(num_online_cpus() > 1, "Don't call after initializing SMP");
2297
2298 retval = __change_page_attr_set_clr(&cpa, 0);
2299 __flush_tlb_all();
2300
2301 return retval;
2302}
2303
d1028a15
AV
2304/*
2305 * The testcases use internal knowledge of the implementation that shouldn't
2306 * be exposed to the rest of the kernel. Include these directly here.
2307 */
2308#ifdef CONFIG_CPA_DEBUG
f9b57cf8 2309#include "cpa-test.c"
d1028a15 2310#endif