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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
7885ea85 RC |
2 | /* |
3 | * Copyright (C) 2017 Andes Technology Corporation | |
4 | * Rick Chen, Andes Technology Corporation <rick@andestech.com> | |
7885ea85 RC |
5 | */ |
6 | ||
7885ea85 | 7 | #include <common.h> |
b79fdc76 | 8 | #include <flash.h> |
4d72caa5 | 9 | #include <image.h> |
9b4a205f | 10 | #include <init.h> |
90526e9f | 11 | #include <net.h> |
7885ea85 RC |
12 | #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) |
13 | #include <netdev.h> | |
14 | #endif | |
15 | #include <linux/io.h> | |
44199ebc RC |
16 | #include <faraday/ftsmc020.h> |
17 | #include <fdtdec.h> | |
edf0acb3 | 18 | #include <dm.h> |
cd61e86e | 19 | #include <spl.h> |
7885ea85 RC |
20 | |
21 | DECLARE_GLOBAL_DATA_PTR; | |
22 | ||
48cbf624 | 23 | extern phys_addr_t prior_stage_fdt_address; |
7885ea85 RC |
24 | /* |
25 | * Miscellaneous platform dependent initializations | |
26 | */ | |
27 | ||
28 | int board_init(void) | |
29 | { | |
7885ea85 RC |
30 | gd->bd->bi_boot_params = PHYS_SDRAM_0 + 0x400; |
31 | ||
32 | return 0; | |
33 | } | |
34 | ||
35 | int dram_init(void) | |
36 | { | |
7e24518c | 37 | return fdtdec_setup_mem_size_base(); |
7885ea85 RC |
38 | } |
39 | ||
40 | int dram_init_banksize(void) | |
41 | { | |
7e24518c | 42 | return fdtdec_setup_memory_banksize(); |
7885ea85 RC |
43 | } |
44 | ||
45 | #if defined(CONFIG_FTMAC100) && !defined(CONFIG_DM_ETH) | |
46 | int board_eth_init(bd_t *bd) | |
47 | { | |
48 | return ftmac100_initialize(bd); | |
49 | } | |
50 | #endif | |
51 | ||
52 | ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) | |
53 | { | |
54 | return 0; | |
55 | } | |
d58717e4 RC |
56 | |
57 | void *board_fdt_blob_setup(void) | |
58 | { | |
d58717e4 RC |
59 | return (void *)CONFIG_SYS_FDT_BASE; |
60 | } | |
44199ebc RC |
61 | |
62 | int smc_init(void) | |
63 | { | |
64 | int node = -1; | |
65 | const char *compat = "andestech,atfsmc020"; | |
66 | void *blob = (void *)gd->fdt_blob; | |
67 | fdt_addr_t addr; | |
68 | struct ftsmc020_bank *regs; | |
69 | ||
70 | node = fdt_node_offset_by_compatible(blob, -1, compat); | |
71 | if (node < 0) | |
72 | return -FDT_ERR_NOTFOUND; | |
73 | ||
74 | addr = fdtdec_get_addr(blob, node, "reg"); | |
75 | ||
76 | if (addr == FDT_ADDR_T_NONE) | |
77 | return -EINVAL; | |
78 | ||
79 | regs = (struct ftsmc020_bank *)addr; | |
80 | regs->cr &= ~FTSMC020_BANK_WPROT; | |
81 | ||
82 | return 0; | |
83 | } | |
84 | ||
edf0acb3 RC |
85 | static void v5l2_init(void) |
86 | { | |
87 | struct udevice *dev; | |
88 | ||
89 | uclass_get_device(UCLASS_CACHE, 0, &dev); | |
90 | } | |
91 | ||
44199ebc RC |
92 | #ifdef CONFIG_BOARD_EARLY_INIT_F |
93 | int board_early_init_f(void) | |
94 | { | |
95 | smc_init(); | |
edf0acb3 | 96 | v5l2_init(); |
44199ebc RC |
97 | |
98 | return 0; | |
99 | } | |
100 | #endif | |
cd61e86e RC |
101 | |
102 | #ifdef CONFIG_SPL | |
103 | void board_boot_order(u32 *spl_boot_list) | |
104 | { | |
105 | u8 i; | |
106 | u32 boot_devices[] = { | |
107 | #ifdef CONFIG_SPL_RAM_SUPPORT | |
108 | BOOT_DEVICE_RAM, | |
109 | #endif | |
110 | #ifdef CONFIG_SPL_MMC_SUPPORT | |
111 | BOOT_DEVICE_MMC1, | |
112 | #endif | |
113 | }; | |
114 | ||
115 | for (i = 0; i < ARRAY_SIZE(boot_devices); i++) | |
116 | spl_boot_list[i] = boot_devices[i]; | |
117 | } | |
118 | #endif | |
119 | ||
120 | #ifdef CONFIG_SPL_LOAD_FIT | |
121 | int board_fit_config_name_match(const char *name) | |
122 | { | |
123 | /* boot using first FIT config */ | |
124 | return 0; | |
125 | } | |
126 | #endif |