[people/ms/u-boot.git] / board / BuR / tseries / mux.c

/*
 * mux.c
 *
 * Pinmux Setting for B&R LEIT Board(s)
 *
 * Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
 * Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <asm/arch/sys_proto.h>
#include <asm/arch/hardware.h>
#include <asm/arch/mux.h>
#include <asm/io.h>
#include <i2c.h>

static struct module_pin_mux uart0_pin_mux[] = {
	/* UART0_CTS */
	{OFFSET(uart0_ctsn), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
	/* UART0_RXD */
	{OFFSET(uart0_rxd), (MODE(0) | PULLUDEN | PULLUP_EN | RXACTIVE)},
	/* UART0_TXD */
	{OFFSET(uart0_txd), (MODE(0) | PULLUDEN)},
	{-1},
};
#ifdef CONFIG_MMC
static struct module_pin_mux mmc1_pin_mux[] = {
	{OFFSET(gpmc_ad7), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT7 */
	{OFFSET(gpmc_ad6), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT6 */
	{OFFSET(gpmc_ad5), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT5 */
	{OFFSET(gpmc_ad4), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT4 */

	{OFFSET(gpmc_ad3), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT3 */
	{OFFSET(gpmc_ad2), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT2 */
	{OFFSET(gpmc_ad1), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT1 */
	{OFFSET(gpmc_ad0), (MODE(1) | RXACTIVE | PULLUP_EN)},	/* MMC1_DAT0 */
	{OFFSET(gpmc_csn1), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CLK */
	{OFFSET(gpmc_csn2), (MODE(2) | RXACTIVE | PULLUP_EN)},	/* MMC1_CMD */
	{OFFSET(gpmc_csn0), (MODE(7) | RXACTIVE | PULLUP_EN)},	/* MMC1_WP */
	{OFFSET(gpmc_advn_ale), (MODE(7) | RXACTIVE | PULLUP_EN)},/* MMC1_CD */
	{-1},
};
#endif
static struct module_pin_mux i2c0_pin_mux[] = {
	/* I2C_DATA */
	{OFFSET(i2c0_sda), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
	/* I2C_SCLK */
	{OFFSET(i2c0_scl), (MODE(0) | RXACTIVE | PULLUDEN | SLEWCTRL)},
	{-1},
};

static struct module_pin_mux spi0_pin_mux[] = {
	/* SPI0_SCLK */
	{OFFSET(spi0_sclk), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
	/* SPI0_D0 */
	{OFFSET(spi0_d0), (MODE(0) | RXACTIVE |	PULLUDEN | PULLUP_EN)},
	/* SPI0_D1 */
	{OFFSET(spi0_d1), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
	/* SPI0_CS0 */
	{OFFSET(spi0_cs0), (MODE(0) | RXACTIVE | PULLUDEN | PULLUP_EN)},
	{-1},
};

static struct module_pin_mux mii1_pin_mux[] = {
	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
	{OFFSET(mii1_txd3), MODE(0)},			/* MII1_TXD3 */
	{OFFSET(mii1_txd2), MODE(0)},			/* MII1_TXD2 */
	{OFFSET(mii1_txd1), MODE(0)},			/* MII1_TXD1 */
	{OFFSET(mii1_txd0), MODE(0)},			/* MII1_TXD0 */
	{OFFSET(mii1_txclk), MODE(0) | RXACTIVE},	/* MII1_TXCLK */
	{OFFSET(mii1_rxclk), MODE(0) | RXACTIVE},	/* MII1_RXCLK */
	{OFFSET(mii1_rxd3), MODE(0) | RXACTIVE},	/* MII1_RXD3 */
	{OFFSET(mii1_rxd2), MODE(0) | RXACTIVE},	/* MII1_RXD2 */
	{OFFSET(mii1_rxd1), MODE(0) | RXACTIVE},	/* MII1_RXD1 */
	{OFFSET(mii1_rxd0), MODE(0) | RXACTIVE},	/* MII1_RXD0 */
	{OFFSET(mdio_data), MODE(0) | RXACTIVE | PULLUP_EN},/* MDIO_DATA */
	{OFFSET(mdio_clk), MODE(0) | PULLUP_EN},	/* MDIO_CLK */
	{-1},
};

static struct module_pin_mux mii2_pin_mux[] = {
	{OFFSET(gpmc_a0), MODE(1)},		/* MII2_TXEN */
	{OFFSET(gpmc_a1), MODE(1) | RXACTIVE},	/* MII2_RXDV */
	{OFFSET(gpmc_a2), MODE(1)},		/* MII2_TXD3 */
	{OFFSET(gpmc_a3), MODE(1)},		/* MII2_TXD2 */
	{OFFSET(gpmc_a4), MODE(1)},		/* MII2_TXD1 */
	{OFFSET(gpmc_a5), MODE(1)},		/* MII2_TXD0 */
	{OFFSET(gpmc_a6), MODE(1) | RXACTIVE},	/* MII2_TXCLK */
	{OFFSET(gpmc_a7), MODE(1) | RXACTIVE},	/* MII2_RXCLK */
	{OFFSET(gpmc_a8), MODE(1) | RXACTIVE},	/* MII2_RXD3 */
	{OFFSET(gpmc_a9), MODE(1) | RXACTIVE},	/* MII2_RXD2 */
	{OFFSET(gpmc_a10), MODE(1) | RXACTIVE},	/* MII2_RXD1 */
	{OFFSET(gpmc_a11), MODE(1) | RXACTIVE},	/* MII2_RXD0 */
	{OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
						/*
						 * MII2_CRS is shared with
						 * NAND_WAIT0
						 */
	{OFFSET(gpmc_be1n), (MODE(1) | RXACTIVE)},/* MII1_COL */
	{-1},
};
#ifdef CONFIG_NAND
static struct module_pin_mux nand_pin_mux[] = {
	{OFFSET(gpmc_ad0), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD0 */
	{OFFSET(gpmc_ad1), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD1 */
	{OFFSET(gpmc_ad2), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD2 */
	{OFFSET(gpmc_ad3), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD3 */
	{OFFSET(gpmc_ad4), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD4 */
	{OFFSET(gpmc_ad5), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD5 */
	{OFFSET(gpmc_ad6), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD6 */
	{OFFSET(gpmc_ad7), (MODE(0) | PULLUP_EN | RXACTIVE)},	/* NAND AD7 */
	{OFFSET(gpmc_wait0), (MODE(0) | RXACTIVE | PULLUP_EN)},	/* NAND WAIT */
	{OFFSET(gpmc_wpn), (MODE(7) | PULLUP_EN | RXACTIVE)},	/* NAND_WPN */
	{OFFSET(gpmc_csn0), (MODE(0) | PULLUDEN)},	/* NAND_CS0 */
	{OFFSET(gpmc_advn_ale), (MODE(0) | PULLUDEN)},	/* NAND_ADV_ALE */
	{OFFSET(gpmc_oen_ren), (MODE(0) | PULLUDEN)},	/* NAND_OE */
	{OFFSET(gpmc_wen), (MODE(0) | PULLUDEN)},	/* NAND_WEN */
	{OFFSET(gpmc_be0n_cle), (MODE(0) | PULLUDEN)},	/* NAND_BE_CLE */
	{-1},
};
#endif
static struct module_pin_mux gpIOs[] = {
	/* GPIO0_6  (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
	{OFFSET(spi0_cs1),  (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
	/* TIMER5   (MMC0_DAT3) - TIMER5 (Buzzer) */
	{OFFSET(mmc0_dat3), (MODE(3) | PULLUDEN | RXACTIVE)},
	/* TIMER6   (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */
	{OFFSET(mmc0_dat2), (MODE(7) | PULLUDEN | RXACTIVE)},
	/* GPIO2_27 (MMC0_DAT1)	 - MII_nNAND */
	{OFFSET(mmc0_dat1), (MODE(7) | PULLUDEN | RXACTIVE)},
	/* GPIO2_29 (MMC0_DAT0)	 - NAND_1n0 */
	{OFFSET(mmc0_dat0), (MODE(7) | PULLUDEN | RXACTIVE)},
	/* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
	{OFFSET(mmc0_clk), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
	/* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
	{OFFSET(mcasp0_aclkr), (MODE(7) | PULLUDEN | PULLUP_EN  | RXACTIVE)},
	/* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
	{OFFSET(mcasp0_fsr), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
	/* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
	{OFFSET(mcasp0_axr1), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
	/* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
	{OFFSET(mcasp0_ahclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
	/* GPIO2_0  (GPMC_nCS3) - DCOK */
	{OFFSET(gpmc_csn3), (MODE(7) | PULLUDDIS | RXACTIVE) },
	/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
	{OFFSET(rmii1_refclk), (MODE(7) | PULLUDDIS | RXACTIVE) },
	/*
	 * GPIO0_7 (PWW0 OUT)
	 * DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
	 */
	{OFFSET(ecap0_in_pwm0_out), (MODE(7) | PULLUDEN | RXACTIVE)},
	/* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
	{OFFSET(xdma_event_intr0), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE)},
	/* GPIO0_20 (DMA_INTR1) - REP-Switch */
	{OFFSET(xdma_event_intr1), (MODE(7) | PULLUP_EN | RXACTIVE)},
	/* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
	{OFFSET(mcasp0_aclkx), (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
	/* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
	{OFFSET(mcasp0_fsx),   (MODE(7) | PULLUDEN | PULLUP_EN | RXACTIVE) },
	/* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
	{OFFSET(mcasp0_axr0),  (MODE(7) | PULLUDDIS) },
	/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
	{OFFSET(mcasp0_ahclkr), (MODE(7) | PULLUDDIS) },

	{-1},
};

static struct module_pin_mux lcd_pin_mux[] = {
	{OFFSET(lcd_data0), (MODE(0) | PULLUDDIS)},	/* LCD-Data(0) */
	{OFFSET(lcd_data1), (MODE(0) | PULLUDDIS)},	/* LCD-Data(1) */
	{OFFSET(lcd_data2), (MODE(0) | PULLUDDIS)},	/* LCD-Data(2) */
	{OFFSET(lcd_data3), (MODE(0) | PULLUDDIS)},	/* LCD-Data(3) */
	{OFFSET(lcd_data4), (MODE(0) | PULLUDDIS)},	/* LCD-Data(4) */
	{OFFSET(lcd_data5), (MODE(0) | PULLUDDIS)},	/* LCD-Data(5) */
	{OFFSET(lcd_data6), (MODE(0) | PULLUDDIS)},	/* LCD-Data(6) */
	{OFFSET(lcd_data7), (MODE(0) | PULLUDDIS)},	/* LCD-Data(7) */
	{OFFSET(lcd_data8), (MODE(0) | PULLUDDIS)},	/* LCD-Data(8) */
	{OFFSET(lcd_data9), (MODE(0) | PULLUDDIS)},	/* LCD-Data(9) */
	{OFFSET(lcd_data10), (MODE(0) | PULLUDDIS)},	/* LCD-Data(10) */
	{OFFSET(lcd_data11), (MODE(0) | PULLUDDIS)},	/* LCD-Data(11) */
	{OFFSET(lcd_data12), (MODE(0) | PULLUDDIS)},	/* LCD-Data(12) */
	{OFFSET(lcd_data13), (MODE(0) | PULLUDDIS)},	/* LCD-Data(13) */
	{OFFSET(lcd_data14), (MODE(0) | PULLUDDIS)},	/* LCD-Data(14) */
	{OFFSET(lcd_data15), (MODE(0) | PULLUDDIS)},	/* LCD-Data(15) */

	{OFFSET(gpmc_ad8), (MODE(1) | PULLUDDIS)},	/* LCD-Data(16) */
	{OFFSET(gpmc_ad9), (MODE(1) | PULLUDDIS)},	/* LCD-Data(17) */
	{OFFSET(gpmc_ad10), (MODE(1) | PULLUDDIS)},	/* LCD-Data(18) */
	{OFFSET(gpmc_ad11), (MODE(1) | PULLUDDIS)},	/* LCD-Data(19) */
	{OFFSET(gpmc_ad12), (MODE(1) | PULLUDDIS)},	/* LCD-Data(20) */
	{OFFSET(gpmc_ad13), (MODE(1) | PULLUDDIS)},	/* LCD-Data(21) */
	{OFFSET(gpmc_ad14), (MODE(1) | PULLUDDIS)},	/* LCD-Data(22) */
	{OFFSET(gpmc_ad15), (MODE(1) | PULLUDDIS)},	/* LCD-Data(23) */

	{OFFSET(lcd_vsync), (MODE(0) | PULLUDDIS)},	/* LCD-VSync */
	{OFFSET(lcd_hsync), (MODE(0) | PULLUDDIS)},	/* LCD-HSync */
	{OFFSET(lcd_ac_bias_en), (MODE(0) | PULLUDDIS)},/* LCD-DE */
	{OFFSET(lcd_pclk), (MODE(0) | PULLUDDIS)},	/* LCD-CLK */

	{-1},
};

void enable_uart0_pin_mux(void)
{
	configure_module_pin_mux(uart0_pin_mux);
}

void enable_i2c0_pin_mux(void)
{
	configure_module_pin_mux(i2c0_pin_mux);
}

void enable_board_pin_mux(void)
{
	configure_module_pin_mux(i2c0_pin_mux);
	configure_module_pin_mux(mii1_pin_mux);
	configure_module_pin_mux(mii2_pin_mux);
#ifdef CONFIG_NAND
	configure_module_pin_mux(nand_pin_mux);
#elif defined(CONFIG_MMC)
	configure_module_pin_mux(mmc1_pin_mux);
#endif
	configure_module_pin_mux(spi0_pin_mux);
	configure_module_pin_mux(lcd_pin_mux);
	configure_module_pin_mux(gpIOs);
}
Commit	Line	Data
893c04e1 HP	1	/*
	2	* mux.c
	3	*
	4	* Pinmux Setting for B&R LEIT Board(s)
	5	*
	6	* Copyright (C) 2013 Hannes Petermaier <oe5hpm@oevsv.at>
	7	* Bernecker & Rainer Industrieelektronik GmbH - http://www.br-automation.com
	8	*
	9	* SPDX-License-Identifier: GPL-2.0+
	10	*/
	11
	12	#include <common.h>
	13	#include <asm/arch/sys_proto.h>
	14	#include <asm/arch/hardware.h>
	15	#include <asm/arch/mux.h>
	16	#include <asm/io.h>
	17	#include <i2c.h>
	18
	19	static struct module_pin_mux uart0_pin_mux[] = {
	20	/* UART0_CTS */
	21	{OFFSET(uart0_ctsn), (MODE(7) \| PULLUDEN \| PULLUP_EN \| RXACTIVE)},
	22	/* UART0_RXD */
	23	{OFFSET(uart0_rxd), (MODE(0) \| PULLUDEN \| PULLUP_EN \| RXACTIVE)},
	24	/* UART0_TXD */
	25	{OFFSET(uart0_txd), (MODE(0) \| PULLUDEN)},
	26	{-1},
	27	};
	28	#ifdef CONFIG_MMC
	29	static struct module_pin_mux mmc1_pin_mux[] = {
9a1063eb HP	30	{OFFSET(gpmc_ad7), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT7 */
	31	{OFFSET(gpmc_ad6), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT6 */
	32	{OFFSET(gpmc_ad5), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT5 */
	33	{OFFSET(gpmc_ad4), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT4 */
	34
893c04e1 HP	35	{OFFSET(gpmc_ad3), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT3 */
	36	{OFFSET(gpmc_ad2), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT2 */
	37	{OFFSET(gpmc_ad1), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT1 */
	38	{OFFSET(gpmc_ad0), (MODE(1) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_DAT0 */
	39	{OFFSET(gpmc_csn1), (MODE(2) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_CLK */
	40	{OFFSET(gpmc_csn2), (MODE(2) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_CMD */
	41	{OFFSET(gpmc_csn0), (MODE(7) \| RXACTIVE \| PULLUP_EN)}, /* MMC1_WP */
	42	{OFFSET(gpmc_advn_ale), (MODE(7) \| RXACTIVE \| PULLUP_EN)},/* MMC1_CD */
	43	{-1},
	44	};
	45	#endif
	46	static struct module_pin_mux i2c0_pin_mux[] = {
	47	/* I2C_DATA */
	48	{OFFSET(i2c0_sda), (MODE(0) \| RXACTIVE \| PULLUDEN \| SLEWCTRL)},
	49	/* I2C_SCLK */
	50	{OFFSET(i2c0_scl), (MODE(0) \| RXACTIVE \| PULLUDEN \| SLEWCTRL)},
	51	{-1},
	52	};
	53
	54	static struct module_pin_mux spi0_pin_mux[] = {
	55	/* SPI0_SCLK */
	56	{OFFSET(spi0_sclk), (MODE(0) \| RXACTIVE \| PULLUDEN \| PULLUP_EN)},
	57	/* SPI0_D0 */
	58	{OFFSET(spi0_d0), (MODE(0) \| RXACTIVE \| PULLUDEN \| PULLUP_EN)},
	59	/* SPI0_D1 */
	60	{OFFSET(spi0_d1), (MODE(0) \| RXACTIVE \| PULLUDEN \| PULLUP_EN)},
	61	/* SPI0_CS0 */
	62	{OFFSET(spi0_cs0), (MODE(0) \| RXACTIVE \| PULLUDEN \| PULLUP_EN)},
	63	{-1},
	64	};
	65
	66	static struct module_pin_mux mii1_pin_mux[] = {
	67	{OFFSET(mii1_rxerr), MODE(0) \| RXACTIVE}, /* MII1_RXERR */
	68	{OFFSET(mii1_txen), MODE(0)}, /* MII1_TXEN */
	69	{OFFSET(mii1_rxdv), MODE(0) \| RXACTIVE}, /* MII1_RXDV */
	70	{OFFSET(mii1_txd3), MODE(0)}, /* MII1_TXD3 */
	71	{OFFSET(mii1_txd2), MODE(0)}, /* MII1_TXD2 */
	72	{OFFSET(mii1_txd1), MODE(0)}, /* MII1_TXD1 */
	73	{OFFSET(mii1_txd0), MODE(0)}, /* MII1_TXD0 */
	74	{OFFSET(mii1_txclk), MODE(0) \| RXACTIVE}, /* MII1_TXCLK */
	75	{OFFSET(mii1_rxclk), MODE(0) \| RXACTIVE}, /* MII1_RXCLK */
	76	{OFFSET(mii1_rxd3), MODE(0) \| RXACTIVE}, /* MII1_RXD3 */
	77	{OFFSET(mii1_rxd2), MODE(0) \| RXACTIVE}, /* MII1_RXD2 */
	78	{OFFSET(mii1_rxd1), MODE(0) \| RXACTIVE}, /* MII1_RXD1 */
	79	{OFFSET(mii1_rxd0), MODE(0) \| RXACTIVE}, /* MII1_RXD0 */
	80	{OFFSET(mdio_data), MODE(0) \| RXACTIVE \| PULLUP_EN},/* MDIO_DATA */
	81	{OFFSET(mdio_clk), MODE(0) \| PULLUP_EN}, /* MDIO_CLK */
	82	{-1},
	83	};
	84
	85	static struct module_pin_mux mii2_pin_mux[] = {
	86	{OFFSET(gpmc_a0), MODE(1)}, /* MII2_TXEN */
	87	{OFFSET(gpmc_a1), MODE(1) \| RXACTIVE}, /* MII2_RXDV */
	88	{OFFSET(gpmc_a2), MODE(1)}, /* MII2_TXD3 */
	89	{OFFSET(gpmc_a3), MODE(1)}, /* MII2_TXD2 */
	90	{OFFSET(gpmc_a4), MODE(1)}, /* MII2_TXD1 */
	91	{OFFSET(gpmc_a5), MODE(1)}, /* MII2_TXD0 */
	92	{OFFSET(gpmc_a6), MODE(1) \| RXACTIVE}, /* MII2_TXCLK */
	93	{OFFSET(gpmc_a7), MODE(1) \| RXACTIVE}, /* MII2_RXCLK */
	94	{OFFSET(gpmc_a8), MODE(1) \| RXACTIVE}, /* MII2_RXD3 */
	95	{OFFSET(gpmc_a9), MODE(1) \| RXACTIVE}, /* MII2_RXD2 */
	96	{OFFSET(gpmc_a10), MODE(1) \| RXACTIVE}, /* MII2_RXD1 */
	97	{OFFSET(gpmc_a11), MODE(1) \| RXACTIVE}, /* MII2_RXD0 */
	98	{OFFSET(gpmc_wpn), (MODE(1) \| RXACTIVE)},/* MII2_RXERR */
99	/*
100	* MII2_CRS is shared with
101	* NAND_WAIT0
102	*/
103	{OFFSET(gpmc_be1n), (MODE(1) \| RXACTIVE)},/* MII1_COL */
104	{-1},
105	};
106	#ifdef CONFIG_NAND
107	static struct module_pin_mux nand_pin_mux[] = {
108	{OFFSET(gpmc_ad0), (MODE(0) \| PULLUP_EN \| RXACTIVE)}, /* NAND AD0 */
109	{OFFSET(gpmc_ad1), (MODE(0) \| PULLUP_EN \| RXACTIVE)}, /* NAND AD1 */
110	{OFFSET(gpmc_ad2), (MODE(0) \| PULLUP_EN \| RXACTIVE)}, /* NAND AD2 */
111	{OFFSET(gpmc_ad3), (MODE(0) \| PULLUP_EN \| RXACTIVE)}, /* NAND AD3 */
112	{OFFSET(gpmc_ad4), (MODE(0) \| PULLUP_EN \| RXACTIVE)}, /* NAND AD4 */
113	{OFFSET(gpmc_ad5), (MODE(0) \| PULLUP_EN \| RXACTIVE)}, /* NAND AD5 */
114	{OFFSET(gpmc_ad6), (MODE(0) \| PULLUP_EN \| RXACTIVE)}, /* NAND AD6 */
115	{OFFSET(gpmc_ad7), (MODE(0) \| PULLUP_EN \| RXACTIVE)}, /* NAND AD7 */
116	{OFFSET(gpmc_wait0), (MODE(0) \| RXACTIVE \| PULLUP_EN)}, /* NAND WAIT */
117	{OFFSET(gpmc_wpn), (MODE(7) \| PULLUP_EN \| RXACTIVE)}, /* NAND_WPN */
118	{OFFSET(gpmc_csn0), (MODE(0) \| PULLUDEN)}, /* NAND_CS0 */
119	{OFFSET(gpmc_advn_ale), (MODE(0) \| PULLUDEN)}, /* NAND_ADV_ALE */
120	{OFFSET(gpmc_oen_ren), (MODE(0) \| PULLUDEN)}, /* NAND_OE */
121	{OFFSET(gpmc_wen), (MODE(0) \| PULLUDEN)}, /* NAND_WEN */
122	{OFFSET(gpmc_be0n_cle), (MODE(0) \| PULLUDEN)}, /* NAND_BE_CLE */
123	{-1},
124	};
125	#endif
126	static struct module_pin_mux gpIOs[] = {
127	/* GPIO0_6 (SPI0_CS1) - 3v3_PWR_nEN (Display Power Supply) */
128	{OFFSET(spi0_cs1), (MODE(7) \| PULLUDEN \| PULLUP_EN \| RXACTIVE)},
129	/* TIMER5 (MMC0_DAT3) - TIMER5 (Buzzer) */
130	{OFFSET(mmc0_dat3), (MODE(3) \| PULLUDEN \| RXACTIVE)},
131	/* TIMER6 (MMC0_DAT2) - PWM_BACK_3V3, later used as MODE3 for PWM */
132	{OFFSET(mmc0_dat2), (MODE(7) \| PULLUDEN \| RXACTIVE)},
1ab6f61a	133	/* GPIO2_27 (MMC0_DAT1) - MII_nNAND */
893c04e1 HP	134	{OFFSET(mmc0_dat1), (MODE(7) \| PULLUDEN \| RXACTIVE)},
	135	/* GPIO2_29 (MMC0_DAT0) - NAND_1n0 */
	136	{OFFSET(mmc0_dat0), (MODE(7) \| PULLUDEN \| RXACTIVE)},
	137	/* GPIO2_30 (MMC0_CLK) - nRESET (PHY) */
	138	{OFFSET(mmc0_clk), (MODE(7) \| PULLUDEN \| PULLUP_EN \| RXACTIVE)},
	139	/* GPIO3_18 (MCASP0_ACLKR) - CPLD JTAG TDI */
	140	{OFFSET(mcasp0_aclkr), (MODE(7) \| PULLUDEN \| PULLUP_EN \| RXACTIVE)},
	141	/* GPIO3_19 (MCASP0_FSR) - CPLD JTAG TMS */
	142	{OFFSET(mcasp0_fsr), (MODE(7) \| PULLUDEN \| PULLUP_EN \| RXACTIVE)},
	143	/* GPIO3_20 (MCASP0_AXR1) - CPLD JTAG TCK */
	144	{OFFSET(mcasp0_axr1), (MODE(7) \| PULLUDEN \| PULLUP_EN \| RXACTIVE)},
	145	/* GPIO3_21 (MCASP0_AHCLKX) - CPLD JTAG TDO */
	146	{OFFSET(mcasp0_ahclkx), (MODE(7) \| PULLUDEN \| PULLUP_EN \| RXACTIVE)},
	147	/* GPIO2_0 (GPMC_nCS3) - DCOK */
	148	{OFFSET(gpmc_csn3), (MODE(7) \| PULLUDDIS \| RXACTIVE) },
	149	/* GPIO0_29 (RMII1_REFCLK) - eMMC nRST */
	150	{OFFSET(rmii1_refclk), (MODE(7) \| PULLUDDIS \| RXACTIVE) },
	151	/*
	152	* GPIO0_7 (PWW0 OUT)
	153	* DISPLAY_ONOFF (Backlight Enable at LVDS Versions)
	154	*/
	155	{OFFSET(ecap0_in_pwm0_out), (MODE(7) \| PULLUDEN \| RXACTIVE)},
1ab6f61a	156	/* GPIO0_19 (DMA_INTR0) - DISPLAY_MODE (CPLD) */
893c04e1 HP	157	{OFFSET(xdma_event_intr0), (MODE(7) \| PULLUDEN \| PULLUP_EN \| RXACTIVE)},
	158	/* GPIO0_20 (DMA_INTR1) - REP-Switch */
	159	{OFFSET(xdma_event_intr1), (MODE(7) \| PULLUP_EN \| RXACTIVE)},
	160	/* GPIO3_14 (MCASP0_ACLKX) - frei / PP709 */
	161	{OFFSET(mcasp0_aclkx), (MODE(7) \| PULLUDEN \| PULLUP_EN \| RXACTIVE) },
	162	/* GPIO3_15 (MCASP0_FSX) - PMIC_nRESET */
	163	{OFFSET(mcasp0_fsx), (MODE(7) \| PULLUDEN \| PULLUP_EN \| RXACTIVE) },
	164	/* GPIO3_16 (MCASP0_AXR0) - ETH1_LEDY */
	165	{OFFSET(mcasp0_axr0), (MODE(7) \| PULLUDDIS) },
	166	/* GPIO3_17 (MCASP0_AHCLKR) - ETH2_LEDY */
	167	{OFFSET(mcasp0_ahclkr), (MODE(7) \| PULLUDDIS) },
	168
	169	{-1},
	170	};
	171
	172	static struct module_pin_mux lcd_pin_mux[] = {
	173	{OFFSET(lcd_data0), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(0) */
	174	{OFFSET(lcd_data1), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(1) */
	175	{OFFSET(lcd_data2), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(2) */
	176	{OFFSET(lcd_data3), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(3) */
	177	{OFFSET(lcd_data4), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(4) */
	178	{OFFSET(lcd_data5), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(5) */
	179	{OFFSET(lcd_data6), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(6) */
	180	{OFFSET(lcd_data7), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(7) */
	181	{OFFSET(lcd_data8), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(8) */
	182	{OFFSET(lcd_data9), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(9) */
	183	{OFFSET(lcd_data10), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(10) */
	184	{OFFSET(lcd_data11), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(11) */
	185	{OFFSET(lcd_data12), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(12) */
	186	{OFFSET(lcd_data13), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(13) */
	187	{OFFSET(lcd_data14), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(14) */
	188	{OFFSET(lcd_data15), (MODE(0) \| PULLUDDIS)}, /* LCD-Data(15) */
	189
	190	{OFFSET(gpmc_ad8), (MODE(1) \| PULLUDDIS)}, /* LCD-Data(16) */
	191	{OFFSET(gpmc_ad9), (MODE(1) \| PULLUDDIS)}, /* LCD-Data(17) */
	192	{OFFSET(gpmc_ad10), (MODE(1) \| PULLUDDIS)}, /* LCD-Data(18) */
	193	{OFFSET(gpmc_ad11), (MODE(1) \| PULLUDDIS)}, /* LCD-Data(19) */
	194	{OFFSET(gpmc_ad12), (MODE(1) \| PULLUDDIS)}, /* LCD-Data(20) */
	195	{OFFSET(gpmc_ad13), (MODE(1) \| PULLUDDIS)}, /* LCD-Data(21) */
	196	{OFFSET(gpmc_ad14), (MODE(1) \| PULLUDDIS)}, /* LCD-Data(22) */
	197	{OFFSET(gpmc_ad15), (MODE(1) \| PULLUDDIS)}, /* LCD-Data(23) */
	198
	199	{OFFSET(lcd_vsync), (MODE(0) \| PULLUDDIS)}, /* LCD-VSync */
	200	{OFFSET(lcd_hsync), (MODE(0) \| PULLUDDIS)}, /* LCD-HSync */
	201	{OFFSET(lcd_ac_bias_en), (MODE(0) \| PULLUDDIS)},/* LCD-DE */
	202	{OFFSET(lcd_pclk), (MODE(0) \| PULLUDDIS)}, /* LCD-CLK */
	203
	204	{-1},
	205	};
	206
	207	void enable_uart0_pin_mux(void)
	208	{
	209	configure_module_pin_mux(uart0_pin_mux);
	210	}
	211
	212	void enable_i2c0_pin_mux(void)
	213	{
	214	configure_module_pin_mux(i2c0_pin_mux);
	215	}
	216
	217	void enable_board_pin_mux(void)
	218	{
	219	configure_module_pin_mux(i2c0_pin_mux);
	220	configure_module_pin_mux(mii1_pin_mux);
221	configure_module_pin_mux(mii2_pin_mux);
222	#ifdef CONFIG_NAND
223	configure_module_pin_mux(nand_pin_mux);
224	#elif defined(CONFIG_MMC)
225	configure_module_pin_mux(mmc1_pin_mux);
226	#endif
227	configure_module_pin_mux(spi0_pin_mux);
228	configure_module_pin_mux(lcd_pin_mux);
229	configure_module_pin_mux(gpIOs);
230	}