[thirdparty/u-boot.git] / board / LEOX / elpt860 / elpt860.c

/*
**=====================================================================
**
** Copyright (C) 2000, 2001, 2002, 2003
** The LEOX team <team@leox.org>, http://www.leox.org
**
** LEOX.org is about the development of free hardware and software resources
**   for system on chip.
**
** Description: U-Boot port on the LEOX's ELPT860 CPU board
** ~~~~~~~~~~~
**
**=====================================================================
**
 * SPDX-License-Identifier:	GPL-2.0+
**
**=====================================================================
*/

/*
** Note 1: In this file, you have to provide the following functions:
** ------
**              int             board_early_init_f(void)
**              int             checkboard(void)
**              phys_size_t     initdram(int board_type)
** called from 'board_init_f()' into 'common/board.c'
**
**              void            reset_phy(void)
** called from 'board_init_r()' into 'common/board.c'
*/

#include <common.h>
#include <mpc8xx.h>

/* ------------------------------------------------------------------------- */

static long int dram_size (long int, long int *, long int);

/* ------------------------------------------------------------------------- */

#define	_NOT_USED_	0xFFFFFFFF

const uint init_sdram_table[] = {
	/*
	 * Single Read. (Offset 0 in UPMA RAM)
	 */
	0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
	0xFFFFFC04,		/* last */
	/*
	 * SDRAM Initialization (offset 5 in UPMA RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,	/* last */
	/*
	 * Burst Read. (Offset 8 in UPMA RAM)
	 */
	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,	/* last */
	/*
	 * Single Write. (Offset 18 in UPMA RAM)
	 */
	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
	0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04,	/* last */
	/*
	 * Burst Write. (Offset 20 in UPMA RAM)
	 */
	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
	0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05,	/* last */
};

const uint sdram_table[] = {
	/*
	 * Single Read. (Offset 0 in UPMA RAM)
	 */
	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
	0xFF0FFC00,		/* last */
	/*
	 * SDRAM Initialization (offset 5 in UPMA RAM)
	 *
	 * This is no UPM entry point. The following definition uses
	 * the remaining space to establish an initialization
	 * sequence, which is executed by a RUN command.
	 *
	 */
	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05,	/* last */
	/*
	 * Burst Read. (Offset 8 in UPMA RAM)
	 */
	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
	0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
	/*
	 * Single Write. (Offset 18 in UPMA RAM)
	 */
	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
	0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05,	/* last */
	_NOT_USED_,
	/*
	 * Burst Write. (Offset 20 in UPMA RAM)
	 */
	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
	0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
	0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
	/*
	 * Refresh  (Offset 30 in UPMA RAM)
	 */
	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04,	/* last */
	/*
	 * Exception. (Offset 3c in UPMA RAM)
	 */
	0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04,	/* last */
};

/* ------------------------------------------------------------------------- */

#define CONFIG_SYS_PC4    0x0800

#define CONFIG_SYS_DS1    CONFIG_SYS_PC4

/*
 * Very early board init code (fpga boot, etc.)
 */
int board_early_init_f (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;

	/*
	 * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
	 */
	immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1;	/* PCDAT (DS1 = 0)                */
	immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1;	/* PCPAR (0=general purpose I/O)  */
	immr->im_ioport.iop_pcdir |= CONFIG_SYS_DS1;	/* PCDIR (I/O: 0=input, 1=output) */

	return (0);		/* success */
}

/*
 * Check Board Identity:
 *
 * Test ELPT860 ID string
 *
 * Return 1 if no second DRAM bank, otherwise returns 0
 */

int checkboard (void)
{
	char buf[64];
	int i = getenv_f("serial#", buf, sizeof(buf));

	if ((i < 0) || strncmp(buf, "ELPT860", 7))
		printf ("### No HW ID - assuming ELPT860\n");

	return (0);		/* success */
}

/* ------------------------------------------------------------------------- */

phys_size_t initdram (int board_type)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;
	long int size8, size9;
	long int size_b0 = 0;

	/*
	 * This sequence initializes SDRAM chips on ELPT860 board
	 */
	upmconfig (UPMA, (uint *) init_sdram_table,
		   sizeof (init_sdram_table) / sizeof (uint));

	memctl->memc_mptpr = 0x0200;
	memctl->memc_mamr = 0x18002111;

	memctl->memc_mar = 0x00000088;
	memctl->memc_mcr = 0x80002000;	/* CS1: SDRAM bank 0 */

	upmconfig (UPMA, (uint *) sdram_table,
		   sizeof (sdram_table) / sizeof (uint));

	/*
	 * Preliminary prescaler for refresh (depends on number of
	 * banks): This value is selected for four cycles every 62.4 us
	 * with two SDRAM banks or four cycles every 31.2 us with one
	 * bank. It will be adjusted after memory sizing.
	 */
	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;

	/*
	 * The following value is used as an address (i.e. opcode) for
	 * the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
	 * the port size is 32bit the SDRAM does NOT "see" the lower two
	 * address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
	 * MICRON SDRAMs:
	 * ->    0 00 010 0 010
	 *       |  |   | |   +- Burst Length = 4
	 *       |  |   | +----- Burst Type   = Sequential
	 *       |  |   +------- CAS Latency  = 2
	 *       |  +----------- Operating Mode = Standard
	 *       +-------------- Write Burst Mode = Programmed Burst Length
	 */
	memctl->memc_mar = 0x00000088;

	/*
	 * Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
	 * preliminary addresses - these have to be modified after the
	 * SDRAM size has been determined.
	 */
	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;

	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */

	udelay (200);

	/* perform SDRAM initializsation sequence */

	memctl->memc_mcr = 0x80002105;	/* CS1: SDRAM bank 0 */
	udelay (1);
	memctl->memc_mcr = 0x80002230;	/* CS1: SDRAM bank 0 - execute twice */
	udelay (1);

	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */

	udelay (1000);

	/*
	 * Check Bank 0 Memory Size for re-configuration
	 *
	 * try 8 column mode
	 */
	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);

	udelay (1000);

	/*
	 * try 9 column mode
	 */
	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);

	if (size8 < size9) {	/* leave configuration at 9 columns       */
		size_b0 = size9;
		/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
	} else {		/* back to 8 columns                      */

		size_b0 = size8;
		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
		udelay (500);
		/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
	}

	udelay (1000);

	/*
	 * Adjust refresh rate depending on SDRAM type, both banks
	 * For types > 128 MBit leave it at the current (fast) rate
	 */
	if (size_b0 < 0x02000000) {
		/* reduce to 15.6 us (62.4 us / quad) */
		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
		udelay (1000);
	}

	/*
	 * Final mapping: map bigger bank first
	 */
	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;

	{
		unsigned long reg;

		/* adjust refresh rate depending on SDRAM type, one bank */
		reg = memctl->memc_mptpr;
		reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
		memctl->memc_mptpr = reg;
	}

	udelay (10000);

	return (size_b0);
}

/* ------------------------------------------------------------------------- */

/*
 * Check memory range for valid RAM. A simple memory test determines
 * the actually available RAM size between addresses `base' and
 * `base + maxsize'. Some (not all) hardware errors are detected:
 * - short between address lines
 * - short between data lines
 */

static long int
dram_size (long int mamr_value, long int *base, long int maxsize)
{
	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
	volatile memctl8xx_t *memctl = &immap->im_memctl;

	memctl->memc_mamr = mamr_value;

	return (get_ram_size (base, maxsize));
}

/* ------------------------------------------------------------------------- */

#define CONFIG_SYS_PA1     0x4000
#define CONFIG_SYS_PA2     0x2000

#define CONFIG_SYS_LBKs    (CONFIG_SYS_PA2 | CONFIG_SYS_PA1)

void reset_phy (void)
{
	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;

	/*
	 * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
	 *                                          and no AUI loopback
	 */
	immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs;	/* PADAT (LBK eth 1&2 = 0)        */
	immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs;	/* PAPAR (0=general purpose I/O)  */
	immr->im_ioport.iop_padir |= CONFIG_SYS_LBKs;	/* PADIR (I/O: 0=input, 1=output) */
}
Commit	Line	Data
3bac3513 WD	1	/*
	2	**=====================================================================
	3	**
	4	** Copyright (C) 2000, 2001, 2002, 2003
	5	** The LEOX team <team@leox.org>, http://www.leox.org
	6	**
	7	** LEOX.org is about the development of free hardware and software resources
	8	** for system on chip.
	9	**
	10	** Description: U-Boot port on the LEOX's ELPT860 CPU board
	11	** ~~~~~~~~~~~
	12	**
	13	**=====================================================================
	14	**
1a459660	15	* SPDX-License-Identifier: GPL-2.0+
3bac3513 WD	16	**
	17	**=====================================================================
	18	*/
	19
	20	/*
	21	** Note 1: In this file, you have to provide the following functions:
	22	** ------
c837dcb1	23	** int board_early_init_f(void)
3bac3513	24	** int checkboard(void)
9973e3c6	25	** phys_size_t initdram(int board_type)
3bac3513 WD	26	** called from 'board_init_f()' into 'common/board.c'
	27	**
	28	** void reset_phy(void)
	29	** called from 'board_init_r()' into 'common/board.c'
	30	*/
	31
	32	#include <common.h>
	33	#include <mpc8xx.h>
	34
	35	/* ------------------------------------------------------------------------- */
	36
	37	static long int dram_size (long int, long int *, long int);
	38
	39	/* ------------------------------------------------------------------------- */
	40
	41	#define _NOT_USED_ 0xFFFFFFFF
	42
c83bf6a2 WD	43	const uint init_sdram_table[] = {
	44	/*
	45	* Single Read. (Offset 0 in UPMA RAM)
	46	*/
	47	0x0FFCCC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04,
	48	0xFFFFFC04, /* last */
	49	/*
	50	* SDRAM Initialization (offset 5 in UPMA RAM)
	51	*
	52	* This is no UPM entry point. The following definition uses
	53	* the remaining space to establish an initialization
	54	* sequence, which is executed by a RUN command.
	55	*
	56	*/
	57	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, /* last */
	58	/*
	59	* Burst Read. (Offset 8 in UPMA RAM)
	60	*/
	61	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	62	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	63	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
	64	0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, /* last */
	65	/*
	66	* Single Write. (Offset 18 in UPMA RAM)
	67	*/
	68	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04, 0x0FFC3C04,
	69	0xFFFFFC04, 0xFFFFFC04, 0x0FFFFC04, 0xFFFFFC04, /* last */
	70	/*
	71	* Burst Write. (Offset 20 in UPMA RAM)
	72	*/
	73	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	74	0xFFFFFC04, 0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04,
	75	0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC34, 0x0FAC0C34,
	76	0xFFFFFC05, 0xFFFFFC04, 0x0FFCFC04, 0xFFFFFC05, /* last */
3bac3513 WD	77	};
3bac3513 WD	78
c83bf6a2 WD	79	const uint sdram_table[] = {
	80	/*
	81	* Single Read. (Offset 0 in UPMA RAM)
	82	*/
	83	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
	84	0xFF0FFC00, /* last */
	85	/*
	86	* SDRAM Initialization (offset 5 in UPMA RAM)
	87	*
	88	* This is no UPM entry point. The following definition uses
	89	* the remaining space to establish an initialization
	90	* sequence, which is executed by a RUN command.
	91	*
	92	*/
	93	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC05, /* last */
	94	/*
	95	* Burst Read. (Offset 8 in UPMA RAM)
	96	*/
	97	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF3C04,
	98	0xF00FFC00, 0xF00FFC00, 0xF00FFC00, 0xFF0FFC00,
	99	0x0FFCCC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
	100	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
	101	/*
	102	* Single Write. (Offset 18 in UPMA RAM)
	103	*/
	104	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC04, 0x00AF0C00,
	105	0xFF0FFC04, 0x0FFCCC04, 0xFFAFFC05, /* last */
	106	_NOT_USED_,
	107	/*
	108	* Burst Write. (Offset 20 in UPMA RAM)
	109	*/
	110	0x0F0FFC24, 0x0F0CFC04, 0xFF0FFC00, 0x00AF0C00,
	111	0xF00FFC00, 0xF00FFC00, 0xF00FFC04, 0x0FFCCC04,
	112	0xFFAFFC04, 0xFFAFFC05, 0xFFAFFC04, 0xFFAFFC04,
	113	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
	114	/*
	115	* Refresh (Offset 30 in UPMA RAM)
	116	*/
	117	0x0FFC3C04, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC04,
	118	0xFFFFFC05, 0xFFFFFC04, 0xFFFFFC05, _NOT_USED_,
	119	0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, 0xFFAFFC04, /* last */
	120	/*
	121	* Exception. (Offset 3c in UPMA RAM)
	122	*/
	123	0x0FFFFC34, 0x0FAC0C34, 0xFFFFFC05, 0xFFAFFC04, /* last */
3bac3513 WD	124	};
	125
	126	/* ------------------------------------------------------------------------- */
	127
6d0f6bcf	128	#define CONFIG_SYS_PC4 0x0800
3bac3513	129
6d0f6bcf	130	#define CONFIG_SYS_DS1 CONFIG_SYS_PC4
3bac3513 WD	131
	132	/*
	133	* Very early board init code (fpga boot, etc.)
	134	*/
c837dcb1	135	int board_early_init_f (void)
3bac3513	136	{
6d0f6bcf	137	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
3bac3513	138
c83bf6a2 WD	139	/*
	140	* Light up the red led on ELPT860 pcb (DS1) (PCDAT)
	141	*/
6d0f6bcf JCPV	142	immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1; /* PCDAT (DS1 = 0) */
	143	immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1; /* PCPAR (0=general purpose I/O) */
	144	immr->im_ioport.iop_pcdir \|= CONFIG_SYS_DS1; /* PCDIR (I/O: 0=input, 1=output) */
3bac3513	145
c83bf6a2	146	return (0); /* success */
3bac3513 WD	147	}
	148
	149	/*
	150	* Check Board Identity:
	151	*
	152	* Test ELPT860 ID string
	153	*
	154	* Return 1 if no second DRAM bank, otherwise returns 0
	155	*/
	156
c83bf6a2	157	int checkboard (void)
3bac3513	158	{
f0c0b3a9 WD	159	char buf[64];
f0c0b3a9 WD	160	int i = getenv_f("serial#", buf, sizeof(buf));
3bac3513	161
f0c0b3a9	162	if ((i < 0) \|\| strncmp(buf, "ELPT860", 7))
c83bf6a2	163	printf ("### No HW ID - assuming ELPT860\n");
8bde7f77	164
c83bf6a2	165	return (0); /* success */
3bac3513 WD	166	}
	167
	168	/* ------------------------------------------------------------------------- */
	169
9973e3c6	170	phys_size_t initdram (int board_type)
3bac3513	171	{
6d0f6bcf	172	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
c83bf6a2 WD	173	volatile memctl8xx_t *memctl = &immap->im_memctl;
	174	long int size8, size9;
	175	long int size_b0 = 0;
	176
	177	/*
	178	* This sequence initializes SDRAM chips on ELPT860 board
	179	*/
	180	upmconfig (UPMA, (uint *) init_sdram_table,
	181	sizeof (init_sdram_table) / sizeof (uint));
	182
	183	memctl->memc_mptpr = 0x0200;
	184	memctl->memc_mamr = 0x18002111;
	185
	186	memctl->memc_mar = 0x00000088;
	187	memctl->memc_mcr = 0x80002000; /* CS1: SDRAM bank 0 */
	188
	189	upmconfig (UPMA, (uint *) sdram_table,
	190	sizeof (sdram_table) / sizeof (uint));
	191
	192	/*
	193	* Preliminary prescaler for refresh (depends on number of
	194	* banks): This value is selected for four cycles every 62.4 us
	195	* with two SDRAM banks or four cycles every 31.2 us with one
	196	* bank. It will be adjusted after memory sizing.
	197	*/
6d0f6bcf	198	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
c83bf6a2 WD	199
	200	/*
	201	* The following value is used as an address (i.e. opcode) for
	202	* the LOAD MODE REGISTER COMMAND during SDRAM initialisation. If
	203	* the port size is 32bit the SDRAM does NOT "see" the lower two
	204	* address lines, i.e. mar=0x00000088 -> opcode=0x00000022 for
	205	* MICRON SDRAMs:
	206	* -> 0 00 010 0 010
	207	* \| \| \| \| +- Burst Length = 4
	208	* \| \| \| +----- Burst Type = Sequential
	209	* \| \| +------- CAS Latency = 2
	210	* \| +----------- Operating Mode = Standard
	211	* +-------------- Write Burst Mode = Programmed Burst Length
	212	*/
	213	memctl->memc_mar = 0x00000088;
	214
	215	/*
	216	* Map controller banks 2 and 3 to the SDRAM banks 2 and 3 at
	217	* preliminary addresses - these have to be modified after the
	218	* SDRAM size has been determined.
	219	*/
6d0f6bcf JCPV	220	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
6d0f6bcf JCPV	221	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
c83bf6a2	222
6d0f6bcf	223	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
c83bf6a2 WD	224
	225	udelay (200);
	226
	227	/* perform SDRAM initializsation sequence */
	228
	229	memctl->memc_mcr = 0x80002105; /* CS1: SDRAM bank 0 */
	230	udelay (1);
	231	memctl->memc_mcr = 0x80002230; /* CS1: SDRAM bank 0 - execute twice */
	232	udelay (1);
	233
	234	memctl->memc_mamr \|= MAMR_PTAE; /* enable refresh */
	235
	236	udelay (1000);
	237
	238	/*
	239	* Check Bank 0 Memory Size for re-configuration
	240	*
	241	* try 8 column mode
	242	*/
6d0f6bcf	243	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
77ddac94	244	SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
c83bf6a2	245
3bac3513	246	udelay (1000);
3bac3513	247
c83bf6a2 WD	248	/*
	249	* try 9 column mode
	250	*/
6d0f6bcf	251	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
77ddac94	252	SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
c83bf6a2 WD	253
	254	if (size8 < size9) { /* leave configuration at 9 columns */
	255	size_b0 = size9;
	256	/* debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20); */
	257	} else { /* back to 8 columns */
	258
	259	size_b0 = size8;
6d0f6bcf	260	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
c83bf6a2 WD	261	udelay (500);
	262	/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
	263	}
	264
	265	udelay (1000);
	266
	267	/*
	268	* Adjust refresh rate depending on SDRAM type, both banks
	269	* For types > 128 MBit leave it at the current (fast) rate
	270	*/
	271	if (size_b0 < 0x02000000) {
	272	/* reduce to 15.6 us (62.4 us / quad) */
6d0f6bcf	273	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
c83bf6a2 WD	274	udelay (1000);
	275	}
	276
	277	/*
	278	* Final mapping: map bigger bank first
	279	*/
6d0f6bcf JCPV	280	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) \| CONFIG_SYS_OR_TIMING_SDRAM;
6d0f6bcf JCPV	281	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMA \| BR_V;
3bac3513	282
c83bf6a2 WD	283	{
c83bf6a2 WD	284	unsigned long reg;
8bde7f77	285
c83bf6a2 WD	286	/* adjust refresh rate depending on SDRAM type, one bank */
c83bf6a2 WD	287	reg = memctl->memc_mptpr;
6d0f6bcf	288	reg >>= 1; /* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
c83bf6a2 WD	289	memctl->memc_mptpr = reg;
c83bf6a2 WD	290	}
3bac3513	291
c83bf6a2	292	udelay (10000);
8bde7f77	293
c83bf6a2	294	return (size_b0);
3bac3513 WD	295	}
	296
	297	/* ------------------------------------------------------------------------- */
	298
	299	/*
	300	* Check memory range for valid RAM. A simple memory test determines
	301	* the actually available RAM size between addresses `base' and
	302	* `base + maxsize'. Some (not all) hardware errors are detected:
	303	* - short between address lines
	304	* - short between data lines
	305	*/
	306
8bde7f77	307	static long int
c83bf6a2	308	dram_size (long int mamr_value, long int *base, long int maxsize)
3bac3513	309	{
6d0f6bcf	310	volatile immap_t immap = (immap_t ) CONFIG_SYS_IMMR;
c83bf6a2	311	volatile memctl8xx_t *memctl = &immap->im_memctl;
8bde7f77	312
c83bf6a2	313	memctl->memc_mamr = mamr_value;
3bac3513	314
c83bf6a2	315	return (get_ram_size (base, maxsize));
3bac3513 WD	316	}
	317
	318	/* ------------------------------------------------------------------------- */
	319
6d0f6bcf JCPV	320	#define CONFIG_SYS_PA1 0x4000
6d0f6bcf JCPV	321	#define CONFIG_SYS_PA2 0x2000
3bac3513	322
6d0f6bcf	323	#define CONFIG_SYS_LBKs (CONFIG_SYS_PA2 \| CONFIG_SYS_PA1)
3bac3513	324
c83bf6a2	325	void reset_phy (void)
3bac3513	326	{
6d0f6bcf	327	volatile immap_t immr = (immap_t ) CONFIG_SYS_IMMR;
c83bf6a2 WD	328
	329	/*
	330	* Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
	331	* and no AUI loopback
	332	*/
6d0f6bcf JCPV	333	immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs; /* PADAT (LBK eth 1&2 = 0) */
	334	immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs; /* PAPAR (0=general purpose I/O) */
	335	immr->im_ioport.iop_padir \|= CONFIG_SYS_LBKs; /* PADIR (I/O: 0=input, 1=output) */
3bac3513	336	}