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83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
ce9c227c | 2 | /* |
57b4bce9 | 3 | * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net> |
ce9c227c AA |
4 | * |
5 | * (C) Copyright 2009 | |
6 | * Marvell Semiconductor <www.marvell.com> | |
7 | * Written-by: Prafulla Wadaskar <prafulla@marvell.com> | |
ce9c227c AA |
8 | */ |
9 | ||
10 | #include <common.h> | |
11 | #include <miiphy.h> | |
12 | #include <asm/arch/orion5x.h> | |
85e04b7a | 13 | #include "../common/common.h" |
9608e7de AA |
14 | #include <spl.h> |
15 | #include <ns16550.h> | |
c62db35d | 16 | #include <asm/mach-types.h> |
ce9c227c AA |
17 | |
18 | DECLARE_GLOBAL_DATA_PTR; | |
19 | ||
ce9c227c AA |
20 | int board_init(void) |
21 | { | |
22 | /* arch number of board */ | |
23 | gd->bd->bi_arch_number = MACH_TYPE_EDMINI_V2; | |
24 | ||
25 | /* boot parameter start at 256th byte of RAM base */ | |
26 | gd->bd->bi_boot_params = gd->bd->bi_dram[0].start + 0x100; | |
27 | ||
28 | return 0; | |
29 | } | |
ab9164d0 AA |
30 | |
31 | #if defined(CONFIG_CMD_NET) && defined(CONFIG_RESET_PHY_R) | |
32 | /* Configure and enable MV88E1116 PHY */ | |
33 | void reset_phy(void) | |
34 | { | |
c59c0857 | 35 | mv_phy_88e1116_init("egiga0", 8); |
ab9164d0 AA |
36 | } |
37 | #endif /* CONFIG_RESET_PHY_R */ | |
9608e7de AA |
38 | |
39 | /* | |
40 | * SPL serial setup and NOR boot device selection | |
41 | */ | |
42 | ||
43 | #ifdef CONFIG_SPL_BUILD | |
44 | ||
45 | void spl_board_init(void) | |
46 | { | |
47 | preloader_console_init(); | |
48 | } | |
49 | ||
50 | u32 spl_boot_device(void) | |
51 | { | |
52 | return BOOT_DEVICE_NOR; | |
53 | } | |
54 | ||
55 | #endif /* CONFIG_SPL_BUILD */ |