[u-boot.git] / board / MAI / AmigaOneG3SE / macros.h


#ifndef _MACROS_H
#define _MACROS_H

	/*
	** Load a long integer into a register
	*/
	.macro liw reg, value
		lis \reg, \value@h
		ori \reg, \reg, \value@l
	.endm


	/*
	** Generate config_addr request
	** This macro expects the values in registers:
	** r3 - bus
	** r4 - devfn
	** r5 - offset
	*/
	.macro config_addr
		rlwinm	r9, r5, 24, 0, 6
		rlwinm	r8, r4, 16, 0, 31
		rlwinm	r7, r3, 8, 0, 31
		or	r9, r8, r9
		or	r9, r7, r9
		ori	r9, r9, 0x80
		liw	r10, 0xfec00cf8
		stw	r9, 0(r10)
		eieio
		sync
	.endm


	/*
	** Generate config_data address
	*/
	.macro config_data mask
		andi.	r9, r5, \mask
		addi	r9, r9, 0xcfc
		oris	r9, r9, 0xfee0
	.endm


	/*
	** Write a byte value to an output port
	*/
	.macro outb port, value
		lis     r2, 0xfe00
		li      r0, \value
		stb     r0, \port(r2)
	.endm


	/*
	** Write a register byte value to an output port
	*/
	.macro outbr port, value
		lis     r2, 0xfe00
		stb     \value, \port(r2)
	.endm


	/*
	** Read a byte value from a port into a specified register
	*/
	.macro inb reg, port
		lis     r2, 0xfe00
		lbz     \reg, \port(r2)
	.endm


	/*
	** Write a byte to the SuperIO config area
	*/
	.macro siowb offset, value
		li      r3, 0
		li      r4, (7<<3)
		li      r5, \offset
		li      r6, \value
		bl      pci_write_cfg_byte
	.endm

#endif
Commit	Line	Data
c7de829c WD	1
	2	#ifndef _MACROS_H
	3	#define _MACROS_H
	4
	5	/*
	6	** Load a long integer into a register
	7	*/
8bde7f77 WD	8	.macro liw reg, value
	9	lis \reg, \value@h
	10	ori \reg, \reg, \value@l
	11	.endm
c7de829c WD	12
c7de829c WD	13
8bde7f77	14	/*
c7de829c WD	15	** Generate config_addr request
	16	** This macro expects the values in registers:
	17	** r3 - bus
	18	** r4 - devfn
	19	** r5 - offset
	20	*/
8bde7f77	21	.macro config_addr
c7de829c WD	22	rlwinm r9, r5, 24, 0, 6
	23	rlwinm r8, r4, 16, 0, 31
	24	rlwinm r7, r3, 8, 0, 31
	25	or r9, r8, r9
	26	or r9, r7, r9
	27	ori r9, r9, 0x80
	28	liw r10, 0xfec00cf8
	29	stw r9, 0(r10)
	30	eieio
	31	sync
	32	.endm
	33
8bde7f77	34
c7de829c WD	35	/*
	36	** Generate config_data address
	37	*/
	38	.macro config_data mask
	39	andi. r9, r5, \mask
	40	addi r9, r9, 0xcfc
	41	oris r9, r9, 0xfee0
	42	.endm
	43
	44
	45	/*
	46	** Write a byte value to an output port
	47	*/
8bde7f77 WD	48	.macro outb port, value
	49	lis r2, 0xfe00
	50	li r0, \value
	51	stb r0, \port(r2)
	52	.endm
c7de829c WD	53
	54
	55	/*
	56	** Write a register byte value to an output port
	57	*/
8bde7f77 WD	58	.macro outbr port, value
	59	lis r2, 0xfe00
	60	stb \value, \port(r2)
	61	.endm
c7de829c WD	62
c7de829c WD	63
8bde7f77	64	/*
c7de829c WD	65	** Read a byte value from a port into a specified register
c7de829c WD	66	*/
8bde7f77 WD	67	.macro inb reg, port
	68	lis r2, 0xfe00
	69	lbz \reg, \port(r2)
	70	.endm
c7de829c WD	71
	72
	73	/*
	74	** Write a byte to the SuperIO config area
	75	*/
8bde7f77 WD	76	.macro siowb offset, value
	77	li r3, 0
	78	li r4, (7<<3)
	79	li r5, \offset
	80	li r6, \value
	81	bl pci_write_cfg_byte
	82	.endm
c7de829c WD	83
c7de829c WD	84	#endif