[u-boot.git] / board / MAI / bios_emulator / scitech / include / pcilib.h

/****************************************************************************
*
*                   SciTech OS Portability Manager Library
*
*  ========================================================================
*
*    The contents of this file are subject to the SciTech MGL Public
*    License Version 1.0 (the "License"); you may not use this file
*    except in compliance with the License. You may obtain a copy of
*    the License at http://www.scitechsoft.com/mgl-license.txt
*
*    Software distributed under the License is distributed on an
*    "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
*    implied. See the License for the specific language governing
*    rights and limitations under the License.
*
*    The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
*
*    The Initial Developer of the Original Code is SciTech Software, Inc.
*    All Rights Reserved.
*
*  ========================================================================
*
* Language:     ANSI C
* Environment:  Any
*
* Description:  Header file for interface routines to the PCI bus.
*
****************************************************************************/

#ifndef __PCILIB_H
#define __PCILIB_H

#include "scitech.h"

/*---------------------- Macros and type definitions ----------------------*/

#pragma pack(1)

/* Defines for PCIDeviceInfo.HeaderType */

typedef enum {
    PCI_deviceType                  = 0x00,
    PCI_bridgeType                  = 0x01,
    PCI_cardBusBridgeType           = 0x02,
    PCI_multiFunctionType           = 0x80
    } PCIHeaderTypeFlags;

/* Defines for PCIDeviceInfo.Command */

typedef enum {
    PCI_enableIOSpace               = 0x0001,
    PCI_enableMemorySpace           = 0x0002,
    PCI_enableBusMaster             = 0x0004,
    PCI_enableSpecialCylces         = 0x0008,
    PCI_enableWriteAndInvalidate    = 0x0010,
    PCI_enableVGACompatiblePalette  = 0x0020,
    PCI_enableParity                = 0x0040,
    PCI_enableWaitCycle             = 0x0080,
    PCI_enableSerr                  = 0x0100,
    PCI_enableFastBackToBack        = 0x0200
    } PCICommandFlags;

/* Defines for PCIDeviceInfo.Status */

typedef enum {
    PCI_statusCapabilitiesList      = 0x0010,
    PCI_status66MhzCapable          = 0x0020,
    PCI_statusUDFSupported          = 0x0040,
    PCI_statusFastBackToBack        = 0x0080,
    PCI_statusDataParityDetected    = 0x0100,
    PCI_statusDevSel                = 0x0600,
    PCI_statusSignaledTargetAbort   = 0x0800,
    PCI_statusRecievedTargetAbort   = 0x1000,
    PCI_statusRecievedMasterAbort   = 0x2000,
    PCI_statusSignaledSystemError   = 0x4000,
    PCI_statusDetectedParityError   = 0x8000
    } PCIStatusFlags;

/* PCI capability IDs */

typedef enum {
    PCI_capsPowerManagement         = 0x01,
    PCI_capsAGP                     = 0x02,
    PCI_capsMSI                     = 0x05
    } PCICapsType;

/* PCI AGP rate definitions */

typedef enum {
    PCI_AGPRate1X                   = 0x1,
    PCI_AGPRate2X                   = 0x2,
    PCI_AGPRate4X                   = 0x4
    } PCIAGPRateType;

/* NOTE: We define all bitfield's as uint's, specifically so that the IBM
 *       Visual Age C++ compiler does not complain. We need them to be
 *       32-bits wide, and this is the width of an unsigned integer, but
 *       we can't use a ulong to make this explicit or we get errors.
 */

/* Structure defining a PCI slot identifier */

typedef union {
    struct {
	uint    Zero:2;
	uint    Register:6;
	uint    Function:3;
	uint    Device:5;
	uint    Bus:8;
	uint    Reserved:7;
	uint    Enable:1;
	} p;
    ulong   i;
    } PCIslot;

/* Structure defining the regular (type 0) PCI configuration register
 * layout. We use this in a union below so we can describe all types of
 * PCI configuration spaces with a single structure.
 */

typedef struct {
    ulong   BaseAddress10;
    ulong   BaseAddress14;
    ulong   BaseAddress18;
    ulong   BaseAddress1C;
    ulong   BaseAddress20;
    ulong   BaseAddress24;
    ulong   CardbusCISPointer;
    ushort  SubSystemVendorID;
    ushort  SubSystemID;
    ulong   ROMBaseAddress;
    uchar   CapabilitiesPointer;
    uchar   reserved1;
    uchar   reserved2;
    uchar   reserved3;
    ulong   reserved4;
    uchar   InterruptLine;
    uchar   InterruptPin;
    uchar   MinimumGrant;
    uchar   MaximumLatency;

    /* These are not in the actual config space, but we enumerate them */
    ulong   BaseAddress10Len;
    ulong   BaseAddress14Len;
    ulong   BaseAddress18Len;
    ulong   BaseAddress1CLen;
    ulong   BaseAddress20Len;
    ulong   BaseAddress24Len;
    ulong   ROMBaseAddressLen;
    } PCIType0Info;

/* Structure defining PCI to PCI bridge (type 1) PCI configuration register
 * layout. We use this in a union below so we can describe all types of
 * PCI configuration spaces with a single structure.
 */

typedef struct {
    ulong   BaseAddress10;
    ulong   BaseAddress14;
    uchar   PrimaryBusNumber;
    uchar   SecondayBusNumber;
    uchar   SubordinateBusNumber;
    uchar   SecondaryLatencyTimer;
    uchar   IOBase;
    uchar   IOLimit;
    ushort  SecondaryStatus;
    ushort  MemoryBase;
    ushort  MemoryLimit;
    ushort  PrefetchableMemoryBase;
    ushort  PrefetchableMemoryLimit;
    ulong   PrefetchableBaseHi;
    ulong   PrefetchableLimitHi;
    ushort  IOBaseHi;
    ushort  IOLimitHi;
    uchar   CapabilitiesPointer;
    uchar   reserved1;
    uchar   reserved2;
    uchar   reserved3;
    ulong   ROMBaseAddress;
    uchar   InterruptLine;
    uchar   InterruptPin;
    ushort  BridgeControl;
    } PCIType1Info;

/* PCI to CardBus bridge (type 2) configuration information */
typedef struct {
    ulong   SocketRegistersBaseAddress;
    uchar   CapabilitiesPointer;
    uchar   reserved1;
    ushort  SecondaryStatus;
    uchar   PrimaryBus;
    uchar   SecondaryBus;
    uchar   SubordinateBus;
    uchar   SecondaryLatency;
    struct  {
	ulong   Base;
	ulong   Limit;
	} Range[4];
    uchar   InterruptLine;
    uchar   InterruptPin;
    ushort  BridgeControl;
    } PCIType2Info;

/* Structure defining the PCI configuration space information for a
 * single PCI device on the PCI bus. We enumerate all this information
 * for all PCI devices on the bus.
 */

typedef struct {
    ulong               dwSize;
    PCIslot             slot;
    ulong               mech1;
    ushort              VendorID;
    ushort              DeviceID;
    ushort              Command;
    ushort              Status;
    uchar               RevID;
    uchar               Interface;
    uchar               SubClass;
    uchar               BaseClass;
    uchar               CacheLineSize;
    uchar               LatencyTimer;
    uchar               HeaderType;
    uchar               BIST;
    union {
	PCIType0Info    type0;
	PCIType1Info    type1;
	PCIType2Info    type2;
	} u;
    } PCIDeviceInfo;

/* PCI Capability header structure. All PCI capabilities have the
 * following header.
 *
 * capsID is used to identify the type of the structure as define above.
 *
 * next is the offset in PCI configuration space (0x40-0xFC) of the
 * next capability structure in the list, or 0x00 if there are no more
 * entries.
 */

typedef struct {
    uchar   capsID;
    uchar   next;
    } PCICapsHeader;

/* Structure defining the PCI AGP status register contents */

typedef struct {
    uint    rate:3;
    uint    rsvd1:1;
    uint    fastWrite:1;
    uint    fourGB:1;
    uint    rsvd2:3;
    uint    sideBandAddressing:1;
    uint    rsvd3:14;
    uint    requestQueueDepthMaximum:8;
    } PCIAGPStatus;

/* Structure defining the PCI AGP command register contents */

typedef struct {
    uint    rate:3;
    uint    rsvd1:1;
    uint    fastWriteEnable:1;
    uint    fourGBEnable:1;
    uint    rsvd2:2;
    uint    AGPEnable:1;
    uint    SBAEnable:1;
    uint    rsvd3:14;
    uint    requestQueueDepth:8;
    } PCIAGPCommand;

/* AGP Capability structure */

typedef struct {
    PCICapsHeader   h;
    ushort          majMin;
    PCIAGPStatus    AGPStatus;
    PCIAGPCommand   AGPCommand;
    } PCIAGPCapability;

/* Structure for obtaining the PCI IRQ routing information */

typedef struct {
    uchar   bus;
    uchar   device;
    uchar   linkA;
    ushort  mapA;
    uchar   linkB;
    ushort  mapB;
    uchar   linkC;
    ushort  mapC;
    uchar   linkD;
    ushort  mapD;
    uchar   slot;
    uchar   reserved;
    } PCIRouteInfo;

typedef struct {
    ushort          BufferSize;
    PCIRouteInfo    *DataBuffer;
    } PCIRoutingOptionsBuffer;

#define NUM_PCI_REG                 (sizeof(PCIDeviceInfo) / 4) - 10
#define PCI_BRIDGE_CLASS            0x06
#define PCI_HOST_BRIDGE_SUBCLASS    0x00
#define PCI_EARLY_VGA_CLASS         0x00
#define PCI_EARLY_VGA_SUBCLASS      0x01
#define PCI_DISPLAY_CLASS           0x03
#define PCI_DISPLAY_VGA_SUBCLASS    0x00
#define PCI_DISPLAY_XGA_SUBCLASS    0x01
#define PCI_DISPLAY_OTHER_SUBCLASS  0x80
#define PCI_MM_CLASS                0x04
#define PCI_AUDIO_SUBCLASS          0x01

/* Macros to detect specific classes of devices */

#define PCI_IS_3DLABS_NONVGA_CLASS(pci) \
   (((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_OTHER_SUBCLASS) \
 && ((pci)->VendorID == 0x3D3D || (pci)->VendorID == 0x104C))

#define PCI_IS_DISPLAY_CLASS(pci) \
   (((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_VGA_SUBCLASS) \
 || ((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_XGA_SUBCLASS) \
 || ((pci)->BaseClass == PCI_EARLY_VGA_CLASS && (pci)->SubClass == PCI_EARLY_VGA_SUBCLASS) \
 || PCI_IS_3DLABS_NONVGA_CLASS(pci))

/* Function codes to pass to PCI_accessReg */

#define PCI_READ_BYTE               0
#define PCI_READ_WORD               1
#define PCI_READ_DWORD              2
#define PCI_WRITE_BYTE              3
#define PCI_WRITE_WORD              4
#define PCI_WRITE_DWORD             5

/* Macros to read/write PCI registers. These assume a global PCI array
 * of device information.
 */

#define PCI_readPCIRegB(index,device)   \
    PCI_accessReg(index,0,0,&PCI[DeviceIndex[device]])

#define PCI_readPCIRegW(index,device)   \
    PCI_accessReg(index,0,1,&PCI[DeviceIndex[device]])

#define PCI_readPCIRegL(index,device)   \
    PCI_accessReg(index,0,2,&PCI[DeviceIndex[device]])

#define PCI_writePCIRegB(index,value,device)    \
    PCI_accessReg(index,value,3,&PCI[DeviceIndex[device]])

#define PCI_writePCIRegW(index,value,device)    \
    PCI_accessReg(index,value,4,&PCI[DeviceIndex[device]])

#define PCI_writePCIRegL(index,value,device)    \
    PCI_accessReg(index,value,5,&PCI[DeviceIndex[device]])

#pragma pack()

/*-------------------------- Function Prototypes --------------------------*/

#ifdef  __cplusplus
extern "C" {                        /* Use "C" linkage when in C++ mode */
#endif

/* Function to determine the number of PCI devices in the system */

int     _ASMAPI PCI_getNumDevices(void);

/* Function to enumerate all device on the PCI bus */

int     _ASMAPI PCI_enumerate(PCIDeviceInfo info[]);

/* Function to access PCI configuration registers */

ulong   _ASMAPI PCI_accessReg(int index,ulong value,int func,PCIDeviceInfo *info);

/* Function to get PCI IRQ routing options for a card */

int     _ASMAPI PCI_getIRQRoutingOptions(int numDevices,PCIRouteInfo *buffer);

/* Function to re-route the PCI IRQ setting for a device */

ibool   _ASMAPI PCI_setHardwareIRQ(PCIDeviceInfo *info,uint intPin,uint IRQ);

/* Function to generate a special cyle on the specified PCI bus */

void    _ASMAPI PCI_generateSpecialCyle(uint bus,ulong specialCycleData);

/* Function to determine the size of a PCI base address register */

ulong   _ASMAPI PCI_findBARSize(int bar,PCIDeviceInfo *pci);

/* Function to read a block of PCI configuration space registers */

void    _ASMAPI PCI_readRegBlock(PCIDeviceInfo *info,int index,void *dst,int count);

/* Function to write a block of PCI configuration space registers */

void    _ASMAPI PCI_writeRegBlock(PCIDeviceInfo *info,int index,void *src,int count);

/* Function to return the 32-bit PCI BIOS entry point */

ulong   _ASMAPI PCIBIOS_getEntry(void);

#ifdef  __cplusplus
}                                   /* End of "C" linkage for C++       */
#endif

#endif  /* __PCILIB_H */
Commit	Line	Data
c7de829c WD	1	/****************************************************************************
	2	*
	3	* SciTech OS Portability Manager Library
	4	*
	5	* ========================================================================
	6	*
	7	* The contents of this file are subject to the SciTech MGL Public
	8	* License Version 1.0 (the "License"); you may not use this file
	9	* except in compliance with the License. You may obtain a copy of
	10	* the License at http://www.scitechsoft.com/mgl-license.txt
	11	*
	12	* Software distributed under the License is distributed on an
	13	* "AS IS" basis, WITHOUT WARRANTY OF ANY KIND, either express or
	14	* implied. See the License for the specific language governing
	15	* rights and limitations under the License.
	16	*
	17	* The Original Code is Copyright (C) 1991-1998 SciTech Software, Inc.
	18	*
	19	* The Initial Developer of the Original Code is SciTech Software, Inc.
	20	* All Rights Reserved.
	21	*
	22	* ========================================================================
	23	*
	24	* Language: ANSI C
	25	* Environment: Any
	26	*
	27	* Description: Header file for interface routines to the PCI bus.
	28	*
	29	****************************************************************************/
	30
	31	#ifndef __PCILIB_H
	32	#define __PCILIB_H
	33
	34	#include "scitech.h"
	35
	36	/---------------------- Macros and type definitions ----------------------/
	37
	38	#pragma pack(1)
	39
	40	/* Defines for PCIDeviceInfo.HeaderType */
	41
	42	typedef enum {
	43	PCI_deviceType = 0x00,
	44	PCI_bridgeType = 0x01,
	45	PCI_cardBusBridgeType = 0x02,
	46	PCI_multiFunctionType = 0x80
	47	} PCIHeaderTypeFlags;
	48
	49	/* Defines for PCIDeviceInfo.Command */
	50
	51	typedef enum {
	52	PCI_enableIOSpace = 0x0001,
	53	PCI_enableMemorySpace = 0x0002,
	54	PCI_enableBusMaster = 0x0004,
	55	PCI_enableSpecialCylces = 0x0008,
	56	PCI_enableWriteAndInvalidate = 0x0010,
	57	PCI_enableVGACompatiblePalette = 0x0020,
	58	PCI_enableParity = 0x0040,
	59	PCI_enableWaitCycle = 0x0080,
	60	PCI_enableSerr = 0x0100,
	61	PCI_enableFastBackToBack = 0x0200
	62	} PCICommandFlags;
	63
	64	/* Defines for PCIDeviceInfo.Status */
65
66	typedef enum {
67	PCI_statusCapabilitiesList = 0x0010,
68	PCI_status66MhzCapable = 0x0020,
69	PCI_statusUDFSupported = 0x0040,
70	PCI_statusFastBackToBack = 0x0080,
71	PCI_statusDataParityDetected = 0x0100,
72	PCI_statusDevSel = 0x0600,
73	PCI_statusSignaledTargetAbort = 0x0800,
74	PCI_statusRecievedTargetAbort = 0x1000,
75	PCI_statusRecievedMasterAbort = 0x2000,
76	PCI_statusSignaledSystemError = 0x4000,
77	PCI_statusDetectedParityError = 0x8000
78	} PCIStatusFlags;
79
80	/* PCI capability IDs */
81
82	typedef enum {
83	PCI_capsPowerManagement = 0x01,
84	PCI_capsAGP = 0x02,
85	PCI_capsMSI = 0x05
86	} PCICapsType;
87
88	/* PCI AGP rate definitions */
89
90	typedef enum {
91	PCI_AGPRate1X = 0x1,
92	PCI_AGPRate2X = 0x2,
93	PCI_AGPRate4X = 0x4
94	} PCIAGPRateType;
95
96	/* NOTE: We define all bitfield's as uint's, specifically so that the IBM
97	* Visual Age C++ compiler does not complain. We need them to be
98	* 32-bits wide, and this is the width of an unsigned integer, but
99	* we can't use a ulong to make this explicit or we get errors.
100	*/
101
102	/* Structure defining a PCI slot identifier */
103
104	typedef union {
105	struct {
8bde7f77 WD	106	uint Zero:2;
	107	uint Register:6;
	108	uint Function:3;
	109	uint Device:5;
	110	uint Bus:8;
	111	uint Reserved:7;
	112	uint Enable:1;
	113	} p;
c7de829c WD	114	ulong i;
	115	} PCIslot;
	116
	117	/* Structure defining the regular (type 0) PCI configuration register
	118	* layout. We use this in a union below so we can describe all types of
	119	* PCI configuration spaces with a single structure.
	120	*/
	121
	122	typedef struct {
	123	ulong BaseAddress10;
	124	ulong BaseAddress14;
	125	ulong BaseAddress18;
	126	ulong BaseAddress1C;
	127	ulong BaseAddress20;
	128	ulong BaseAddress24;
	129	ulong CardbusCISPointer;
	130	ushort SubSystemVendorID;
	131	ushort SubSystemID;
	132	ulong ROMBaseAddress;
	133	uchar CapabilitiesPointer;
	134	uchar reserved1;
	135	uchar reserved2;
	136	uchar reserved3;
	137	ulong reserved4;
	138	uchar InterruptLine;
	139	uchar InterruptPin;
	140	uchar MinimumGrant;
	141	uchar MaximumLatency;
	142
	143	/* These are not in the actual config space, but we enumerate them */
	144	ulong BaseAddress10Len;
	145	ulong BaseAddress14Len;
	146	ulong BaseAddress18Len;
	147	ulong BaseAddress1CLen;
	148	ulong BaseAddress20Len;
	149	ulong BaseAddress24Len;
	150	ulong ROMBaseAddressLen;
	151	} PCIType0Info;
	152
	153	/* Structure defining PCI to PCI bridge (type 1) PCI configuration register
	154	* layout. We use this in a union below so we can describe all types of
	155	* PCI configuration spaces with a single structure.
	156	*/
	157
	158	typedef struct {
	159	ulong BaseAddress10;
	160	ulong BaseAddress14;
	161	uchar PrimaryBusNumber;
	162	uchar SecondayBusNumber;
	163	uchar SubordinateBusNumber;
	164	uchar SecondaryLatencyTimer;
	165	uchar IOBase;
	166	uchar IOLimit;
	167	ushort SecondaryStatus;
	168	ushort MemoryBase;
	169	ushort MemoryLimit;
	170	ushort PrefetchableMemoryBase;
	171	ushort PrefetchableMemoryLimit;
	172	ulong PrefetchableBaseHi;
	173	ulong PrefetchableLimitHi;
	174	ushort IOBaseHi;
	175	ushort IOLimitHi;
	176	uchar CapabilitiesPointer;
	177	uchar reserved1;
178	uchar reserved2;
179	uchar reserved3;
180	ulong ROMBaseAddress;
181	uchar InterruptLine;
182	uchar InterruptPin;
183	ushort BridgeControl;
184	} PCIType1Info;
185
186	/* PCI to CardBus bridge (type 2) configuration information */
187	typedef struct {
188	ulong SocketRegistersBaseAddress;
189	uchar CapabilitiesPointer;
190	uchar reserved1;
191	ushort SecondaryStatus;
192	uchar PrimaryBus;
193	uchar SecondaryBus;
194	uchar SubordinateBus;
195	uchar SecondaryLatency;
196	struct {
8bde7f77 WD	197	ulong Base;
	198	ulong Limit;
	199	} Range[4];
c7de829c WD	200	uchar InterruptLine;
	201	uchar InterruptPin;
	202	ushort BridgeControl;
	203	} PCIType2Info;
	204
	205	/* Structure defining the PCI configuration space information for a
	206	* single PCI device on the PCI bus. We enumerate all this information
	207	* for all PCI devices on the bus.
	208	*/
	209
	210	typedef struct {
	211	ulong dwSize;
	212	PCIslot slot;
	213	ulong mech1;
	214	ushort VendorID;
	215	ushort DeviceID;
	216	ushort Command;
	217	ushort Status;
	218	uchar RevID;
	219	uchar Interface;
	220	uchar SubClass;
	221	uchar BaseClass;
	222	uchar CacheLineSize;
	223	uchar LatencyTimer;
	224	uchar HeaderType;
	225	uchar BIST;
	226	union {
8bde7f77 WD	227	PCIType0Info type0;
	228	PCIType1Info type1;
	229	PCIType2Info type2;
	230	} u;
c7de829c WD	231	} PCIDeviceInfo;
	232
	233	/* PCI Capability header structure. All PCI capabilities have the
	234	* following header.
	235	*
	236	* capsID is used to identify the type of the structure as define above.
	237	*
	238	* next is the offset in PCI configuration space (0x40-0xFC) of the
	239	* next capability structure in the list, or 0x00 if there are no more
	240	* entries.
	241	*/
	242
	243	typedef struct {
	244	uchar capsID;
	245	uchar next;
	246	} PCICapsHeader;
	247
	248	/* Structure defining the PCI AGP status register contents */
	249
	250	typedef struct {
	251	uint rate:3;
	252	uint rsvd1:1;
	253	uint fastWrite:1;
	254	uint fourGB:1;
	255	uint rsvd2:3;
	256	uint sideBandAddressing:1;
	257	uint rsvd3:14;
	258	uint requestQueueDepthMaximum:8;
	259	} PCIAGPStatus;
	260
	261	/* Structure defining the PCI AGP command register contents */
	262
	263	typedef struct {
	264	uint rate:3;
	265	uint rsvd1:1;
	266	uint fastWriteEnable:1;
	267	uint fourGBEnable:1;
	268	uint rsvd2:2;
	269	uint AGPEnable:1;
	270	uint SBAEnable:1;
	271	uint rsvd3:14;
	272	uint requestQueueDepth:8;
	273	} PCIAGPCommand;
	274
	275	/* AGP Capability structure */
	276
	277	typedef struct {
	278	PCICapsHeader h;
	279	ushort majMin;
	280	PCIAGPStatus AGPStatus;
	281	PCIAGPCommand AGPCommand;
	282	} PCIAGPCapability;
	283
	284	/* Structure for obtaining the PCI IRQ routing information */
	285
	286	typedef struct {
	287	uchar bus;
	288	uchar device;
	289	uchar linkA;
	290	ushort mapA;
	291	uchar linkB;
	292	ushort mapB;
	293	uchar linkC;
	294	ushort mapC;
295	uchar linkD;
296	ushort mapD;
297	uchar slot;
298	uchar reserved;
299	} PCIRouteInfo;
300
301	typedef struct {
302	ushort BufferSize;
303	PCIRouteInfo *DataBuffer;
304	} PCIRoutingOptionsBuffer;
305
306	#define NUM_PCI_REG (sizeof(PCIDeviceInfo) / 4) - 10
307	#define PCI_BRIDGE_CLASS 0x06
308	#define PCI_HOST_BRIDGE_SUBCLASS 0x00
309	#define PCI_EARLY_VGA_CLASS 0x00
310	#define PCI_EARLY_VGA_SUBCLASS 0x01
311	#define PCI_DISPLAY_CLASS 0x03
312	#define PCI_DISPLAY_VGA_SUBCLASS 0x00
313	#define PCI_DISPLAY_XGA_SUBCLASS 0x01
314	#define PCI_DISPLAY_OTHER_SUBCLASS 0x80
315	#define PCI_MM_CLASS 0x04
316	#define PCI_AUDIO_SUBCLASS 0x01
317
318	/* Macros to detect specific classes of devices */
319
320	#define PCI_IS_3DLABS_NONVGA_CLASS(pci) \
321	(((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_OTHER_SUBCLASS) \
322	&& ((pci)->VendorID == 0x3D3D \|\| (pci)->VendorID == 0x104C))
323
324	#define PCI_IS_DISPLAY_CLASS(pci) \
325	(((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_VGA_SUBCLASS) \
326	\|\| ((pci)->BaseClass == PCI_DISPLAY_CLASS && (pci)->SubClass == PCI_DISPLAY_XGA_SUBCLASS) \
327	\|\| ((pci)->BaseClass == PCI_EARLY_VGA_CLASS && (pci)->SubClass == PCI_EARLY_VGA_SUBCLASS) \
328	\|\| PCI_IS_3DLABS_NONVGA_CLASS(pci))
329
330	/* Function codes to pass to PCI_accessReg */
331
332	#define PCI_READ_BYTE 0
333	#define PCI_READ_WORD 1
334	#define PCI_READ_DWORD 2
335	#define PCI_WRITE_BYTE 3
336	#define PCI_WRITE_WORD 4
337	#define PCI_WRITE_DWORD 5
338
339	/* Macros to read/write PCI registers. These assume a global PCI array
340	* of device information.
341	*/
342
343	#define PCI_readPCIRegB(index,device) \
344	PCI_accessReg(index,0,0,&PCI[DeviceIndex[device]])
345
346	#define PCI_readPCIRegW(index,device) \
347	PCI_accessReg(index,0,1,&PCI[DeviceIndex[device]])
348
349	#define PCI_readPCIRegL(index,device) \
350	PCI_accessReg(index,0,2,&PCI[DeviceIndex[device]])
351
352	#define PCI_writePCIRegB(index,value,device) \
353	PCI_accessReg(index,value,3,&PCI[DeviceIndex[device]])
354
355	#define PCI_writePCIRegW(index,value,device) \
356	PCI_accessReg(index,value,4,&PCI[DeviceIndex[device]])
357
358	#define PCI_writePCIRegL(index,value,device) \
359	PCI_accessReg(index,value,5,&PCI[DeviceIndex[device]])
360
361	#pragma pack()
362
363	/-------------------------- Function Prototypes --------------------------/
364
365	#ifdef __cplusplus
366	extern "C" { /* Use "C" linkage when in C++ mode */
367	#endif
368
369	/* Function to determine the number of PCI devices in the system */
370
371	int _ASMAPI PCI_getNumDevices(void);
372
373	/* Function to enumerate all device on the PCI bus */
374
375	int _ASMAPI PCI_enumerate(PCIDeviceInfo info[]);
376
377	/* Function to access PCI configuration registers */
378
379	ulong _ASMAPI PCI_accessReg(int index,ulong value,int func,PCIDeviceInfo *info);
380
381	/* Function to get PCI IRQ routing options for a card */
382
383	int _ASMAPI PCI_getIRQRoutingOptions(int numDevices,PCIRouteInfo *buffer);
384
385	/* Function to re-route the PCI IRQ setting for a device */
386
387	ibool _ASMAPI PCI_setHardwareIRQ(PCIDeviceInfo *info,uint intPin,uint IRQ);
388
389	/* Function to generate a special cyle on the specified PCI bus */
390
391	void _ASMAPI PCI_generateSpecialCyle(uint bus,ulong specialCycleData);
392
393	/* Function to determine the size of a PCI base address register */
394
395	ulong _ASMAPI PCI_findBARSize(int bar,PCIDeviceInfo *pci);
396
397	/* Function to read a block of PCI configuration space registers */
398
399	void _ASMAPI PCI_readRegBlock(PCIDeviceInfo info,int index,void dst,int count);
400
401	/* Function to write a block of PCI configuration space registers */
402
403	void _ASMAPI PCI_writeRegBlock(PCIDeviceInfo info,int index,void src,int count);
404
405	/* Function to return the 32-bit PCI BIOS entry point */
406
407	ulong _ASMAPI PCIBIOS_getEntry(void);
408
409	#ifdef __cplusplus
410	} /* End of "C" linkage for C++ */
411	#endif
412
413	#endif /* __PCILIB_H */