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c0def248 CP |
1 | /* |
2 | * Copyright (C) 2015 Stefan Roese <sr@denx.de> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #include <common.h> | |
8 | #include <i2c.h> | |
9 | #include <miiphy.h> | |
10 | #include <netdev.h> | |
11 | #include <asm/io.h> | |
12 | #include <asm/arch/cpu.h> | |
13 | #include <asm/arch/soc.h> | |
14 | ||
15 | #include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h" | |
16 | #include <../serdes/a38x/high_speed_env_spec.h> | |
17 | ||
18 | DECLARE_GLOBAL_DATA_PTR; | |
19 | ||
20 | #define ETH_PHY_CTRL_REG 0 | |
21 | #define ETH_PHY_CTRL_POWER_DOWN_BIT 11 | |
22 | #define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT) | |
23 | ||
24 | /* | |
25 | * Those values and defines are taken from the Marvell U-Boot version | |
26 | * "u-boot-2013.01-2016_T1.0.eng_drop_v10" | |
27 | */ | |
28 | #define DB_AMC_88F68XX_GPP_OUT_ENA_LOW \ | |
29 | (~(BIT(29))) | |
30 | #define DB_AMC_88F68XX_GPP_OUT_ENA_MID \ | |
31 | (~(BIT(12) | BIT(17) | BIT(18) | BIT(20) | BIT(21))) | |
32 | #define DB_AMC_88F68XX_GPP_OUT_VAL_LOW (BIT(29)) | |
33 | #define DB_AMC_88F68XX_GPP_OUT_VAL_MID 0x0 | |
34 | #define DB_AMC_88F68XX_GPP_OUT_VAL_HIGH 0x0 | |
35 | #define DB_AMC_88F68XX_GPP_POL_LOW 0x0 | |
36 | #define DB_AMC_88F68XX_GPP_POL_MID 0x0 | |
37 | ||
38 | static struct serdes_map board_serdes_map[] = { | |
39 | {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, | |
40 | {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, | |
41 | {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, | |
42 | {DEFAULT_SERDES, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0}, | |
43 | {SGMII1, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0}, | |
44 | {SGMII2, SERDES_SPEED_1_25_GBPS, SERDES_DEFAULT_MODE, 0, 0} | |
45 | }; | |
46 | ||
47 | int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) | |
48 | { | |
49 | *serdes_map_array = board_serdes_map; | |
50 | *count = ARRAY_SIZE(board_serdes_map); | |
51 | return 0; | |
52 | } | |
53 | ||
54 | /* | |
55 | * Define the DDR layout / topology here in the board file. This will | |
56 | * be used by the DDR3 init code in the SPL U-Boot version to configure | |
57 | * the DDR3 controller. | |
58 | */ | |
59 | static struct hws_topology_map board_topology_map = { | |
60 | 0x1, /* active interfaces */ | |
61 | /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ | |
62 | { { { {0x1, 0, 0, 0}, | |
63 | {0x1, 0, 0, 0}, | |
64 | {0x1, 0, 0, 0}, | |
65 | {0x1, 0, 0, 0}, | |
66 | {0x1, 0, 0, 0} }, | |
67 | SPEED_BIN_DDR_1866L, /* speed_bin */ | |
68 | BUS_WIDTH_8, /* memory_width */ | |
6ab09b05 | 69 | MEM_2G, /* mem_size */ |
c0def248 | 70 | DDR_FREQ_800, /* frequency */ |
01c541e0 | 71 | 0, 0, /* cas_wl cas_l */ |
90bcc3d3 MB |
72 | HWS_TEMP_LOW, /* temperature */ |
73 | HWS_TIM_DEFAULT} }, /* timing */ | |
c0def248 CP |
74 | 5, /* Num Of Bus Per Interface*/ |
75 | BUS_MASK_32BIT /* Busses mask */ | |
76 | }; | |
77 | ||
78 | struct hws_topology_map *ddr3_get_topology_map(void) | |
79 | { | |
80 | /* Return the board topology as defined in the board code */ | |
81 | return &board_topology_map; | |
82 | } | |
83 | ||
84 | int board_early_init_f(void) | |
85 | { | |
86 | /* Configure MPP */ | |
87 | writel(0x11111111, MVEBU_MPP_BASE + 0x00); | |
88 | writel(0x11111111, MVEBU_MPP_BASE + 0x04); | |
89 | writel(0x55066011, MVEBU_MPP_BASE + 0x08); | |
90 | writel(0x05055550, MVEBU_MPP_BASE + 0x0c); | |
91 | writel(0x05055555, MVEBU_MPP_BASE + 0x10); | |
92 | writel(0x01106565, MVEBU_MPP_BASE + 0x14); | |
93 | writel(0x40000000, MVEBU_MPP_BASE + 0x18); | |
94 | writel(0x00004444, MVEBU_MPP_BASE + 0x1c); | |
95 | ||
96 | /* Set GPP Out value */ | |
97 | writel(DB_AMC_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); | |
98 | writel(DB_AMC_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); | |
99 | ||
100 | /* Set GPP Polarity */ | |
101 | writel(DB_AMC_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); | |
102 | writel(DB_AMC_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); | |
103 | ||
104 | /* Set GPP Out Enable */ | |
105 | writel(DB_AMC_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); | |
106 | writel(DB_AMC_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); | |
107 | ||
108 | return 0; | |
109 | } | |
110 | ||
111 | int board_init(void) | |
112 | { | |
113 | /* adress of boot parameters */ | |
114 | gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; | |
115 | ||
116 | return 0; | |
117 | } | |
118 | ||
119 | int checkboard(void) | |
120 | { | |
121 | puts("Board: Marvell DB-88F6820-AMC\n"); | |
122 | ||
123 | return 0; | |
124 | } | |
125 | ||
126 | int board_eth_init(bd_t *bis) | |
127 | { | |
128 | cpu_eth_init(bis); /* Built in controller(s) come first */ | |
129 | return pci_eth_init(bis); | |
130 | } |