[people/ms/u-boot.git] / board / Marvell / db-88f6820-gp / db-88f6820-gp.c

/*
 * Copyright (C) 2015 Stefan Roese <sr@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <i2c.h>
#include <miiphy.h>
#include <netdev.h>
#include <asm/io.h>
#include <asm/arch/cpu.h>
#include <asm/arch/soc.h>

#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"

DECLARE_GLOBAL_DATA_PTR;

#define ETH_PHY_CTRL_REG		0
#define ETH_PHY_CTRL_POWER_DOWN_BIT	11
#define ETH_PHY_CTRL_POWER_DOWN_MASK	(1 << ETH_PHY_CTRL_POWER_DOWN_BIT)

/*
 * Those values and defines are taken from the Marvell U-Boot version
 * "u-boot-2013.01-2014_T3.0"
 */
#define DB_GP_88F68XX_GPP_OUT_ENA_LOW					\
	(~(BIT(1)  | BIT(4)  | BIT(6)  | BIT(7)  | BIT(8)  | BIT(9)  |	\
	   BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) |	\
	   BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31)))
#define DB_GP_88F68XX_GPP_OUT_ENA_MID					\
	(~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) |	\
	   BIT(16) | BIT(17) | BIT(18)))

#define DB_GP_88F68XX_GPP_OUT_VAL_LOW	0x0
#define DB_GP_88F68XX_GPP_OUT_VAL_MID	0x0
#define DB_GP_88F68XX_GPP_POL_LOW	0x0
#define DB_GP_88F68XX_GPP_POL_MID	0x0

/* IO expander on Marvell GP board includes e.g. fan enabling */
struct marvell_io_exp {
	u8 chip;
	u8 addr;
	u8 val;
};

static struct marvell_io_exp io_exp[] = {
	{ 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
	{ 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
	{ 0x20, 2, 0x1D }, /* Output Data, register#0 */
	{ 0x20, 3, 0x18 }, /* Output Data, register#1 */
	{ 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits  */
	{ 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits  */
	{ 0x21, 2, 0x08 }, /* Output Data, register#0 */
	{ 0x21, 3, 0xC0 }  /* Output Data, register#1 */
};

/*
 * Define the DDR layout / topology here in the board file. This will
 * be used by the DDR3 init code in the SPL U-Boot version to configure
 * the DDR3 controller.
 */
static struct hws_topology_map board_topology_map = {
	0x1, /* active interfaces */
	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
	{ { { {0x1, 0, 0, 0},
	      {0x1, 0, 0, 0},
	      {0x1, 0, 0, 0},
	      {0x1, 0, 0, 0},
	      {0x1, 0, 0, 0} },
	    SPEED_BIN_DDR_1866L,	/* speed_bin */
	    BUS_WIDTH_8,		/* memory_width */
	    MEM_4G,			/* mem_size */
	    DDR_FREQ_800,		/* frequency */
	    0, 0,			/* cas_l cas_wl */
	    HWS_TEMP_LOW} },		/* temperature */
	5,				/* Num Of Bus Per Interface*/
	BUS_MASK_32BIT			/* Busses mask */
};

struct hws_topology_map *ddr3_get_topology_map(void)
{
	/* Return the board topology as defined in the board code */
	return &board_topology_map;
}

int board_early_init_f(void)
{
	/* Configure MPP */
	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
	writel(0x11244011, MVEBU_MPP_BASE + 0x08);
	writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
	writel(0x22200002, MVEBU_MPP_BASE + 0x10);
	writel(0x30042022, MVEBU_MPP_BASE + 0x14);
	writel(0x55550555, MVEBU_MPP_BASE + 0x18);
	writel(0x00005550, MVEBU_MPP_BASE + 0x1c);

	/* Set GPP Out value */
	writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
	writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);

	/* Set GPP Polarity */
	writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
	writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);

	/* Set GPP Out Enable */
	writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
	writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);

	return 0;
}

int board_init(void)
{
	int i;

	/* adress of boot parameters */
	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;

	/* Init I2C IO expanders */
	for (i = 0; i < ARRAY_SIZE(io_exp); i++)
		i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);

	return 0;
}

int checkboard(void)
{
	puts("Board: Marvell DB-88F6820-GP\n");

	return 0;
}

int board_eth_init(bd_t *bis)
{
	cpu_eth_init(bis); /* Built in controller(s) come first */
	return pci_eth_init(bis);
}
Commit	Line	Data
2bae75a4 SR	1	/*
	2	* Copyright (C) 2015 Stefan Roese <sr@denx.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6
	7	#include <common.h>
	8	#include <i2c.h>
	9	#include <miiphy.h>
ce2cb1d3	10	#include <netdev.h>
2bae75a4 SR	11	#include <asm/io.h>
	12	#include <asm/arch/cpu.h>
	13	#include <asm/arch/soc.h>
	14
9e30b31d SR	15	#include "../drivers/ddr/marvell/a38x/ddr3_a38x_topology.h"
9e30b31d SR	16
2bae75a4 SR	17	DECLARE_GLOBAL_DATA_PTR;
2bae75a4 SR	18
2bae75a4 SR	19	#define ETH_PHY_CTRL_REG 0
	20	#define ETH_PHY_CTRL_POWER_DOWN_BIT 11
	21	#define ETH_PHY_CTRL_POWER_DOWN_MASK (1 << ETH_PHY_CTRL_POWER_DOWN_BIT)
	22
	23	/*
	24	* Those values and defines are taken from the Marvell U-Boot version
	25	* "u-boot-2013.01-2014_T3.0"
	26	*/
	27	#define DB_GP_88F68XX_GPP_OUT_ENA_LOW \
	28	(~(BIT(1) \| BIT(4) \| BIT(6) \| BIT(7) \| BIT(8) \| BIT(9) \| \
	29	BIT(10) \| BIT(11) \| BIT(19) \| BIT(22) \| BIT(23) \| BIT(25) \| \
	30	BIT(26) \| BIT(27) \| BIT(29) \| BIT(30) \| BIT(31)))
	31	#define DB_GP_88F68XX_GPP_OUT_ENA_MID \
	32	(~(BIT(0) \| BIT(1) \| BIT(2) \| BIT(3) \| BIT(4) \| BIT(15) \| \
	33	BIT(16) \| BIT(17) \| BIT(18)))
	34
	35	#define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0
	36	#define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0
	37	#define DB_GP_88F68XX_GPP_POL_LOW 0x0
	38	#define DB_GP_88F68XX_GPP_POL_MID 0x0
	39
	40	/* IO expander on Marvell GP board includes e.g. fan enabling */
	41	struct marvell_io_exp {
	42	u8 chip;
	43	u8 addr;
	44	u8 val;
	45	};
	46
	47	static struct marvell_io_exp io_exp[] = {
	48	{ 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */
	49	{ 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
	50	{ 0x20, 2, 0x1D }, /* Output Data, register#0 */
	51	{ 0x20, 3, 0x18 }, /* Output Data, register#1 */
	52	{ 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */
	53	{ 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */
	54	{ 0x21, 2, 0x08 }, /* Output Data, register#0 */
	55	{ 0x21, 3, 0xC0 } /* Output Data, register#1 */
	56	};
	57
9e30b31d SR	58	/*
	59	* Define the DDR layout / topology here in the board file. This will
	60	* be used by the DDR3 init code in the SPL U-Boot version to configure
	61	* the DDR3 controller.
	62	*/
	63	static struct hws_topology_map board_topology_map = {
	64	0x1, /* active interfaces */
	65	/* cs_mask, mirror, dqs_swap, ck_swap X PUPs */
	66	{ { { {0x1, 0, 0, 0},
	67	{0x1, 0, 0, 0},
	68	{0x1, 0, 0, 0},
	69	{0x1, 0, 0, 0},
	70	{0x1, 0, 0, 0} },
	71	SPEED_BIN_DDR_1866L, /* speed_bin */
	72	BUS_WIDTH_8, /* memory_width */
	73	MEM_4G, /* mem_size */
	74	DDR_FREQ_800, /* frequency */
	75	0, 0, /* cas_l cas_wl */
	76	HWS_TEMP_LOW} }, /* temperature */
	77	5, /* Num Of Bus Per Interface*/
	78	BUS_MASK_32BIT /* Busses mask */
	79	};
	80
	81	struct hws_topology_map *ddr3_get_topology_map(void)
	82	{
	83	/* Return the board topology as defined in the board code */
	84	return &board_topology_map;
	85	}
	86
2bae75a4 SR	87	int board_early_init_f(void)
	88	{
	89	/* Configure MPP */
	90	writel(0x11111111, MVEBU_MPP_BASE + 0x00);
	91	writel(0x11111111, MVEBU_MPP_BASE + 0x04);
	92	writel(0x11244011, MVEBU_MPP_BASE + 0x08);
	93	writel(0x22222111, MVEBU_MPP_BASE + 0x0c);
	94	writel(0x22200002, MVEBU_MPP_BASE + 0x10);
	95	writel(0x30042022, MVEBU_MPP_BASE + 0x14);
	96	writel(0x55550555, MVEBU_MPP_BASE + 0x18);
	97	writel(0x00005550, MVEBU_MPP_BASE + 0x1c);
	98
	99	/* Set GPP Out value */
	100	writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00);
	101	writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00);
	102
	103	/* Set GPP Polarity */
	104	writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c);
	105	writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c);
	106
	107	/* Set GPP Out Enable */
	108	writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04);
	109	writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04);
	110
	111	return 0;
	112	}
	113
	114	int board_init(void)
	115	{
	116	int i;
	117
	118	/* adress of boot parameters */
	119	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
	120
	121	/* Init I2C IO expanders */
	122	for (i = 0; i < ARRAY_SIZE(io_exp); i++)
	123	i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1);
	124
	125	return 0;
	126	}
	127
	128	int checkboard(void)
	129	{
	130	puts("Board: Marvell DB-88F6820-GP\n");
	131
	132	return 0;
	133	}
ce2cb1d3 SR	134
	135	int board_eth_init(bd_t *bis)
	136	{
	137	cpu_eth_init(bis); /* Built in controller(s) come first */
	138	return pci_eth_init(bis);
	139	}