]>
Commit | Line | Data |
---|---|---|
83d290c5 | 1 | // SPDX-License-Identifier: GPL-2.0+ |
2bae75a4 SR |
2 | /* |
3 | * Copyright (C) 2015 Stefan Roese <sr@denx.de> | |
2bae75a4 SR |
4 | */ |
5 | ||
d678a59d | 6 | #include <common.h> |
2bae75a4 | 7 | #include <i2c.h> |
691d719d | 8 | #include <init.h> |
2bae75a4 | 9 | #include <miiphy.h> |
90526e9f | 10 | #include <net.h> |
ce2cb1d3 | 11 | #include <netdev.h> |
401d1c4f | 12 | #include <asm/global_data.h> |
2bae75a4 SR |
13 | #include <asm/io.h> |
14 | #include <asm/arch/cpu.h> | |
15 | #include <asm/arch/soc.h> | |
cd93d625 | 16 | #include <linux/bitops.h> |
2bae75a4 | 17 | |
2b4ffbf6 | 18 | #include "../drivers/ddr/marvell/a38x/ddr3_init.h" |
544acb07 | 19 | #include <../serdes/a38x/high_speed_env_spec.h> |
9e30b31d | 20 | |
2bae75a4 SR |
21 | DECLARE_GLOBAL_DATA_PTR; |
22 | ||
2bae75a4 SR |
23 | /* |
24 | * Those values and defines are taken from the Marvell U-Boot version | |
25 | * "u-boot-2013.01-2014_T3.0" | |
26 | */ | |
27 | #define DB_GP_88F68XX_GPP_OUT_ENA_LOW \ | |
28 | (~(BIT(1) | BIT(4) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | \ | |
29 | BIT(10) | BIT(11) | BIT(19) | BIT(22) | BIT(23) | BIT(25) | \ | |
30 | BIT(26) | BIT(27) | BIT(29) | BIT(30) | BIT(31))) | |
31 | #define DB_GP_88F68XX_GPP_OUT_ENA_MID \ | |
32 | (~(BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) | BIT(15) | \ | |
33 | BIT(16) | BIT(17) | BIT(18))) | |
34 | ||
35 | #define DB_GP_88F68XX_GPP_OUT_VAL_LOW 0x0 | |
36 | #define DB_GP_88F68XX_GPP_OUT_VAL_MID 0x0 | |
37 | #define DB_GP_88F68XX_GPP_POL_LOW 0x0 | |
38 | #define DB_GP_88F68XX_GPP_POL_MID 0x0 | |
39 | ||
40 | /* IO expander on Marvell GP board includes e.g. fan enabling */ | |
41 | struct marvell_io_exp { | |
42 | u8 chip; | |
43 | u8 addr; | |
44 | u8 val; | |
45 | }; | |
46 | ||
47 | static struct marvell_io_exp io_exp[] = { | |
48 | { 0x20, 6, 0x20 }, /* Configuration registers: Bit on --> Input bits */ | |
49 | { 0x20, 7, 0xC3 }, /* Configuration registers: Bit on --> Input bits */ | |
50 | { 0x20, 2, 0x1D }, /* Output Data, register#0 */ | |
51 | { 0x20, 3, 0x18 }, /* Output Data, register#1 */ | |
52 | { 0x21, 6, 0xC3 }, /* Configuration registers: Bit on --> Input bits */ | |
53 | { 0x21, 7, 0x31 }, /* Configuration registers: Bit on --> Input bits */ | |
54 | { 0x21, 2, 0x08 }, /* Output Data, register#0 */ | |
55 | { 0x21, 3, 0xC0 } /* Output Data, register#1 */ | |
56 | }; | |
57 | ||
544acb07 KS |
58 | static struct serdes_map board_serdes_map[] = { |
59 | {PEX0, SERDES_SPEED_5_GBPS, PEX_ROOT_COMPLEX_X1, 0, 0}, | |
60 | {SATA0, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, | |
61 | {SATA1, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, | |
62 | {SATA3, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, | |
63 | {SATA2, SERDES_SPEED_3_GBPS, SERDES_DEFAULT_MODE, 0, 0}, | |
64 | {USB3_HOST1, SERDES_SPEED_5_GBPS, SERDES_DEFAULT_MODE, 0, 0} | |
65 | }; | |
66 | ||
490753ac | 67 | int hws_board_topology_load(struct serdes_map **serdes_map_array, u8 *count) |
544acb07 | 68 | { |
490753ac KS |
69 | *serdes_map_array = board_serdes_map; |
70 | *count = ARRAY_SIZE(board_serdes_map); | |
544acb07 KS |
71 | return 0; |
72 | } | |
73 | ||
9e30b31d SR |
74 | /* |
75 | * Define the DDR layout / topology here in the board file. This will | |
76 | * be used by the DDR3 init code in the SPL U-Boot version to configure | |
77 | * the DDR3 controller. | |
78 | */ | |
2b4ffbf6 CP |
79 | static struct mv_ddr_topology_map board_topology_map = { |
80 | DEBUG_LEVEL_ERROR, | |
9e30b31d SR |
81 | 0x1, /* active interfaces */ |
82 | /* cs_mask, mirror, dqs_swap, ck_swap X PUPs */ | |
83 | { { { {0x1, 0, 0, 0}, | |
84 | {0x1, 0, 0, 0}, | |
85 | {0x1, 0, 0, 0}, | |
86 | {0x1, 0, 0, 0}, | |
87 | {0x1, 0, 0, 0} }, | |
88 | SPEED_BIN_DDR_1866L, /* speed_bin */ | |
2b4ffbf6 CP |
89 | MV_DDR_DEV_WIDTH_8BIT, /* memory_width */ |
90 | MV_DDR_DIE_CAP_4GBIT, /* mem_size */ | |
ebb1a593 | 91 | MV_DDR_FREQ_800, /* frequency */ |
01c541e0 | 92 | 0, 0, /* cas_wl cas_l */ |
e6f61622 CP |
93 | MV_DDR_TEMP_LOW, /* temperature */ |
94 | MV_DDR_TIM_DEFAULT} }, /* timing */ | |
2b4ffbf6 CP |
95 | BUS_MASK_32BIT, /* Busses mask */ |
96 | MV_DDR_CFG_DEFAULT, /* ddr configuration data source */ | |
32e7a6ba | 97 | NOT_COMBINED, /* ddr twin-die combined */ |
2b4ffbf6 CP |
98 | { {0} }, /* raw spd data */ |
99 | {0} /* timing parameters */ | |
9e30b31d SR |
100 | }; |
101 | ||
2b4ffbf6 | 102 | struct mv_ddr_topology_map *mv_ddr_topology_map_get(void) |
9e30b31d SR |
103 | { |
104 | /* Return the board topology as defined in the board code */ | |
105 | return &board_topology_map; | |
106 | } | |
107 | ||
2bae75a4 SR |
108 | int board_early_init_f(void) |
109 | { | |
110 | /* Configure MPP */ | |
111 | writel(0x11111111, MVEBU_MPP_BASE + 0x00); | |
112 | writel(0x11111111, MVEBU_MPP_BASE + 0x04); | |
113 | writel(0x11244011, MVEBU_MPP_BASE + 0x08); | |
114 | writel(0x22222111, MVEBU_MPP_BASE + 0x0c); | |
115 | writel(0x22200002, MVEBU_MPP_BASE + 0x10); | |
116 | writel(0x30042022, MVEBU_MPP_BASE + 0x14); | |
117 | writel(0x55550555, MVEBU_MPP_BASE + 0x18); | |
118 | writel(0x00005550, MVEBU_MPP_BASE + 0x1c); | |
119 | ||
120 | /* Set GPP Out value */ | |
121 | writel(DB_GP_88F68XX_GPP_OUT_VAL_LOW, MVEBU_GPIO0_BASE + 0x00); | |
122 | writel(DB_GP_88F68XX_GPP_OUT_VAL_MID, MVEBU_GPIO1_BASE + 0x00); | |
123 | ||
124 | /* Set GPP Polarity */ | |
125 | writel(DB_GP_88F68XX_GPP_POL_LOW, MVEBU_GPIO0_BASE + 0x0c); | |
126 | writel(DB_GP_88F68XX_GPP_POL_MID, MVEBU_GPIO1_BASE + 0x0c); | |
127 | ||
128 | /* Set GPP Out Enable */ | |
129 | writel(DB_GP_88F68XX_GPP_OUT_ENA_LOW, MVEBU_GPIO0_BASE + 0x04); | |
130 | writel(DB_GP_88F68XX_GPP_OUT_ENA_MID, MVEBU_GPIO1_BASE + 0x04); | |
131 | ||
132 | return 0; | |
133 | } | |
134 | ||
135 | int board_init(void) | |
136 | { | |
137 | int i; | |
138 | ||
139 | /* adress of boot parameters */ | |
140 | gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100; | |
141 | ||
142 | /* Init I2C IO expanders */ | |
143 | for (i = 0; i < ARRAY_SIZE(io_exp); i++) | |
144 | i2c_write(io_exp[i].chip, io_exp[i].addr, 1, &io_exp[i].val, 1); | |
145 | ||
146 | return 0; | |
147 | } | |
148 | ||
149 | int checkboard(void) | |
150 | { | |
151 | puts("Board: Marvell DB-88F6820-GP\n"); | |
152 | ||
153 | return 0; | |
154 | } | |
ce2cb1d3 | 155 | |
b75d8dc5 | 156 | int board_eth_init(struct bd_info *bis) |
ce2cb1d3 SR |
157 | { |
158 | cpu_eth_init(bis); /* Built in controller(s) come first */ | |
159 | return pci_eth_init(bis); | |
160 | } |