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3a473b2a WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Ingo Assmus <ingo.assmus@keymile.com> | |
4 | * | |
5 | * based on - Driver for MV64360X ethernet ports | |
6 | * Copyright (C) 2002 rabeeh@galileo.co.il | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | /* | |
28 | * mv_eth.c - header file for the polled mode GT ethernet driver | |
29 | */ | |
30 | #include <common.h> | |
31 | #include <net.h> | |
32 | #include <malloc.h> | |
33 | ||
34 | #include "mv_eth.h" | |
35 | ||
36 | /* enable Debug outputs */ | |
37 | ||
38 | #undef DEBUG_MV_ETH | |
39 | ||
40 | #ifdef DEBUG_MV_ETH | |
41 | #define DEBUG | |
42 | #define DP(x) x | |
43 | #else | |
44 | #define DP(x) | |
45 | #endif | |
46 | ||
47 | #undef MV64360_CHECKSUM_OFFLOAD | |
48 | /************************************************************************* | |
49 | ************************************************************************** | |
50 | ************************************************************************** | |
51 | * The first part is the high level driver of the gigE ethernet ports. * | |
52 | ************************************************************************** | |
53 | ************************************************************************** | |
54 | *************************************************************************/ | |
55 | ||
56 | /* Definition for configuring driver */ | |
57 | /* #define UPDATE_STATS_BY_SOFTWARE */ | |
58 | #undef MV64360_RX_QUEUE_FILL_ON_TASK | |
59 | ||
60 | ||
61 | /* Constants */ | |
62 | #define MAGIC_ETH_RUNNING 8031971 | |
63 | #define MV64360_INTERNAL_SRAM_SIZE _256K | |
64 | #define EXTRA_BYTES 32 | |
65 | #define WRAP ETH_HLEN + 2 + 4 + 16 | |
66 | #define BUFFER_MTU dev->mtu + WRAP | |
67 | #define INT_CAUSE_UNMASK_ALL 0x0007ffff | |
68 | #define INT_CAUSE_UNMASK_ALL_EXT 0x0011ffff | |
69 | #ifdef MV64360_RX_FILL_ON_TASK | |
70 | #define INT_CAUSE_MASK_ALL 0x00000000 | |
71 | #define INT_CAUSE_CHECK_BITS INT_CAUSE_UNMASK_ALL | |
72 | #define INT_CAUSE_CHECK_BITS_EXT INT_CAUSE_UNMASK_ALL_EXT | |
73 | #endif | |
74 | ||
75 | /* Read/Write to/from MV64360 internal registers */ | |
76 | #define MV_REG_READ(offset) my_le32_to_cpu(* (volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset)) | |
77 | #define MV_REG_WRITE(offset,data) *(volatile unsigned int *) (INTERNAL_REG_BASE_ADDR + offset) = my_cpu_to_le32 (data) | |
78 | #define MV_SET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) |= ((unsigned int)my_cpu_to_le32(bits))) | |
79 | #define MV_RESET_REG_BITS(regOffset,bits) ((*((volatile unsigned int*)((INTERNAL_REG_BASE_ADDR) + (regOffset)))) &= ~((unsigned int)my_cpu_to_le32(bits))) | |
80 | ||
81 | /* Static function declarations */ | |
82 | static int mv64360_eth_real_open (struct eth_device *eth); | |
83 | static int mv64360_eth_real_stop (struct eth_device *eth); | |
84 | static struct net_device_stats *mv64360_eth_get_stats (struct eth_device | |
85 | *dev); | |
86 | static void eth_port_init_mac_tables (ETH_PORT eth_port_num); | |
87 | static void mv64360_eth_update_stat (struct eth_device *dev); | |
88 | bool db64360_eth_start (struct eth_device *eth); | |
89 | unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, | |
90 | unsigned int mib_offset); | |
91 | int mv64360_eth_receive (struct eth_device *dev); | |
92 | ||
93 | int mv64360_eth_xmit (struct eth_device *, volatile void *packet, int length); | |
94 | ||
95 | #ifndef UPDATE_STATS_BY_SOFTWARE | |
96 | static void mv64360_eth_print_stat (struct eth_device *dev); | |
97 | #endif | |
98 | /* Processes a received packet */ | |
99 | extern void NetReceive (volatile uchar *, int); | |
100 | ||
101 | extern unsigned int INTERNAL_REG_BASE_ADDR; | |
102 | ||
103 | /************************************************* | |
104 | *Helper functions - used inside the driver only * | |
105 | *************************************************/ | |
106 | #ifdef DEBUG_MV_ETH | |
107 | void print_globals (struct eth_device *dev) | |
108 | { | |
109 | printf ("Ethernet PRINT_Globals-Debug function\n"); | |
110 | printf ("Base Address for ETH_PORT_INFO: %08x\n", | |
111 | (unsigned int) dev->priv); | |
112 | printf ("Base Address for mv64360_eth_priv: %08x\n", | |
113 | (unsigned int) &(((ETH_PORT_INFO *) dev->priv)-> | |
114 | port_private)); | |
115 | ||
116 | printf ("GT Internal Base Address: %08x\n", | |
117 | INTERNAL_REG_BASE_ADDR); | |
118 | printf ("Base Address for TX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_tx_desc_area_base[0], MV64360_TX_QUEUE_SIZE); | |
119 | printf ("Base Address for RX-DESCs: %08x Number of allocated Buffers %d\n", (unsigned int) ((ETH_PORT_INFO *) dev->priv)->p_rx_desc_area_base[0], MV64360_RX_QUEUE_SIZE); | |
120 | printf ("Base Address for RX-Buffer: %08x allocated Bytes %d\n", | |
121 | (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> | |
122 | p_rx_buffer_base[0], | |
123 | (MV64360_RX_QUEUE_SIZE * MV64360_RX_BUFFER_SIZE) + 32); | |
124 | printf ("Base Address for TX-Buffer: %08x allocated Bytes %d\n", | |
125 | (unsigned int) ((ETH_PORT_INFO *) dev->priv)-> | |
126 | p_tx_buffer_base[0], | |
127 | (MV64360_TX_QUEUE_SIZE * MV64360_TX_BUFFER_SIZE) + 32); | |
128 | } | |
129 | #endif | |
130 | ||
131 | #define my_cpu_to_le32(x) my_le32_to_cpu((x)) | |
132 | ||
133 | unsigned long my_le32_to_cpu (unsigned long x) | |
134 | { | |
135 | return (((x & 0x000000ffU) << 24) | | |
136 | ((x & 0x0000ff00U) << 8) | | |
137 | ((x & 0x00ff0000U) >> 8) | ((x & 0xff000000U) >> 24)); | |
138 | } | |
139 | ||
140 | ||
141 | /********************************************************************** | |
142 | * mv64360_eth_print_phy_status | |
143 | * | |
144 | * Prints gigabit ethenret phy status | |
145 | * | |
146 | * Input : pointer to ethernet interface network device structure | |
147 | * Output : N/A | |
148 | **********************************************************************/ | |
149 | ||
150 | static void mv64360_eth_print_phy_status (struct eth_device *dev) | |
151 | { | |
152 | struct mv64360_eth_priv *port_private; | |
153 | unsigned int port_num; | |
154 | ETH_PORT_INFO *ethernet_private = (ETH_PORT_INFO *) dev->priv; | |
155 | unsigned int port_status, phy_reg_data; | |
156 | ||
157 | port_private = | |
158 | (struct mv64360_eth_priv *) ethernet_private->port_private; | |
159 | port_num = port_private->port_num; | |
160 | ||
161 | /* Check Link status on phy */ | |
162 | eth_port_read_smi_reg (port_num, 1, &phy_reg_data); | |
163 | if (!(phy_reg_data & 0x20)) { | |
164 | printf ("Ethernet port changed link status to DOWN\n"); | |
165 | } else { | |
166 | port_status = | |
167 | MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); | |
168 | printf ("Ethernet status port %d: Link up", port_num); | |
169 | printf (", %s", | |
170 | (port_status & BIT2) ? "Full Duplex" : "Half Duplex"); | |
171 | if (port_status & BIT4) | |
172 | printf (", Speed 1 Gbps"); | |
173 | else | |
174 | printf (", %s", | |
175 | (port_status & BIT5) ? "Speed 100 Mbps" : | |
176 | "Speed 10 Mbps"); | |
177 | printf ("\n"); | |
178 | } | |
179 | } | |
180 | ||
181 | /********************************************************************** | |
182 | * u-boot entry functions for mv64360_eth | |
183 | * | |
184 | **********************************************************************/ | |
185 | int db64360_eth_probe (struct eth_device *dev) | |
186 | { | |
187 | return ((int) db64360_eth_start (dev)); | |
188 | } | |
189 | ||
190 | int db64360_eth_poll (struct eth_device *dev) | |
191 | { | |
192 | return mv64360_eth_receive (dev); | |
193 | } | |
194 | ||
195 | int db64360_eth_transmit (struct eth_device *dev, volatile void *packet, | |
196 | int length) | |
197 | { | |
198 | mv64360_eth_xmit (dev, packet, length); | |
199 | return 0; | |
200 | } | |
201 | ||
202 | void db64360_eth_disable (struct eth_device *dev) | |
203 | { | |
204 | mv64360_eth_stop (dev); | |
205 | } | |
206 | ||
207 | ||
208 | void mv6436x_eth_initialize (bd_t * bis) | |
209 | { | |
210 | struct eth_device *dev; | |
211 | ETH_PORT_INFO *ethernet_private; | |
212 | struct mv64360_eth_priv *port_private; | |
213 | int devnum, x, temp; | |
214 | char *s, *e, buf[64]; | |
215 | ||
216 | for (devnum = 0; devnum < MV_ETH_DEVS; devnum++) { | |
217 | dev = calloc (sizeof (*dev), 1); | |
218 | if (!dev) { | |
219 | printf ("%s: mv_enet%d allocation failure, %s\n", | |
220 | __FUNCTION__, devnum, "eth_device structure"); | |
221 | return; | |
222 | } | |
223 | ||
224 | /* must be less than NAMESIZE (16) */ | |
225 | sprintf (dev->name, "mv_enet%d", devnum); | |
226 | ||
227 | #ifdef DEBUG | |
228 | printf ("Initializing %s\n", dev->name); | |
229 | #endif | |
230 | ||
231 | /* Extract the MAC address from the environment */ | |
232 | switch (devnum) { | |
233 | case 0: | |
234 | s = "ethaddr"; | |
235 | break; | |
236 | ||
237 | case 1: | |
238 | s = "eth1addr"; | |
239 | break; | |
240 | ||
241 | case 2: | |
242 | s = "eth2addr"; | |
243 | break; | |
244 | ||
245 | default: /* this should never happen */ | |
246 | printf ("%s: Invalid device number %d\n", | |
247 | __FUNCTION__, devnum); | |
248 | return; | |
249 | } | |
250 | ||
251 | temp = getenv_r (s, buf, sizeof (buf)); | |
252 | s = (temp > 0) ? buf : NULL; | |
253 | ||
254 | #ifdef DEBUG | |
255 | printf ("Setting MAC %d to %s\n", devnum, s); | |
256 | #endif | |
257 | for (x = 0; x < 6; ++x) { | |
258 | dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; | |
259 | if (s) | |
260 | s = (*e) ? e + 1 : e; | |
261 | } | |
262 | /* ronen - set the MAC addr in the HW */ | |
263 | eth_port_uc_addr_set (devnum, dev->enetaddr, 0); | |
264 | ||
265 | dev->init = (void *) db64360_eth_probe; | |
266 | dev->halt = (void *) ethernet_phy_reset; | |
267 | dev->send = (void *) db64360_eth_transmit; | |
268 | dev->recv = (void *) db64360_eth_poll; | |
269 | ||
77ddac94 WD |
270 | ethernet_private = calloc (sizeof (*ethernet_private), 1); |
271 | dev->priv = (void *) ethernet_private; | |
272 | ||
3a473b2a WD |
273 | if (!ethernet_private) { |
274 | printf ("%s: %s allocation failure, %s\n", | |
275 | __FUNCTION__, dev->name, | |
276 | "Private Device Structure"); | |
277 | free (dev); | |
278 | return; | |
279 | } | |
280 | /* start with an zeroed ETH_PORT_INFO */ | |
281 | memset (ethernet_private, 0, sizeof (ETH_PORT_INFO)); | |
282 | memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); | |
283 | ||
284 | /* set pointer to memory for stats data structure etc... */ | |
77ddac94 | 285 | port_private = calloc (sizeof (*ethernet_private), 1); |
f013dacf | 286 | ethernet_private->port_private = (void *)port_private; |
3a473b2a WD |
287 | if (!port_private) { |
288 | printf ("%s: %s allocation failure, %s\n", | |
289 | __FUNCTION__, dev->name, | |
290 | "Port Private Device Structure"); | |
291 | ||
292 | free (ethernet_private); | |
293 | free (dev); | |
294 | return; | |
295 | } | |
296 | ||
297 | port_private->stats = | |
298 | calloc (sizeof (struct net_device_stats), 1); | |
299 | if (!port_private->stats) { | |
300 | printf ("%s: %s allocation failure, %s\n", | |
301 | __FUNCTION__, dev->name, | |
302 | "Net stat Structure"); | |
303 | ||
304 | free (port_private); | |
305 | free (ethernet_private); | |
306 | free (dev); | |
307 | return; | |
308 | } | |
309 | memset (ethernet_private->port_private, 0, | |
310 | sizeof (struct mv64360_eth_priv)); | |
311 | switch (devnum) { | |
312 | case 0: | |
313 | ethernet_private->port_num = ETH_0; | |
314 | break; | |
315 | case 1: | |
316 | ethernet_private->port_num = ETH_1; | |
317 | break; | |
318 | case 2: | |
319 | ethernet_private->port_num = ETH_2; | |
320 | break; | |
321 | default: | |
322 | printf ("Invalid device number %d\n", devnum); | |
323 | break; | |
324 | }; | |
325 | ||
326 | port_private->port_num = devnum; | |
327 | /* | |
328 | * Read MIB counter on the GT in order to reset them, | |
329 | * then zero all the stats fields in memory | |
330 | */ | |
331 | mv64360_eth_update_stat (dev); | |
332 | memset (port_private->stats, 0, | |
333 | sizeof (struct net_device_stats)); | |
334 | /* Extract the MAC address from the environment */ | |
335 | switch (devnum) { | |
336 | case 0: | |
337 | s = "ethaddr"; | |
338 | break; | |
339 | ||
340 | case 1: | |
341 | s = "eth1addr"; | |
342 | break; | |
343 | ||
344 | case 2: | |
345 | s = "eth2addr"; | |
346 | break; | |
347 | ||
348 | default: /* this should never happen */ | |
349 | printf ("%s: Invalid device number %d\n", | |
350 | __FUNCTION__, devnum); | |
351 | return; | |
352 | } | |
353 | ||
354 | temp = getenv_r (s, buf, sizeof (buf)); | |
355 | s = (temp > 0) ? buf : NULL; | |
356 | ||
357 | #ifdef DEBUG | |
358 | printf ("Setting MAC %d to %s\n", devnum, s); | |
359 | #endif | |
360 | for (x = 0; x < 6; ++x) { | |
361 | dev->enetaddr[x] = s ? simple_strtoul (s, &e, 16) : 0; | |
362 | if (s) | |
363 | s = (*e) ? e + 1 : e; | |
364 | } | |
365 | ||
366 | DP (printf ("Allocating descriptor and buffer rings\n")); | |
367 | ||
368 | ethernet_private->p_rx_desc_area_base[0] = | |
369 | (ETH_RX_DESC *) memalign (16, | |
370 | RX_DESC_ALIGNED_SIZE * | |
371 | MV64360_RX_QUEUE_SIZE + 1); | |
372 | ethernet_private->p_tx_desc_area_base[0] = | |
373 | (ETH_TX_DESC *) memalign (16, | |
374 | TX_DESC_ALIGNED_SIZE * | |
375 | MV64360_TX_QUEUE_SIZE + 1); | |
376 | ||
377 | ethernet_private->p_rx_buffer_base[0] = | |
378 | (char *) memalign (16, | |
379 | MV64360_RX_QUEUE_SIZE * | |
380 | MV64360_TX_BUFFER_SIZE + 1); | |
381 | ethernet_private->p_tx_buffer_base[0] = | |
382 | (char *) memalign (16, | |
383 | MV64360_RX_QUEUE_SIZE * | |
384 | MV64360_TX_BUFFER_SIZE + 1); | |
385 | ||
386 | #ifdef DEBUG_MV_ETH | |
387 | /* DEBUG OUTPUT prints adresses of globals */ | |
388 | print_globals (dev); | |
389 | #endif | |
390 | eth_register (dev); | |
391 | ||
392 | } | |
393 | DP (printf ("%s: exit\n", __FUNCTION__)); | |
394 | ||
395 | } | |
396 | ||
397 | /********************************************************************** | |
398 | * mv64360_eth_open | |
399 | * | |
400 | * This function is called when openning the network device. The function | |
401 | * should initialize all the hardware, initialize cyclic Rx/Tx | |
402 | * descriptors chain and buffers and allocate an IRQ to the network | |
403 | * device. | |
404 | * | |
405 | * Input : a pointer to the network device structure | |
406 | * / / ronen - changed the output to match net/eth.c needs | |
407 | * Output : nonzero of success , zero if fails. | |
408 | * under construction | |
409 | **********************************************************************/ | |
410 | ||
411 | int mv64360_eth_open (struct eth_device *dev) | |
412 | { | |
413 | return (mv64360_eth_real_open (dev)); | |
414 | } | |
415 | ||
416 | /* Helper function for mv64360_eth_open */ | |
417 | static int mv64360_eth_real_open (struct eth_device *dev) | |
418 | { | |
419 | ||
420 | unsigned int queue; | |
421 | ETH_PORT_INFO *ethernet_private; | |
422 | struct mv64360_eth_priv *port_private; | |
423 | unsigned int port_num; | |
424 | u32 port_status, phy_reg_data; | |
425 | ||
426 | ethernet_private = (ETH_PORT_INFO *) dev->priv; | |
427 | /* ronen - when we update the MAC env params we only update dev->enetaddr | |
428 | see ./net/eth.c eth_set_enetaddr() */ | |
429 | memcpy (ethernet_private->port_mac_addr, dev->enetaddr, 6); | |
430 | ||
431 | port_private = | |
432 | (struct mv64360_eth_priv *) ethernet_private->port_private; | |
433 | port_num = port_private->port_num; | |
434 | ||
435 | /* Stop RX Queues */ | |
436 | MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), | |
437 | 0x0000ff00); | |
438 | ||
439 | /* Clear the ethernet port interrupts */ | |
440 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); | |
441 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); | |
442 | ||
443 | /* Unmask RX buffer and TX end interrupt */ | |
444 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), | |
445 | INT_CAUSE_UNMASK_ALL); | |
446 | ||
447 | /* Unmask phy and link status changes interrupts */ | |
448 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), | |
449 | INT_CAUSE_UNMASK_ALL_EXT); | |
450 | ||
451 | /* Set phy address of the port */ | |
452 | ethernet_private->port_phy_addr = 0x8 + port_num; | |
453 | ||
454 | /* Activate the DMA channels etc */ | |
455 | eth_port_init (ethernet_private); | |
456 | ||
457 | ||
458 | /* "Allocate" setup TX rings */ | |
459 | ||
460 | for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { | |
461 | unsigned int size; | |
462 | ||
463 | port_private->tx_ring_size[queue] = MV64360_TX_QUEUE_SIZE; | |
464 | size = (port_private->tx_ring_size[queue] * TX_DESC_ALIGNED_SIZE); /*size = no of DESCs times DESC-size */ | |
465 | ethernet_private->tx_desc_area_size[queue] = size; | |
466 | ||
467 | /* first clear desc area completely */ | |
468 | memset ((void *) ethernet_private->p_tx_desc_area_base[queue], | |
469 | 0, ethernet_private->tx_desc_area_size[queue]); | |
470 | ||
471 | /* initialize tx desc ring with low level driver */ | |
472 | if (ether_init_tx_desc_ring | |
473 | (ethernet_private, ETH_Q0, | |
474 | port_private->tx_ring_size[queue], | |
475 | MV64360_TX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , | |
476 | (unsigned int) ethernet_private-> | |
477 | p_tx_desc_area_base[queue], | |
478 | (unsigned int) ethernet_private-> | |
479 | p_tx_buffer_base[queue]) == false) | |
480 | printf ("### Error initializing TX Ring\n"); | |
481 | } | |
482 | ||
483 | /* "Allocate" setup RX rings */ | |
484 | for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { | |
485 | unsigned int size; | |
486 | ||
487 | /* Meantime RX Ring are fixed - but must be configurable by user */ | |
488 | port_private->rx_ring_size[queue] = MV64360_RX_QUEUE_SIZE; | |
489 | size = (port_private->rx_ring_size[queue] * | |
490 | RX_DESC_ALIGNED_SIZE); | |
491 | ethernet_private->rx_desc_area_size[queue] = size; | |
492 | ||
493 | /* first clear desc area completely */ | |
494 | memset ((void *) ethernet_private->p_rx_desc_area_base[queue], | |
495 | 0, ethernet_private->rx_desc_area_size[queue]); | |
496 | if ((ether_init_rx_desc_ring | |
497 | (ethernet_private, ETH_Q0, | |
498 | port_private->rx_ring_size[queue], | |
499 | MV64360_RX_BUFFER_SIZE /* Each Buffer is 1600 Byte */ , | |
500 | (unsigned int) ethernet_private-> | |
501 | p_rx_desc_area_base[queue], | |
502 | (unsigned int) ethernet_private-> | |
503 | p_rx_buffer_base[queue])) == false) | |
504 | printf ("### Error initializing RX Ring\n"); | |
505 | } | |
506 | ||
507 | eth_port_start (ethernet_private); | |
508 | ||
509 | /* Set maximum receive buffer to 9700 bytes */ | |
510 | MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num), | |
511 | (0x5 << 17) | | |
512 | (MV_REG_READ | |
513 | (MV64360_ETH_PORT_SERIAL_CONTROL_REG (port_num)) | |
514 | & 0xfff1ffff)); | |
515 | ||
516 | /* | |
517 | * Set ethernet MTU for leaky bucket mechanism to 0 - this will | |
518 | * disable the leaky bucket mechanism . | |
519 | */ | |
520 | ||
521 | MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (port_num), 0); | |
522 | port_status = MV_REG_READ (MV64360_ETH_PORT_STATUS_REG (port_num)); | |
523 | ||
524 | /* Check Link status on phy */ | |
525 | eth_port_read_smi_reg (port_num, 1, &phy_reg_data); | |
526 | if (!(phy_reg_data & 0x20)) { | |
527 | /* Reset PHY */ | |
528 | if ((ethernet_phy_reset (port_num)) != true) { | |
529 | printf ("$$ Warnning: No link on port %d \n", | |
530 | port_num); | |
531 | return 0; | |
532 | } else { | |
533 | eth_port_read_smi_reg (port_num, 1, &phy_reg_data); | |
534 | if (!(phy_reg_data & 0x20)) { | |
535 | printf ("### Error: Phy is not active\n"); | |
536 | return 0; | |
537 | } | |
538 | } | |
539 | } else { | |
540 | mv64360_eth_print_phy_status (dev); | |
541 | } | |
542 | port_private->eth_running = MAGIC_ETH_RUNNING; | |
543 | return 1; | |
544 | } | |
545 | ||
546 | ||
547 | static int mv64360_eth_free_tx_rings (struct eth_device *dev) | |
548 | { | |
549 | unsigned int queue; | |
550 | ETH_PORT_INFO *ethernet_private; | |
551 | struct mv64360_eth_priv *port_private; | |
552 | unsigned int port_num; | |
553 | volatile ETH_TX_DESC *p_tx_curr_desc; | |
554 | ||
555 | ethernet_private = (ETH_PORT_INFO *) dev->priv; | |
556 | port_private = | |
557 | (struct mv64360_eth_priv *) ethernet_private->port_private; | |
558 | port_num = port_private->port_num; | |
559 | ||
560 | /* Stop Tx Queues */ | |
561 | MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG (port_num), | |
562 | 0x0000ff00); | |
563 | ||
564 | /* Free TX rings */ | |
565 | DP (printf ("Clearing previously allocated TX queues... ")); | |
566 | for (queue = 0; queue < MV64360_TX_QUEUE_NUM; queue++) { | |
567 | /* Free on TX rings */ | |
568 | for (p_tx_curr_desc = | |
569 | ethernet_private->p_tx_desc_area_base[queue]; | |
570 | ((unsigned int) p_tx_curr_desc <= (unsigned int) | |
571 | ethernet_private->p_tx_desc_area_base[queue] + | |
572 | ethernet_private->tx_desc_area_size[queue]); | |
573 | p_tx_curr_desc = | |
574 | (ETH_TX_DESC *) ((unsigned int) p_tx_curr_desc + | |
575 | TX_DESC_ALIGNED_SIZE)) { | |
576 | /* this is inside for loop */ | |
577 | if (p_tx_curr_desc->return_info != 0) { | |
578 | p_tx_curr_desc->return_info = 0; | |
579 | DP (printf ("freed\n")); | |
580 | } | |
581 | } | |
582 | DP (printf ("Done\n")); | |
583 | } | |
584 | return 0; | |
585 | } | |
586 | ||
587 | static int mv64360_eth_free_rx_rings (struct eth_device *dev) | |
588 | { | |
589 | unsigned int queue; | |
590 | ETH_PORT_INFO *ethernet_private; | |
591 | struct mv64360_eth_priv *port_private; | |
592 | unsigned int port_num; | |
593 | volatile ETH_RX_DESC *p_rx_curr_desc; | |
594 | ||
595 | ethernet_private = (ETH_PORT_INFO *) dev->priv; | |
596 | port_private = | |
597 | (struct mv64360_eth_priv *) ethernet_private->port_private; | |
598 | port_num = port_private->port_num; | |
599 | ||
600 | ||
601 | /* Stop RX Queues */ | |
602 | MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (port_num), | |
603 | 0x0000ff00); | |
604 | ||
605 | /* Free RX rings */ | |
606 | DP (printf ("Clearing previously allocated RX queues... ")); | |
607 | for (queue = 0; queue < MV64360_RX_QUEUE_NUM; queue++) { | |
608 | /* Free preallocated skb's on RX rings */ | |
609 | for (p_rx_curr_desc = | |
610 | ethernet_private->p_rx_desc_area_base[queue]; | |
611 | (((unsigned int) p_rx_curr_desc < | |
612 | ((unsigned int) ethernet_private-> | |
613 | p_rx_desc_area_base[queue] + | |
614 | ethernet_private->rx_desc_area_size[queue]))); | |
615 | p_rx_curr_desc = | |
616 | (ETH_RX_DESC *) ((unsigned int) p_rx_curr_desc + | |
617 | RX_DESC_ALIGNED_SIZE)) { | |
618 | if (p_rx_curr_desc->return_info != 0) { | |
619 | p_rx_curr_desc->return_info = 0; | |
620 | DP (printf ("freed\n")); | |
621 | } | |
622 | } | |
623 | DP (printf ("Done\n")); | |
624 | } | |
625 | return 0; | |
626 | } | |
627 | ||
628 | /********************************************************************** | |
629 | * mv64360_eth_stop | |
630 | * | |
631 | * This function is used when closing the network device. | |
632 | * It updates the hardware, | |
633 | * release all memory that holds buffers and descriptors and release the IRQ. | |
634 | * Input : a pointer to the device structure | |
635 | * Output : zero if success , nonzero if fails | |
636 | *********************************************************************/ | |
637 | ||
638 | int mv64360_eth_stop (struct eth_device *dev) | |
639 | { | |
640 | ETH_PORT_INFO *ethernet_private; | |
641 | struct mv64360_eth_priv *port_private; | |
642 | unsigned int port_num; | |
643 | ||
644 | ethernet_private = (ETH_PORT_INFO *) dev->priv; | |
645 | port_private = | |
646 | (struct mv64360_eth_priv *) ethernet_private->port_private; | |
647 | port_num = port_private->port_num; | |
648 | ||
649 | /* Disable all gigE address decoder */ | |
650 | MV_REG_WRITE (MV64360_ETH_BASE_ADDR_ENABLE_REG, 0x3f); | |
651 | DP (printf ("%s Ethernet stop called ... \n", __FUNCTION__)); | |
652 | mv64360_eth_real_stop (dev); | |
653 | ||
654 | return 0; | |
655 | }; | |
656 | ||
657 | /* Helper function for mv64360_eth_stop */ | |
658 | ||
659 | static int mv64360_eth_real_stop (struct eth_device *dev) | |
660 | { | |
661 | ETH_PORT_INFO *ethernet_private; | |
662 | struct mv64360_eth_priv *port_private; | |
663 | unsigned int port_num; | |
664 | ||
665 | ethernet_private = (ETH_PORT_INFO *) dev->priv; | |
666 | port_private = | |
667 | (struct mv64360_eth_priv *) ethernet_private->port_private; | |
668 | port_num = port_private->port_num; | |
669 | ||
670 | ||
671 | mv64360_eth_free_tx_rings (dev); | |
672 | mv64360_eth_free_rx_rings (dev); | |
673 | ||
674 | eth_port_reset (ethernet_private->port_num); | |
675 | /* Disable ethernet port interrupts */ | |
676 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_REG (port_num), 0); | |
677 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_CAUSE_EXTEND_REG (port_num), 0); | |
678 | /* Mask RX buffer and TX end interrupt */ | |
679 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_MASK_REG (port_num), 0); | |
680 | /* Mask phy and link status changes interrupts */ | |
681 | MV_REG_WRITE (MV64360_ETH_INTERRUPT_EXTEND_MASK_REG (port_num), 0); | |
682 | MV_RESET_REG_BITS (MV64360_CPU_INTERRUPT0_MASK_HIGH, | |
683 | BIT0 << port_num); | |
684 | /* Print Network statistics */ | |
685 | #ifndef UPDATE_STATS_BY_SOFTWARE | |
686 | /* | |
687 | * Print statistics (only if ethernet is running), | |
688 | * then zero all the stats fields in memory | |
689 | */ | |
690 | if (port_private->eth_running == MAGIC_ETH_RUNNING) { | |
691 | port_private->eth_running = 0; | |
692 | mv64360_eth_print_stat (dev); | |
693 | } | |
694 | memset (port_private->stats, 0, sizeof (struct net_device_stats)); | |
695 | #endif | |
696 | DP (printf ("\nEthernet stopped ... \n")); | |
697 | return 0; | |
698 | } | |
699 | ||
700 | ||
701 | /********************************************************************** | |
702 | * mv64360_eth_start_xmit | |
703 | * | |
704 | * This function is queues a packet in the Tx descriptor for | |
705 | * required port. | |
706 | * | |
707 | * Input : skb - a pointer to socket buffer | |
708 | * dev - a pointer to the required port | |
709 | * | |
710 | * Output : zero upon success | |
711 | **********************************************************************/ | |
712 | ||
713 | int mv64360_eth_xmit (struct eth_device *dev, volatile void *dataPtr, | |
714 | int dataSize) | |
715 | { | |
716 | ETH_PORT_INFO *ethernet_private; | |
717 | struct mv64360_eth_priv *port_private; | |
718 | unsigned int port_num; | |
719 | PKT_INFO pkt_info; | |
720 | ETH_FUNC_RET_STATUS status; | |
721 | struct net_device_stats *stats; | |
722 | ETH_FUNC_RET_STATUS release_result; | |
723 | ||
724 | ethernet_private = (ETH_PORT_INFO *) dev->priv; | |
725 | port_private = | |
726 | (struct mv64360_eth_priv *) ethernet_private->port_private; | |
727 | port_num = port_private->port_num; | |
728 | ||
729 | stats = port_private->stats; | |
730 | ||
731 | /* Update packet info data structure */ | |
732 | pkt_info.cmd_sts = ETH_TX_FIRST_DESC | ETH_TX_LAST_DESC; /* DMA owned, first last */ | |
733 | pkt_info.byte_cnt = dataSize; | |
734 | pkt_info.buf_ptr = (unsigned int) dataPtr; | |
735 | ||
736 | status = eth_port_send (ethernet_private, ETH_Q0, &pkt_info); | |
737 | if ((status == ETH_ERROR) || (status == ETH_QUEUE_FULL)) { | |
738 | printf ("Error on transmitting packet .."); | |
739 | if (status == ETH_QUEUE_FULL) | |
740 | printf ("ETH Queue is full. \n"); | |
741 | if (status == ETH_QUEUE_LAST_RESOURCE) | |
742 | printf ("ETH Queue: using last available resource. \n"); | |
743 | goto error; | |
744 | } | |
745 | ||
746 | /* Update statistics and start of transmittion time */ | |
747 | stats->tx_bytes += dataSize; | |
748 | stats->tx_packets++; | |
749 | ||
750 | /* Check if packet(s) is(are) transmitted correctly (release everything) */ | |
751 | do { | |
752 | release_result = | |
753 | eth_tx_return_desc (ethernet_private, ETH_Q0, | |
754 | &pkt_info); | |
755 | switch (release_result) { | |
756 | case ETH_OK: | |
757 | DP (printf ("descriptor released\n")); | |
758 | if (pkt_info.cmd_sts & BIT0) { | |
759 | printf ("Error in TX\n"); | |
760 | stats->tx_errors++; | |
761 | ||
762 | } | |
763 | break; | |
764 | case ETH_RETRY: | |
765 | DP (printf ("transmission still in process\n")); | |
766 | break; | |
767 | ||
768 | case ETH_ERROR: | |
769 | printf ("routine can not access Tx desc ring\n"); | |
770 | break; | |
771 | ||
772 | case ETH_END_OF_JOB: | |
773 | DP (printf ("the routine has nothing to release\n")); | |
774 | break; | |
775 | default: /* should not happen */ | |
776 | break; | |
777 | } | |
778 | } while (release_result == ETH_OK); | |
779 | ||
780 | ||
781 | return 0; /* success */ | |
782 | error: | |
783 | return 1; /* Failed - higher layers will free the skb */ | |
784 | } | |
785 | ||
786 | /********************************************************************** | |
787 | * mv64360_eth_receive | |
788 | * | |
789 | * This function is forward packets that are received from the port's | |
790 | * queues toward kernel core or FastRoute them to another interface. | |
791 | * | |
792 | * Input : dev - a pointer to the required interface | |
793 | * max - maximum number to receive (0 means unlimted) | |
794 | * | |
795 | * Output : number of served packets | |
796 | **********************************************************************/ | |
797 | ||
798 | int mv64360_eth_receive (struct eth_device *dev) | |
799 | { | |
800 | ETH_PORT_INFO *ethernet_private; | |
801 | struct mv64360_eth_priv *port_private; | |
802 | unsigned int port_num; | |
803 | PKT_INFO pkt_info; | |
804 | struct net_device_stats *stats; | |
805 | ||
806 | ||
807 | ethernet_private = (ETH_PORT_INFO *) dev->priv; | |
808 | port_private = | |
809 | (struct mv64360_eth_priv *) ethernet_private->port_private; | |
810 | port_num = port_private->port_num; | |
811 | stats = port_private->stats; | |
812 | ||
813 | while ((eth_port_receive (ethernet_private, ETH_Q0, &pkt_info) == | |
814 | ETH_OK)) { | |
815 | ||
816 | #ifdef DEBUG_MV_ETH | |
817 | if (pkt_info.byte_cnt != 0) { | |
818 | printf ("%s: Received %d byte Packet @ 0x%x\n", | |
819 | __FUNCTION__, pkt_info.byte_cnt, | |
820 | pkt_info.buf_ptr); | |
821 | } | |
822 | #endif | |
823 | /* Update statistics. Note byte count includes 4 byte CRC count */ | |
824 | stats->rx_packets++; | |
825 | stats->rx_bytes += pkt_info.byte_cnt; | |
826 | ||
827 | /* | |
828 | * In case received a packet without first / last bits on OR the error | |
829 | * summary bit is on, the packets needs to be dropeed. | |
830 | */ | |
831 | if (((pkt_info. | |
832 | cmd_sts & (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) != | |
833 | (ETH_RX_FIRST_DESC | ETH_RX_LAST_DESC)) | |
834 | || (pkt_info.cmd_sts & ETH_ERROR_SUMMARY)) { | |
835 | stats->rx_dropped++; | |
836 | ||
837 | printf ("Received packet spread on multiple descriptors\n"); | |
838 | ||
839 | /* Is this caused by an error ? */ | |
840 | if (pkt_info.cmd_sts & ETH_ERROR_SUMMARY) { | |
841 | stats->rx_errors++; | |
842 | } | |
843 | ||
844 | /* free these descriptors again without forwarding them to the higher layers */ | |
845 | pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ | |
846 | pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ | |
847 | ||
848 | if (eth_rx_return_buff | |
849 | (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { | |
850 | printf ("Error while returning the RX Desc to Ring\n"); | |
851 | } else { | |
852 | DP (printf ("RX Desc returned to Ring\n")); | |
853 | } | |
854 | /* /free these descriptors again */ | |
855 | } else { | |
856 | ||
857 | /* !!! call higher layer processing */ | |
858 | #ifdef DEBUG_MV_ETH | |
859 | printf ("\nNow send it to upper layer protocols (NetReceive) ...\n"); | |
860 | #endif | |
861 | /* let the upper layer handle the packet */ | |
862 | NetReceive ((uchar *) pkt_info.buf_ptr, | |
863 | (int) pkt_info.byte_cnt); | |
864 | ||
865 | /* **************************************************************** */ | |
866 | /* free descriptor */ | |
867 | pkt_info.buf_ptr &= ~0x7; /* realign buffer again */ | |
868 | pkt_info.byte_cnt = 0x0000; /* Reset Byte count */ | |
869 | DP (printf | |
870 | ("RX: pkt_info.buf_ptr = %x\n", | |
871 | pkt_info.buf_ptr)); | |
872 | if (eth_rx_return_buff | |
873 | (ethernet_private, ETH_Q0, &pkt_info) != ETH_OK) { | |
874 | printf ("Error while returning the RX Desc to Ring\n"); | |
875 | } else { | |
876 | DP (printf ("RX Desc returned to Ring\n")); | |
877 | } | |
878 | ||
879 | /* **************************************************************** */ | |
880 | ||
881 | } | |
882 | } | |
883 | mv64360_eth_get_stats (dev); /* update statistics */ | |
884 | return 1; | |
885 | } | |
886 | ||
887 | /********************************************************************** | |
888 | * mv64360_eth_get_stats | |
889 | * | |
890 | * Returns a pointer to the interface statistics. | |
891 | * | |
892 | * Input : dev - a pointer to the required interface | |
893 | * | |
894 | * Output : a pointer to the interface's statistics | |
895 | **********************************************************************/ | |
896 | ||
897 | static struct net_device_stats *mv64360_eth_get_stats (struct eth_device *dev) | |
898 | { | |
899 | ETH_PORT_INFO *ethernet_private; | |
900 | struct mv64360_eth_priv *port_private; | |
901 | unsigned int port_num; | |
902 | ||
903 | ethernet_private = (ETH_PORT_INFO *) dev->priv; | |
904 | port_private = | |
905 | (struct mv64360_eth_priv *) ethernet_private->port_private; | |
906 | port_num = port_private->port_num; | |
907 | ||
908 | mv64360_eth_update_stat (dev); | |
909 | ||
910 | return port_private->stats; | |
911 | } | |
912 | ||
913 | ||
914 | /********************************************************************** | |
915 | * mv64360_eth_update_stat | |
916 | * | |
917 | * Update the statistics structure in the private data structure | |
918 | * | |
919 | * Input : pointer to ethernet interface network device structure | |
920 | * Output : N/A | |
921 | **********************************************************************/ | |
922 | ||
923 | static void mv64360_eth_update_stat (struct eth_device *dev) | |
924 | { | |
925 | ETH_PORT_INFO *ethernet_private; | |
926 | struct mv64360_eth_priv *port_private; | |
927 | struct net_device_stats *stats; | |
928 | unsigned int port_num; | |
929 | volatile unsigned int dummy; | |
930 | ||
931 | ethernet_private = (ETH_PORT_INFO *) dev->priv; | |
932 | port_private = | |
933 | (struct mv64360_eth_priv *) ethernet_private->port_private; | |
934 | port_num = port_private->port_num; | |
935 | stats = port_private->stats; | |
936 | ||
937 | /* These are false updates */ | |
938 | stats->rx_packets += (unsigned long) | |
939 | eth_read_mib_counter (ethernet_private->port_num, | |
940 | ETH_MIB_GOOD_FRAMES_RECEIVED); | |
941 | stats->tx_packets += (unsigned long) | |
942 | eth_read_mib_counter (ethernet_private->port_num, | |
943 | ETH_MIB_GOOD_FRAMES_SENT); | |
944 | stats->rx_bytes += (unsigned long) | |
945 | eth_read_mib_counter (ethernet_private->port_num, | |
946 | ETH_MIB_GOOD_OCTETS_RECEIVED_LOW); | |
947 | /* | |
948 | * Ideally this should be as follows - | |
949 | * | |
950 | * stats->rx_bytes += stats->rx_bytes + | |
951 | * ((unsigned long) ethReadMibCounter (ethernet_private->port_num , | |
952 | * ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH) << 32); | |
953 | * | |
954 | * But the unsigned long in PowerPC and MIPS are 32bit. So the next read | |
955 | * is just a dummy read for proper work of the GigE port | |
956 | */ | |
957 | dummy = eth_read_mib_counter (ethernet_private->port_num, | |
958 | ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH); | |
959 | stats->tx_bytes += (unsigned long) | |
960 | eth_read_mib_counter (ethernet_private->port_num, | |
961 | ETH_MIB_GOOD_OCTETS_SENT_LOW); | |
962 | dummy = eth_read_mib_counter (ethernet_private->port_num, | |
963 | ETH_MIB_GOOD_OCTETS_SENT_HIGH); | |
964 | stats->rx_errors += (unsigned long) | |
965 | eth_read_mib_counter (ethernet_private->port_num, | |
966 | ETH_MIB_MAC_RECEIVE_ERROR); | |
967 | ||
968 | /* Rx dropped is for received packet with CRC error */ | |
969 | stats->rx_dropped += | |
970 | (unsigned long) eth_read_mib_counter (ethernet_private-> | |
971 | port_num, | |
972 | ETH_MIB_BAD_CRC_EVENT); | |
973 | stats->multicast += (unsigned long) | |
974 | eth_read_mib_counter (ethernet_private->port_num, | |
975 | ETH_MIB_MULTICAST_FRAMES_RECEIVED); | |
976 | stats->collisions += | |
977 | (unsigned long) eth_read_mib_counter (ethernet_private-> | |
978 | port_num, | |
979 | ETH_MIB_COLLISION) + | |
980 | (unsigned long) eth_read_mib_counter (ethernet_private-> | |
981 | port_num, | |
982 | ETH_MIB_LATE_COLLISION); | |
983 | /* detailed rx errors */ | |
984 | stats->rx_length_errors += | |
985 | (unsigned long) eth_read_mib_counter (ethernet_private-> | |
986 | port_num, | |
987 | ETH_MIB_UNDERSIZE_RECEIVED) | |
988 | + | |
989 | (unsigned long) eth_read_mib_counter (ethernet_private-> | |
990 | port_num, | |
991 | ETH_MIB_OVERSIZE_RECEIVED); | |
992 | /* detailed tx errors */ | |
993 | } | |
994 | ||
995 | #ifndef UPDATE_STATS_BY_SOFTWARE | |
996 | /********************************************************************** | |
997 | * mv64360_eth_print_stat | |
998 | * | |
999 | * Update the statistics structure in the private data structure | |
1000 | * | |
1001 | * Input : pointer to ethernet interface network device structure | |
1002 | * Output : N/A | |
1003 | **********************************************************************/ | |
1004 | ||
1005 | static void mv64360_eth_print_stat (struct eth_device *dev) | |
1006 | { | |
1007 | ETH_PORT_INFO *ethernet_private; | |
1008 | struct mv64360_eth_priv *port_private; | |
1009 | struct net_device_stats *stats; | |
1010 | unsigned int port_num; | |
1011 | ||
1012 | ethernet_private = (ETH_PORT_INFO *) dev->priv; | |
1013 | port_private = | |
1014 | (struct mv64360_eth_priv *) ethernet_private->port_private; | |
1015 | port_num = port_private->port_num; | |
1016 | stats = port_private->stats; | |
1017 | ||
1018 | /* These are false updates */ | |
1019 | printf ("\n### Network statistics: ###\n"); | |
1020 | printf ("--------------------------\n"); | |
1021 | printf (" Packets received: %ld\n", stats->rx_packets); | |
1022 | printf (" Packets send: %ld\n", stats->tx_packets); | |
1023 | printf (" Received bytes: %ld\n", stats->rx_bytes); | |
1024 | printf (" Send bytes: %ld\n", stats->tx_bytes); | |
1025 | if (stats->rx_errors != 0) | |
1026 | printf (" Rx Errors: %ld\n", | |
1027 | stats->rx_errors); | |
1028 | if (stats->rx_dropped != 0) | |
1029 | printf (" Rx dropped (CRC Errors): %ld\n", | |
1030 | stats->rx_dropped); | |
1031 | if (stats->multicast != 0) | |
1032 | printf (" Rx mulicast frames: %ld\n", | |
1033 | stats->multicast); | |
1034 | if (stats->collisions != 0) | |
1035 | printf (" No. of collisions: %ld\n", | |
1036 | stats->collisions); | |
1037 | if (stats->rx_length_errors != 0) | |
1038 | printf (" Rx length errors: %ld\n", | |
1039 | stats->rx_length_errors); | |
1040 | } | |
1041 | #endif | |
1042 | ||
1043 | /************************************************************************** | |
1044 | *network_start - Network Kick Off Routine UBoot | |
1045 | *Inputs : | |
1046 | *Outputs : | |
1047 | **************************************************************************/ | |
1048 | ||
1049 | bool db64360_eth_start (struct eth_device *dev) | |
1050 | { | |
1051 | return (mv64360_eth_open (dev)); /* calls real open */ | |
1052 | } | |
1053 | ||
1054 | /************************************************************************* | |
1055 | ************************************************************************** | |
1056 | ************************************************************************** | |
1057 | * The second part is the low level driver of the gigE ethernet ports. * | |
1058 | ************************************************************************** | |
1059 | ************************************************************************** | |
1060 | *************************************************************************/ | |
1061 | /* | |
1062 | * based on Linux code | |
1063 | * arch/ppc/galileo/EVB64360/mv64360_eth.c - Driver for MV64360X ethernet ports | |
1064 | * Copyright (C) 2002 rabeeh@galileo.co.il | |
1065 | ||
1066 | * This program is free software; you can redistribute it and/or | |
1067 | * modify it under the terms of the GNU General Public License | |
1068 | * as published by the Free Software Foundation; either version 2 | |
1069 | * of the License, or (at your option) any later version. | |
1070 | ||
1071 | * This program is distributed in the hope that it will be useful, | |
1072 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
1073 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
1074 | * GNU General Public License for more details. | |
1075 | ||
1076 | * You should have received a copy of the GNU General Public License | |
1077 | * along with this program; if not, write to the Free Software | |
1078 | * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. | |
1079 | * | |
1080 | */ | |
1081 | ||
1082 | /******************************************************************************** | |
1083 | * Marvell's Gigabit Ethernet controller low level driver | |
1084 | * | |
1085 | * DESCRIPTION: | |
1086 | * This file introduce low level API to Marvell's Gigabit Ethernet | |
1087 | * controller. This Gigabit Ethernet Controller driver API controls | |
1088 | * 1) Operations (i.e. port init, start, reset etc'). | |
1089 | * 2) Data flow (i.e. port send, receive etc'). | |
1090 | * Each Gigabit Ethernet port is controlled via ETH_PORT_INFO | |
1091 | * struct. | |
1092 | * This struct includes user configuration information as well as | |
1093 | * driver internal data needed for its operations. | |
1094 | * | |
1095 | * Supported Features: | |
1096 | * - This low level driver is OS independent. Allocating memory for | |
1097 | * the descriptor rings and buffers are not within the scope of | |
1098 | * this driver. | |
1099 | * - The user is free from Rx/Tx queue managing. | |
1100 | * - This low level driver introduce functionality API that enable | |
1101 | * the to operate Marvell's Gigabit Ethernet Controller in a | |
1102 | * convenient way. | |
1103 | * - Simple Gigabit Ethernet port operation API. | |
1104 | * - Simple Gigabit Ethernet port data flow API. | |
1105 | * - Data flow and operation API support per queue functionality. | |
1106 | * - Support cached descriptors for better performance. | |
1107 | * - Enable access to all four DRAM banks and internal SRAM memory | |
1108 | * spaces. | |
1109 | * - PHY access and control API. | |
1110 | * - Port control register configuration API. | |
1111 | * - Full control over Unicast and Multicast MAC configurations. | |
1112 | * | |
1113 | * Operation flow: | |
1114 | * | |
1115 | * Initialization phase | |
1116 | * This phase complete the initialization of the ETH_PORT_INFO | |
1117 | * struct. | |
1118 | * User information regarding port configuration has to be set | |
1119 | * prior to calling the port initialization routine. For example, | |
1120 | * the user has to assign the port_phy_addr field which is board | |
1121 | * depended parameter. | |
1122 | * In this phase any port Tx/Rx activity is halted, MIB counters | |
1123 | * are cleared, PHY address is set according to user parameter and | |
1124 | * access to DRAM and internal SRAM memory spaces. | |
1125 | * | |
1126 | * Driver ring initialization | |
1127 | * Allocating memory for the descriptor rings and buffers is not | |
1128 | * within the scope of this driver. Thus, the user is required to | |
1129 | * allocate memory for the descriptors ring and buffers. Those | |
1130 | * memory parameters are used by the Rx and Tx ring initialization | |
1131 | * routines in order to curve the descriptor linked list in a form | |
1132 | * of a ring. | |
1133 | * Note: Pay special attention to alignment issues when using | |
1134 | * cached descriptors/buffers. In this phase the driver store | |
1135 | * information in the ETH_PORT_INFO struct regarding each queue | |
1136 | * ring. | |
1137 | * | |
1138 | * Driver start | |
1139 | * This phase prepares the Ethernet port for Rx and Tx activity. | |
1140 | * It uses the information stored in the ETH_PORT_INFO struct to | |
1141 | * initialize the various port registers. | |
1142 | * | |
1143 | * Data flow: | |
1144 | * All packet references to/from the driver are done using PKT_INFO | |
1145 | * struct. | |
1146 | * This struct is a unified struct used with Rx and Tx operations. | |
1147 | * This way the user is not required to be familiar with neither | |
1148 | * Tx nor Rx descriptors structures. | |
1149 | * The driver's descriptors rings are management by indexes. | |
1150 | * Those indexes controls the ring resources and used to indicate | |
1151 | * a SW resource error: | |
1152 | * 'current' | |
1153 | * This index points to the current available resource for use. For | |
1154 | * example in Rx process this index will point to the descriptor | |
1155 | * that will be passed to the user upon calling the receive routine. | |
1156 | * In Tx process, this index will point to the descriptor | |
1157 | * that will be assigned with the user packet info and transmitted. | |
1158 | * 'used' | |
1159 | * This index points to the descriptor that need to restore its | |
1160 | * resources. For example in Rx process, using the Rx buffer return | |
1161 | * API will attach the buffer returned in packet info to the | |
1162 | * descriptor pointed by 'used'. In Tx process, using the Tx | |
1163 | * descriptor return will merely return the user packet info with | |
1164 | * the command status of the transmitted buffer pointed by the | |
1165 | * 'used' index. Nevertheless, it is essential to use this routine | |
1166 | * to update the 'used' index. | |
1167 | * 'first' | |
1168 | * This index supports Tx Scatter-Gather. It points to the first | |
1169 | * descriptor of a packet assembled of multiple buffers. For example | |
1170 | * when in middle of Such packet we have a Tx resource error the | |
1171 | * 'curr' index get the value of 'first' to indicate that the ring | |
1172 | * returned to its state before trying to transmit this packet. | |
1173 | * | |
1174 | * Receive operation: | |
1175 | * The eth_port_receive API set the packet information struct, | |
1176 | * passed by the caller, with received information from the | |
1177 | * 'current' SDMA descriptor. | |
1178 | * It is the user responsibility to return this resource back | |
1179 | * to the Rx descriptor ring to enable the reuse of this source. | |
1180 | * Return Rx resource is done using the eth_rx_return_buff API. | |
1181 | * | |
1182 | * Transmit operation: | |
1183 | * The eth_port_send API supports Scatter-Gather which enables to | |
1184 | * send a packet spanned over multiple buffers. This means that | |
1185 | * for each packet info structure given by the user and put into | |
1186 | * the Tx descriptors ring, will be transmitted only if the 'LAST' | |
1187 | * bit will be set in the packet info command status field. This | |
1188 | * API also consider restriction regarding buffer alignments and | |
1189 | * sizes. | |
1190 | * The user must return a Tx resource after ensuring the buffer | |
1191 | * has been transmitted to enable the Tx ring indexes to update. | |
1192 | * | |
1193 | * BOARD LAYOUT | |
1194 | * This device is on-board. No jumper diagram is necessary. | |
1195 | * | |
1196 | * EXTERNAL INTERFACE | |
1197 | * | |
1198 | * Prior to calling the initialization routine eth_port_init() the user | |
1199 | * must set the following fields under ETH_PORT_INFO struct: | |
1200 | * port_num User Ethernet port number. | |
1201 | * port_phy_addr User PHY address of Ethernet port. | |
1202 | * port_mac_addr[6] User defined port MAC address. | |
1203 | * port_config User port configuration value. | |
1204 | * port_config_extend User port config extend value. | |
1205 | * port_sdma_config User port SDMA config value. | |
1206 | * port_serial_control User port serial control value. | |
1207 | * *port_virt_to_phys () User function to cast virtual addr to CPU bus addr. | |
1208 | * *port_private User scratch pad for user specific data structures. | |
1209 | * | |
1210 | * This driver introduce a set of default values: | |
1211 | * PORT_CONFIG_VALUE Default port configuration value | |
1212 | * PORT_CONFIG_EXTEND_VALUE Default port extend configuration value | |
1213 | * PORT_SDMA_CONFIG_VALUE Default sdma control value | |
1214 | * PORT_SERIAL_CONTROL_VALUE Default port serial control value | |
1215 | * | |
1216 | * This driver data flow is done using the PKT_INFO struct which is | |
1217 | * a unified struct for Rx and Tx operations: | |
1218 | * byte_cnt Tx/Rx descriptor buffer byte count. | |
1219 | * l4i_chk CPU provided TCP Checksum. For Tx operation only. | |
1220 | * cmd_sts Tx/Rx descriptor command status. | |
1221 | * buf_ptr Tx/Rx descriptor buffer pointer. | |
1222 | * return_info Tx/Rx user resource return information. | |
1223 | * | |
1224 | * | |
1225 | * EXTERNAL SUPPORT REQUIREMENTS | |
1226 | * | |
1227 | * This driver requires the following external support: | |
1228 | * | |
1229 | * D_CACHE_FLUSH_LINE (address, address offset) | |
1230 | * | |
1231 | * This macro applies assembly code to flush and invalidate cache | |
1232 | * line. | |
1233 | * address - address base. | |
1234 | * address offset - address offset | |
1235 | * | |
1236 | * | |
1237 | * CPU_PIPE_FLUSH | |
1238 | * | |
1239 | * This macro applies assembly code to flush the CPU pipeline. | |
1240 | * | |
1241 | *******************************************************************************/ | |
1242 | /* includes */ | |
1243 | ||
1244 | /* defines */ | |
1245 | /* SDMA command macros */ | |
1246 | #define ETH_ENABLE_TX_QUEUE(tx_queue, eth_port) \ | |
1247 | MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port), (1 << tx_queue)) | |
1248 | ||
1249 | #define ETH_DISABLE_TX_QUEUE(tx_queue, eth_port) \ | |
1250 | MV_REG_WRITE(MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG(eth_port),\ | |
1251 | (1 << (8 + tx_queue))) | |
1252 | ||
1253 | #define ETH_ENABLE_RX_QUEUE(rx_queue, eth_port) \ | |
1254 | MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << rx_queue)) | |
1255 | ||
1256 | #define ETH_DISABLE_RX_QUEUE(rx_queue, eth_port) \ | |
1257 | MV_REG_WRITE(MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(eth_port), (1 << (8 + rx_queue))) | |
1258 | ||
1259 | #define CURR_RFD_GET(p_curr_desc, queue) \ | |
1260 | ((p_curr_desc) = p_eth_port_ctrl->p_rx_curr_desc_q[queue]) | |
1261 | ||
1262 | #define CURR_RFD_SET(p_curr_desc, queue) \ | |
1263 | (p_eth_port_ctrl->p_rx_curr_desc_q[queue] = (p_curr_desc)) | |
1264 | ||
1265 | #define USED_RFD_GET(p_used_desc, queue) \ | |
1266 | ((p_used_desc) = p_eth_port_ctrl->p_rx_used_desc_q[queue]) | |
1267 | ||
1268 | #define USED_RFD_SET(p_used_desc, queue)\ | |
1269 | (p_eth_port_ctrl->p_rx_used_desc_q[queue] = (p_used_desc)) | |
1270 | ||
1271 | ||
1272 | #define CURR_TFD_GET(p_curr_desc, queue) \ | |
1273 | ((p_curr_desc) = p_eth_port_ctrl->p_tx_curr_desc_q[queue]) | |
1274 | ||
1275 | #define CURR_TFD_SET(p_curr_desc, queue) \ | |
1276 | (p_eth_port_ctrl->p_tx_curr_desc_q[queue] = (p_curr_desc)) | |
1277 | ||
1278 | #define USED_TFD_GET(p_used_desc, queue) \ | |
1279 | ((p_used_desc) = p_eth_port_ctrl->p_tx_used_desc_q[queue]) | |
1280 | ||
1281 | #define USED_TFD_SET(p_used_desc, queue) \ | |
1282 | (p_eth_port_ctrl->p_tx_used_desc_q[queue] = (p_used_desc)) | |
1283 | ||
1284 | #define FIRST_TFD_GET(p_first_desc, queue) \ | |
1285 | ((p_first_desc) = p_eth_port_ctrl->p_tx_first_desc_q[queue]) | |
1286 | ||
1287 | #define FIRST_TFD_SET(p_first_desc, queue) \ | |
1288 | (p_eth_port_ctrl->p_tx_first_desc_q[queue] = (p_first_desc)) | |
1289 | ||
1290 | ||
1291 | /* Macros that save access to desc in order to find next desc pointer */ | |
1292 | #define RX_NEXT_DESC_PTR(p_rx_desc, queue) (ETH_RX_DESC*)(((((unsigned int)p_rx_desc - (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) + RX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->rx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_rx_desc_area_base[queue]) | |
1293 | ||
1294 | #define TX_NEXT_DESC_PTR(p_tx_desc, queue) (ETH_TX_DESC*)(((((unsigned int)p_tx_desc - (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) + TX_DESC_ALIGNED_SIZE) % p_eth_port_ctrl->tx_desc_area_size[queue]) + (unsigned int)p_eth_port_ctrl->p_tx_desc_area_base[queue]) | |
1295 | ||
1296 | #define LINK_UP_TIMEOUT 100000 | |
1297 | #define PHY_BUSY_TIMEOUT 10000000 | |
1298 | ||
1299 | /* locals */ | |
1300 | ||
1301 | /* PHY routines */ | |
1302 | static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr); | |
1303 | static int ethernet_phy_get (ETH_PORT eth_port_num); | |
1304 | ||
1305 | /* Ethernet Port routines */ | |
1306 | static void eth_set_access_control (ETH_PORT eth_port_num, | |
1307 | ETH_WIN_PARAM * param); | |
1308 | static bool eth_port_uc_addr (ETH_PORT eth_port_num, unsigned char uc_nibble, | |
1309 | ETH_QUEUE queue, int option); | |
1310 | #if 0 /* FIXME */ | |
1311 | static bool eth_port_smc_addr (ETH_PORT eth_port_num, | |
1312 | unsigned char mc_byte, | |
1313 | ETH_QUEUE queue, int option); | |
1314 | static bool eth_port_omc_addr (ETH_PORT eth_port_num, | |
1315 | unsigned char crc8, | |
1316 | ETH_QUEUE queue, int option); | |
1317 | #endif | |
1318 | ||
1319 | static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, | |
1320 | int byte_count); | |
1321 | ||
1322 | void eth_dbg (ETH_PORT_INFO * p_eth_port_ctrl); | |
1323 | ||
1324 | ||
1325 | typedef enum _memory_bank { BANK0, BANK1, BANK2, BANK3 } MEMORY_BANK; | |
1326 | u32 mv_get_dram_bank_base_addr (MEMORY_BANK bank) | |
1327 | { | |
1328 | u32 result = 0; | |
1329 | u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); | |
1330 | ||
1331 | if (enable & (1 << bank)) | |
1332 | return 0; | |
1333 | if (bank == BANK0) | |
1334 | result = MV_REG_READ (MV64360_CS_0_BASE_ADDR); | |
1335 | if (bank == BANK1) | |
1336 | result = MV_REG_READ (MV64360_CS_1_BASE_ADDR); | |
1337 | if (bank == BANK2) | |
1338 | result = MV_REG_READ (MV64360_CS_2_BASE_ADDR); | |
1339 | if (bank == BANK3) | |
1340 | result = MV_REG_READ (MV64360_CS_3_BASE_ADDR); | |
1341 | result &= 0x0000ffff; | |
1342 | result = result << 16; | |
1343 | return result; | |
1344 | } | |
1345 | ||
1346 | u32 mv_get_dram_bank_size (MEMORY_BANK bank) | |
1347 | { | |
1348 | u32 result = 0; | |
1349 | u32 enable = MV_REG_READ (MV64360_BASE_ADDR_ENABLE); | |
1350 | ||
1351 | if (enable & (1 << bank)) | |
1352 | return 0; | |
1353 | if (bank == BANK0) | |
1354 | result = MV_REG_READ (MV64360_CS_0_SIZE); | |
1355 | if (bank == BANK1) | |
1356 | result = MV_REG_READ (MV64360_CS_1_SIZE); | |
1357 | if (bank == BANK2) | |
1358 | result = MV_REG_READ (MV64360_CS_2_SIZE); | |
1359 | if (bank == BANK3) | |
1360 | result = MV_REG_READ (MV64360_CS_3_SIZE); | |
1361 | result += 1; | |
1362 | result &= 0x0000ffff; | |
1363 | result = result << 16; | |
1364 | return result; | |
1365 | } | |
1366 | ||
1367 | u32 mv_get_internal_sram_base (void) | |
1368 | { | |
1369 | u32 result; | |
1370 | ||
1371 | result = MV_REG_READ (MV64360_INTEGRATED_SRAM_BASE_ADDR); | |
1372 | result &= 0x0000ffff; | |
1373 | result = result << 16; | |
1374 | return result; | |
1375 | } | |
1376 | ||
1377 | /******************************************************************************* | |
1378 | * eth_port_init - Initialize the Ethernet port driver | |
1379 | * | |
1380 | * DESCRIPTION: | |
1381 | * This function prepares the ethernet port to start its activity: | |
1382 | * 1) Completes the ethernet port driver struct initialization toward port | |
1383 | * start routine. | |
1384 | * 2) Resets the device to a quiescent state in case of warm reboot. | |
1385 | * 3) Enable SDMA access to all four DRAM banks as well as internal SRAM. | |
1386 | * 4) Clean MAC tables. The reset status of those tables is unknown. | |
1387 | * 5) Set PHY address. | |
1388 | * Note: Call this routine prior to eth_port_start routine and after setting | |
1389 | * user values in the user fields of Ethernet port control struct (i.e. | |
1390 | * port_phy_addr). | |
1391 | * | |
1392 | * INPUT: | |
1393 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct | |
1394 | * | |
1395 | * OUTPUT: | |
1396 | * See description. | |
1397 | * | |
1398 | * RETURN: | |
1399 | * None. | |
1400 | * | |
1401 | *******************************************************************************/ | |
1402 | static void eth_port_init (ETH_PORT_INFO * p_eth_port_ctrl) | |
1403 | { | |
1404 | int queue; | |
1405 | ETH_WIN_PARAM win_param; | |
1406 | ||
1407 | p_eth_port_ctrl->port_config = PORT_CONFIG_VALUE; | |
1408 | p_eth_port_ctrl->port_config_extend = PORT_CONFIG_EXTEND_VALUE; | |
1409 | p_eth_port_ctrl->port_sdma_config = PORT_SDMA_CONFIG_VALUE; | |
1410 | p_eth_port_ctrl->port_serial_control = PORT_SERIAL_CONTROL_VALUE; | |
1411 | ||
1412 | p_eth_port_ctrl->port_rx_queue_command = 0; | |
1413 | p_eth_port_ctrl->port_tx_queue_command = 0; | |
1414 | ||
1415 | /* Zero out SW structs */ | |
1416 | for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { | |
1417 | CURR_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); | |
1418 | USED_RFD_SET ((ETH_RX_DESC *) 0x00000000, queue); | |
1419 | p_eth_port_ctrl->rx_resource_err[queue] = false; | |
1420 | } | |
1421 | ||
1422 | for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { | |
1423 | CURR_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); | |
1424 | USED_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); | |
1425 | FIRST_TFD_SET ((ETH_TX_DESC *) 0x00000000, queue); | |
1426 | p_eth_port_ctrl->tx_resource_err[queue] = false; | |
1427 | } | |
1428 | ||
1429 | eth_port_reset (p_eth_port_ctrl->port_num); | |
1430 | ||
1431 | /* Set access parameters for DRAM bank 0 */ | |
1432 | win_param.win = ETH_WIN0; /* Use Ethernet window 0 */ | |
1433 | win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ | |
1434 | win_param.attributes = EBAR_ATTR_DRAM_CS0; /* Enable DRAM bank */ | |
1435 | #ifndef CONFIG_NOT_COHERENT_CACHE | |
1436 | win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; | |
1437 | #endif | |
1438 | win_param.high_addr = 0; | |
1439 | /* Get bank base */ | |
1440 | win_param.base_addr = mv_get_dram_bank_base_addr (BANK0); | |
1441 | win_param.size = mv_get_dram_bank_size (BANK0); /* Get bank size */ | |
1442 | if (win_param.size == 0) | |
1443 | win_param.enable = 0; | |
1444 | else | |
1445 | win_param.enable = 1; /* Enable the access */ | |
1446 | win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ | |
1447 | ||
1448 | /* Set the access control for address window (EPAPR) READ & WRITE */ | |
1449 | eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); | |
1450 | ||
1451 | /* Set access parameters for DRAM bank 1 */ | |
1452 | win_param.win = ETH_WIN1; /* Use Ethernet window 1 */ | |
1453 | win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ | |
1454 | win_param.attributes = EBAR_ATTR_DRAM_CS1; /* Enable DRAM bank */ | |
1455 | #ifndef CONFIG_NOT_COHERENT_CACHE | |
1456 | win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; | |
1457 | #endif | |
1458 | win_param.high_addr = 0; | |
1459 | /* Get bank base */ | |
1460 | win_param.base_addr = mv_get_dram_bank_base_addr (BANK1); | |
1461 | win_param.size = mv_get_dram_bank_size (BANK1); /* Get bank size */ | |
1462 | if (win_param.size == 0) | |
1463 | win_param.enable = 0; | |
1464 | else | |
1465 | win_param.enable = 1; /* Enable the access */ | |
1466 | win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ | |
1467 | ||
1468 | /* Set the access control for address window (EPAPR) READ & WRITE */ | |
1469 | eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); | |
1470 | ||
1471 | /* Set access parameters for DRAM bank 2 */ | |
1472 | win_param.win = ETH_WIN2; /* Use Ethernet window 2 */ | |
1473 | win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ | |
1474 | win_param.attributes = EBAR_ATTR_DRAM_CS2; /* Enable DRAM bank */ | |
1475 | #ifndef CONFIG_NOT_COHERENT_CACHE | |
1476 | win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; | |
1477 | #endif | |
1478 | win_param.high_addr = 0; | |
1479 | /* Get bank base */ | |
1480 | win_param.base_addr = mv_get_dram_bank_base_addr (BANK2); | |
1481 | win_param.size = mv_get_dram_bank_size (BANK2); /* Get bank size */ | |
1482 | if (win_param.size == 0) | |
1483 | win_param.enable = 0; | |
1484 | else | |
1485 | win_param.enable = 1; /* Enable the access */ | |
1486 | win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ | |
1487 | ||
1488 | /* Set the access control for address window (EPAPR) READ & WRITE */ | |
1489 | eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); | |
1490 | ||
1491 | /* Set access parameters for DRAM bank 3 */ | |
1492 | win_param.win = ETH_WIN3; /* Use Ethernet window 3 */ | |
1493 | win_param.target = ETH_TARGET_DRAM; /* Window target - DDR */ | |
1494 | win_param.attributes = EBAR_ATTR_DRAM_CS3; /* Enable DRAM bank */ | |
1495 | #ifndef CONFIG_NOT_COHERENT_CACHE | |
1496 | win_param.attributes |= EBAR_ATTR_DRAM_CACHE_COHERENCY_WB; | |
1497 | #endif | |
1498 | win_param.high_addr = 0; | |
1499 | /* Get bank base */ | |
1500 | win_param.base_addr = mv_get_dram_bank_base_addr (BANK3); | |
1501 | win_param.size = mv_get_dram_bank_size (BANK3); /* Get bank size */ | |
1502 | if (win_param.size == 0) | |
1503 | win_param.enable = 0; | |
1504 | else | |
1505 | win_param.enable = 1; /* Enable the access */ | |
1506 | win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ | |
1507 | ||
1508 | /* Set the access control for address window (EPAPR) READ & WRITE */ | |
1509 | eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); | |
1510 | ||
1511 | /* Set access parameters for Internal SRAM */ | |
1512 | win_param.win = ETH_WIN4; /* Use Ethernet window 0 */ | |
1513 | win_param.target = EBAR_TARGET_CBS; /* Target - Internal SRAM */ | |
1514 | win_param.attributes = EBAR_ATTR_CBS_SRAM | EBAR_ATTR_CBS_SRAM_BLOCK0; | |
1515 | win_param.high_addr = 0; | |
1516 | win_param.base_addr = mv_get_internal_sram_base (); /* Get base addr */ | |
1517 | win_param.size = MV64360_INTERNAL_SRAM_SIZE; /* Get bank size */ | |
1518 | win_param.enable = 1; /* Enable the access */ | |
1519 | win_param.access_ctrl = EWIN_ACCESS_FULL; /* Enable full access */ | |
1520 | ||
1521 | /* Set the access control for address window (EPAPR) READ & WRITE */ | |
1522 | eth_set_access_control (p_eth_port_ctrl->port_num, &win_param); | |
1523 | ||
1524 | eth_port_init_mac_tables (p_eth_port_ctrl->port_num); | |
1525 | ||
1526 | ethernet_phy_set (p_eth_port_ctrl->port_num, | |
1527 | p_eth_port_ctrl->port_phy_addr); | |
1528 | ||
1529 | return; | |
1530 | ||
1531 | } | |
1532 | ||
1533 | /******************************************************************************* | |
1534 | * eth_port_start - Start the Ethernet port activity. | |
1535 | * | |
1536 | * DESCRIPTION: | |
1537 | * This routine prepares the Ethernet port for Rx and Tx activity: | |
1538 | * 1. Initialize Tx and Rx Current Descriptor Pointer for each queue that | |
1539 | * has been initialized a descriptor's ring (using ether_init_tx_desc_ring | |
1540 | * for Tx and ether_init_rx_desc_ring for Rx) | |
1541 | * 2. Initialize and enable the Ethernet configuration port by writing to | |
1542 | * the port's configuration and command registers. | |
1543 | * 3. Initialize and enable the SDMA by writing to the SDMA's | |
1544 | * configuration and command registers. | |
1545 | * After completing these steps, the ethernet port SDMA can starts to | |
1546 | * perform Rx and Tx activities. | |
1547 | * | |
1548 | * Note: Each Rx and Tx queue descriptor's list must be initialized prior | |
1549 | * to calling this function (use ether_init_tx_desc_ring for Tx queues and | |
1550 | * ether_init_rx_desc_ring for Rx queues). | |
1551 | * | |
1552 | * INPUT: | |
1553 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet port control struct | |
1554 | * | |
1555 | * OUTPUT: | |
1556 | * Ethernet port is ready to receive and transmit. | |
1557 | * | |
1558 | * RETURN: | |
1559 | * false if the port PHY is not up. | |
1560 | * true otherwise. | |
1561 | * | |
1562 | *******************************************************************************/ | |
1563 | static bool eth_port_start (ETH_PORT_INFO * p_eth_port_ctrl) | |
1564 | { | |
1565 | int queue; | |
1566 | volatile ETH_TX_DESC *p_tx_curr_desc; | |
1567 | volatile ETH_RX_DESC *p_rx_curr_desc; | |
1568 | unsigned int phy_reg_data; | |
1569 | ETH_PORT eth_port_num = p_eth_port_ctrl->port_num; | |
1570 | ||
1571 | ||
1572 | /* Assignment of Tx CTRP of given queue */ | |
1573 | for (queue = 0; queue < MAX_TX_QUEUE_NUM; queue++) { | |
1574 | CURR_TFD_GET (p_tx_curr_desc, queue); | |
1575 | MV_REG_WRITE ((MV64360_ETH_TX_CURRENT_QUEUE_DESC_PTR_0 | |
1576 | (eth_port_num) | |
1577 | + (4 * queue)), | |
1578 | ((unsigned int) p_tx_curr_desc)); | |
1579 | ||
1580 | } | |
1581 | ||
1582 | /* Assignment of Rx CRDP of given queue */ | |
1583 | for (queue = 0; queue < MAX_RX_QUEUE_NUM; queue++) { | |
1584 | CURR_RFD_GET (p_rx_curr_desc, queue); | |
1585 | MV_REG_WRITE ((MV64360_ETH_RX_CURRENT_QUEUE_DESC_PTR_0 | |
1586 | (eth_port_num) | |
1587 | + (4 * queue)), | |
1588 | ((unsigned int) p_rx_curr_desc)); | |
1589 | ||
1590 | if (p_rx_curr_desc != NULL) | |
1591 | /* Add the assigned Ethernet address to the port's address table */ | |
1592 | eth_port_uc_addr_set (p_eth_port_ctrl->port_num, | |
1593 | p_eth_port_ctrl->port_mac_addr, | |
1594 | queue); | |
1595 | } | |
1596 | ||
1597 | /* Assign port configuration and command. */ | |
1598 | MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), | |
1599 | p_eth_port_ctrl->port_config); | |
1600 | ||
1601 | MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), | |
1602 | p_eth_port_ctrl->port_config_extend); | |
1603 | ||
1604 | MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), | |
1605 | p_eth_port_ctrl->port_serial_control); | |
1606 | ||
1607 | MV_SET_REG_BITS (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), | |
1608 | ETH_SERIAL_PORT_ENABLE); | |
1609 | ||
1610 | /* Assign port SDMA configuration */ | |
1611 | MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), | |
1612 | p_eth_port_ctrl->port_sdma_config); | |
1613 | ||
1614 | MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_COUNT | |
1615 | (eth_port_num), 0x3fffffff); | |
1616 | MV_REG_WRITE (MV64360_ETH_TX_QUEUE_0_TOKEN_BUCKET_CONFIG | |
1617 | (eth_port_num), 0x03fffcff); | |
1618 | /* Turn off the port/queue bandwidth limitation */ | |
1619 | MV_REG_WRITE (MV64360_ETH_MAXIMUM_TRANSMIT_UNIT (eth_port_num), 0x0); | |
1620 | ||
1621 | /* Enable port Rx. */ | |
1622 | MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (eth_port_num), | |
1623 | p_eth_port_ctrl->port_rx_queue_command); | |
1624 | ||
1625 | /* Check if link is up */ | |
1626 | eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); | |
1627 | ||
1628 | if (!(phy_reg_data & 0x20)) | |
1629 | return false; | |
1630 | ||
1631 | return true; | |
1632 | } | |
1633 | ||
1634 | /******************************************************************************* | |
1635 | * eth_port_uc_addr_set - This function Set the port Unicast address. | |
1636 | * | |
1637 | * DESCRIPTION: | |
1638 | * This function Set the port Ethernet MAC address. | |
1639 | * | |
1640 | * INPUT: | |
1641 | * ETH_PORT eth_port_num Port number. | |
1642 | * char * p_addr Address to be set | |
1643 | * ETH_QUEUE queue Rx queue number for this MAC address. | |
1644 | * | |
1645 | * OUTPUT: | |
1646 | * Set MAC address low and high registers. also calls eth_port_uc_addr() | |
1647 | * To set the unicast table with the proper information. | |
1648 | * | |
1649 | * RETURN: | |
1650 | * N/A. | |
1651 | * | |
1652 | *******************************************************************************/ | |
1653 | static void eth_port_uc_addr_set (ETH_PORT eth_port_num, | |
1654 | unsigned char *p_addr, ETH_QUEUE queue) | |
1655 | { | |
1656 | unsigned int mac_h; | |
1657 | unsigned int mac_l; | |
1658 | ||
1659 | mac_l = (p_addr[4] << 8) | (p_addr[5]); | |
1660 | mac_h = (p_addr[0] << 24) | (p_addr[1] << 16) | | |
1661 | (p_addr[2] << 8) | (p_addr[3] << 0); | |
1662 | ||
1663 | MV_REG_WRITE (MV64360_ETH_MAC_ADDR_LOW (eth_port_num), mac_l); | |
1664 | MV_REG_WRITE (MV64360_ETH_MAC_ADDR_HIGH (eth_port_num), mac_h); | |
1665 | ||
1666 | /* Accept frames of this address */ | |
1667 | eth_port_uc_addr (eth_port_num, p_addr[5], queue, ACCEPT_MAC_ADDR); | |
1668 | ||
1669 | return; | |
1670 | } | |
1671 | ||
1672 | /******************************************************************************* | |
1673 | * eth_port_uc_addr - This function Set the port unicast address table | |
1674 | * | |
1675 | * DESCRIPTION: | |
1676 | * This function locates the proper entry in the Unicast table for the | |
1677 | * specified MAC nibble and sets its properties according to function | |
1678 | * parameters. | |
1679 | * | |
1680 | * INPUT: | |
1681 | * ETH_PORT eth_port_num Port number. | |
1682 | * unsigned char uc_nibble Unicast MAC Address last nibble. | |
1683 | * ETH_QUEUE queue Rx queue number for this MAC address. | |
1684 | * int option 0 = Add, 1 = remove address. | |
1685 | * | |
1686 | * OUTPUT: | |
1687 | * This function add/removes MAC addresses from the port unicast address | |
1688 | * table. | |
1689 | * | |
1690 | * RETURN: | |
1691 | * true is output succeeded. | |
1692 | * false if option parameter is invalid. | |
1693 | * | |
1694 | *******************************************************************************/ | |
1695 | static bool eth_port_uc_addr (ETH_PORT eth_port_num, | |
1696 | unsigned char uc_nibble, | |
1697 | ETH_QUEUE queue, int option) | |
1698 | { | |
1699 | unsigned int unicast_reg; | |
1700 | unsigned int tbl_offset; | |
1701 | unsigned int reg_offset; | |
1702 | ||
1703 | /* Locate the Unicast table entry */ | |
1704 | uc_nibble = (0xf & uc_nibble); | |
1705 | tbl_offset = (uc_nibble / 4) * 4; /* Register offset from unicast table base */ | |
1706 | reg_offset = uc_nibble % 4; /* Entry offset within the above register */ | |
1707 | ||
1708 | switch (option) { | |
1709 | case REJECT_MAC_ADDR: | |
1710 | /* Clear accepts frame bit at specified unicast DA table entry */ | |
1711 | unicast_reg = | |
1712 | MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE | |
1713 | (eth_port_num) | |
1714 | + tbl_offset)); | |
1715 | ||
1716 | unicast_reg &= (0x0E << (8 * reg_offset)); | |
1717 | ||
1718 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE | |
1719 | (eth_port_num) | |
1720 | + tbl_offset), unicast_reg); | |
1721 | break; | |
1722 | ||
1723 | case ACCEPT_MAC_ADDR: | |
1724 | /* Set accepts frame bit at unicast DA filter table entry */ | |
1725 | unicast_reg = | |
1726 | MV_REG_READ ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE | |
1727 | (eth_port_num) | |
1728 | + tbl_offset)); | |
1729 | ||
1730 | unicast_reg |= ((0x01 | queue) << (8 * reg_offset)); | |
1731 | ||
1732 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE | |
1733 | (eth_port_num) | |
1734 | + tbl_offset), unicast_reg); | |
1735 | ||
1736 | break; | |
1737 | ||
1738 | default: | |
1739 | return false; | |
1740 | } | |
1741 | return true; | |
1742 | } | |
1743 | ||
1744 | #if 0 /* FIXME */ | |
1745 | /******************************************************************************* | |
1746 | * eth_port_mc_addr - Multicast address settings. | |
1747 | * | |
1748 | * DESCRIPTION: | |
1749 | * This API controls the MV device MAC multicast support. | |
1750 | * The MV device supports multicast using two tables: | |
1751 | * 1) Special Multicast Table for MAC addresses of the form | |
1752 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). | |
1753 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
1754 | * Table entries in the DA-Filter table. | |
1755 | * In this case, the function calls eth_port_smc_addr() routine to set the | |
1756 | * Special Multicast Table. | |
1757 | * 2) Other Multicast Table for multicast of another type. A CRC-8bit | |
1758 | * is used as an index to the Other Multicast Table entries in the | |
1759 | * DA-Filter table. | |
1760 | * In this case, the function calculates the CRC-8bit value and calls | |
1761 | * eth_port_omc_addr() routine to set the Other Multicast Table. | |
1762 | * INPUT: | |
1763 | * ETH_PORT eth_port_num Port number. | |
1764 | * unsigned char *p_addr Unicast MAC Address. | |
1765 | * ETH_QUEUE queue Rx queue number for this MAC address. | |
1766 | * int option 0 = Add, 1 = remove address. | |
1767 | * | |
1768 | * OUTPUT: | |
1769 | * See description. | |
1770 | * | |
1771 | * RETURN: | |
1772 | * true is output succeeded. | |
1773 | * false if add_address_table_entry( ) failed. | |
1774 | * | |
1775 | *******************************************************************************/ | |
1776 | static void eth_port_mc_addr (ETH_PORT eth_port_num, | |
1777 | unsigned char *p_addr, | |
1778 | ETH_QUEUE queue, int option) | |
1779 | { | |
1780 | unsigned int mac_h; | |
1781 | unsigned int mac_l; | |
1782 | unsigned char crc_result = 0; | |
1783 | int mac_array[48]; | |
1784 | int crc[8]; | |
1785 | int i; | |
1786 | ||
1787 | ||
1788 | if ((p_addr[0] == 0x01) && | |
1789 | (p_addr[1] == 0x00) && | |
1790 | (p_addr[2] == 0x5E) && (p_addr[3] == 0x00) && (p_addr[4] == 0x00)) | |
1791 | ||
1792 | eth_port_smc_addr (eth_port_num, p_addr[5], queue, option); | |
1793 | else { | |
1794 | /* Calculate CRC-8 out of the given address */ | |
1795 | mac_h = (p_addr[0] << 8) | (p_addr[1]); | |
1796 | mac_l = (p_addr[2] << 24) | (p_addr[3] << 16) | | |
1797 | (p_addr[4] << 8) | (p_addr[5] << 0); | |
1798 | ||
1799 | for (i = 0; i < 32; i++) | |
1800 | mac_array[i] = (mac_l >> i) & 0x1; | |
1801 | for (i = 32; i < 48; i++) | |
1802 | mac_array[i] = (mac_h >> (i - 32)) & 0x1; | |
1803 | ||
1804 | ||
1805 | crc[0] = mac_array[45] ^ mac_array[43] ^ mac_array[40] ^ | |
1806 | mac_array[39] ^ mac_array[35] ^ mac_array[34] ^ | |
1807 | mac_array[31] ^ mac_array[30] ^ mac_array[28] ^ | |
1808 | mac_array[23] ^ mac_array[21] ^ mac_array[19] ^ | |
1809 | mac_array[18] ^ mac_array[16] ^ mac_array[14] ^ | |
1810 | mac_array[12] ^ mac_array[8] ^ mac_array[7] ^ | |
1811 | mac_array[6] ^ mac_array[0]; | |
1812 | ||
1813 | crc[1] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ | |
1814 | mac_array[43] ^ mac_array[41] ^ mac_array[39] ^ | |
1815 | mac_array[36] ^ mac_array[34] ^ mac_array[32] ^ | |
1816 | mac_array[30] ^ mac_array[29] ^ mac_array[28] ^ | |
1817 | mac_array[24] ^ mac_array[23] ^ mac_array[22] ^ | |
1818 | mac_array[21] ^ mac_array[20] ^ mac_array[18] ^ | |
1819 | mac_array[17] ^ mac_array[16] ^ mac_array[15] ^ | |
1820 | mac_array[14] ^ mac_array[13] ^ mac_array[12] ^ | |
1821 | mac_array[9] ^ mac_array[6] ^ mac_array[1] ^ | |
1822 | mac_array[0]; | |
1823 | ||
1824 | crc[2] = mac_array[47] ^ mac_array[46] ^ mac_array[44] ^ | |
1825 | mac_array[43] ^ mac_array[42] ^ mac_array[39] ^ | |
1826 | mac_array[37] ^ mac_array[34] ^ mac_array[33] ^ | |
1827 | mac_array[29] ^ mac_array[28] ^ mac_array[25] ^ | |
1828 | mac_array[24] ^ mac_array[22] ^ mac_array[17] ^ | |
1829 | mac_array[15] ^ mac_array[13] ^ mac_array[12] ^ | |
1830 | mac_array[10] ^ mac_array[8] ^ mac_array[6] ^ | |
1831 | mac_array[2] ^ mac_array[1] ^ mac_array[0]; | |
1832 | ||
1833 | crc[3] = mac_array[47] ^ mac_array[45] ^ mac_array[44] ^ | |
1834 | mac_array[43] ^ mac_array[40] ^ mac_array[38] ^ | |
1835 | mac_array[35] ^ mac_array[34] ^ mac_array[30] ^ | |
1836 | mac_array[29] ^ mac_array[26] ^ mac_array[25] ^ | |
1837 | mac_array[23] ^ mac_array[18] ^ mac_array[16] ^ | |
1838 | mac_array[14] ^ mac_array[13] ^ mac_array[11] ^ | |
1839 | mac_array[9] ^ mac_array[7] ^ mac_array[3] ^ | |
1840 | mac_array[2] ^ mac_array[1]; | |
1841 | ||
1842 | crc[4] = mac_array[46] ^ mac_array[45] ^ mac_array[44] ^ | |
1843 | mac_array[41] ^ mac_array[39] ^ mac_array[36] ^ | |
1844 | mac_array[35] ^ mac_array[31] ^ mac_array[30] ^ | |
1845 | mac_array[27] ^ mac_array[26] ^ mac_array[24] ^ | |
1846 | mac_array[19] ^ mac_array[17] ^ mac_array[15] ^ | |
1847 | mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ | |
1848 | mac_array[8] ^ mac_array[4] ^ mac_array[3] ^ | |
1849 | mac_array[2]; | |
1850 | ||
1851 | crc[5] = mac_array[47] ^ mac_array[46] ^ mac_array[45] ^ | |
1852 | mac_array[42] ^ mac_array[40] ^ mac_array[37] ^ | |
1853 | mac_array[36] ^ mac_array[32] ^ mac_array[31] ^ | |
1854 | mac_array[28] ^ mac_array[27] ^ mac_array[25] ^ | |
1855 | mac_array[20] ^ mac_array[18] ^ mac_array[16] ^ | |
1856 | mac_array[15] ^ mac_array[13] ^ mac_array[11] ^ | |
1857 | mac_array[9] ^ mac_array[5] ^ mac_array[4] ^ | |
1858 | mac_array[3]; | |
1859 | ||
1860 | crc[6] = mac_array[47] ^ mac_array[46] ^ mac_array[43] ^ | |
1861 | mac_array[41] ^ mac_array[38] ^ mac_array[37] ^ | |
1862 | mac_array[33] ^ mac_array[32] ^ mac_array[29] ^ | |
1863 | mac_array[28] ^ mac_array[26] ^ mac_array[21] ^ | |
1864 | mac_array[19] ^ mac_array[17] ^ mac_array[16] ^ | |
1865 | mac_array[14] ^ mac_array[12] ^ mac_array[10] ^ | |
1866 | mac_array[6] ^ mac_array[5] ^ mac_array[4]; | |
1867 | ||
1868 | crc[7] = mac_array[47] ^ mac_array[44] ^ mac_array[42] ^ | |
1869 | mac_array[39] ^ mac_array[38] ^ mac_array[34] ^ | |
1870 | mac_array[33] ^ mac_array[30] ^ mac_array[29] ^ | |
1871 | mac_array[27] ^ mac_array[22] ^ mac_array[20] ^ | |
1872 | mac_array[18] ^ mac_array[17] ^ mac_array[15] ^ | |
1873 | mac_array[13] ^ mac_array[11] ^ mac_array[7] ^ | |
1874 | mac_array[6] ^ mac_array[5]; | |
1875 | ||
1876 | for (i = 0; i < 8; i++) | |
1877 | crc_result = crc_result | (crc[i] << i); | |
1878 | ||
1879 | eth_port_omc_addr (eth_port_num, crc_result, queue, option); | |
1880 | } | |
1881 | return; | |
1882 | } | |
1883 | ||
1884 | /******************************************************************************* | |
1885 | * eth_port_smc_addr - Special Multicast address settings. | |
1886 | * | |
1887 | * DESCRIPTION: | |
1888 | * This routine controls the MV device special MAC multicast support. | |
1889 | * The Special Multicast Table for MAC addresses supports MAC of the form | |
1890 | * 0x01-00-5E-00-00-XX (where XX is between 0x00 and 0x_fF). | |
1891 | * The MAC DA[7:0] bits are used as a pointer to the Special Multicast | |
1892 | * Table entries in the DA-Filter table. | |
1893 | * This function set the Special Multicast Table appropriate entry | |
1894 | * according to the argument given. | |
1895 | * | |
1896 | * INPUT: | |
1897 | * ETH_PORT eth_port_num Port number. | |
1898 | * unsigned char mc_byte Multicast addr last byte (MAC DA[7:0] bits). | |
1899 | * ETH_QUEUE queue Rx queue number for this MAC address. | |
1900 | * int option 0 = Add, 1 = remove address. | |
1901 | * | |
1902 | * OUTPUT: | |
1903 | * See description. | |
1904 | * | |
1905 | * RETURN: | |
1906 | * true is output succeeded. | |
1907 | * false if option parameter is invalid. | |
1908 | * | |
1909 | *******************************************************************************/ | |
1910 | static bool eth_port_smc_addr (ETH_PORT eth_port_num, | |
1911 | unsigned char mc_byte, | |
1912 | ETH_QUEUE queue, int option) | |
1913 | { | |
1914 | unsigned int smc_table_reg; | |
1915 | unsigned int tbl_offset; | |
1916 | unsigned int reg_offset; | |
1917 | ||
1918 | /* Locate the SMC table entry */ | |
1919 | tbl_offset = (mc_byte / 4) * 4; /* Register offset from SMC table base */ | |
1920 | reg_offset = mc_byte % 4; /* Entry offset within the above register */ | |
1921 | queue &= 0x7; | |
1922 | ||
1923 | switch (option) { | |
1924 | case REJECT_MAC_ADDR: | |
1925 | /* Clear accepts frame bit at specified Special DA table entry */ | |
1926 | smc_table_reg = | |
1927 | MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); | |
1928 | smc_table_reg &= (0x0E << (8 * reg_offset)); | |
1929 | ||
1930 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); | |
1931 | break; | |
1932 | ||
1933 | case ACCEPT_MAC_ADDR: | |
1934 | /* Set accepts frame bit at specified Special DA table entry */ | |
1935 | smc_table_reg = | |
1936 | MV_REG_READ ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); | |
1937 | smc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); | |
1938 | ||
1939 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), smc_table_reg); | |
1940 | break; | |
1941 | ||
1942 | default: | |
1943 | return false; | |
1944 | } | |
1945 | return true; | |
1946 | } | |
1947 | ||
1948 | /******************************************************************************* | |
1949 | * eth_port_omc_addr - Multicast address settings. | |
1950 | * | |
1951 | * DESCRIPTION: | |
1952 | * This routine controls the MV device Other MAC multicast support. | |
1953 | * The Other Multicast Table is used for multicast of another type. | |
1954 | * A CRC-8bit is used as an index to the Other Multicast Table entries | |
1955 | * in the DA-Filter table. | |
1956 | * The function gets the CRC-8bit value from the calling routine and | |
1957 | * set the Other Multicast Table appropriate entry according to the | |
1958 | * CRC-8 argument given. | |
1959 | * | |
1960 | * INPUT: | |
1961 | * ETH_PORT eth_port_num Port number. | |
1962 | * unsigned char crc8 A CRC-8bit (Polynomial: x^8+x^2+x^1+1). | |
1963 | * ETH_QUEUE queue Rx queue number for this MAC address. | |
1964 | * int option 0 = Add, 1 = remove address. | |
1965 | * | |
1966 | * OUTPUT: | |
1967 | * See description. | |
1968 | * | |
1969 | * RETURN: | |
1970 | * true is output succeeded. | |
1971 | * false if option parameter is invalid. | |
1972 | * | |
1973 | *******************************************************************************/ | |
1974 | static bool eth_port_omc_addr (ETH_PORT eth_port_num, | |
1975 | unsigned char crc8, | |
1976 | ETH_QUEUE queue, int option) | |
1977 | { | |
1978 | unsigned int omc_table_reg; | |
1979 | unsigned int tbl_offset; | |
1980 | unsigned int reg_offset; | |
1981 | ||
1982 | /* Locate the OMC table entry */ | |
1983 | tbl_offset = (crc8 / 4) * 4; /* Register offset from OMC table base */ | |
1984 | reg_offset = crc8 % 4; /* Entry offset within the above register */ | |
1985 | queue &= 0x7; | |
1986 | ||
1987 | switch (option) { | |
1988 | case REJECT_MAC_ADDR: | |
1989 | /* Clear accepts frame bit at specified Other DA table entry */ | |
1990 | omc_table_reg = | |
1991 | MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); | |
1992 | omc_table_reg &= (0x0E << (8 * reg_offset)); | |
1993 | ||
1994 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); | |
1995 | break; | |
1996 | ||
1997 | case ACCEPT_MAC_ADDR: | |
1998 | /* Set accepts frame bit at specified Other DA table entry */ | |
1999 | omc_table_reg = | |
2000 | MV_REG_READ ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset)); | |
2001 | omc_table_reg |= ((0x01 | queue) << (8 * reg_offset)); | |
2002 | ||
2003 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + tbl_offset), omc_table_reg); | |
2004 | break; | |
2005 | ||
2006 | default: | |
2007 | return false; | |
2008 | } | |
2009 | return true; | |
2010 | } | |
2011 | #endif | |
2012 | ||
2013 | /******************************************************************************* | |
2014 | * eth_port_init_mac_tables - Clear all entrance in the UC, SMC and OMC tables | |
2015 | * | |
2016 | * DESCRIPTION: | |
2017 | * Go through all the DA filter tables (Unicast, Special Multicast & Other | |
2018 | * Multicast) and set each entry to 0. | |
2019 | * | |
2020 | * INPUT: | |
2021 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. | |
2022 | * | |
2023 | * OUTPUT: | |
2024 | * Multicast and Unicast packets are rejected. | |
2025 | * | |
2026 | * RETURN: | |
2027 | * None. | |
2028 | * | |
2029 | *******************************************************************************/ | |
2030 | static void eth_port_init_mac_tables (ETH_PORT eth_port_num) | |
2031 | { | |
2032 | int table_index; | |
2033 | ||
2034 | /* Clear DA filter unicast table (Ex_dFUT) */ | |
2035 | for (table_index = 0; table_index <= 0xC; table_index += 4) | |
2036 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_UNICAST_TABLE_BASE | |
2037 | (eth_port_num) + table_index), 0); | |
2038 | ||
2039 | for (table_index = 0; table_index <= 0xFC; table_index += 4) { | |
2040 | /* Clear DA filter special multicast table (Ex_dFSMT) */ | |
2041 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_SPECIAL_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); | |
2042 | /* Clear DA filter other multicast table (Ex_dFOMT) */ | |
2043 | MV_REG_WRITE ((MV64360_ETH_DA_FILTER_OTHER_MULTICAST_TABLE_BASE (eth_port_num) + table_index), 0); | |
2044 | } | |
2045 | } | |
2046 | ||
2047 | /******************************************************************************* | |
2048 | * eth_clear_mib_counters - Clear all MIB counters | |
2049 | * | |
2050 | * DESCRIPTION: | |
2051 | * This function clears all MIB counters of a specific ethernet port. | |
2052 | * A read from the MIB counter will reset the counter. | |
2053 | * | |
2054 | * INPUT: | |
2055 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. | |
2056 | * | |
2057 | * OUTPUT: | |
2058 | * After reading all MIB counters, the counters resets. | |
2059 | * | |
2060 | * RETURN: | |
2061 | * MIB counter value. | |
2062 | * | |
2063 | *******************************************************************************/ | |
2064 | static void eth_clear_mib_counters (ETH_PORT eth_port_num) | |
2065 | { | |
2066 | int i; | |
2067 | unsigned int dummy; | |
2068 | ||
2069 | /* Perform dummy reads from MIB counters */ | |
2070 | for (i = ETH_MIB_GOOD_OCTETS_RECEIVED_LOW; i < ETH_MIB_LATE_COLLISION; | |
2071 | i += 4) | |
2072 | dummy = MV_REG_READ ((MV64360_ETH_MIB_COUNTERS_BASE | |
2073 | (eth_port_num) + i)); | |
2074 | ||
2075 | return; | |
2076 | } | |
2077 | ||
2078 | /******************************************************************************* | |
2079 | * eth_read_mib_counter - Read a MIB counter | |
2080 | * | |
2081 | * DESCRIPTION: | |
2082 | * This function reads a MIB counter of a specific ethernet port. | |
2083 | * NOTE - If read from ETH_MIB_GOOD_OCTETS_RECEIVED_LOW, then the | |
2084 | * following read must be from ETH_MIB_GOOD_OCTETS_RECEIVED_HIGH | |
2085 | * register. The same applies for ETH_MIB_GOOD_OCTETS_SENT_LOW and | |
2086 | * ETH_MIB_GOOD_OCTETS_SENT_HIGH | |
2087 | * | |
2088 | * INPUT: | |
2089 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. | |
2090 | * unsigned int mib_offset MIB counter offset (use ETH_MIB_... macros). | |
2091 | * | |
2092 | * OUTPUT: | |
2093 | * After reading the MIB counter, the counter resets. | |
2094 | * | |
2095 | * RETURN: | |
2096 | * MIB counter value. | |
2097 | * | |
2098 | *******************************************************************************/ | |
2099 | unsigned int eth_read_mib_counter (ETH_PORT eth_port_num, | |
2100 | unsigned int mib_offset) | |
2101 | { | |
2102 | return (MV_REG_READ (MV64360_ETH_MIB_COUNTERS_BASE (eth_port_num) | |
2103 | + mib_offset)); | |
2104 | } | |
2105 | ||
2106 | /******************************************************************************* | |
2107 | * ethernet_phy_set - Set the ethernet port PHY address. | |
2108 | * | |
2109 | * DESCRIPTION: | |
2110 | * This routine set the ethernet port PHY address according to given | |
2111 | * parameter. | |
2112 | * | |
2113 | * INPUT: | |
2114 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. | |
2115 | * | |
2116 | * OUTPUT: | |
2117 | * Set PHY Address Register with given PHY address parameter. | |
2118 | * | |
2119 | * RETURN: | |
2120 | * None. | |
2121 | * | |
2122 | *******************************************************************************/ | |
2123 | static void ethernet_phy_set (ETH_PORT eth_port_num, int phy_addr) | |
2124 | { | |
2125 | unsigned int reg_data; | |
2126 | ||
2127 | reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); | |
2128 | ||
2129 | reg_data &= ~(0x1F << (5 * eth_port_num)); | |
2130 | reg_data |= (phy_addr << (5 * eth_port_num)); | |
2131 | ||
2132 | MV_REG_WRITE (MV64360_ETH_PHY_ADDR_REG, reg_data); | |
2133 | ||
2134 | return; | |
2135 | } | |
2136 | ||
2137 | /******************************************************************************* | |
2138 | * ethernet_phy_get - Get the ethernet port PHY address. | |
2139 | * | |
2140 | * DESCRIPTION: | |
2141 | * This routine returns the given ethernet port PHY address. | |
2142 | * | |
2143 | * INPUT: | |
2144 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. | |
2145 | * | |
2146 | * OUTPUT: | |
2147 | * None. | |
2148 | * | |
2149 | * RETURN: | |
2150 | * PHY address. | |
2151 | * | |
2152 | *******************************************************************************/ | |
2153 | static int ethernet_phy_get (ETH_PORT eth_port_num) | |
2154 | { | |
2155 | unsigned int reg_data; | |
2156 | ||
2157 | reg_data = MV_REG_READ (MV64360_ETH_PHY_ADDR_REG); | |
2158 | ||
2159 | return ((reg_data >> (5 * eth_port_num)) & 0x1f); | |
2160 | } | |
2161 | ||
2162 | /******************************************************************************* | |
2163 | * ethernet_phy_reset - Reset Ethernet port PHY. | |
2164 | * | |
2165 | * DESCRIPTION: | |
2166 | * This routine utilize the SMI interface to reset the ethernet port PHY. | |
2167 | * The routine waits until the link is up again or link up is timeout. | |
2168 | * | |
2169 | * INPUT: | |
2170 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. | |
2171 | * | |
2172 | * OUTPUT: | |
2173 | * The ethernet port PHY renew its link. | |
2174 | * | |
2175 | * RETURN: | |
2176 | * None. | |
2177 | * | |
2178 | *******************************************************************************/ | |
2179 | static bool ethernet_phy_reset (ETH_PORT eth_port_num) | |
2180 | { | |
2181 | unsigned int time_out = 50; | |
2182 | unsigned int phy_reg_data; | |
2183 | ||
2184 | /* Reset the PHY */ | |
2185 | eth_port_read_smi_reg (eth_port_num, 0, &phy_reg_data); | |
2186 | phy_reg_data |= 0x8000; /* Set bit 15 to reset the PHY */ | |
2187 | eth_port_write_smi_reg (eth_port_num, 0, phy_reg_data); | |
2188 | ||
2189 | /* Poll on the PHY LINK */ | |
2190 | do { | |
2191 | eth_port_read_smi_reg (eth_port_num, 1, &phy_reg_data); | |
2192 | ||
2193 | if (time_out-- == 0) | |
2194 | return false; | |
2195 | } | |
2196 | while (!(phy_reg_data & 0x20)); | |
2197 | ||
2198 | return true; | |
2199 | } | |
2200 | ||
2201 | /******************************************************************************* | |
2202 | * eth_port_reset - Reset Ethernet port | |
2203 | * | |
2204 | * DESCRIPTION: | |
2205 | * This routine resets the chip by aborting any SDMA engine activity and | |
2206 | * clearing the MIB counters. The Receiver and the Transmit unit are in | |
2207 | * idle state after this command is performed and the port is disabled. | |
2208 | * | |
2209 | * INPUT: | |
2210 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. | |
2211 | * | |
2212 | * OUTPUT: | |
2213 | * Channel activity is halted. | |
2214 | * | |
2215 | * RETURN: | |
2216 | * None. | |
2217 | * | |
2218 | *******************************************************************************/ | |
2219 | static void eth_port_reset (ETH_PORT eth_port_num) | |
2220 | { | |
2221 | unsigned int reg_data; | |
2222 | ||
2223 | /* Stop Tx port activity. Check port Tx activity. */ | |
2224 | reg_data = | |
2225 | MV_REG_READ (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG | |
2226 | (eth_port_num)); | |
2227 | ||
2228 | if (reg_data & 0xFF) { | |
2229 | /* Issue stop command for active channels only */ | |
2230 | MV_REG_WRITE (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG | |
2231 | (eth_port_num), (reg_data << 8)); | |
2232 | ||
2233 | /* Wait for all Tx activity to terminate. */ | |
2234 | do { | |
2235 | /* Check port cause register that all Tx queues are stopped */ | |
2236 | reg_data = | |
2237 | MV_REG_READ | |
2238 | (MV64360_ETH_TRANSMIT_QUEUE_COMMAND_REG | |
2239 | (eth_port_num)); | |
2240 | } | |
2241 | while (reg_data & 0xFF); | |
2242 | } | |
2243 | ||
2244 | /* Stop Rx port activity. Check port Rx activity. */ | |
2245 | reg_data = | |
2246 | MV_REG_READ (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG | |
2247 | (eth_port_num)); | |
2248 | ||
2249 | if (reg_data & 0xFF) { | |
2250 | /* Issue stop command for active channels only */ | |
2251 | MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG | |
2252 | (eth_port_num), (reg_data << 8)); | |
2253 | ||
2254 | /* Wait for all Rx activity to terminate. */ | |
2255 | do { | |
2256 | /* Check port cause register that all Rx queues are stopped */ | |
2257 | reg_data = | |
2258 | MV_REG_READ | |
2259 | (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG | |
2260 | (eth_port_num)); | |
2261 | } | |
2262 | while (reg_data & 0xFF); | |
2263 | } | |
2264 | ||
2265 | ||
2266 | /* Clear all MIB counters */ | |
2267 | eth_clear_mib_counters (eth_port_num); | |
2268 | ||
2269 | /* Reset the Enable bit in the Configuration Register */ | |
2270 | reg_data = | |
2271 | MV_REG_READ (MV64360_ETH_PORT_SERIAL_CONTROL_REG | |
2272 | (eth_port_num)); | |
2273 | reg_data &= ~ETH_SERIAL_PORT_ENABLE; | |
2274 | MV_REG_WRITE (MV64360_ETH_PORT_SERIAL_CONTROL_REG (eth_port_num), | |
2275 | reg_data); | |
2276 | ||
2277 | return; | |
2278 | } | |
2279 | ||
2280 | #if 0 /* Not needed here */ | |
2281 | /******************************************************************************* | |
2282 | * ethernet_set_config_reg - Set specified bits in configuration register. | |
2283 | * | |
2284 | * DESCRIPTION: | |
2285 | * This function sets specified bits in the given ethernet | |
2286 | * configuration register. | |
2287 | * | |
2288 | * INPUT: | |
2289 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. | |
2290 | * unsigned int value 32 bit value. | |
2291 | * | |
2292 | * OUTPUT: | |
2293 | * The set bits in the value parameter are set in the configuration | |
2294 | * register. | |
2295 | * | |
2296 | * RETURN: | |
2297 | * None. | |
2298 | * | |
2299 | *******************************************************************************/ | |
2300 | static void ethernet_set_config_reg (ETH_PORT eth_port_num, | |
2301 | unsigned int value) | |
2302 | { | |
2303 | unsigned int eth_config_reg; | |
2304 | ||
2305 | eth_config_reg = | |
2306 | MV_REG_READ (MV64360_ETH_PORT_CONFIG_REG (eth_port_num)); | |
2307 | eth_config_reg |= value; | |
2308 | MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_REG (eth_port_num), | |
2309 | eth_config_reg); | |
2310 | ||
2311 | return; | |
2312 | } | |
2313 | #endif | |
2314 | ||
2315 | #if 0 /* FIXME */ | |
2316 | /******************************************************************************* | |
2317 | * ethernet_reset_config_reg - Reset specified bits in configuration register. | |
2318 | * | |
2319 | * DESCRIPTION: | |
2320 | * This function resets specified bits in the given Ethernet | |
2321 | * configuration register. | |
2322 | * | |
2323 | * INPUT: | |
2324 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. | |
2325 | * unsigned int value 32 bit value. | |
2326 | * | |
2327 | * OUTPUT: | |
2328 | * The set bits in the value parameter are reset in the configuration | |
2329 | * register. | |
2330 | * | |
2331 | * RETURN: | |
2332 | * None. | |
2333 | * | |
2334 | *******************************************************************************/ | |
2335 | static void ethernet_reset_config_reg (ETH_PORT eth_port_num, | |
2336 | unsigned int value) | |
2337 | { | |
2338 | unsigned int eth_config_reg; | |
2339 | ||
2340 | eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG | |
2341 | (eth_port_num)); | |
2342 | eth_config_reg &= ~value; | |
2343 | MV_REG_WRITE (MV64360_ETH_PORT_CONFIG_EXTEND_REG (eth_port_num), | |
2344 | eth_config_reg); | |
2345 | ||
2346 | return; | |
2347 | } | |
2348 | #endif | |
2349 | ||
2350 | #if 0 /* Not needed here */ | |
2351 | /******************************************************************************* | |
2352 | * ethernet_get_config_reg - Get the port configuration register | |
2353 | * | |
2354 | * DESCRIPTION: | |
2355 | * This function returns the configuration register value of the given | |
2356 | * ethernet port. | |
2357 | * | |
2358 | * INPUT: | |
2359 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. | |
2360 | * | |
2361 | * OUTPUT: | |
2362 | * None. | |
2363 | * | |
2364 | * RETURN: | |
2365 | * Port configuration register value. | |
2366 | * | |
2367 | *******************************************************************************/ | |
2368 | static unsigned int ethernet_get_config_reg (ETH_PORT eth_port_num) | |
2369 | { | |
2370 | unsigned int eth_config_reg; | |
2371 | ||
2372 | eth_config_reg = MV_REG_READ (MV64360_ETH_PORT_CONFIG_EXTEND_REG | |
2373 | (eth_port_num)); | |
2374 | return eth_config_reg; | |
2375 | } | |
2376 | ||
2377 | #endif | |
2378 | ||
2379 | /******************************************************************************* | |
2380 | * eth_port_read_smi_reg - Read PHY registers | |
2381 | * | |
2382 | * DESCRIPTION: | |
2383 | * This routine utilize the SMI interface to interact with the PHY in | |
2384 | * order to perform PHY register read. | |
2385 | * | |
2386 | * INPUT: | |
2387 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. | |
2388 | * unsigned int phy_reg PHY register address offset. | |
2389 | * unsigned int *value Register value buffer. | |
2390 | * | |
2391 | * OUTPUT: | |
2392 | * Write the value of a specified PHY register into given buffer. | |
2393 | * | |
2394 | * RETURN: | |
2395 | * false if the PHY is busy or read data is not in valid state. | |
2396 | * true otherwise. | |
2397 | * | |
2398 | *******************************************************************************/ | |
2399 | static bool eth_port_read_smi_reg (ETH_PORT eth_port_num, | |
2400 | unsigned int phy_reg, unsigned int *value) | |
2401 | { | |
2402 | unsigned int reg_value; | |
2403 | unsigned int time_out = PHY_BUSY_TIMEOUT; | |
2404 | int phy_addr; | |
2405 | ||
2406 | phy_addr = ethernet_phy_get (eth_port_num); | |
2407 | /* printf(" Phy-Port %d has addess %d \n",eth_port_num, phy_addr );*/ | |
2408 | ||
2409 | /* first check that it is not busy */ | |
2410 | do { | |
2411 | reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); | |
2412 | if (time_out-- == 0) { | |
2413 | return false; | |
2414 | } | |
2415 | } | |
2416 | while (reg_value & ETH_SMI_BUSY); | |
2417 | ||
2418 | /* not busy */ | |
2419 | ||
2420 | MV_REG_WRITE (MV64360_ETH_SMI_REG, | |
2421 | (phy_addr << 16) | (phy_reg << 21) | | |
2422 | ETH_SMI_OPCODE_READ); | |
2423 | ||
2424 | time_out = PHY_BUSY_TIMEOUT; /* initialize the time out var again */ | |
2425 | ||
2426 | do { | |
2427 | reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); | |
2428 | if (time_out-- == 0) { | |
2429 | return false; | |
2430 | } | |
2431 | } | |
2432 | while ((reg_value & ETH_SMI_READ_VALID) != ETH_SMI_READ_VALID); /* Bit set equ operation done */ | |
2433 | ||
2434 | /* Wait for the data to update in the SMI register */ | |
2435 | #define PHY_UPDATE_TIMEOUT 10000 | |
2436 | for (time_out = 0; time_out < PHY_UPDATE_TIMEOUT; time_out++); | |
2437 | ||
2438 | reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); | |
2439 | ||
2440 | *value = reg_value & 0xffff; | |
2441 | ||
2442 | return true; | |
2443 | } | |
2444 | ||
2445 | /******************************************************************************* | |
2446 | * eth_port_write_smi_reg - Write to PHY registers | |
2447 | * | |
2448 | * DESCRIPTION: | |
2449 | * This routine utilize the SMI interface to interact with the PHY in | |
2450 | * order to perform writes to PHY registers. | |
2451 | * | |
2452 | * INPUT: | |
2453 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. | |
2454 | * unsigned int phy_reg PHY register address offset. | |
2455 | * unsigned int value Register value. | |
2456 | * | |
2457 | * OUTPUT: | |
2458 | * Write the given value to the specified PHY register. | |
2459 | * | |
2460 | * RETURN: | |
2461 | * false if the PHY is busy. | |
2462 | * true otherwise. | |
2463 | * | |
2464 | *******************************************************************************/ | |
2465 | static bool eth_port_write_smi_reg (ETH_PORT eth_port_num, | |
2466 | unsigned int phy_reg, unsigned int value) | |
2467 | { | |
2468 | unsigned int reg_value; | |
2469 | unsigned int time_out = PHY_BUSY_TIMEOUT; | |
2470 | int phy_addr; | |
2471 | ||
2472 | phy_addr = ethernet_phy_get (eth_port_num); | |
2473 | ||
2474 | /* first check that it is not busy */ | |
2475 | do { | |
2476 | reg_value = MV_REG_READ (MV64360_ETH_SMI_REG); | |
2477 | if (time_out-- == 0) { | |
2478 | return false; | |
2479 | } | |
2480 | } | |
2481 | while (reg_value & ETH_SMI_BUSY); | |
2482 | ||
2483 | /* not busy */ | |
2484 | MV_REG_WRITE (MV64360_ETH_SMI_REG, | |
2485 | (phy_addr << 16) | (phy_reg << 21) | | |
2486 | ETH_SMI_OPCODE_WRITE | (value & 0xffff)); | |
2487 | return true; | |
2488 | } | |
2489 | ||
2490 | /******************************************************************************* | |
2491 | * eth_set_access_control - Config address decode parameters for Ethernet unit | |
2492 | * | |
2493 | * DESCRIPTION: | |
2494 | * This function configures the address decode parameters for the Gigabit | |
2495 | * Ethernet Controller according the given parameters struct. | |
2496 | * | |
2497 | * INPUT: | |
2498 | * ETH_PORT eth_port_num Ethernet Port number. See ETH_PORT enum. | |
2499 | * ETH_WIN_PARAM *param Address decode parameter struct. | |
2500 | * | |
2501 | * OUTPUT: | |
2502 | * An access window is opened using the given access parameters. | |
2503 | * | |
2504 | * RETURN: | |
2505 | * None. | |
2506 | * | |
2507 | *******************************************************************************/ | |
2508 | static void eth_set_access_control (ETH_PORT eth_port_num, | |
2509 | ETH_WIN_PARAM * param) | |
2510 | { | |
2511 | unsigned int access_prot_reg; | |
2512 | ||
2513 | /* Set access control register */ | |
2514 | access_prot_reg = MV_REG_READ (MV64360_ETH_ACCESS_PROTECTION_REG | |
2515 | (eth_port_num)); | |
2516 | access_prot_reg &= (~(3 << (param->win * 2))); /* clear window permission */ | |
2517 | access_prot_reg |= (param->access_ctrl << (param->win * 2)); | |
2518 | MV_REG_WRITE (MV64360_ETH_ACCESS_PROTECTION_REG (eth_port_num), | |
2519 | access_prot_reg); | |
2520 | ||
2521 | /* Set window Size reg (SR) */ | |
2522 | MV_REG_WRITE ((MV64360_ETH_SIZE_REG_0 + | |
2523 | (ETH_SIZE_REG_GAP * param->win)), | |
2524 | (((param->size / 0x10000) - 1) << 16)); | |
2525 | ||
2526 | /* Set window Base address reg (BA) */ | |
2527 | MV_REG_WRITE ((MV64360_ETH_BAR_0 + (ETH_BAR_GAP * param->win)), | |
2528 | (param->target | param->attributes | param->base_addr)); | |
2529 | /* High address remap reg (HARR) */ | |
2530 | if (param->win < 4) | |
2531 | MV_REG_WRITE ((MV64360_ETH_HIGH_ADDR_REMAP_REG_0 + | |
2532 | (ETH_HIGH_ADDR_REMAP_REG_GAP * param->win)), | |
2533 | param->high_addr); | |
2534 | ||
2535 | /* Base address enable reg (BARER) */ | |
2536 | if (param->enable == 1) | |
2537 | MV_RESET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, | |
2538 | (1 << param->win)); | |
2539 | else | |
2540 | MV_SET_REG_BITS (MV64360_ETH_BASE_ADDR_ENABLE_REG, | |
2541 | (1 << param->win)); | |
2542 | } | |
2543 | ||
2544 | /******************************************************************************* | |
2545 | * ether_init_rx_desc_ring - Curve a Rx chain desc list and buffer in memory. | |
2546 | * | |
2547 | * DESCRIPTION: | |
2548 | * This function prepares a Rx chained list of descriptors and packet | |
2549 | * buffers in a form of a ring. The routine must be called after port | |
2550 | * initialization routine and before port start routine. | |
2551 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
2552 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
2553 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
2554 | * with physical addresses. | |
2555 | * | |
2556 | * INPUT: | |
2557 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. | |
2558 | * ETH_QUEUE rx_queue Number of Rx queue. | |
2559 | * int rx_desc_num Number of Rx descriptors | |
2560 | * int rx_buff_size Size of Rx buffer | |
2561 | * unsigned int rx_desc_base_addr Rx descriptors memory area base addr. | |
2562 | * unsigned int rx_buff_base_addr Rx buffer memory area base addr. | |
2563 | * | |
2564 | * OUTPUT: | |
2565 | * The routine updates the Ethernet port control struct with information | |
2566 | * regarding the Rx descriptors and buffers. | |
2567 | * | |
2568 | * RETURN: | |
2569 | * false if the given descriptors memory area is not aligned according to | |
2570 | * Ethernet SDMA specifications. | |
2571 | * true otherwise. | |
2572 | * | |
2573 | *******************************************************************************/ | |
2574 | static bool ether_init_rx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, | |
2575 | ETH_QUEUE rx_queue, | |
2576 | int rx_desc_num, | |
2577 | int rx_buff_size, | |
2578 | unsigned int rx_desc_base_addr, | |
2579 | unsigned int rx_buff_base_addr) | |
2580 | { | |
2581 | ETH_RX_DESC *p_rx_desc; | |
2582 | ETH_RX_DESC *p_rx_prev_desc; /* pointer to link with the last descriptor */ | |
2583 | unsigned int buffer_addr; | |
2584 | int ix; /* a counter */ | |
2585 | ||
2586 | ||
2587 | p_rx_desc = (ETH_RX_DESC *) rx_desc_base_addr; | |
2588 | p_rx_prev_desc = p_rx_desc; | |
2589 | buffer_addr = rx_buff_base_addr; | |
2590 | ||
2591 | /* Rx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ | |
2592 | if (rx_buff_base_addr & 0xF) | |
2593 | return false; | |
2594 | ||
2595 | /* Rx buffers are limited to 64K bytes and Minimum size is 8 bytes */ | |
2596 | if ((rx_buff_size < 8) || (rx_buff_size > RX_BUFFER_MAX_SIZE)) | |
2597 | return false; | |
2598 | ||
2599 | /* Rx buffers must be 64-bit aligned. */ | |
2600 | if ((rx_buff_base_addr + rx_buff_size) & 0x7) | |
2601 | return false; | |
2602 | ||
2603 | /* initialize the Rx descriptors ring */ | |
2604 | for (ix = 0; ix < rx_desc_num; ix++) { | |
2605 | p_rx_desc->buf_size = rx_buff_size; | |
2606 | p_rx_desc->byte_cnt = 0x0000; | |
2607 | p_rx_desc->cmd_sts = | |
2608 | ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; | |
2609 | p_rx_desc->next_desc_ptr = | |
2610 | ((unsigned int) p_rx_desc) + RX_DESC_ALIGNED_SIZE; | |
2611 | p_rx_desc->buf_ptr = buffer_addr; | |
2612 | p_rx_desc->return_info = 0x00000000; | |
2613 | D_CACHE_FLUSH_LINE (p_rx_desc, 0); | |
2614 | buffer_addr += rx_buff_size; | |
2615 | p_rx_prev_desc = p_rx_desc; | |
2616 | p_rx_desc = (ETH_RX_DESC *) | |
2617 | ((unsigned int) p_rx_desc + RX_DESC_ALIGNED_SIZE); | |
2618 | } | |
2619 | ||
2620 | /* Closing Rx descriptors ring */ | |
2621 | p_rx_prev_desc->next_desc_ptr = (rx_desc_base_addr); | |
2622 | D_CACHE_FLUSH_LINE (p_rx_prev_desc, 0); | |
2623 | ||
2624 | /* Save Rx desc pointer to driver struct. */ | |
2625 | CURR_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); | |
2626 | USED_RFD_SET ((ETH_RX_DESC *) rx_desc_base_addr, rx_queue); | |
2627 | ||
2628 | p_eth_port_ctrl->p_rx_desc_area_base[rx_queue] = | |
2629 | (ETH_RX_DESC *) rx_desc_base_addr; | |
2630 | p_eth_port_ctrl->rx_desc_area_size[rx_queue] = | |
2631 | rx_desc_num * RX_DESC_ALIGNED_SIZE; | |
2632 | ||
2633 | p_eth_port_ctrl->port_rx_queue_command |= (1 << rx_queue); | |
2634 | ||
2635 | return true; | |
2636 | } | |
2637 | ||
2638 | /******************************************************************************* | |
2639 | * ether_init_tx_desc_ring - Curve a Tx chain desc list and buffer in memory. | |
2640 | * | |
2641 | * DESCRIPTION: | |
2642 | * This function prepares a Tx chained list of descriptors and packet | |
2643 | * buffers in a form of a ring. The routine must be called after port | |
2644 | * initialization routine and before port start routine. | |
2645 | * The Ethernet SDMA engine uses CPU bus addresses to access the various | |
2646 | * devices in the system (i.e. DRAM). This function uses the ethernet | |
2647 | * struct 'virtual to physical' routine (set by the user) to set the ring | |
2648 | * with physical addresses. | |
2649 | * | |
2650 | * INPUT: | |
2651 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. | |
2652 | * ETH_QUEUE tx_queue Number of Tx queue. | |
2653 | * int tx_desc_num Number of Tx descriptors | |
2654 | * int tx_buff_size Size of Tx buffer | |
2655 | * unsigned int tx_desc_base_addr Tx descriptors memory area base addr. | |
2656 | * unsigned int tx_buff_base_addr Tx buffer memory area base addr. | |
2657 | * | |
2658 | * OUTPUT: | |
2659 | * The routine updates the Ethernet port control struct with information | |
2660 | * regarding the Tx descriptors and buffers. | |
2661 | * | |
2662 | * RETURN: | |
2663 | * false if the given descriptors memory area is not aligned according to | |
2664 | * Ethernet SDMA specifications. | |
2665 | * true otherwise. | |
2666 | * | |
2667 | *******************************************************************************/ | |
2668 | static bool ether_init_tx_desc_ring (ETH_PORT_INFO * p_eth_port_ctrl, | |
2669 | ETH_QUEUE tx_queue, | |
2670 | int tx_desc_num, | |
2671 | int tx_buff_size, | |
2672 | unsigned int tx_desc_base_addr, | |
2673 | unsigned int tx_buff_base_addr) | |
2674 | { | |
2675 | ||
2676 | ETH_TX_DESC *p_tx_desc; | |
2677 | ETH_TX_DESC *p_tx_prev_desc; | |
2678 | unsigned int buffer_addr; | |
2679 | int ix; /* a counter */ | |
2680 | ||
2681 | ||
2682 | /* save the first desc pointer to link with the last descriptor */ | |
2683 | p_tx_desc = (ETH_TX_DESC *) tx_desc_base_addr; | |
2684 | p_tx_prev_desc = p_tx_desc; | |
2685 | buffer_addr = tx_buff_base_addr; | |
2686 | ||
2687 | /* Tx desc Must be 4LW aligned (i.e. Descriptor_Address[3:0]=0000). */ | |
2688 | if (tx_buff_base_addr & 0xF) | |
2689 | return false; | |
2690 | ||
2691 | /* Tx buffers are limited to 64K bytes and Minimum size is 8 bytes */ | |
2692 | if ((tx_buff_size > TX_BUFFER_MAX_SIZE) | |
2693 | || (tx_buff_size < TX_BUFFER_MIN_SIZE)) | |
2694 | return false; | |
2695 | ||
2696 | /* Initialize the Tx descriptors ring */ | |
2697 | for (ix = 0; ix < tx_desc_num; ix++) { | |
2698 | p_tx_desc->byte_cnt = 0x0000; | |
2699 | p_tx_desc->l4i_chk = 0x0000; | |
2700 | p_tx_desc->cmd_sts = 0x00000000; | |
2701 | p_tx_desc->next_desc_ptr = | |
2702 | ((unsigned int) p_tx_desc) + TX_DESC_ALIGNED_SIZE; | |
2703 | ||
2704 | p_tx_desc->buf_ptr = buffer_addr; | |
2705 | p_tx_desc->return_info = 0x00000000; | |
2706 | D_CACHE_FLUSH_LINE (p_tx_desc, 0); | |
2707 | buffer_addr += tx_buff_size; | |
2708 | p_tx_prev_desc = p_tx_desc; | |
2709 | p_tx_desc = (ETH_TX_DESC *) | |
2710 | ((unsigned int) p_tx_desc + TX_DESC_ALIGNED_SIZE); | |
2711 | ||
2712 | } | |
2713 | /* Closing Tx descriptors ring */ | |
2714 | p_tx_prev_desc->next_desc_ptr = tx_desc_base_addr; | |
2715 | D_CACHE_FLUSH_LINE (p_tx_prev_desc, 0); | |
2716 | /* Set Tx desc pointer in driver struct. */ | |
2717 | CURR_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); | |
2718 | USED_TFD_SET ((ETH_TX_DESC *) tx_desc_base_addr, tx_queue); | |
2719 | ||
2720 | /* Init Tx ring base and size parameters */ | |
2721 | p_eth_port_ctrl->p_tx_desc_area_base[tx_queue] = | |
2722 | (ETH_TX_DESC *) tx_desc_base_addr; | |
2723 | p_eth_port_ctrl->tx_desc_area_size[tx_queue] = | |
2724 | (tx_desc_num * TX_DESC_ALIGNED_SIZE); | |
2725 | ||
2726 | /* Add the queue to the list of Tx queues of this port */ | |
2727 | p_eth_port_ctrl->port_tx_queue_command |= (1 << tx_queue); | |
2728 | ||
2729 | return true; | |
2730 | } | |
2731 | ||
2732 | /******************************************************************************* | |
2733 | * eth_port_send - Send an Ethernet packet | |
2734 | * | |
2735 | * DESCRIPTION: | |
2736 | * This routine send a given packet described by p_pktinfo parameter. It | |
2737 | * supports transmitting of a packet spaned over multiple buffers. The | |
2738 | * routine updates 'curr' and 'first' indexes according to the packet | |
2739 | * segment passed to the routine. In case the packet segment is first, | |
2740 | * the 'first' index is update. In any case, the 'curr' index is updated. | |
2741 | * If the routine get into Tx resource error it assigns 'curr' index as | |
2742 | * 'first'. This way the function can abort Tx process of multiple | |
2743 | * descriptors per packet. | |
2744 | * | |
2745 | * INPUT: | |
2746 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. | |
2747 | * ETH_QUEUE tx_queue Number of Tx queue. | |
2748 | * PKT_INFO *p_pkt_info User packet buffer. | |
2749 | * | |
2750 | * OUTPUT: | |
2751 | * Tx ring 'curr' and 'first' indexes are updated. | |
2752 | * | |
2753 | * RETURN: | |
2754 | * ETH_QUEUE_FULL in case of Tx resource error. | |
2755 | * ETH_ERROR in case the routine can not access Tx desc ring. | |
2756 | * ETH_QUEUE_LAST_RESOURCE if the routine uses the last Tx resource. | |
2757 | * ETH_OK otherwise. | |
2758 | * | |
2759 | *******************************************************************************/ | |
2760 | static ETH_FUNC_RET_STATUS eth_port_send (ETH_PORT_INFO * p_eth_port_ctrl, | |
2761 | ETH_QUEUE tx_queue, | |
2762 | PKT_INFO * p_pkt_info) | |
2763 | { | |
2764 | volatile ETH_TX_DESC *p_tx_desc_first; | |
2765 | volatile ETH_TX_DESC *p_tx_desc_curr; | |
2766 | volatile ETH_TX_DESC *p_tx_next_desc_curr; | |
2767 | volatile ETH_TX_DESC *p_tx_desc_used; | |
2768 | unsigned int command_status; | |
2769 | ||
2770 | /* Do not process Tx ring in case of Tx ring resource error */ | |
2771 | if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) | |
2772 | return ETH_QUEUE_FULL; | |
2773 | ||
2774 | /* Get the Tx Desc ring indexes */ | |
2775 | CURR_TFD_GET (p_tx_desc_curr, tx_queue); | |
2776 | USED_TFD_GET (p_tx_desc_used, tx_queue); | |
2777 | ||
2778 | if (p_tx_desc_curr == NULL) | |
2779 | return ETH_ERROR; | |
2780 | ||
2781 | /* The following parameters are used to save readings from memory */ | |
2782 | p_tx_next_desc_curr = TX_NEXT_DESC_PTR (p_tx_desc_curr, tx_queue); | |
2783 | command_status = p_pkt_info->cmd_sts | ETH_ZERO_PADDING | ETH_GEN_CRC; | |
2784 | ||
2785 | if (command_status & (ETH_TX_FIRST_DESC)) { | |
2786 | /* Update first desc */ | |
2787 | FIRST_TFD_SET (p_tx_desc_curr, tx_queue); | |
2788 | p_tx_desc_first = p_tx_desc_curr; | |
2789 | } else { | |
2790 | FIRST_TFD_GET (p_tx_desc_first, tx_queue); | |
2791 | command_status |= ETH_BUFFER_OWNED_BY_DMA; | |
2792 | } | |
2793 | ||
2794 | /* Buffers with a payload smaller than 8 bytes must be aligned to 64-bit */ | |
2795 | /* boundary. We use the memory allocated for Tx descriptor. This memory */ | |
2796 | /* located in TX_BUF_OFFSET_IN_DESC offset within the Tx descriptor. */ | |
2797 | if (p_pkt_info->byte_cnt <= 8) { | |
2798 | printf ("You have failed in the < 8 bytes errata - fixme\n"); /* RABEEH - TBD */ | |
2799 | return ETH_ERROR; | |
2800 | ||
2801 | p_tx_desc_curr->buf_ptr = | |
2802 | (unsigned int) p_tx_desc_curr + TX_BUF_OFFSET_IN_DESC; | |
2803 | eth_b_copy (p_pkt_info->buf_ptr, p_tx_desc_curr->buf_ptr, | |
2804 | p_pkt_info->byte_cnt); | |
2805 | } else | |
2806 | p_tx_desc_curr->buf_ptr = p_pkt_info->buf_ptr; | |
2807 | ||
2808 | p_tx_desc_curr->byte_cnt = p_pkt_info->byte_cnt; | |
2809 | p_tx_desc_curr->return_info = p_pkt_info->return_info; | |
2810 | ||
2811 | if (p_pkt_info->cmd_sts & (ETH_TX_LAST_DESC)) { | |
2812 | /* Set last desc with DMA ownership and interrupt enable. */ | |
2813 | p_tx_desc_curr->cmd_sts = command_status | | |
2814 | ETH_BUFFER_OWNED_BY_DMA | ETH_TX_ENABLE_INTERRUPT; | |
2815 | ||
2816 | if (p_tx_desc_curr != p_tx_desc_first) | |
2817 | p_tx_desc_first->cmd_sts |= ETH_BUFFER_OWNED_BY_DMA; | |
2818 | ||
2819 | /* Flush CPU pipe */ | |
2820 | ||
2821 | D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); | |
2822 | D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_first, 0); | |
2823 | CPU_PIPE_FLUSH; | |
2824 | ||
2825 | /* Apply send command */ | |
2826 | ETH_ENABLE_TX_QUEUE (tx_queue, p_eth_port_ctrl->port_num); | |
2827 | ||
2828 | /* Finish Tx packet. Update first desc in case of Tx resource error */ | |
2829 | p_tx_desc_first = p_tx_next_desc_curr; | |
2830 | FIRST_TFD_SET (p_tx_desc_first, tx_queue); | |
2831 | ||
2832 | } else { | |
2833 | p_tx_desc_curr->cmd_sts = command_status; | |
2834 | D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_curr, 0); | |
2835 | } | |
2836 | ||
2837 | /* Check for ring index overlap in the Tx desc ring */ | |
2838 | if (p_tx_next_desc_curr == p_tx_desc_used) { | |
2839 | /* Update the current descriptor */ | |
2840 | CURR_TFD_SET (p_tx_desc_first, tx_queue); | |
2841 | ||
2842 | p_eth_port_ctrl->tx_resource_err[tx_queue] = true; | |
2843 | return ETH_QUEUE_LAST_RESOURCE; | |
2844 | } else { | |
2845 | /* Update the current descriptor */ | |
2846 | CURR_TFD_SET (p_tx_next_desc_curr, tx_queue); | |
2847 | return ETH_OK; | |
2848 | } | |
2849 | } | |
2850 | ||
2851 | /******************************************************************************* | |
2852 | * eth_tx_return_desc - Free all used Tx descriptors | |
2853 | * | |
2854 | * DESCRIPTION: | |
2855 | * This routine returns the transmitted packet information to the caller. | |
2856 | * It uses the 'first' index to support Tx desc return in case a transmit | |
2857 | * of a packet spanned over multiple buffer still in process. | |
2858 | * In case the Tx queue was in "resource error" condition, where there are | |
2859 | * no available Tx resources, the function resets the resource error flag. | |
2860 | * | |
2861 | * INPUT: | |
2862 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. | |
2863 | * ETH_QUEUE tx_queue Number of Tx queue. | |
2864 | * PKT_INFO *p_pkt_info User packet buffer. | |
2865 | * | |
2866 | * OUTPUT: | |
2867 | * Tx ring 'first' and 'used' indexes are updated. | |
2868 | * | |
2869 | * RETURN: | |
2870 | * ETH_ERROR in case the routine can not access Tx desc ring. | |
2871 | * ETH_RETRY in case there is transmission in process. | |
2872 | * ETH_END_OF_JOB if the routine has nothing to release. | |
2873 | * ETH_OK otherwise. | |
2874 | * | |
2875 | *******************************************************************************/ | |
2876 | static ETH_FUNC_RET_STATUS eth_tx_return_desc (ETH_PORT_INFO * | |
2877 | p_eth_port_ctrl, | |
2878 | ETH_QUEUE tx_queue, | |
2879 | PKT_INFO * p_pkt_info) | |
2880 | { | |
2881 | volatile ETH_TX_DESC *p_tx_desc_used = NULL; | |
2882 | volatile ETH_TX_DESC *p_tx_desc_first = NULL; | |
2883 | unsigned int command_status; | |
2884 | ||
2885 | ||
2886 | /* Get the Tx Desc ring indexes */ | |
2887 | USED_TFD_GET (p_tx_desc_used, tx_queue); | |
2888 | FIRST_TFD_GET (p_tx_desc_first, tx_queue); | |
2889 | ||
2890 | ||
2891 | /* Sanity check */ | |
2892 | if (p_tx_desc_used == NULL) | |
2893 | return ETH_ERROR; | |
2894 | ||
2895 | command_status = p_tx_desc_used->cmd_sts; | |
2896 | ||
2897 | /* Still transmitting... */ | |
2898 | if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { | |
2899 | D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); | |
2900 | return ETH_RETRY; | |
2901 | } | |
2902 | ||
2903 | /* Stop release. About to overlap the current available Tx descriptor */ | |
2904 | if ((p_tx_desc_used == p_tx_desc_first) && | |
2905 | (p_eth_port_ctrl->tx_resource_err[tx_queue] == false)) { | |
2906 | D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); | |
2907 | return ETH_END_OF_JOB; | |
2908 | } | |
2909 | ||
2910 | /* Pass the packet information to the caller */ | |
2911 | p_pkt_info->cmd_sts = command_status; | |
2912 | p_pkt_info->return_info = p_tx_desc_used->return_info; | |
2913 | p_tx_desc_used->return_info = 0; | |
2914 | ||
2915 | /* Update the next descriptor to release. */ | |
2916 | USED_TFD_SET (TX_NEXT_DESC_PTR (p_tx_desc_used, tx_queue), tx_queue); | |
2917 | ||
2918 | /* Any Tx return cancels the Tx resource error status */ | |
2919 | if (p_eth_port_ctrl->tx_resource_err[tx_queue] == true) | |
2920 | p_eth_port_ctrl->tx_resource_err[tx_queue] = false; | |
2921 | ||
2922 | D_CACHE_FLUSH_LINE ((unsigned int) p_tx_desc_used, 0); | |
2923 | ||
2924 | return ETH_OK; | |
2925 | ||
2926 | } | |
2927 | ||
2928 | /******************************************************************************* | |
2929 | * eth_port_receive - Get received information from Rx ring. | |
2930 | * | |
2931 | * DESCRIPTION: | |
2932 | * This routine returns the received data to the caller. There is no | |
2933 | * data copying during routine operation. All information is returned | |
2934 | * using pointer to packet information struct passed from the caller. | |
2935 | * If the routine exhausts Rx ring resources then the resource error flag | |
2936 | * is set. | |
2937 | * | |
2938 | * INPUT: | |
2939 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. | |
2940 | * ETH_QUEUE rx_queue Number of Rx queue. | |
2941 | * PKT_INFO *p_pkt_info User packet buffer. | |
2942 | * | |
2943 | * OUTPUT: | |
2944 | * Rx ring current and used indexes are updated. | |
2945 | * | |
2946 | * RETURN: | |
2947 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
2948 | * ETH_QUEUE_FULL if Rx ring resources are exhausted. | |
2949 | * ETH_END_OF_JOB if there is no received data. | |
2950 | * ETH_OK otherwise. | |
2951 | * | |
2952 | *******************************************************************************/ | |
2953 | static ETH_FUNC_RET_STATUS eth_port_receive (ETH_PORT_INFO * p_eth_port_ctrl, | |
2954 | ETH_QUEUE rx_queue, | |
2955 | PKT_INFO * p_pkt_info) | |
2956 | { | |
2957 | volatile ETH_RX_DESC *p_rx_curr_desc; | |
2958 | volatile ETH_RX_DESC *p_rx_next_curr_desc; | |
2959 | volatile ETH_RX_DESC *p_rx_used_desc; | |
2960 | unsigned int command_status; | |
2961 | ||
2962 | /* Do not process Rx ring in case of Rx ring resource error */ | |
2963 | if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) { | |
2964 | printf ("\nRx Queue is full ...\n"); | |
2965 | return ETH_QUEUE_FULL; | |
2966 | } | |
2967 | ||
2968 | /* Get the Rx Desc ring 'curr and 'used' indexes */ | |
2969 | CURR_RFD_GET (p_rx_curr_desc, rx_queue); | |
2970 | USED_RFD_GET (p_rx_used_desc, rx_queue); | |
2971 | ||
2972 | /* Sanity check */ | |
2973 | if (p_rx_curr_desc == NULL) | |
2974 | return ETH_ERROR; | |
2975 | ||
2976 | /* The following parameters are used to save readings from memory */ | |
2977 | p_rx_next_curr_desc = RX_NEXT_DESC_PTR (p_rx_curr_desc, rx_queue); | |
2978 | command_status = p_rx_curr_desc->cmd_sts; | |
2979 | ||
2980 | /* Nothing to receive... */ | |
2981 | if (command_status & (ETH_BUFFER_OWNED_BY_DMA)) { | |
2982 | /* DP(printf("Rx: command_status: %08x\n", command_status)); */ | |
2983 | D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); | |
2984 | /* DP(printf("\nETH_END_OF_JOB ...\n"));*/ | |
2985 | return ETH_END_OF_JOB; | |
2986 | } | |
2987 | ||
2988 | p_pkt_info->byte_cnt = (p_rx_curr_desc->byte_cnt) - RX_BUF_OFFSET; | |
2989 | p_pkt_info->cmd_sts = command_status; | |
2990 | p_pkt_info->buf_ptr = (p_rx_curr_desc->buf_ptr) + RX_BUF_OFFSET; | |
2991 | p_pkt_info->return_info = p_rx_curr_desc->return_info; | |
2992 | p_pkt_info->l4i_chk = p_rx_curr_desc->buf_size; /* IP fragment indicator */ | |
2993 | ||
2994 | /* Clean the return info field to indicate that the packet has been */ | |
2995 | /* moved to the upper layers */ | |
2996 | p_rx_curr_desc->return_info = 0; | |
2997 | ||
2998 | /* Update 'curr' in data structure */ | |
2999 | CURR_RFD_SET (p_rx_next_curr_desc, rx_queue); | |
3000 | ||
3001 | /* Rx descriptors resource exhausted. Set the Rx ring resource error flag */ | |
3002 | if (p_rx_next_curr_desc == p_rx_used_desc) | |
3003 | p_eth_port_ctrl->rx_resource_err[rx_queue] = true; | |
3004 | ||
3005 | D_CACHE_FLUSH_LINE ((unsigned int) p_rx_curr_desc, 0); | |
3006 | CPU_PIPE_FLUSH; | |
3007 | return ETH_OK; | |
3008 | } | |
3009 | ||
3010 | /******************************************************************************* | |
3011 | * eth_rx_return_buff - Returns a Rx buffer back to the Rx ring. | |
3012 | * | |
3013 | * DESCRIPTION: | |
3014 | * This routine returns a Rx buffer back to the Rx ring. It retrieves the | |
3015 | * next 'used' descriptor and attached the returned buffer to it. | |
3016 | * In case the Rx ring was in "resource error" condition, where there are | |
3017 | * no available Rx resources, the function resets the resource error flag. | |
3018 | * | |
3019 | * INPUT: | |
3020 | * ETH_PORT_INFO *p_eth_port_ctrl Ethernet Port Control srtuct. | |
3021 | * ETH_QUEUE rx_queue Number of Rx queue. | |
3022 | * PKT_INFO *p_pkt_info Information on the returned buffer. | |
3023 | * | |
3024 | * OUTPUT: | |
3025 | * New available Rx resource in Rx descriptor ring. | |
3026 | * | |
3027 | * RETURN: | |
3028 | * ETH_ERROR in case the routine can not access Rx desc ring. | |
3029 | * ETH_OK otherwise. | |
3030 | * | |
3031 | *******************************************************************************/ | |
3032 | static ETH_FUNC_RET_STATUS eth_rx_return_buff (ETH_PORT_INFO * | |
3033 | p_eth_port_ctrl, | |
3034 | ETH_QUEUE rx_queue, | |
3035 | PKT_INFO * p_pkt_info) | |
3036 | { | |
3037 | volatile ETH_RX_DESC *p_used_rx_desc; /* Where to return Rx resource */ | |
3038 | ||
3039 | /* Get 'used' Rx descriptor */ | |
3040 | USED_RFD_GET (p_used_rx_desc, rx_queue); | |
3041 | ||
3042 | /* Sanity check */ | |
3043 | if (p_used_rx_desc == NULL) | |
3044 | return ETH_ERROR; | |
3045 | ||
3046 | p_used_rx_desc->buf_ptr = p_pkt_info->buf_ptr; | |
3047 | p_used_rx_desc->return_info = p_pkt_info->return_info; | |
3048 | p_used_rx_desc->byte_cnt = p_pkt_info->byte_cnt; | |
3049 | p_used_rx_desc->buf_size = MV64360_RX_BUFFER_SIZE; /* Reset Buffer size */ | |
3050 | ||
3051 | /* Flush the write pipe */ | |
3052 | CPU_PIPE_FLUSH; | |
3053 | ||
3054 | /* Return the descriptor to DMA ownership */ | |
3055 | p_used_rx_desc->cmd_sts = | |
3056 | ETH_BUFFER_OWNED_BY_DMA | ETH_RX_ENABLE_INTERRUPT; | |
3057 | ||
3058 | /* Flush descriptor and CPU pipe */ | |
3059 | D_CACHE_FLUSH_LINE ((unsigned int) p_used_rx_desc, 0); | |
3060 | CPU_PIPE_FLUSH; | |
3061 | ||
3062 | /* Move the used descriptor pointer to the next descriptor */ | |
3063 | USED_RFD_SET (RX_NEXT_DESC_PTR (p_used_rx_desc, rx_queue), rx_queue); | |
3064 | ||
3065 | /* Any Rx return cancels the Rx resource error status */ | |
3066 | if (p_eth_port_ctrl->rx_resource_err[rx_queue] == true) | |
3067 | p_eth_port_ctrl->rx_resource_err[rx_queue] = false; | |
3068 | ||
3069 | return ETH_OK; | |
3070 | } | |
3071 | ||
3072 | /******************************************************************************* | |
3073 | * eth_port_set_rx_coal - Sets coalescing interrupt mechanism on RX path | |
3074 | * | |
3075 | * DESCRIPTION: | |
3076 | * This routine sets the RX coalescing interrupt mechanism parameter. | |
3077 | * This parameter is a timeout counter, that counts in 64 t_clk | |
3078 | * chunks ; that when timeout event occurs a maskable interrupt | |
3079 | * occurs. | |
3080 | * The parameter is calculated using the tClk of the MV-643xx chip | |
3081 | * , and the required delay of the interrupt in usec. | |
3082 | * | |
3083 | * INPUT: | |
3084 | * ETH_PORT eth_port_num Ethernet port number | |
3085 | * unsigned int t_clk t_clk of the MV-643xx chip in HZ units | |
3086 | * unsigned int delay Delay in usec | |
3087 | * | |
3088 | * OUTPUT: | |
3089 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
3090 | * | |
3091 | * RETURN: | |
3092 | * The interrupt coalescing value set in the gigE port. | |
3093 | * | |
3094 | *******************************************************************************/ | |
3095 | #if 0 /* FIXME */ | |
3096 | static unsigned int eth_port_set_rx_coal (ETH_PORT eth_port_num, | |
3097 | unsigned int t_clk, | |
3098 | unsigned int delay) | |
3099 | { | |
3100 | unsigned int coal; | |
3101 | ||
3102 | coal = ((t_clk / 1000000) * delay) / 64; | |
3103 | /* Set RX Coalescing mechanism */ | |
3104 | MV_REG_WRITE (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num), | |
3105 | ((coal & 0x3fff) << 8) | | |
3106 | (MV_REG_READ | |
3107 | (MV64360_ETH_SDMA_CONFIG_REG (eth_port_num)) | |
3108 | & 0xffc000ff)); | |
3109 | return coal; | |
3110 | } | |
3111 | ||
3112 | #endif | |
3113 | /******************************************************************************* | |
3114 | * eth_port_set_tx_coal - Sets coalescing interrupt mechanism on TX path | |
3115 | * | |
3116 | * DESCRIPTION: | |
3117 | * This routine sets the TX coalescing interrupt mechanism parameter. | |
3118 | * This parameter is a timeout counter, that counts in 64 t_clk | |
3119 | * chunks ; that when timeout event occurs a maskable interrupt | |
3120 | * occurs. | |
3121 | * The parameter is calculated using the t_cLK frequency of the | |
3122 | * MV-643xx chip and the required delay in the interrupt in uSec | |
3123 | * | |
3124 | * INPUT: | |
3125 | * ETH_PORT eth_port_num Ethernet port number | |
3126 | * unsigned int t_clk t_clk of the MV-643xx chip in HZ units | |
3127 | * unsigned int delay Delay in uSeconds | |
3128 | * | |
3129 | * OUTPUT: | |
3130 | * Interrupt coalescing mechanism value is set in MV-643xx chip. | |
3131 | * | |
3132 | * RETURN: | |
3133 | * The interrupt coalescing value set in the gigE port. | |
3134 | * | |
3135 | *******************************************************************************/ | |
3136 | #if 0 /* FIXME */ | |
3137 | static unsigned int eth_port_set_tx_coal (ETH_PORT eth_port_num, | |
3138 | unsigned int t_clk, | |
3139 | unsigned int delay) | |
3140 | { | |
3141 | unsigned int coal; | |
3142 | ||
3143 | coal = ((t_clk / 1000000) * delay) / 64; | |
3144 | /* Set TX Coalescing mechanism */ | |
3145 | MV_REG_WRITE (MV64360_ETH_TX_FIFO_URGENT_THRESHOLD_REG (eth_port_num), | |
3146 | coal << 4); | |
3147 | return coal; | |
3148 | } | |
3149 | #endif | |
3150 | ||
3151 | /******************************************************************************* | |
3152 | * eth_b_copy - Copy bytes from source to destination | |
3153 | * | |
3154 | * DESCRIPTION: | |
3155 | * This function supports the eight bytes limitation on Tx buffer size. | |
3156 | * The routine will zero eight bytes starting from the destination address | |
3157 | * followed by copying bytes from the source address to the destination. | |
3158 | * | |
3159 | * INPUT: | |
3160 | * unsigned int src_addr 32 bit source address. | |
3161 | * unsigned int dst_addr 32 bit destination address. | |
3162 | * int byte_count Number of bytes to copy. | |
3163 | * | |
3164 | * OUTPUT: | |
3165 | * See description. | |
3166 | * | |
3167 | * RETURN: | |
3168 | * None. | |
3169 | * | |
3170 | *******************************************************************************/ | |
3171 | static void eth_b_copy (unsigned int src_addr, unsigned int dst_addr, | |
3172 | int byte_count) | |
3173 | { | |
3174 | /* Zero the dst_addr area */ | |
3175 | *(unsigned int *) dst_addr = 0x0; | |
3176 | ||
3177 | while (byte_count != 0) { | |
3178 | *(char *) dst_addr = *(char *) src_addr; | |
3179 | dst_addr++; | |
3180 | src_addr++; | |
3181 | byte_count--; | |
3182 | } | |
3183 | } |