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3a473b2a WD |
1 | /* |
2 | * (C) Copyright 2001 | |
3 | * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
3a473b2a WD |
6 | */ |
7 | ||
8 | /************************************************************************* | |
9 | * adaption for the Marvell DB64360 Board | |
10 | * Ingo Assmus (ingo.assmus@keymile.com) | |
11 | ************************************************************************/ | |
12 | ||
13 | ||
14 | /* sdram_init.c - automatic memory sizing */ | |
15 | ||
16 | #include <common.h> | |
17 | #include <74xx_7xx.h> | |
18 | #include "../include/memory.h" | |
19 | #include "../include/pci.h" | |
20 | #include "../include/mv_gen_reg.h" | |
21 | #include <net.h> | |
22 | ||
23 | #include "eth.h" | |
24 | #include "mpsc.h" | |
25 | #include "../common/i2c.h" | |
26 | #include "64360.h" | |
27 | #include "mv_regs.h" | |
28 | ||
d87080b7 WD |
29 | DECLARE_GLOBAL_DATA_PTR; |
30 | ||
3a473b2a WD |
31 | #define MAP_PCI |
32 | ||
3a473b2a WD |
33 | int set_dfcdlInit (void); /* setup delay line of Mv64360 */ |
34 | int mvDmaIsChannelActive (int); | |
35 | int mvDmaSetMemorySpace (ulong, ulong, ulong, ulong, ulong); | |
36 | int mvDmaTransfer (int, ulong, ulong, ulong, ulong); | |
37 | ||
38 | /* ------------------------------------------------------------------------- */ | |
39 | ||
40 | int | |
41 | memory_map_bank (unsigned int bankNo, | |
42 | unsigned int bankBase, unsigned int bankLength) | |
43 | { | |
44 | #ifdef MAP_PCI | |
45 | PCI_HOST host; | |
46 | #endif | |
47 | ||
48 | ||
49 | #ifdef DEBUG | |
50 | if (bankLength > 0) { | |
51 | printf ("mapping bank %d at %08x - %08x\n", | |
52 | bankNo, bankBase, bankBase + bankLength - 1); | |
53 | } else { | |
54 | printf ("unmapping bank %d\n", bankNo); | |
55 | } | |
56 | #endif | |
57 | ||
58 | memoryMapBank (bankNo, bankBase, bankLength); | |
59 | ||
60 | #ifdef MAP_PCI | |
61 | for (host = PCI_HOST0; host <= PCI_HOST1; host++) { | |
62 | const int features = | |
63 | PREFETCH_ENABLE | | |
64 | DELAYED_READ_ENABLE | | |
65 | AGGRESSIVE_PREFETCH | | |
66 | READ_LINE_AGGRESSIVE_PREFETCH | | |
67 | READ_MULTI_AGGRESSIVE_PREFETCH | | |
68 | MAX_BURST_4 | PCI_NO_SWAP; | |
69 | ||
70 | pciMapMemoryBank (host, bankNo, bankBase, bankLength); | |
71 | ||
72 | pciSetRegionSnoopMode (host, bankNo, PCI_SNOOP_WB, bankBase, | |
73 | bankLength); | |
74 | ||
75 | pciSetRegionFeatures (host, bankNo, features, bankBase, | |
76 | bankLength); | |
77 | } | |
78 | #endif | |
79 | return 0; | |
80 | } | |
81 | ||
82 | #define GB (1 << 30) | |
83 | ||
84 | /* much of this code is based on (or is) the code in the pip405 port */ | |
85 | /* thanks go to the authors of said port - Josh */ | |
86 | ||
87 | /* structure to store the relevant information about an sdram bank */ | |
88 | typedef struct sdram_info { | |
89 | uchar drb_size; | |
90 | uchar registered, ecc; | |
91 | uchar tpar; | |
92 | uchar tras_clocks; | |
93 | uchar burst_len; | |
94 | uchar banks, slot; | |
95 | } sdram_info_t; | |
96 | ||
97 | /* Typedefs for 'gtAuxilGetDIMMinfo' function */ | |
98 | ||
99 | typedef enum _memoryType { SDRAM, DDR } MEMORY_TYPE; | |
100 | ||
101 | typedef enum _voltageInterface { TTL_5V_TOLERANT, LVTTL, HSTL_1_5V, | |
102 | SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN, | |
103 | } VOLTAGE_INTERFACE; | |
104 | ||
105 | typedef enum _max_CL_supported_DDR { DDR_CL_1 = 1, DDR_CL_1_5 = 2, DDR_CL_2 = | |
106 | 4, DDR_CL_2_5 = 8, DDR_CL_3 = 16, DDR_CL_3_5 = | |
107 | 32, DDR_CL_FAULT } MAX_CL_SUPPORTED_DDR; | |
108 | typedef enum _max_CL_supported_SD { SD_CL_1 = | |
109 | 1, SD_CL_2, SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, | |
110 | SD_FAULT } MAX_CL_SUPPORTED_SD; | |
111 | ||
112 | ||
113 | /* SDRAM/DDR information struct */ | |
114 | typedef struct _gtMemoryDimmInfo { | |
115 | MEMORY_TYPE memoryType; | |
116 | unsigned int numOfRowAddresses; | |
117 | unsigned int numOfColAddresses; | |
118 | unsigned int numOfModuleBanks; | |
119 | unsigned int dataWidth; | |
120 | VOLTAGE_INTERFACE voltageInterface; | |
121 | unsigned int errorCheckType; /* ECC , PARITY.. */ | |
122 | unsigned int sdramWidth; /* 4,8,16 or 32 */ ; | |
123 | unsigned int errorCheckDataWidth; /* 0 - no, 1 - Yes */ | |
124 | unsigned int minClkDelay; | |
125 | unsigned int burstLengthSupported; | |
126 | unsigned int numOfBanksOnEachDevice; | |
127 | unsigned int suportedCasLatencies; | |
128 | unsigned int RefreshInterval; | |
129 | unsigned int maxCASlatencySupported_LoP; /* LoP left of point (measured in ns) */ | |
130 | unsigned int maxCASlatencySupported_RoP; /* RoP right of point (measured in ns) */ | |
131 | MAX_CL_SUPPORTED_DDR maxClSupported_DDR; | |
132 | MAX_CL_SUPPORTED_SD maxClSupported_SD; | |
133 | unsigned int moduleBankDensity; | |
134 | /* module attributes (true for yes) */ | |
135 | bool bufferedAddrAndControlInputs; | |
136 | bool registeredAddrAndControlInputs; | |
137 | bool onCardPLL; | |
138 | bool bufferedDQMBinputs; | |
139 | bool registeredDQMBinputs; | |
140 | bool differentialClockInput; | |
141 | bool redundantRowAddressing; | |
142 | ||
143 | /* module general attributes */ | |
144 | bool suportedAutoPreCharge; | |
145 | bool suportedPreChargeAll; | |
146 | bool suportedEarlyRasPreCharge; | |
147 | bool suportedWrite1ReadBurst; | |
148 | bool suported5PercentLowVCC; | |
149 | bool suported5PercentUpperVCC; | |
150 | /* module timing parameters */ | |
151 | unsigned int minRasToCasDelay; | |
152 | unsigned int minRowActiveRowActiveDelay; | |
153 | unsigned int minRasPulseWidth; | |
154 | unsigned int minRowPrechargeTime; /* measured in ns */ | |
155 | ||
156 | int addrAndCommandHoldTime; /* LoP left of point (measured in ns) */ | |
157 | int addrAndCommandSetupTime; /* (measured in ns/100) */ | |
158 | int dataInputSetupTime; /* LoP left of point (measured in ns) */ | |
159 | int dataInputHoldTime; /* LoP left of point (measured in ns) */ | |
160 | /* tAC times for highest 2nd and 3rd highest CAS Latency values */ | |
161 | unsigned int clockToDataOut_LoP; /* LoP left of point (measured in ns) */ | |
162 | unsigned int clockToDataOut_RoP; /* RoP right of point (measured in ns) */ | |
163 | unsigned int clockToDataOutMinus1_LoP; /* LoP left of point (measured in ns) */ | |
164 | unsigned int clockToDataOutMinus1_RoP; /* RoP right of point (measured in ns) */ | |
165 | unsigned int clockToDataOutMinus2_LoP; /* LoP left of point (measured in ns) */ | |
166 | unsigned int clockToDataOutMinus2_RoP; /* RoP right of point (measured in ns) */ | |
167 | ||
168 | unsigned int minimumCycleTimeAtMaxCasLatancy_LoP; /* LoP left of point (measured in ns) */ | |
169 | unsigned int minimumCycleTimeAtMaxCasLatancy_RoP; /* RoP right of point (measured in ns) */ | |
170 | ||
171 | unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */ | |
172 | unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */ | |
173 | ||
174 | unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */ | |
175 | unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */ | |
176 | ||
177 | /* Parameters calculated from | |
178 | the extracted DIMM information */ | |
179 | unsigned int size; | |
180 | unsigned int deviceDensity; /* 16,64,128,256 or 512 Mbit */ | |
181 | unsigned int numberOfDevices; | |
182 | uchar drb_size; /* DRAM size in n*64Mbit */ | |
183 | uchar slot; /* Slot Number this module is inserted in */ | |
184 | uchar spd_raw_data[128]; /* Content of SPD-EEPROM copied 1:1 */ | |
185 | #ifdef DEBUG | |
186 | uchar manufactura[8]; /* Content of SPD-EEPROM Byte 64-71 */ | |
187 | uchar modul_id[18]; /* Content of SPD-EEPROM Byte 73-90 */ | |
188 | uchar vendor_data[27]; /* Content of SPD-EEPROM Byte 99-125 */ | |
189 | unsigned long modul_serial_no; /* Content of SPD-EEPROM Byte 95-98 */ | |
190 | unsigned int manufac_date; /* Content of SPD-EEPROM Byte 93-94 */ | |
191 | unsigned int modul_revision; /* Content of SPD-EEPROM Byte 91-92 */ | |
192 | uchar manufac_place; /* Content of SPD-EEPROM Byte 72 */ | |
193 | ||
194 | #endif | |
195 | } AUX_MEM_DIMM_INFO; | |
196 | ||
197 | ||
198 | /* | |
199 | * translate ns.ns/10 coding of SPD timing values | |
200 | * into 10 ps unit values | |
201 | */ | |
202 | static inline unsigned short NS10to10PS (unsigned char spd_byte) | |
203 | { | |
204 | unsigned short ns, ns10; | |
205 | ||
206 | /* isolate upper nibble */ | |
207 | ns = (spd_byte >> 4) & 0x0F; | |
208 | /* isolate lower nibble */ | |
209 | ns10 = (spd_byte & 0x0F); | |
210 | ||
211 | return (ns * 100 + ns10 * 10); | |
212 | } | |
213 | ||
214 | /* | |
215 | * translate ns coding of SPD timing values | |
216 | * into 10 ps unit values | |
217 | */ | |
218 | static inline unsigned short NSto10PS (unsigned char spd_byte) | |
219 | { | |
220 | return (spd_byte * 100); | |
221 | } | |
222 | ||
223 | /* This code reads the SPD chip on the sdram and populates | |
224 | * the array which is passed in with the relevant information */ | |
225 | /* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */ | |
226 | static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo) | |
227 | { | |
3a473b2a WD |
228 | unsigned long spd_checksum; |
229 | ||
230 | #ifdef ZUMA_NTL | |
231 | /* zero all the values */ | |
232 | memset (info, 0, sizeof (*info)); | |
233 | ||
234 | /* | |
235 | if (!slot) { | |
236 | info->slot = 0; | |
237 | info->banks = 1; | |
238 | info->registered = 0; | |
239 | info->drb_size = 16;*/ /* 16 - 256MBit, 32 - 512MBit */ | |
240 | /* info->tpar = 3; | |
241 | info->tras_clocks = 5; | |
242 | info->burst_len = 4; | |
243 | */ | |
244 | #ifdef CONFIG_MV64360_ECC | |
245 | /* check for ECC/parity [0 = none, 1 = parity, 2 = ecc] */ | |
246 | dimmInfo->errorCheckType = 2; | |
247 | /* info->ecc = 2;*/ | |
248 | #endif | |
249 | } | |
250 | ||
251 | return 0; | |
252 | ||
253 | #else | |
254 | uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR; | |
255 | int ret; | |
4fcfbec0 | 256 | unsigned int i, j, density = 1; |
3a473b2a WD |
257 | |
258 | #ifdef DEBUG | |
259 | unsigned int k; | |
260 | #endif | |
261 | unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp; | |
262 | int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint; | |
263 | uchar supp_cal, cal_val; | |
264 | ulong memclk, tmemclk; | |
265 | ulong tmp; | |
4fcfbec0 | 266 | uchar trp_clocks = 0, tras_clocks; |
3a473b2a WD |
267 | uchar data[128]; |
268 | ||
269 | memclk = gd->bus_clk; | |
270 | tmemclk = 1000000000 / (memclk / 100); /* in 10 ps units */ | |
271 | ||
4fcfbec0 | 272 | debug("before i2c read\n"); |
3a473b2a WD |
273 | |
274 | ret = i2c_read (addr, 0, 1, data, 128); | |
275 | ||
4fcfbec0 | 276 | debug("after i2c read\n"); |
3a473b2a WD |
277 | |
278 | /* zero all the values */ | |
279 | memset (dimmInfo, 0, sizeof (*dimmInfo)); | |
280 | ||
281 | /* copy the SPD content 1:1 into the dimmInfo structure */ | |
282 | for (i = 0; i <= 127; i++) { | |
283 | dimmInfo->spd_raw_data[i] = data[i]; | |
284 | } | |
285 | ||
286 | if (ret) { | |
4fcfbec0 | 287 | debug("No DIMM in slot %d [err = %x]\n", slot, ret); |
3a473b2a WD |
288 | return 0; |
289 | } else | |
290 | dimmInfo->slot = slot; /* start to fill up dimminfo for this "slot" */ | |
291 | ||
6d0f6bcf | 292 | #ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT |
3a473b2a WD |
293 | |
294 | for (i = 0; i <= 127; i++) { | |
295 | printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i], | |
296 | data[i]); | |
297 | } | |
298 | ||
299 | #endif | |
300 | #ifdef DEBUG | |
301 | /* find Manufactura of Dimm Module */ | |
302 | for (i = 0; i < sizeof (dimmInfo->manufactura); i++) { | |
303 | dimmInfo->manufactura[i] = data[64 + i]; | |
304 | } | |
305 | printf ("\nThis RAM-Module is produced by: %s\n", | |
306 | dimmInfo->manufactura); | |
307 | ||
308 | /* find Manul-ID of Dimm Module */ | |
309 | for (i = 0; i < sizeof (dimmInfo->modul_id); i++) { | |
310 | dimmInfo->modul_id[i] = data[73 + i]; | |
311 | } | |
312 | printf ("The Module-ID of this RAM-Module is: %s\n", | |
313 | dimmInfo->modul_id); | |
314 | ||
315 | /* find Vendor-Data of Dimm Module */ | |
316 | for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) { | |
317 | dimmInfo->vendor_data[i] = data[99 + i]; | |
318 | } | |
319 | printf ("Vendor Data of this RAM-Module is: %s\n", | |
320 | dimmInfo->vendor_data); | |
321 | ||
322 | /* find modul_serial_no of Dimm Module */ | |
323 | dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95]))); | |
324 | printf ("Serial No. of this RAM-Module is: %ld (%lx)\n", | |
325 | dimmInfo->modul_serial_no, dimmInfo->modul_serial_no); | |
326 | ||
327 | /* find Manufac-Data of Dimm Module */ | |
328 | dimmInfo->manufac_date = (*((unsigned int *) (&data[93]))); | |
329 | printf ("Manufactoring Date of this RAM-Module is: %d.%d\n", data[93], data[94]); /*dimmInfo->manufac_date */ | |
330 | ||
331 | /* find modul_revision of Dimm Module */ | |
332 | dimmInfo->modul_revision = (*((unsigned int *) (&data[91]))); | |
333 | printf ("Module Revision of this RAM-Module is: %d.%d\n", data[91], data[92]); /* dimmInfo->modul_revision */ | |
334 | ||
335 | /* find manufac_place of Dimm Module */ | |
336 | dimmInfo->manufac_place = (*((unsigned char *) (&data[72]))); | |
337 | printf ("manufac_place of this RAM-Module is: %d\n", | |
338 | dimmInfo->manufac_place); | |
339 | ||
340 | #endif | |
341 | ||
342 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
343 | /* calculate SPD checksum */ | |
344 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
345 | spd_checksum = 0; | |
346 | ||
347 | for (i = 0; i <= 62; i++) { | |
348 | spd_checksum += data[i]; | |
349 | } | |
350 | ||
351 | if ((spd_checksum & 0xff) != data[63]) { | |
352 | printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]); | |
353 | hang (); | |
354 | } | |
355 | ||
356 | else | |
357 | printf ("SPD Checksum ok!\n"); | |
358 | ||
359 | ||
360 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
361 | for (i = 2; i <= 35; i++) { | |
362 | switch (i) { | |
363 | case 2: /* Memory type (DDR / SDRAM) */ | |
364 | dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM; | |
3a473b2a | 365 | if (dimmInfo->memoryType == 0) |
4fcfbec0 | 366 | debug |
3a473b2a | 367 | ("Dram_type in slot %d is: SDRAM\n", |
4fcfbec0 | 368 | dimmInfo->slot); |
3a473b2a | 369 | if (dimmInfo->memoryType == 1) |
4fcfbec0 | 370 | debug |
3a473b2a | 371 | ("Dram_type in slot %d is: DDRAM\n", |
4fcfbec0 | 372 | dimmInfo->slot); |
3a473b2a WD |
373 | break; |
374 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
375 | ||
376 | case 3: /* Number Of Row Addresses */ | |
377 | dimmInfo->numOfRowAddresses = data[i]; | |
4fcfbec0 | 378 | debug |
3a473b2a | 379 | ("Module Number of row addresses: %d\n", |
4fcfbec0 | 380 | dimmInfo->numOfRowAddresses); |
3a473b2a WD |
381 | break; |
382 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
383 | ||
384 | case 4: /* Number Of Column Addresses */ | |
385 | dimmInfo->numOfColAddresses = data[i]; | |
4fcfbec0 | 386 | debug |
3a473b2a | 387 | ("Module Number of col addresses: %d\n", |
4fcfbec0 | 388 | dimmInfo->numOfColAddresses); |
3a473b2a WD |
389 | break; |
390 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
391 | ||
392 | case 5: /* Number Of Module Banks */ | |
393 | dimmInfo->numOfModuleBanks = data[i]; | |
4fcfbec0 | 394 | debug |
3a473b2a | 395 | ("Number of Banks on Mod. : %d\n", |
4fcfbec0 | 396 | dimmInfo->numOfModuleBanks); |
3a473b2a WD |
397 | break; |
398 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
399 | ||
400 | case 6: /* Data Width */ | |
401 | dimmInfo->dataWidth = data[i]; | |
4fcfbec0 | 402 | debug |
3a473b2a | 403 | ("Module Data Width: %d\n", |
4fcfbec0 | 404 | dimmInfo->dataWidth); |
3a473b2a WD |
405 | break; |
406 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
407 | ||
408 | case 8: /* Voltage Interface */ | |
409 | switch (data[i]) { | |
410 | case 0x0: | |
411 | dimmInfo->voltageInterface = TTL_5V_TOLERANT; | |
4fcfbec0 WD |
412 | debug |
413 | ("Module is TTL_5V_TOLERANT\n"); | |
3a473b2a WD |
414 | break; |
415 | case 0x1: | |
416 | dimmInfo->voltageInterface = LVTTL; | |
4fcfbec0 WD |
417 | debug |
418 | ("Module is LVTTL\n"); | |
3a473b2a WD |
419 | break; |
420 | case 0x2: | |
421 | dimmInfo->voltageInterface = HSTL_1_5V; | |
4fcfbec0 WD |
422 | debug |
423 | ("Module is TTL_5V_TOLERANT\n"); | |
3a473b2a WD |
424 | break; |
425 | case 0x3: | |
426 | dimmInfo->voltageInterface = SSTL_3_3V; | |
4fcfbec0 WD |
427 | debug |
428 | ("Module is HSTL_1_5V\n"); | |
3a473b2a WD |
429 | break; |
430 | case 0x4: | |
431 | dimmInfo->voltageInterface = SSTL_2_5V; | |
4fcfbec0 WD |
432 | debug |
433 | ("Module is SSTL_2_5V\n"); | |
3a473b2a WD |
434 | break; |
435 | default: | |
436 | dimmInfo->voltageInterface = VOLTAGE_UNKNOWN; | |
4fcfbec0 WD |
437 | debug |
438 | ("Module is VOLTAGE_UNKNOWN\n"); | |
3a473b2a WD |
439 | break; |
440 | } | |
441 | break; | |
442 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
443 | ||
444 | case 9: /* Minimum Cycle Time At Max CasLatancy */ | |
445 | shift = (dimmInfo->memoryType == DDR) ? 4 : 2; | |
446 | mult = (dimmInfo->memoryType == DDR) ? 10 : 25; | |
447 | maskLeftOfPoint = | |
448 | (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; | |
449 | maskRightOfPoint = | |
450 | (dimmInfo->memoryType == DDR) ? 0xf : 0x03; | |
451 | leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; | |
452 | rightOfPoint = (data[i] & maskRightOfPoint) * mult; | |
453 | dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP = | |
454 | leftOfPoint; | |
455 | dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP = | |
456 | rightOfPoint; | |
4fcfbec0 | 457 | debug |
3a473b2a | 458 | ("Minimum Cycle Time At Max CasLatancy: %d.%d [ns]\n", |
4fcfbec0 | 459 | leftOfPoint, rightOfPoint); |
3a473b2a WD |
460 | break; |
461 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
462 | ||
463 | case 10: /* Clock To Data Out */ | |
464 | div = (dimmInfo->memoryType == DDR) ? 100 : 10; | |
465 | time_tmp = | |
466 | (((data[i] & 0xf0) >> 4) * 10) + | |
467 | ((data[i] & 0x0f)); | |
468 | leftOfPoint = time_tmp / div; | |
469 | rightOfPoint = time_tmp % div; | |
470 | dimmInfo->clockToDataOut_LoP = leftOfPoint; | |
471 | dimmInfo->clockToDataOut_RoP = rightOfPoint; | |
4fcfbec0 | 472 | debug("Clock To Data Out: %d.%2d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->clockToDataOut */ |
3a473b2a WD |
473 | break; |
474 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
475 | ||
476 | /*#ifdef CONFIG_ECC */ | |
477 | case 11: /* Error Check Type */ | |
478 | dimmInfo->errorCheckType = data[i]; | |
4fcfbec0 | 479 | debug |
3a473b2a | 480 | ("Error Check Type (0=NONE): %d\n", |
4fcfbec0 | 481 | dimmInfo->errorCheckType); |
3a473b2a WD |
482 | break; |
483 | /* #endif */ | |
484 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
485 | ||
486 | case 12: /* Refresh Interval */ | |
487 | dimmInfo->RefreshInterval = data[i]; | |
4fcfbec0 | 488 | debug |
3a473b2a | 489 | ("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n", |
4fcfbec0 | 490 | dimmInfo->RefreshInterval); |
3a473b2a WD |
491 | break; |
492 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
493 | ||
494 | case 13: /* Sdram Width */ | |
495 | dimmInfo->sdramWidth = data[i]; | |
4fcfbec0 | 496 | debug |
3a473b2a | 497 | ("Sdram Width: %d\n", |
4fcfbec0 | 498 | dimmInfo->sdramWidth); |
3a473b2a WD |
499 | break; |
500 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
501 | ||
502 | case 14: /* Error Check Data Width */ | |
503 | dimmInfo->errorCheckDataWidth = data[i]; | |
4fcfbec0 | 504 | debug |
3a473b2a | 505 | ("Error Check Data Width: %d\n", |
4fcfbec0 | 506 | dimmInfo->errorCheckDataWidth); |
3a473b2a WD |
507 | break; |
508 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
509 | ||
510 | case 15: /* Minimum Clock Delay */ | |
511 | dimmInfo->minClkDelay = data[i]; | |
4fcfbec0 | 512 | debug |
3a473b2a | 513 | ("Minimum Clock Delay: %d\n", |
4fcfbec0 | 514 | dimmInfo->minClkDelay); |
3a473b2a WD |
515 | break; |
516 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
517 | ||
518 | case 16: /* Burst Length Supported */ | |
519 | /******-******-******-******* | |
520 | * bit3 | bit2 | bit1 | bit0 * | |
521 | *******-******-******-******* | |
522 | burst length = * 8 | 4 | 2 | 1 * | |
523 | ***************************** | |
524 | ||
525 | If for example bit0 and bit2 are set, the burst | |
526 | length supported are 1 and 4. */ | |
527 | ||
528 | dimmInfo->burstLengthSupported = data[i]; | |
529 | #ifdef DEBUG | |
4fcfbec0 WD |
530 | debug |
531 | ("Burst Length Supported: "); | |
3a473b2a | 532 | if (dimmInfo->burstLengthSupported & 0x01) |
4fcfbec0 | 533 | debug("1, "); |
3a473b2a | 534 | if (dimmInfo->burstLengthSupported & 0x02) |
4fcfbec0 | 535 | debug("2, "); |
3a473b2a | 536 | if (dimmInfo->burstLengthSupported & 0x04) |
4fcfbec0 | 537 | debug("4, "); |
3a473b2a | 538 | if (dimmInfo->burstLengthSupported & 0x08) |
4fcfbec0 WD |
539 | debug("8, "); |
540 | debug(" Bit \n"); | |
3a473b2a WD |
541 | #endif |
542 | break; | |
543 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
544 | ||
545 | case 17: /* Number Of Banks On Each Device */ | |
546 | dimmInfo->numOfBanksOnEachDevice = data[i]; | |
4fcfbec0 | 547 | debug |
3a473b2a | 548 | ("Number Of Banks On Each Chip: %d\n", |
4fcfbec0 | 549 | dimmInfo->numOfBanksOnEachDevice); |
3a473b2a WD |
550 | break; |
551 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
552 | ||
553 | case 18: /* Suported Cas Latencies */ | |
554 | ||
555 | /* DDR: | |
556 | *******-******-******-******-******-******-******-******* | |
557 | * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * | |
558 | *******-******-******-******-******-******-******-******* | |
559 | CAS = * TBD | TBD | 3.5 | 3 | 2.5 | 2 | 1.5 | 1 * | |
560 | ********************************************************* | |
561 | SDRAM: | |
562 | *******-******-******-******-******-******-******-******* | |
563 | * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 * | |
564 | *******-******-******-******-******-******-******-******* | |
565 | CAS = * TBD | 7 | 6 | 5 | 4 | 3 | 2 | 1 * | |
566 | ********************************************************/ | |
567 | dimmInfo->suportedCasLatencies = data[i]; | |
568 | #ifdef DEBUG | |
4fcfbec0 WD |
569 | debug |
570 | ("Suported Cas Latencies: (CL) "); | |
3a473b2a WD |
571 | if (dimmInfo->memoryType == 0) { /* SDRAM */ |
572 | for (k = 0; k <= 7; k++) { | |
573 | if (dimmInfo-> | |
574 | suportedCasLatencies & (1 << k)) | |
4fcfbec0 | 575 | debug |
3a473b2a | 576 | ("%d, ", |
4fcfbec0 | 577 | k + 1); |
3a473b2a WD |
578 | } |
579 | ||
580 | } else { /* DDR-RAM */ | |
581 | ||
582 | if (dimmInfo->suportedCasLatencies & 1) | |
4fcfbec0 | 583 | debug("1, "); |
3a473b2a | 584 | if (dimmInfo->suportedCasLatencies & 2) |
4fcfbec0 | 585 | debug("1.5, "); |
3a473b2a | 586 | if (dimmInfo->suportedCasLatencies & 4) |
4fcfbec0 | 587 | debug("2, "); |
3a473b2a | 588 | if (dimmInfo->suportedCasLatencies & 8) |
4fcfbec0 | 589 | debug("2.5, "); |
3a473b2a | 590 | if (dimmInfo->suportedCasLatencies & 16) |
4fcfbec0 | 591 | debug("3, "); |
3a473b2a | 592 | if (dimmInfo->suportedCasLatencies & 32) |
4fcfbec0 | 593 | debug("3.5, "); |
3a473b2a WD |
594 | |
595 | } | |
4fcfbec0 | 596 | debug("\n"); |
3a473b2a WD |
597 | #endif |
598 | /* Calculating MAX CAS latency */ | |
599 | for (j = 7; j > 0; j--) { | |
600 | if (((dimmInfo-> | |
601 | suportedCasLatencies >> j) & 0x1) == | |
602 | 1) { | |
603 | switch (dimmInfo->memoryType) { | |
604 | case DDR: | |
605 | /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */ | |
606 | switch (j) { | |
607 | case 7: | |
4fcfbec0 WD |
608 | debug |
609 | ("Max. Cas Latencies (DDR): ERROR !!!\n"); | |
3a473b2a WD |
610 | dimmInfo-> |
611 | maxClSupported_DDR | |
612 | = | |
613 | DDR_CL_FAULT; | |
614 | hang (); | |
615 | break; | |
616 | case 6: | |
4fcfbec0 WD |
617 | debug |
618 | ("Max. Cas Latencies (DDR): ERROR !!!\n"); | |
3a473b2a WD |
619 | dimmInfo-> |
620 | maxClSupported_DDR | |
621 | = | |
622 | DDR_CL_FAULT; | |
623 | hang (); | |
624 | break; | |
625 | case 5: | |
4fcfbec0 WD |
626 | debug |
627 | ("Max. Cas Latencies (DDR): 3.5 clk's\n"); | |
3a473b2a WD |
628 | dimmInfo-> |
629 | maxClSupported_DDR | |
630 | = DDR_CL_3_5; | |
631 | break; | |
632 | case 4: | |
4fcfbec0 WD |
633 | debug |
634 | ("Max. Cas Latencies (DDR): 3 clk's \n"); | |
3a473b2a WD |
635 | dimmInfo-> |
636 | maxClSupported_DDR | |
637 | = DDR_CL_3; | |
638 | break; | |
639 | case 3: | |
4fcfbec0 WD |
640 | debug |
641 | ("Max. Cas Latencies (DDR): 2.5 clk's \n"); | |
3a473b2a WD |
642 | dimmInfo-> |
643 | maxClSupported_DDR | |
644 | = DDR_CL_2_5; | |
645 | break; | |
646 | case 2: | |
4fcfbec0 WD |
647 | debug |
648 | ("Max. Cas Latencies (DDR): 2 clk's \n"); | |
3a473b2a WD |
649 | dimmInfo-> |
650 | maxClSupported_DDR | |
651 | = DDR_CL_2; | |
652 | break; | |
653 | case 1: | |
4fcfbec0 WD |
654 | debug |
655 | ("Max. Cas Latencies (DDR): 1.5 clk's \n"); | |
3a473b2a WD |
656 | dimmInfo-> |
657 | maxClSupported_DDR | |
658 | = DDR_CL_1_5; | |
659 | break; | |
660 | } | |
661 | ||
662 | /* ronen - in case we have a DIMM with minimumCycleTimeAtMaxCasLatancy | |
663 | lower then our SDRAM cycle count, we won't be able to support this CAL | |
664 | and we will have to use lower CAL. (minus - means from 3.0 to 2.5) */ | |
665 | if ((dimmInfo-> | |
666 | minimumCycleTimeAtMaxCasLatancy_LoP | |
667 | < | |
6d0f6bcf | 668 | CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) |
3a473b2a WD |
669 | || |
670 | ((dimmInfo-> | |
671 | minimumCycleTimeAtMaxCasLatancy_LoP | |
672 | == | |
6d0f6bcf | 673 | CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) |
3a473b2a WD |
674 | && (dimmInfo-> |
675 | minimumCycleTimeAtMaxCasLatancy_RoP | |
676 | < | |
6d0f6bcf | 677 | CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) |
3a473b2a WD |
678 | { |
679 | dimmInfo-> | |
680 | maxClSupported_DDR | |
681 | = | |
682 | dimmInfo-> | |
683 | maxClSupported_DDR | |
684 | >> 1; | |
4fcfbec0 WD |
685 | debug |
686 | ("*** Change actual Cas Latencies cause of minimumCycleTime n"); | |
3a473b2a WD |
687 | } |
688 | /* ronen - checkif the Dimm frequency compared to the Sysclock. */ | |
689 | if ((dimmInfo-> | |
690 | minimumCycleTimeAtMaxCasLatancy_LoP | |
691 | > | |
6d0f6bcf | 692 | CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) |
3a473b2a WD |
693 | || |
694 | ((dimmInfo-> | |
695 | minimumCycleTimeAtMaxCasLatancy_LoP | |
696 | == | |
6d0f6bcf | 697 | CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP) |
3a473b2a WD |
698 | && (dimmInfo-> |
699 | minimumCycleTimeAtMaxCasLatancy_RoP | |
700 | > | |
6d0f6bcf | 701 | CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP))) |
3a473b2a WD |
702 | { |
703 | printf ("*********************************************************\n"); | |
704 | printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n"); | |
705 | printf ("*********************************************************\n"); | |
706 | hang (); | |
707 | } | |
708 | ||
709 | dimmInfo-> | |
710 | maxCASlatencySupported_LoP | |
711 | = | |
712 | 1 + | |
713 | (int) (5 * j / 10); | |
714 | if (((5 * j) % 10) != 0) | |
715 | dimmInfo-> | |
716 | maxCASlatencySupported_RoP | |
717 | = 5; | |
718 | else | |
719 | dimmInfo-> | |
720 | maxCASlatencySupported_RoP | |
721 | = 0; | |
4fcfbec0 | 722 | debug |
3a473b2a WD |
723 | ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", |
724 | dimmInfo-> | |
725 | maxCASlatencySupported_LoP, | |
726 | dimmInfo-> | |
4fcfbec0 | 727 | maxCASlatencySupported_RoP); |
3a473b2a WD |
728 | break; |
729 | case SDRAM: | |
730 | /* CAS latency 1, 2, 3, 4, 5, 6, 7 */ | |
731 | dimmInfo->maxClSupported_SD = j; /* Cas Latency DDR-RAM Coded */ | |
4fcfbec0 | 732 | debug |
3a473b2a WD |
733 | ("Max. Cas Latencies (SD): %d\n", |
734 | dimmInfo-> | |
4fcfbec0 | 735 | maxClSupported_SD); |
3a473b2a WD |
736 | dimmInfo-> |
737 | maxCASlatencySupported_LoP | |
738 | = j; | |
739 | dimmInfo-> | |
740 | maxCASlatencySupported_RoP | |
741 | = 0; | |
4fcfbec0 | 742 | debug |
3a473b2a WD |
743 | ("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n", |
744 | dimmInfo-> | |
745 | maxCASlatencySupported_LoP, | |
746 | dimmInfo-> | |
4fcfbec0 | 747 | maxCASlatencySupported_RoP); |
3a473b2a WD |
748 | break; |
749 | } | |
750 | break; | |
751 | } | |
752 | } | |
753 | break; | |
754 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
755 | ||
756 | case 21: /* Buffered Address And Control Inputs */ | |
4fcfbec0 | 757 | debug("\nModul Attributes (SPD Byte 21): \n"); |
3a473b2a WD |
758 | dimmInfo->bufferedAddrAndControlInputs = |
759 | data[i] & BIT0; | |
760 | dimmInfo->registeredAddrAndControlInputs = | |
761 | (data[i] & BIT1) >> 1; | |
762 | dimmInfo->onCardPLL = (data[i] & BIT2) >> 2; | |
763 | dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3; | |
764 | dimmInfo->registeredDQMBinputs = | |
765 | (data[i] & BIT4) >> 4; | |
766 | dimmInfo->differentialClockInput = | |
767 | (data[i] & BIT5) >> 5; | |
768 | dimmInfo->redundantRowAddressing = | |
769 | (data[i] & BIT6) >> 6; | |
770 | #ifdef DEBUG | |
771 | if (dimmInfo->bufferedAddrAndControlInputs == 1) | |
4fcfbec0 WD |
772 | debug |
773 | (" - Buffered Address/Control Input: Yes \n"); | |
3a473b2a | 774 | else |
4fcfbec0 WD |
775 | debug |
776 | (" - Buffered Address/Control Input: No \n"); | |
3a473b2a WD |
777 | |
778 | if (dimmInfo->registeredAddrAndControlInputs == 1) | |
4fcfbec0 WD |
779 | debug |
780 | (" - Registered Address/Control Input: Yes \n"); | |
3a473b2a | 781 | else |
4fcfbec0 WD |
782 | debug |
783 | (" - Registered Address/Control Input: No \n"); | |
3a473b2a WD |
784 | |
785 | if (dimmInfo->onCardPLL == 1) | |
4fcfbec0 WD |
786 | debug |
787 | (" - On-Card PLL (clock): Yes \n"); | |
3a473b2a | 788 | else |
4fcfbec0 WD |
789 | debug |
790 | (" - On-Card PLL (clock): No \n"); | |
3a473b2a WD |
791 | |
792 | if (dimmInfo->bufferedDQMBinputs == 1) | |
4fcfbec0 WD |
793 | debug |
794 | (" - Bufferd DQMB Inputs: Yes \n"); | |
3a473b2a | 795 | else |
4fcfbec0 WD |
796 | debug |
797 | (" - Bufferd DQMB Inputs: No \n"); | |
3a473b2a WD |
798 | |
799 | if (dimmInfo->registeredDQMBinputs == 1) | |
4fcfbec0 WD |
800 | debug |
801 | (" - Registered DQMB Inputs: Yes \n"); | |
3a473b2a | 802 | else |
4fcfbec0 WD |
803 | debug |
804 | (" - Registered DQMB Inputs: No \n"); | |
3a473b2a WD |
805 | |
806 | if (dimmInfo->differentialClockInput == 1) | |
4fcfbec0 WD |
807 | debug |
808 | (" - Differential Clock Input: Yes \n"); | |
3a473b2a | 809 | else |
4fcfbec0 WD |
810 | debug |
811 | (" - Differential Clock Input: No \n"); | |
3a473b2a WD |
812 | |
813 | if (dimmInfo->redundantRowAddressing == 1) | |
4fcfbec0 WD |
814 | debug |
815 | (" - redundant Row Addressing: Yes \n"); | |
3a473b2a | 816 | else |
4fcfbec0 WD |
817 | debug |
818 | (" - redundant Row Addressing: No \n"); | |
3a473b2a WD |
819 | |
820 | #endif | |
821 | break; | |
822 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
823 | ||
824 | case 22: /* Suported AutoPreCharge */ | |
4fcfbec0 | 825 | debug("\nModul Attributes (SPD Byte 22): \n"); |
3a473b2a WD |
826 | dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0; |
827 | dimmInfo->suportedAutoPreCharge = | |
828 | (data[i] & BIT1) >> 1; | |
829 | dimmInfo->suportedPreChargeAll = | |
830 | (data[i] & BIT2) >> 2; | |
831 | dimmInfo->suportedWrite1ReadBurst = | |
832 | (data[i] & BIT3) >> 3; | |
833 | dimmInfo->suported5PercentLowVCC = | |
834 | (data[i] & BIT4) >> 4; | |
835 | dimmInfo->suported5PercentUpperVCC = | |
836 | (data[i] & BIT5) >> 5; | |
837 | #ifdef DEBUG | |
838 | if (dimmInfo->suportedEarlyRasPreCharge == 1) | |
4fcfbec0 WD |
839 | debug |
840 | (" - Early Ras Precharge: Yes \n"); | |
3a473b2a | 841 | else |
4fcfbec0 WD |
842 | debug |
843 | (" - Early Ras Precharge: No \n"); | |
3a473b2a WD |
844 | |
845 | if (dimmInfo->suportedAutoPreCharge == 1) | |
4fcfbec0 WD |
846 | debug |
847 | (" - AutoPreCharge: Yes \n"); | |
3a473b2a | 848 | else |
4fcfbec0 WD |
849 | debug |
850 | (" - AutoPreCharge: No \n"); | |
3a473b2a WD |
851 | |
852 | if (dimmInfo->suportedPreChargeAll == 1) | |
4fcfbec0 WD |
853 | debug |
854 | (" - Precharge All: Yes \n"); | |
3a473b2a | 855 | else |
4fcfbec0 WD |
856 | debug |
857 | (" - Precharge All: No \n"); | |
3a473b2a WD |
858 | |
859 | if (dimmInfo->suportedWrite1ReadBurst == 1) | |
4fcfbec0 WD |
860 | debug |
861 | (" - Write 1/ReadBurst: Yes \n"); | |
3a473b2a | 862 | else |
4fcfbec0 WD |
863 | debug |
864 | (" - Write 1/ReadBurst: No \n"); | |
3a473b2a WD |
865 | |
866 | if (dimmInfo->suported5PercentLowVCC == 1) | |
4fcfbec0 WD |
867 | debug |
868 | (" - lower VCC tolerance: 5 Percent \n"); | |
3a473b2a | 869 | else |
4fcfbec0 WD |
870 | debug |
871 | (" - lower VCC tolerance: 10 Percent \n"); | |
3a473b2a WD |
872 | |
873 | if (dimmInfo->suported5PercentUpperVCC == 1) | |
4fcfbec0 WD |
874 | debug |
875 | (" - upper VCC tolerance: 5 Percent \n"); | |
3a473b2a | 876 | else |
4fcfbec0 WD |
877 | debug |
878 | (" - upper VCC tolerance: 10 Percent \n"); | |
3a473b2a WD |
879 | |
880 | #endif | |
881 | break; | |
882 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
883 | ||
884 | case 23: /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */ | |
885 | shift = (dimmInfo->memoryType == DDR) ? 4 : 2; | |
886 | mult = (dimmInfo->memoryType == DDR) ? 10 : 25; | |
887 | maskLeftOfPoint = | |
888 | (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; | |
889 | maskRightOfPoint = | |
890 | (dimmInfo->memoryType == DDR) ? 0xf : 0x03; | |
891 | leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; | |
892 | rightOfPoint = (data[i] & maskRightOfPoint) * mult; | |
893 | dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP = | |
894 | leftOfPoint; | |
895 | dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP = | |
896 | rightOfPoint; | |
4fcfbec0 | 897 | debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ |
3a473b2a WD |
898 | break; |
899 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
900 | ||
901 | case 24: /* Clock To Data Out 2nd highest Cas Latency Value */ | |
902 | div = (dimmInfo->memoryType == DDR) ? 100 : 10; | |
903 | time_tmp = | |
904 | (((data[i] & 0xf0) >> 4) * 10) + | |
905 | ((data[i] & 0x0f)); | |
906 | leftOfPoint = time_tmp / div; | |
907 | rightOfPoint = time_tmp % div; | |
908 | dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint; | |
909 | dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint; | |
4fcfbec0 | 910 | debug |
3a473b2a | 911 | ("Clock To Data Out (2nd CL value): %d.%2d [ns]\n", |
4fcfbec0 | 912 | leftOfPoint, rightOfPoint); |
3a473b2a WD |
913 | break; |
914 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
915 | ||
916 | case 25: /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */ | |
917 | shift = (dimmInfo->memoryType == DDR) ? 4 : 2; | |
918 | mult = (dimmInfo->memoryType == DDR) ? 10 : 25; | |
919 | maskLeftOfPoint = | |
920 | (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc; | |
921 | maskRightOfPoint = | |
922 | (dimmInfo->memoryType == DDR) ? 0xf : 0x03; | |
923 | leftOfPoint = (data[i] & maskLeftOfPoint) >> shift; | |
924 | rightOfPoint = (data[i] & maskRightOfPoint) * mult; | |
925 | dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP = | |
926 | leftOfPoint; | |
927 | dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP = | |
928 | rightOfPoint; | |
4fcfbec0 | 929 | debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n", leftOfPoint, rightOfPoint); /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */ |
3a473b2a WD |
930 | break; |
931 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
932 | ||
933 | case 26: /* Clock To Data Out 3rd highest Cas Latency Value */ | |
934 | div = (dimmInfo->memoryType == DDR) ? 100 : 10; | |
935 | time_tmp = | |
936 | (((data[i] & 0xf0) >> 4) * 10) + | |
937 | ((data[i] & 0x0f)); | |
938 | leftOfPoint = time_tmp / div; | |
939 | rightOfPoint = time_tmp % div; | |
940 | dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint; | |
941 | dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint; | |
4fcfbec0 | 942 | debug |
3a473b2a | 943 | ("Clock To Data Out (3rd CL value): %d.%2d [ns]\n", |
4fcfbec0 | 944 | leftOfPoint, rightOfPoint); |
3a473b2a WD |
945 | break; |
946 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
947 | ||
948 | case 27: /* Minimum Row Precharge Time */ | |
949 | shift = (dimmInfo->memoryType == DDR) ? 2 : 0; | |
950 | maskLeftOfPoint = | |
951 | (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; | |
952 | maskRightOfPoint = | |
953 | (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; | |
954 | leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); | |
955 | rightOfPoint = (data[i] & maskRightOfPoint) * 25; | |
956 | ||
957 | dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint); /* measured in n times 10ps Intervals */ | |
958 | trp_clocks = | |
959 | (dimmInfo->minRowPrechargeTime + | |
960 | (tmemclk - 1)) / tmemclk; | |
4fcfbec0 | 961 | debug |
3a473b2a | 962 | ("*** 1 clock cycle = %ld 10ps intervalls = %ld.%ld ns****\n", |
4fcfbec0 WD |
963 | tmemclk, tmemclk / 100, tmemclk % 100); |
964 | debug | |
3a473b2a | 965 | ("Minimum Row Precharge Time [ns]: %d.%2d = in Clk cycles %d\n", |
4fcfbec0 | 966 | leftOfPoint, rightOfPoint, trp_clocks); |
3a473b2a WD |
967 | break; |
968 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
969 | ||
970 | case 28: /* Minimum Row Active to Row Active Time */ | |
971 | shift = (dimmInfo->memoryType == DDR) ? 2 : 0; | |
972 | maskLeftOfPoint = | |
973 | (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; | |
974 | maskRightOfPoint = | |
975 | (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; | |
976 | leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); | |
977 | rightOfPoint = (data[i] & maskRightOfPoint) * 25; | |
978 | ||
979 | dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ | |
4fcfbec0 | 980 | debug |
3a473b2a | 981 | ("Minimum Row Active -To- Row Active Delay [ns]: %d.%2d = in Clk cycles %d\n", |
4fcfbec0 | 982 | leftOfPoint, rightOfPoint, trp_clocks); |
3a473b2a WD |
983 | break; |
984 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
985 | ||
986 | case 29: /* Minimum Ras-To-Cas Delay */ | |
987 | shift = (dimmInfo->memoryType == DDR) ? 2 : 0; | |
988 | maskLeftOfPoint = | |
989 | (dimmInfo->memoryType == DDR) ? 0xfc : 0xff; | |
990 | maskRightOfPoint = | |
991 | (dimmInfo->memoryType == DDR) ? 0x03 : 0x00; | |
992 | leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift); | |
993 | rightOfPoint = (data[i] & maskRightOfPoint) * 25; | |
994 | ||
995 | dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint); /* measured in 100ns Intervals */ | |
4fcfbec0 | 996 | debug |
3a473b2a | 997 | ("Minimum Ras-To-Cas Delay [ns]: %d.%2d = in Clk cycles %d\n", |
4fcfbec0 | 998 | leftOfPoint, rightOfPoint, trp_clocks); |
3a473b2a WD |
999 | break; |
1000 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
1001 | ||
1002 | case 30: /* Minimum Ras Pulse Width */ | |
1003 | dimmInfo->minRasPulseWidth = data[i]; | |
1004 | tras_clocks = | |
1005 | (NSto10PS (data[i]) + | |
1006 | (tmemclk - 1)) / tmemclk; | |
4fcfbec0 | 1007 | debug |
3a473b2a | 1008 | ("Minimum Ras Pulse Width [ns]: %d = in Clk cycles %d\n", |
4fcfbec0 | 1009 | dimmInfo->minRasPulseWidth, tras_clocks); |
3a473b2a WD |
1010 | |
1011 | break; | |
1012 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
1013 | ||
1014 | case 31: /* Module Bank Density */ | |
1015 | dimmInfo->moduleBankDensity = data[i]; | |
4fcfbec0 | 1016 | debug |
3a473b2a | 1017 | ("Module Bank Density: %d\n", |
4fcfbec0 | 1018 | dimmInfo->moduleBankDensity); |
3a473b2a | 1019 | #ifdef DEBUG |
4fcfbec0 WD |
1020 | debug |
1021 | ("*** Offered Densities (more than 1 = Multisize-Module): "); | |
3a473b2a WD |
1022 | { |
1023 | if (dimmInfo->moduleBankDensity & 1) | |
4fcfbec0 | 1024 | debug("4MB, "); |
3a473b2a | 1025 | if (dimmInfo->moduleBankDensity & 2) |
4fcfbec0 | 1026 | debug("8MB, "); |
3a473b2a | 1027 | if (dimmInfo->moduleBankDensity & 4) |
4fcfbec0 | 1028 | debug("16MB, "); |
3a473b2a | 1029 | if (dimmInfo->moduleBankDensity & 8) |
4fcfbec0 | 1030 | debug("32MB, "); |
3a473b2a | 1031 | if (dimmInfo->moduleBankDensity & 16) |
4fcfbec0 | 1032 | debug("64MB, "); |
3a473b2a | 1033 | if (dimmInfo->moduleBankDensity & 32) |
4fcfbec0 | 1034 | debug("128MB, "); |
3a473b2a WD |
1035 | if ((dimmInfo->moduleBankDensity & 64) |
1036 | || (dimmInfo->moduleBankDensity & 128)) { | |
4fcfbec0 | 1037 | debug("ERROR, "); |
3a473b2a WD |
1038 | hang (); |
1039 | } | |
1040 | } | |
4fcfbec0 | 1041 | debug("\n"); |
3a473b2a WD |
1042 | #endif |
1043 | break; | |
1044 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
1045 | ||
1046 | case 32: /* Address And Command Setup Time (measured in ns/1000) */ | |
1047 | sign = 1; | |
1048 | switch (dimmInfo->memoryType) { | |
1049 | case DDR: | |
1050 | time_tmp = | |
1051 | (((data[i] & 0xf0) >> 4) * 10) + | |
1052 | ((data[i] & 0x0f)); | |
1053 | leftOfPoint = time_tmp / 100; | |
1054 | rightOfPoint = time_tmp % 100; | |
1055 | break; | |
1056 | case SDRAM: | |
1057 | leftOfPoint = (data[i] & 0xf0) >> 4; | |
1058 | if (leftOfPoint > 7) { | |
1059 | leftOfPoint = data[i] & 0x70 >> 4; | |
1060 | sign = -1; | |
1061 | } | |
1062 | rightOfPoint = (data[i] & 0x0f); | |
1063 | break; | |
1064 | } | |
1065 | dimmInfo->addrAndCommandSetupTime = | |
1066 | (leftOfPoint * 100 + rightOfPoint) * sign; | |
4fcfbec0 | 1067 | debug |
3a473b2a | 1068 | ("Address And Command Setup Time [ns]: %d.%d\n", |
4fcfbec0 | 1069 | sign * leftOfPoint, rightOfPoint); |
3a473b2a WD |
1070 | break; |
1071 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
1072 | ||
1073 | case 33: /* Address And Command Hold Time */ | |
1074 | sign = 1; | |
1075 | switch (dimmInfo->memoryType) { | |
1076 | case DDR: | |
1077 | time_tmp = | |
1078 | (((data[i] & 0xf0) >> 4) * 10) + | |
1079 | ((data[i] & 0x0f)); | |
1080 | leftOfPoint = time_tmp / 100; | |
1081 | rightOfPoint = time_tmp % 100; | |
1082 | break; | |
1083 | case SDRAM: | |
1084 | leftOfPoint = (data[i] & 0xf0) >> 4; | |
1085 | if (leftOfPoint > 7) { | |
1086 | leftOfPoint = data[i] & 0x70 >> 4; | |
1087 | sign = -1; | |
1088 | } | |
1089 | rightOfPoint = (data[i] & 0x0f); | |
1090 | break; | |
1091 | } | |
1092 | dimmInfo->addrAndCommandHoldTime = | |
1093 | (leftOfPoint * 100 + rightOfPoint) * sign; | |
4fcfbec0 | 1094 | debug |
3a473b2a | 1095 | ("Address And Command Hold Time [ns]: %d.%d\n", |
4fcfbec0 | 1096 | sign * leftOfPoint, rightOfPoint); |
3a473b2a WD |
1097 | break; |
1098 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
1099 | ||
1100 | case 34: /* Data Input Setup Time */ | |
1101 | sign = 1; | |
1102 | switch (dimmInfo->memoryType) { | |
1103 | case DDR: | |
1104 | time_tmp = | |
1105 | (((data[i] & 0xf0) >> 4) * 10) + | |
1106 | ((data[i] & 0x0f)); | |
1107 | leftOfPoint = time_tmp / 100; | |
1108 | rightOfPoint = time_tmp % 100; | |
1109 | break; | |
1110 | case SDRAM: | |
1111 | leftOfPoint = (data[i] & 0xf0) >> 4; | |
1112 | if (leftOfPoint > 7) { | |
1113 | leftOfPoint = data[i] & 0x70 >> 4; | |
1114 | sign = -1; | |
1115 | } | |
1116 | rightOfPoint = (data[i] & 0x0f); | |
1117 | break; | |
1118 | } | |
1119 | dimmInfo->dataInputSetupTime = | |
1120 | (leftOfPoint * 100 + rightOfPoint) * sign; | |
4fcfbec0 | 1121 | debug |
3a473b2a | 1122 | ("Data Input Setup Time [ns]: %d.%d\n", |
4fcfbec0 | 1123 | sign * leftOfPoint, rightOfPoint); |
3a473b2a WD |
1124 | break; |
1125 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
1126 | ||
1127 | case 35: /* Data Input Hold Time */ | |
1128 | sign = 1; | |
1129 | switch (dimmInfo->memoryType) { | |
1130 | case DDR: | |
1131 | time_tmp = | |
1132 | (((data[i] & 0xf0) >> 4) * 10) + | |
1133 | ((data[i] & 0x0f)); | |
1134 | leftOfPoint = time_tmp / 100; | |
1135 | rightOfPoint = time_tmp % 100; | |
1136 | break; | |
1137 | case SDRAM: | |
1138 | leftOfPoint = (data[i] & 0xf0) >> 4; | |
1139 | if (leftOfPoint > 7) { | |
1140 | leftOfPoint = data[i] & 0x70 >> 4; | |
1141 | sign = -1; | |
1142 | } | |
1143 | rightOfPoint = (data[i] & 0x0f); | |
1144 | break; | |
1145 | } | |
1146 | dimmInfo->dataInputHoldTime = | |
1147 | (leftOfPoint * 100 + rightOfPoint) * sign; | |
4fcfbec0 | 1148 | debug |
3a473b2a | 1149 | ("Data Input Hold Time [ns]: %d.%d\n\n", |
4fcfbec0 | 1150 | sign * leftOfPoint, rightOfPoint); |
3a473b2a WD |
1151 | break; |
1152 | /*------------------------------------------------------------------------------------------------------------------------------*/ | |
1153 | } | |
1154 | } | |
1155 | /* calculating the sdram density */ | |
1156 | for (i = 0; | |
1157 | i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses; | |
1158 | i++) { | |
1159 | density = density * 2; | |
1160 | } | |
1161 | dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice * | |
1162 | dimmInfo->sdramWidth; | |
1163 | dimmInfo->numberOfDevices = | |
1164 | (dimmInfo->dataWidth / dimmInfo->sdramWidth) * | |
1165 | dimmInfo->numOfModuleBanks; | |
3a473b2a WD |
1166 | if ((dimmInfo->errorCheckType == 0x1) |
1167 | || (dimmInfo->errorCheckType == 0x2) | |
1168 | || (dimmInfo->errorCheckType == 0x3)) { | |
1169 | dimmInfo->size = | |
1170 | (dimmInfo->deviceDensity / 8) * | |
1171 | (dimmInfo->numberOfDevices - | |
1172 | /* ronen on the 1G dimm we get wrong value. (was devicesForErrCheck) */ | |
1173 | dimmInfo->numberOfDevices / 8); | |
1174 | } else { | |
1175 | dimmInfo->size = | |
1176 | (dimmInfo->deviceDensity / 8) * | |
1177 | dimmInfo->numberOfDevices; | |
1178 | } | |
1179 | ||
1180 | /* compute the module DRB size */ | |
1181 | tmp = (1 << | |
1182 | (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses)); | |
1183 | tmp *= dimmInfo->numOfModuleBanks; | |
1184 | tmp *= dimmInfo->sdramWidth; | |
1185 | tmp = tmp >> 24; /* div by 0x4000000 (64M) */ | |
1186 | dimmInfo->drb_size = (uchar) tmp; | |
4fcfbec0 | 1187 | debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size); |
3a473b2a WD |
1188 | |
1189 | /* try a CAS latency of 3 first... */ | |
1190 | ||
1191 | /* bit 1 is CL2, bit 2 is CL3 */ | |
1192 | supp_cal = (dimmInfo->suportedCasLatencies & 0x6) >> 1; | |
1193 | ||
1194 | cal_val = 0; | |
1195 | if (supp_cal & 3) { | |
1196 | if (NS10to10PS (data[9]) <= tmemclk) | |
1197 | cal_val = 3; | |
1198 | } | |
1199 | ||
1200 | /* then 2... */ | |
1201 | if (supp_cal & 2) { | |
1202 | if (NS10to10PS (data[23]) <= tmemclk) | |
1203 | cal_val = 2; | |
1204 | } | |
1205 | ||
4fcfbec0 | 1206 | debug("cal_val = %d\n", cal_val); |
3a473b2a WD |
1207 | |
1208 | /* bummer, did't work... */ | |
1209 | if (cal_val == 0) { | |
4fcfbec0 | 1210 | debug("Couldn't find a good CAS latency\n"); |
3a473b2a WD |
1211 | hang (); |
1212 | return 0; | |
1213 | } | |
1214 | ||
1215 | return true; | |
1216 | ||
1217 | #endif | |
1218 | } | |
1219 | ||
1220 | /* sets up the GT properly with information passed in */ | |
1221 | int setup_sdram (AUX_MEM_DIMM_INFO * info) | |
1222 | { | |
1223 | ulong tmp, check; | |
1224 | ulong tmp_sdram_mode = 0; /* 0x141c */ | |
1225 | ulong tmp_dunit_control_low = 0; /* 0x1404 */ | |
1226 | int i; | |
1227 | ||
1228 | /* added 8/21/2003 P. Marchese */ | |
1229 | unsigned int sdram_config_reg; | |
1230 | ||
1231 | /* added 10/10/2003 P. Marchese */ | |
1232 | ulong sdram_chip_size; | |
1233 | ||
1234 | /* sanity checking */ | |
1235 | if (!info->numOfModuleBanks) { | |
1236 | printf ("setup_sdram called with 0 banks\n"); | |
1237 | return 1; | |
1238 | } | |
1239 | ||
1240 | /* delay line */ | |
1241 | set_dfcdlInit (); /* may be its not needed */ | |
4fcfbec0 | 1242 | debug("Delay line set done\n"); |
3a473b2a WD |
1243 | |
1244 | /* set SDRAM mode NOP */ /* To_do check it */ | |
1245 | GT_REG_WRITE (SDRAM_OPERATION, 0x5); | |
1246 | while (GTREGREAD (SDRAM_OPERATION) != 0) { | |
4fcfbec0 WD |
1247 | debug |
1248 | ("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n"); | |
3a473b2a WD |
1249 | } |
1250 | ||
1251 | /* SDRAM configuration */ | |
1252 | /* added 8/21/2003 P. Marchese */ | |
1253 | /* code allows usage of registered DIMMS */ | |
1254 | ||
1255 | /* figure out the memory refresh internal */ | |
1256 | switch (info->RefreshInterval) { | |
1257 | case 0x0: | |
1258 | case 0x80: /* refresh period is 15.625 usec */ | |
1259 | sdram_config_reg = | |
ee80fa7b | 1260 | (unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_CLK) |
3a473b2a WD |
1261 | / (float) 1000000.0); |
1262 | break; | |
1263 | case 0x1: | |
1264 | case 0x81: /* refresh period is 3.9 usec */ | |
1265 | sdram_config_reg = | |
ee80fa7b | 1266 | (unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_CLK) / |
3a473b2a WD |
1267 | (float) 1000000.0); |
1268 | break; | |
1269 | case 0x2: | |
1270 | case 0x82: /* refresh period is 7.8 usec */ | |
1271 | sdram_config_reg = | |
ee80fa7b | 1272 | (unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_CLK) / |
3a473b2a WD |
1273 | (float) 1000000.0); |
1274 | break; | |
1275 | case 0x3: | |
1276 | case 0x83: /* refresh period is 31.3 usec */ | |
1277 | sdram_config_reg = | |
ee80fa7b | 1278 | (unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_CLK) / |
3a473b2a WD |
1279 | (float) 1000000.0); |
1280 | break; | |
1281 | case 0x4: | |
1282 | case 0x84: /* refresh period is 62.5 usec */ | |
1283 | sdram_config_reg = | |
ee80fa7b | 1284 | (unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_CLK) / |
3a473b2a WD |
1285 | (float) 1000000.0); |
1286 | break; | |
1287 | case 0x5: | |
1288 | case 0x85: /* refresh period is 125 usec */ | |
1289 | sdram_config_reg = | |
ee80fa7b | 1290 | (unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_CLK) / |
3a473b2a WD |
1291 | (float) 1000000.0); |
1292 | break; | |
1293 | default: /* refresh period undefined */ | |
1294 | printf ("DRAM refresh period is unknown!\n"); | |
1295 | printf ("Aborting DRAM setup with an error\n"); | |
1296 | hang (); | |
1297 | break; | |
1298 | } | |
4fcfbec0 | 1299 | debug("calculated refresh interval %0x\n", sdram_config_reg); |
3a473b2a WD |
1300 | |
1301 | /* make sure the refresh value is only 14 bits */ | |
1302 | if (sdram_config_reg > 0x1fff) | |
1303 | sdram_config_reg = 0x1fff; | |
4fcfbec0 | 1304 | debug("adjusted refresh interval %0x\n", sdram_config_reg); |
3a473b2a WD |
1305 | |
1306 | /* we want physical bank interleaving and */ | |
1307 | /* virtual bank interleaving enabled so do nothing */ | |
1308 | /* since these bits need to be zero to enable the interleaving */ | |
1309 | ||
1310 | /* registered DRAM ? */ | |
1311 | if (info->registeredAddrAndControlInputs == 1) { | |
1312 | /* it's registered DRAM, so set the reg. DRAM bit */ | |
1313 | sdram_config_reg = sdram_config_reg | BIT17; | |
4fcfbec0 | 1314 | debug("Enabling registered DRAM bit\n"); |
3a473b2a WD |
1315 | } |
1316 | /* turn on DRAM ECC? */ | |
1317 | #ifdef CONFIG_MV64360_ECC | |
1318 | if (info->errorCheckType == 0x2) { | |
1319 | /* DRAM has ECC, so turn it on */ | |
1320 | sdram_config_reg = sdram_config_reg | BIT18; | |
4fcfbec0 | 1321 | debug("Enabling ECC\n"); |
3a473b2a WD |
1322 | } |
1323 | #endif | |
1324 | /* set the data DQS pin configuration */ | |
1325 | switch (info->sdramWidth) { | |
1326 | case 0x4: /* memory is x4 */ | |
1327 | sdram_config_reg = sdram_config_reg | BIT20 | BIT21; | |
4fcfbec0 | 1328 | debug("Data DQS pins set for 16 pins\n"); |
3a473b2a WD |
1329 | break; |
1330 | case 0x8: /* memory is x8 or x16 */ | |
1331 | case 0x10: | |
1332 | sdram_config_reg = sdram_config_reg | BIT21; | |
4fcfbec0 | 1333 | debug("Data DQS pins set for 8 pins\n"); |
3a473b2a WD |
1334 | break; |
1335 | case 0x20: /* memory is x32 */ | |
1336 | /* both bits are cleared for x32 so nothing to do */ | |
4fcfbec0 | 1337 | debug("Data DQS pins set for 2 pins\n"); |
3a473b2a WD |
1338 | break; |
1339 | default: /* memory width unsupported */ | |
1340 | printf ("DRAM chip width is unknown!\n"); | |
1341 | printf ("Aborting DRAM setup with an error\n"); | |
1342 | hang (); | |
1343 | break; | |
1344 | } | |
1345 | ||
1346 | /* perform read buffer assignments */ | |
1347 | /* we are going to use the Power-up defaults */ | |
1348 | /* bit 26 = CPU = buffer 1 */ | |
1349 | /* bit 27 = PCI bus #0 = buffer 0 */ | |
1350 | /* bit 28 = PCI bus #1 = buffer 0 */ | |
1351 | /* bit 29 = MPSC = buffer 0 */ | |
1352 | /* bit 30 = IDMA = buffer 0 */ | |
1353 | /* bit 31 = Gigabit = buffer 0 */ | |
1354 | sdram_config_reg = sdram_config_reg | BIT26; | |
1355 | /* sdram_config_reg = sdram_config_reg | 0x58000000; */ | |
1356 | /* sdram_config_reg = sdram_config_reg & 0xffffff00; */ | |
1357 | ||
1358 | /* write the value into the SDRAM configuration register */ | |
1359 | GT_REG_WRITE (SDRAM_CONFIG, sdram_config_reg); | |
4fcfbec0 | 1360 | debug |
3a473b2a | 1361 | ("OOOOOOOOO sdram_conf 0x1400: %08x\n", |
4fcfbec0 | 1362 | GTREGREAD (SDRAM_CONFIG)); |
3a473b2a WD |
1363 | |
1364 | /* SDRAM open pages control keep open as much as I can */ | |
1365 | GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0); | |
4fcfbec0 | 1366 | debug |
3a473b2a | 1367 | ("sdram_open_pages_controll 0x1414: %08x\n", |
4fcfbec0 | 1368 | GTREGREAD (SDRAM_OPEN_PAGES_CONTROL)); |
3a473b2a WD |
1369 | |
1370 | /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ | |
1371 | tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01); /* Clock Domain Sync from power on reset */ | |
1372 | if (tmp == 0) | |
4fcfbec0 | 1373 | debug("Core Signals are sync (by HW-Setting)!!!\n"); |
3a473b2a | 1374 | else |
4fcfbec0 WD |
1375 | debug |
1376 | ("Core Signals syncs. are bypassed (by HW-Setting)!!!\n"); | |
3a473b2a WD |
1377 | |
1378 | /* SDRAM set CAS Latency according to SPD information */ | |
1379 | switch (info->memoryType) { | |
1380 | case SDRAM: | |
1381 | printf ("### SD-RAM not supported !!!\n"); | |
1382 | printf ("Aborting!!!\n"); | |
1383 | hang (); | |
1384 | /* ToDo fill SD-RAM if needed !!!!! */ | |
1385 | break; | |
1386 | /* Calculate the settings for SDRAM mode and Dunit control low registers */ | |
1387 | /* Values set according to technical bulletin TB-92 rev. c */ | |
1388 | case DDR: | |
4fcfbec0 | 1389 | debug("### SET-CL for DDR-RAM\n"); |
3a473b2a WD |
1390 | switch (info->maxClSupported_DDR) { |
1391 | case DDR_CL_3: | |
1392 | tmp_sdram_mode = 0x32; /* CL=3 Burstlength = 4 */ | |
1393 | if (tmp == 1) { /* clocks sync */ | |
1394 | if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ | |
1395 | tmp_dunit_control_low = 0x05110051; | |
1396 | else | |
1397 | tmp_dunit_control_low = 0x24110051; | |
4fcfbec0 | 1398 | debug |
3a473b2a | 1399 | ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", |
4fcfbec0 | 1400 | tmp_sdram_mode, tmp_dunit_control_low); |
3a473b2a WD |
1401 | } else { /* clk sync. bypassed */ |
1402 | ||
1403 | if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ | |
1404 | tmp_dunit_control_low = 0x2C1107F2; | |
1405 | else | |
1406 | tmp_dunit_control_low = 0x3C1107d2; | |
4fcfbec0 | 1407 | debug |
3a473b2a | 1408 | ("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", |
4fcfbec0 | 1409 | tmp_sdram_mode, tmp_dunit_control_low); |
3a473b2a WD |
1410 | } |
1411 | break; | |
1412 | case DDR_CL_2_5: | |
1413 | tmp_sdram_mode = 0x62; /* CL=2.5 Burstlength = 4 */ | |
1414 | if (tmp == 1) { /* clocks sync */ | |
1415 | if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ | |
1416 | tmp_dunit_control_low = 0x25110051; | |
1417 | else | |
1418 | tmp_dunit_control_low = 0x24110051; | |
4fcfbec0 | 1419 | debug |
3a473b2a | 1420 | ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", |
4fcfbec0 | 1421 | tmp_sdram_mode, tmp_dunit_control_low); |
3a473b2a WD |
1422 | } else { /* clk sync. bypassed */ |
1423 | ||
1424 | if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ | |
1425 | printf ("CL = 2.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n"); | |
1426 | printf ("Aborting!!!\n"); | |
1427 | hang (); | |
1428 | } else | |
1429 | tmp_dunit_control_low = 0x1B1107d2; | |
4fcfbec0 | 1430 | debug |
3a473b2a | 1431 | ("Max. CL is 2.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", |
4fcfbec0 | 1432 | tmp_sdram_mode, tmp_dunit_control_low); |
3a473b2a WD |
1433 | } |
1434 | break; | |
1435 | case DDR_CL_2: | |
1436 | tmp_sdram_mode = 0x22; /* CL=2 Burstlength = 4 */ | |
1437 | if (tmp == 1) { /* clocks sync */ | |
1438 | if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ | |
1439 | tmp_dunit_control_low = 0x04110051; | |
1440 | else | |
1441 | tmp_dunit_control_low = 0x03110051; | |
4fcfbec0 | 1442 | debug |
3a473b2a | 1443 | ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", |
4fcfbec0 | 1444 | tmp_sdram_mode, tmp_dunit_control_low); |
3a473b2a WD |
1445 | } else { /* clk sync. bypassed */ |
1446 | ||
1447 | if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ | |
1448 | printf ("CL = 2, Clock Unsync'ed, Dunit Control Low register setting undefined\n"); | |
1449 | printf ("Aborting!!!\n"); | |
1450 | hang (); | |
1451 | } else | |
1452 | tmp_dunit_control_low = 0x3B1107d2; | |
4fcfbec0 | 1453 | debug |
3a473b2a | 1454 | ("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", |
4fcfbec0 | 1455 | tmp_sdram_mode, tmp_dunit_control_low); |
3a473b2a WD |
1456 | } |
1457 | break; | |
1458 | case DDR_CL_1_5: | |
1459 | tmp_sdram_mode = 0x52; /* CL=1.5 Burstlength = 4 */ | |
1460 | if (tmp == 1) { /* clocks sync */ | |
1461 | if (info->registeredAddrAndControlInputs == 1) /* registerd DDR SDRAM? */ | |
1462 | tmp_dunit_control_low = 0x24110051; | |
1463 | else | |
1464 | tmp_dunit_control_low = 0x23110051; | |
4fcfbec0 | 1465 | debug |
3a473b2a | 1466 | ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", |
4fcfbec0 | 1467 | tmp_sdram_mode, tmp_dunit_control_low); |
3a473b2a WD |
1468 | } else { /* clk sync. bypassed */ |
1469 | ||
1470 | if (info->registeredAddrAndControlInputs == 1) { /* registerd DDR SDRAM? */ | |
1471 | printf ("CL = 1.5, Clock Unsync'ed, Dunit Control Low register setting undefined\n"); | |
1472 | printf ("Aborting!!!\n"); | |
1473 | hang (); | |
1474 | } else | |
1475 | tmp_dunit_control_low = 0x1A1107d2; | |
4fcfbec0 | 1476 | debug |
3a473b2a | 1477 | ("Max. CL is 1.5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n", |
4fcfbec0 | 1478 | tmp_sdram_mode, tmp_dunit_control_low); |
3a473b2a WD |
1479 | } |
1480 | break; | |
1481 | ||
1482 | default: | |
1483 | printf ("Max. CL is out of range %d\n", | |
1484 | info->maxClSupported_DDR); | |
1485 | hang (); | |
1486 | break; | |
1487 | } /* end DDR switch */ | |
1488 | break; | |
1489 | } /* end CL switch */ | |
1490 | ||
1491 | /* Write results of CL detection procedure */ | |
1492 | /* set SDRAM mode reg. 0x141c */ | |
1493 | GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode); | |
1494 | ||
1495 | /* set SDRAM mode SetCommand 0x1418 */ | |
1496 | GT_REG_WRITE (SDRAM_OPERATION, 0x3); | |
1497 | while (GTREGREAD (SDRAM_OPERATION) != 0) { | |
4fcfbec0 WD |
1498 | debug |
1499 | ("\n*** SDRAM_OPERATION 0x1418 after SDRAM_MODE: Module still busy ... please wait... ***\n"); | |
3a473b2a WD |
1500 | } |
1501 | ||
1502 | /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */ | |
1503 | GT_REG_WRITE (D_UNIT_CONTROL_LOW, tmp_dunit_control_low); | |
1504 | ||
1505 | /* set SDRAM mode SetCommand 0x1418 */ | |
1506 | GT_REG_WRITE (SDRAM_OPERATION, 0x3); | |
1507 | while (GTREGREAD (SDRAM_OPERATION) != 0) { | |
4fcfbec0 WD |
1508 | debug |
1509 | ("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n"); | |
3a473b2a WD |
1510 | } |
1511 | ||
1512 | /*------------------------------------------------------------------------------ */ | |
1513 | ||
1514 | /* bank parameters */ | |
1515 | /* SDRAM address decode register 0x1410 */ | |
1516 | /* program this with the default value */ | |
1517 | tmp = 0x02; /* power-up default address select decoding value */ | |
1518 | ||
4fcfbec0 | 1519 | debug("drb_size (n*64Mbit): %d\n", info->drb_size); |
3a473b2a WD |
1520 | /* figure out the DRAM chip size */ |
1521 | sdram_chip_size = | |
1522 | (1 << (info->numOfRowAddresses + info->numOfColAddresses)); | |
1523 | sdram_chip_size *= info->sdramWidth; | |
1524 | sdram_chip_size *= 4; | |
4fcfbec0 | 1525 | debug("computed sdram chip size is %#lx\n", sdram_chip_size); |
3a473b2a WD |
1526 | /* divide sdram chip size by 64 Mbits */ |
1527 | sdram_chip_size = sdram_chip_size / 0x4000000; | |
1528 | switch (sdram_chip_size) { | |
1529 | case 1: /* 64 Mbit */ | |
1530 | case 2: /* 128 Mbit */ | |
4fcfbec0 | 1531 | debug("RAM-Device_size 64Mbit or 128Mbit)\n"); |
3a473b2a WD |
1532 | tmp |= (0x00 << 4); |
1533 | break; | |
1534 | case 4: /* 256 Mbit */ | |
1535 | case 8: /* 512 Mbit */ | |
4fcfbec0 | 1536 | debug("RAM-Device_size 256Mbit or 512Mbit)\n"); |
3a473b2a WD |
1537 | tmp |= (0x01 << 4); |
1538 | break; | |
1539 | case 16: /* 1 Gbit */ | |
1540 | case 32: /* 2 Gbit */ | |
4fcfbec0 | 1541 | debug("RAM-Device_size 1Gbit or 2Gbit)\n"); |
3a473b2a WD |
1542 | tmp |= (0x02 << 4); |
1543 | break; | |
1544 | default: | |
1545 | printf ("Error in dram size calculation\n"); | |
1546 | printf ("RAM-Device_size is unsupported\n"); | |
1547 | hang (); | |
1548 | } | |
1549 | ||
1550 | /* SDRAM address control */ | |
1551 | GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp); | |
4fcfbec0 | 1552 | debug |
3a473b2a | 1553 | ("setting up sdram address control (0x1410) with: %08lx \n", |
4fcfbec0 | 1554 | tmp); |
3a473b2a WD |
1555 | |
1556 | /* ------------------------------------------------------------------------------ */ | |
1557 | /* same settings for registerd & non-registerd DDR SDRAM */ | |
4fcfbec0 | 1558 | debug |
3a473b2a | 1559 | ("setting up sdram_timing_control_low (0x1408) with: %08x \n", |
4fcfbec0 | 1560 | 0x11511220); |
3a473b2a WD |
1561 | GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220); |
1562 | ||
1563 | ||
1564 | /* ------------------------------------------------------------------------------ */ | |
1565 | ||
1566 | /* SDRAM configuration */ | |
1567 | tmp = GTREGREAD (SDRAM_CONFIG); | |
1568 | ||
1569 | if (info->registeredAddrAndControlInputs | |
1570 | || info->registeredDQMBinputs) { | |
1571 | tmp |= (1 << 17); | |
4fcfbec0 | 1572 | debug |
3a473b2a WD |
1573 | ("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n", |
1574 | info->registeredAddrAndControlInputs, | |
4fcfbec0 | 1575 | info->registeredDQMBinputs); |
3a473b2a WD |
1576 | } |
1577 | ||
1578 | /* Use buffer 1 to return read data to the CPU | |
1579 | * Page 426 MV64360 */ | |
1580 | tmp |= (1 << 26); | |
4fcfbec0 | 1581 | debug |
3a473b2a | 1582 | ("Before Buffer assignment - sdram_conf (0x1400): %08x\n", |
4fcfbec0 WD |
1583 | GTREGREAD (SDRAM_CONFIG)); |
1584 | debug | |
3a473b2a | 1585 | ("After Buffer assignment - sdram_conf (0x1400): %08x\n", |
4fcfbec0 | 1586 | GTREGREAD (SDRAM_CONFIG)); |
3a473b2a WD |
1587 | |
1588 | /* SDRAM timing To_do: */ | |
1589 | /* ------------------------------------------------------------------------------ */ | |
1590 | ||
4fcfbec0 | 1591 | debug |
3a473b2a | 1592 | ("setting up sdram_timing_control_high (0x140c) with: %08x \n", |
4fcfbec0 | 1593 | 0x9); |
3a473b2a WD |
1594 | GT_REG_WRITE (SDRAM_TIMING_CONTROL_HIGH, 0x9); |
1595 | ||
4fcfbec0 | 1596 | debug |
3a473b2a | 1597 | ("setting up sdram address pads control (0x14c0) with: %08x \n", |
4fcfbec0 | 1598 | 0x7d5014a); |
3a473b2a WD |
1599 | GT_REG_WRITE (SDRAM_ADDR_CTRL_PADS_CALIBRATION, 0x7d5014a); |
1600 | ||
4fcfbec0 | 1601 | debug |
3a473b2a | 1602 | ("setting up sdram data pads control (0x14c4) with: %08x \n", |
4fcfbec0 | 1603 | 0x7d5014a); |
3a473b2a WD |
1604 | GT_REG_WRITE (SDRAM_DATA_PADS_CALIBRATION, 0x7d5014a); |
1605 | ||
1606 | /* ------------------------------------------------------------------------------ */ | |
1607 | ||
1608 | /* set the SDRAM configuration for each bank */ | |
1609 | ||
1610 | /* for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */ | |
1611 | { | |
1612 | i = info->slot; | |
4fcfbec0 WD |
1613 | debug |
1614 | ("\n*** Running a MRS cycle for bank %d ***\n", i); | |
3a473b2a WD |
1615 | |
1616 | /* map the bank */ | |
1617 | memory_map_bank (i, 0, GB / 4); | |
1618 | ||
1619 | /* set SDRAM mode */ /* To_do check it */ | |
1620 | GT_REG_WRITE (SDRAM_OPERATION, 0x3); | |
1621 | check = GTREGREAD (SDRAM_OPERATION); | |
4fcfbec0 | 1622 | debug |
3a473b2a | 1623 | ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", |
4fcfbec0 | 1624 | check); |
3a473b2a WD |
1625 | |
1626 | ||
1627 | /* switch back to normal operation mode */ | |
1628 | GT_REG_WRITE (SDRAM_OPERATION, 0); | |
1629 | check = GTREGREAD (SDRAM_OPERATION); | |
4fcfbec0 | 1630 | debug |
3a473b2a | 1631 | ("\n*** SDRAM_OPERATION 1418 (0 = Normal Operation) = %08lx ***\n", |
4fcfbec0 | 1632 | check); |
3a473b2a WD |
1633 | |
1634 | /* unmap the bank */ | |
1635 | memory_map_bank (i, 0, 0); | |
1636 | } | |
1637 | ||
1638 | return 0; | |
1639 | ||
1640 | } | |
1641 | ||
1642 | /* | |
1643 | * Check memory range for valid RAM. A simple memory test determines | |
1644 | * the actually available RAM size between addresses `base' and | |
1645 | * `base + maxsize'. Some (not all) hardware errors are detected: | |
1646 | * - short between address lines | |
1647 | * - short between data lines | |
1648 | */ | |
1649 | long int dram_size (long int *base, long int maxsize) | |
1650 | { | |
1651 | volatile long int *addr, *b = base; | |
1652 | long int cnt, val, save1, save2; | |
1653 | ||
1654 | #define STARTVAL (1<<20) /* start test at 1M */ | |
1655 | for (cnt = STARTVAL / sizeof (long); cnt < maxsize / sizeof (long); | |
1656 | cnt <<= 1) { | |
1657 | addr = base + cnt; /* pointer arith! */ | |
1658 | ||
1659 | save1 = *addr; /* save contents of addr */ | |
1660 | save2 = *b; /* save contents of base */ | |
1661 | ||
1662 | *addr = cnt; /* write cnt to addr */ | |
1663 | *b = 0; /* put null at base */ | |
1664 | ||
1665 | /* check at base address */ | |
1666 | if ((*b) != 0) { | |
1667 | *addr = save1; /* restore *addr */ | |
1668 | *b = save2; /* restore *b */ | |
1669 | return (0); | |
1670 | } | |
1671 | val = *addr; /* read *addr */ | |
1672 | val = *addr; /* read *addr */ | |
1673 | ||
1674 | *addr = save1; | |
1675 | *b = save2; | |
1676 | ||
1677 | if (val != cnt) { | |
4fcfbec0 | 1678 | debug |
3a473b2a | 1679 | ("Found %08x at Address %08x (failure)\n", |
4fcfbec0 | 1680 | (unsigned int) val, (unsigned int) addr); |
3a473b2a WD |
1681 | /* fix boundary condition.. STARTVAL means zero */ |
1682 | if (cnt == STARTVAL / sizeof (long)) | |
1683 | cnt = 0; | |
1684 | return (cnt * sizeof (long)); | |
1685 | } | |
1686 | } | |
1687 | return maxsize; | |
1688 | } | |
1689 | ||
1690 | /* ------------------------------------------------------------------------- */ | |
1691 | ||
1692 | /* ppcboot interface function to SDRAM init - this is where all the | |
1693 | * controlling logic happens */ | |
9973e3c6 | 1694 | phys_size_t initdram (int board_type) |
3a473b2a | 1695 | { |
3a473b2a | 1696 | int checkbank[4] = {[0 ... 3] = 0 }; |
4fcfbec0 | 1697 | ulong realsize, total; |
3a473b2a WD |
1698 | AUX_MEM_DIMM_INFO dimmInfo1; |
1699 | AUX_MEM_DIMM_INFO dimmInfo2; | |
1700 | int nhr, bank_no; | |
1701 | ulong dest, memSpaceAttr; | |
1702 | ||
1703 | /* first, use the SPD to get info about the SDRAM/ DDRRAM */ | |
1704 | ||
1705 | /* check the NHR bit and skip mem init if it's already done */ | |
1706 | nhr = get_hid0 () & (1 << 16); | |
1707 | ||
1708 | if (nhr) { | |
1709 | printf ("Skipping SD- DDRRAM setup due to NHR bit being set\n"); | |
1710 | } else { | |
1711 | /* DIMM0 */ | |
4fcfbec0 | 1712 | check_dimm (0, &dimmInfo1); |
3a473b2a WD |
1713 | |
1714 | /* DIMM1 */ | |
4fcfbec0 | 1715 | check_dimm (1, &dimmInfo2); |
3a473b2a WD |
1716 | |
1717 | memory_map_bank (0, 0, 0); | |
1718 | memory_map_bank (1, 0, 0); | |
1719 | memory_map_bank (2, 0, 0); | |
1720 | memory_map_bank (3, 0, 0); | |
1721 | ||
1722 | /* ronen check correct set of DIMMS */ | |
1723 | if (dimmInfo1.numOfModuleBanks && dimmInfo2.numOfModuleBanks) { | |
1724 | if (dimmInfo1.errorCheckType != | |
1725 | dimmInfo2.errorCheckType) | |
1726 | printf ("***WARNNING***!!!! different ECC support of the DIMMS\n"); | |
1727 | if (dimmInfo1.maxClSupported_DDR != | |
1728 | dimmInfo2.maxClSupported_DDR) | |
1729 | printf ("***WARNNING***!!!! different CAL setting of the DIMMS\n"); | |
1730 | if (dimmInfo1.registeredAddrAndControlInputs != | |
1731 | dimmInfo2.registeredAddrAndControlInputs) | |
1732 | printf ("***WARNNING***!!!! different Registration setting of the DIMMS\n"); | |
1733 | } | |
1734 | ||
1735 | if (dimmInfo1.numOfModuleBanks && setup_sdram (&dimmInfo1)) { | |
1736 | printf ("Setup for DIMM1 failed.\n"); | |
1737 | } | |
1738 | ||
1739 | if (dimmInfo2.numOfModuleBanks && setup_sdram (&dimmInfo2)) { | |
1740 | printf ("Setup for DIMM2 failed.\n"); | |
1741 | } | |
1742 | ||
1743 | /* set the NHR bit */ | |
1744 | set_hid0 (get_hid0 () | (1 << 16)); | |
1745 | } | |
1746 | /* next, size the SDRAM banks */ | |
1747 | ||
1748 | realsize = total = 0; | |
3a473b2a WD |
1749 | if (dimmInfo1.numOfModuleBanks > 0) { |
1750 | checkbank[0] = 1; | |
1751 | } | |
1752 | if (dimmInfo1.numOfModuleBanks > 1) { | |
1753 | checkbank[1] = 1; | |
1754 | } | |
1755 | if (dimmInfo1.numOfModuleBanks > 2) | |
1756 | printf ("Error, SPD claims DIMM1 has >2 banks\n"); | |
1757 | ||
1758 | printf ("-- DIMM1 has %d banks\n", dimmInfo1.numOfModuleBanks); | |
1759 | ||
1760 | if (dimmInfo2.numOfModuleBanks > 0) { | |
1761 | checkbank[2] = 1; | |
1762 | } | |
1763 | if (dimmInfo2.numOfModuleBanks > 1) { | |
1764 | checkbank[3] = 1; | |
1765 | } | |
1766 | if (dimmInfo2.numOfModuleBanks > 2) | |
1767 | printf ("Error, SPD claims DIMM2 has >2 banks\n"); | |
1768 | ||
1769 | printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks); | |
1770 | ||
6d0f6bcf | 1771 | for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) { |
3a473b2a WD |
1772 | /* skip over banks that are not populated */ |
1773 | if (!checkbank[bank_no]) | |
1774 | continue; | |
1775 | ||
1776 | /* ronen - realsize = dram_size((long int *)total, check); */ | |
1777 | if (bank_no == 0 || bank_no == 1) { | |
1778 | if (checkbank[1] == 1) | |
1779 | realsize = dimmInfo1.size / 2; | |
1780 | else | |
1781 | realsize = dimmInfo1.size; | |
1782 | } | |
1783 | if (bank_no == 2 || bank_no == 3) { | |
1784 | if (checkbank[3] == 1) | |
1785 | realsize = dimmInfo2.size / 2; | |
1786 | else | |
1787 | realsize = dimmInfo2.size; | |
1788 | } | |
1789 | memory_map_bank (bank_no, total, realsize); | |
1790 | ||
1791 | /* ronen - initialize the DRAM for ECC */ | |
1792 | #ifdef CONFIG_MV64360_ECC | |
1793 | if ((dimmInfo1.errorCheckType != 0) && | |
1794 | ((dimmInfo2.errorCheckType != 0) | |
1795 | || (dimmInfo2.numOfModuleBanks == 0))) { | |
1796 | printf ("ECC Initialization of Bank %d:", bank_no); | |
1797 | memSpaceAttr = ((~(BIT0 << bank_no)) & 0xf) << 8; | |
1798 | mvDmaSetMemorySpace (0, 0, memSpaceAttr, total, | |
1799 | realsize); | |
1800 | for (dest = total; dest < total + realsize; | |
1801 | dest += _8M) { | |
1802 | mvDmaTransfer (0, total, dest, _8M, | |
1803 | BIT8 /*DMA_DTL_128BYTES */ | | |
1804 | BIT3 /*DMA_HOLD_SOURCE_ADDR */ | |
1805 | | | |
1806 | BIT11 | |
1807 | /*DMA_BLOCK_TRANSFER_MODE */ ); | |
1808 | while (mvDmaIsChannelActive (0)); | |
1809 | } | |
1810 | printf (" PASS\n"); | |
1811 | } | |
1812 | #endif | |
1813 | ||
1814 | total += realsize; | |
1815 | } | |
1816 | ||
1817 | /* ronen- add DRAM conf prints */ | |
1818 | switch ((GTREGREAD (0x141c) >> 4) & 0x7) { | |
1819 | case 0x2: | |
1820 | printf ("CAS Latency = 2"); | |
1821 | break; | |
1822 | case 0x3: | |
1823 | printf ("CAS Latency = 3"); | |
1824 | break; | |
1825 | case 0x5: | |
1826 | printf ("CAS Latency = 1.5"); | |
1827 | break; | |
1828 | case 0x6: | |
1829 | printf ("CAS Latency = 2.5"); | |
1830 | break; | |
1831 | } | |
1832 | printf (" tRP = %d tRAS = %d tRCD=%d\n", | |
1833 | ((GTREGREAD (0x1408) >> 8) & 0xf) + 1, | |
1834 | ((GTREGREAD (0x1408) >> 20) & 0xf) + 1, | |
1835 | ((GTREGREAD (0x1408) >> 4) & 0xf) + 1); | |
1836 | ||
1837 | /* Setup Ethernet DMA Adress window to DRAM Area */ | |
1838 | if (total > _256M) | |
1839 | printf ("*** ONLY the first 256MB DRAM memory are used out of the "); | |
1840 | else | |
1841 | printf ("Total SDRAM memory is "); | |
1842 | /* (cause all the 4 BATS are taken) */ | |
1843 | return (total); | |
1844 | } | |
1845 | ||
1846 | ||
1847 | /* ronen- add Idma functions for usage of the ecc dram init. */ | |
1848 | /******************************************************************************* | |
1849 | * mvDmaIsChannelActive - Checks if a engine is busy. | |
1850 | ********************************************************************************/ | |
1851 | int mvDmaIsChannelActive (int engine) | |
1852 | { | |
1853 | ulong data; | |
1854 | ||
1855 | data = GTREGREAD (MV64360_DMA_CHANNEL0_CONTROL + 4 * engine); | |
1856 | if (data & BIT14 /*activity status */ ) { | |
1857 | return 1; | |
1858 | } | |
1859 | return 0; | |
1860 | } | |
1861 | ||
1862 | /******************************************************************************* | |
1863 | * mvDmaSetMemorySpace - Set a DMA memory window for the DMA's address decoding | |
1864 | * map. | |
1865 | *******************************************************************************/ | |
1866 | int mvDmaSetMemorySpace (ulong memSpace, | |
1867 | ulong memSpaceTarget, | |
1868 | ulong memSpaceAttr, ulong baseAddress, ulong size) | |
1869 | { | |
1870 | ulong temp; | |
1871 | ||
1872 | /* The base address must be aligned to the size. */ | |
1873 | if (baseAddress % size != 0) { | |
1874 | return 0; | |
1875 | } | |
1876 | if (size >= 0x10000 /*64K */ ) { | |
1877 | size &= 0xffff0000; | |
1878 | baseAddress = (baseAddress & 0xffff0000); | |
1879 | /* Set the new attributes */ | |
1880 | GT_REG_WRITE (MV64360_DMA_BASE_ADDR_REG0 + memSpace * 8, | |
1881 | (baseAddress | memSpaceTarget | memSpaceAttr)); | |
1882 | GT_REG_WRITE ((MV64360_DMA_SIZE_REG0 + memSpace * 8), | |
1883 | (size - 1) & 0xffff0000); | |
1884 | temp = GTREGREAD (MV64360_DMA_BASE_ADDR_ENABLE_REG); | |
1885 | GT_REG_WRITE (DMA_BASE_ADDR_ENABLE_REG, | |
1886 | (temp & ~(BIT0 << memSpace))); | |
1887 | return 1; | |
1888 | } | |
1889 | return 0; | |
1890 | } | |
1891 | ||
1892 | ||
1893 | /******************************************************************************* | |
1894 | * mvDmaTransfer - Transfer data from sourceAddr to destAddr on one of the 4 | |
1895 | * DMA channels. | |
1896 | ********************************************************************************/ | |
1897 | int mvDmaTransfer (int engine, ulong sourceAddr, | |
1898 | ulong destAddr, ulong numOfBytes, ulong command) | |
1899 | { | |
1900 | ulong engOffReg = 0; /* Engine Offset Register */ | |
1901 | ||
1902 | if (numOfBytes > 0xffff) { | |
1903 | command = command | BIT31 /*DMA_16M_DESCRIPTOR_MODE */ ; | |
1904 | } | |
1905 | command = command | ((command >> 6) & 0x7); | |
1906 | engOffReg = engine * 4; | |
1907 | GT_REG_WRITE (MV64360_DMA_CHANNEL0_BYTE_COUNT + engOffReg, | |
1908 | numOfBytes); | |
1909 | GT_REG_WRITE (MV64360_DMA_CHANNEL0_SOURCE_ADDR + engOffReg, | |
1910 | sourceAddr); | |
1911 | GT_REG_WRITE (MV64360_DMA_CHANNEL0_DESTINATION_ADDR + engOffReg, | |
1912 | destAddr); | |
1913 | command = | |
1914 | command | BIT12 /*DMA_CHANNEL_ENABLE */ | BIT9 | |
1915 | /*DMA_NON_CHAIN_MODE */ ; | |
1916 | /* Activate DMA engine By writting to mvDmaControlRegister */ | |
1917 | GT_REG_WRITE (MV64360_DMA_CHANNEL0_CONTROL + engOffReg, command); | |
1918 | return 1; | |
1919 | } | |
1920 | ||
1921 | /**************************************************************************************** | |
1922 | * SDRAM INIT * | |
1923 | * This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb * | |
1924 | * This procedure fits only the Atlantis * | |
1925 | * * | |
1926 | ***************************************************************************************/ | |
1927 | ||
1928 | ||
1929 | /**************************************************************************************** | |
1930 | * DFCDL initialize MV643xx Design Considerations * | |
1931 | * * | |
1932 | ***************************************************************************************/ | |
1933 | int set_dfcdlInit (void) | |
1934 | { | |
1935 | int i; | |
1936 | unsigned int dfcdl_word = 0x391; /* 0x14f; ronen new dfcdl */ | |
1937 | ||
1938 | for (i = 0; i < 64; i++) { | |
1939 | GT_REG_WRITE (SRAM_DATA0, dfcdl_word); | |
1940 | /* dfcdl_word += 0x41; - ronen new dfcdl */ | |
1941 | } | |
1942 | GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000); /* enable dynamic delay line updating */ | |
1943 | ||
1944 | return (0); | |
1945 | } |