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3a473b2a
WD		 1/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24/* PCI.c - PCI functions */
25
26
27#include <common.h>
28#include <pci.h>
29
30#include "../include/pci.h"
31
32#undef DEBUG
33#undef IDE_SET_NATIVE_MODE
34static unsigned int local_buses[] = { 0, 0 };
35
36static const unsigned char pci_irq_swizzle[2][PCI_MAX_DEVICES] = {
37 {0, 0, 0, 0, 0, 0, 0, 27, 27, [9 ... PCI_MAX_DEVICES - 1] = 0 },
38 {0, 0, 0, 0, 0, 0, 0, 29, 29, [9 ... PCI_MAX_DEVICES - 1] = 0 },
39};
40
41
42#ifdef DEBUG
43static const unsigned int pci_bus_list[] = { PCI_0_MODE, PCI_1_MODE };
44static void gt_pci_bus_mode_display (PCI_HOST host)
45{
46 unsigned int mode;
47
48
49 mode = (GTREGREAD (pci_bus_list[host]) & (BIT4 | BIT5)) >> 4;
50 switch (mode) {
51 case 0:
52 printf ("PCI %d bus mode: Conventional PCI\n", host);
53 break;
54 case 1:
55 printf ("PCI %d bus mode: 66 Mhz PCIX\n", host);
56 break;
57 case 2:
58 printf ("PCI %d bus mode: 100 Mhz PCIX\n", host);
59 break;
60 case 3:
61 printf ("PCI %d bus mode: 133 Mhz PCIX\n", host);
62 break;
63 default:
64 printf ("Unknown BUS %d\n", mode);
65 }
66}
67#endif
68
69static const unsigned int pci_p2p_configuration_reg[] = {
70 PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
71};
72
73static const unsigned int pci_configuration_address[] = {
74 PCI_0CONFIGURATION_ADDRESS, PCI_1CONFIGURATION_ADDRESS
75};
76
77static const unsigned int pci_configuration_data[] = {
78 PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER,
79 PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER
80};
81
82static const unsigned int pci_error_cause_reg[] = {
83 PCI_0ERROR_CAUSE, PCI_1ERROR_CAUSE
84};
85
86static const unsigned int pci_arbiter_control[] = {
87 PCI_0ARBITER_CONTROL, PCI_1ARBITER_CONTROL
88};
89
90static const unsigned int pci_address_space_en[] = {
91 PCI_0_BASE_ADDR_REG_ENABLE, PCI_1_BASE_ADDR_REG_ENABLE
92};
93
94static const unsigned int pci_snoop_control_base_0_low[] = {
95 PCI_0SNOOP_CONTROL_BASE_0_LOW, PCI_1SNOOP_CONTROL_BASE_0_LOW
96};
97static const unsigned int pci_snoop_control_top_0[] = {
98 PCI_0SNOOP_CONTROL_TOP_0, PCI_1SNOOP_CONTROL_TOP_0
99};
100
101static const unsigned int pci_access_control_base_0_low[] = {
102 PCI_0ACCESS_CONTROL_BASE_0_LOW, PCI_1ACCESS_CONTROL_BASE_0_LOW
103};
104static const unsigned int pci_access_control_top_0[] = {
105 PCI_0ACCESS_CONTROL_TOP_0, PCI_1ACCESS_CONTROL_TOP_0
106};
107
108static const unsigned int pci_scs_bank_size[2][4] = {
109 {PCI_0SCS_0_BANK_SIZE, PCI_0SCS_1_BANK_SIZE,
110 PCI_0SCS_2_BANK_SIZE, PCI_0SCS_3_BANK_SIZE},
111 {PCI_1SCS_0_BANK_SIZE, PCI_1SCS_1_BANK_SIZE,
112 PCI_1SCS_2_BANK_SIZE, PCI_1SCS_3_BANK_SIZE}
113};
114
115static const unsigned int pci_p2p_configuration[] = {
116 PCI_0P2P_CONFIGURATION, PCI_1P2P_CONFIGURATION
117};
118
119
120/********************************************************************
121* pciWriteConfigReg - Write to a PCI configuration register
122* - Make sure the GT is configured as a master before writing
123* to another device on the PCI.
124* - The function takes care of Big/Little endian conversion.
125*
126*
127* Inputs: unsigned int regOffset: The register offset as it apears in the GT spec
128* (or any other PCI device spec)
129* pciDevNum: The device number needs to be addressed.
130*
131* Configuration Address 0xCF8:
132*
133* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
134* |congif|Reserved| Bus |Device|Function|Register|00|
135* |Enable| |Number|Number| Number | Number | | <=field Name
136*
137*********************************************************************/
138void pciWriteConfigReg (PCI_HOST host, unsigned int regOffset,
139 unsigned int pciDevNum, unsigned int data)
140{
141 volatile unsigned int DataForAddrReg;
142 unsigned int functionNum;
143 unsigned int busNum = 0;
144 unsigned int addr;
145
146 if (pciDevNum > 32) /* illegal device Number */
147 return;
148 if (pciDevNum == SELF) { /* configure our configuration space. */
149 pciDevNum =
150 (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
151 0x1f;
152 busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
153 0xff0000;
154 }
155 functionNum = regOffset & 0x00000700;
156 pciDevNum = pciDevNum << 11;
157 regOffset = regOffset & 0xfc;
158 DataForAddrReg =
159 (regOffset | pciDevNum | functionNum | busNum) | BIT31;
160 GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
161 GT_REG_READ (pci_configuration_address[host], &addr);
162 if (addr != DataForAddrReg)
163 return;
164 GT_REG_WRITE (pci_configuration_data[host], data);
165}
166
167/********************************************************************
168* pciReadConfigReg - Read from a PCI0 configuration register
169* - Make sure the GT is configured as a master before reading
170* from another device on the PCI.
171* - The function takes care of Big/Little endian conversion.
172* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
173* spec)
174* pciDevNum: The device number needs to be addressed.
175* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
176* cause register to make sure the data is valid
177*
178* Configuration Address 0xCF8:
179*
180* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
181* |congif|Reserved| Bus |Device|Function|Register|00|
182* |Enable| |Number|Number| Number | Number | | <=field Name
183*
184*********************************************************************/
185unsigned int pciReadConfigReg (PCI_HOST host, unsigned int regOffset,
186 unsigned int pciDevNum)
187{
188 volatile unsigned int DataForAddrReg;
189 unsigned int data;
190 unsigned int functionNum;
191 unsigned int busNum = 0;
192
193 if (pciDevNum > 32) /* illegal device Number */
194 return 0xffffffff;
195 if (pciDevNum == SELF) { /* configure our configuration space. */
196 pciDevNum =
197 (GTREGREAD (pci_p2p_configuration_reg[host]) >> 24) &
198 0x1f;
199 busNum = GTREGREAD (pci_p2p_configuration_reg[host]) &
200 0xff0000;
201 }
202 functionNum = regOffset & 0x00000700;
203 pciDevNum = pciDevNum << 11;
204 regOffset = regOffset & 0xfc;
205 DataForAddrReg =
206 (regOffset | pciDevNum | functionNum | busNum) | BIT31;
207 GT_REG_WRITE (pci_configuration_address[host], DataForAddrReg);
208 GT_REG_READ (pci_configuration_address[host], &data);
209 if (data != DataForAddrReg)
210 return 0xffffffff;
211 GT_REG_READ (pci_configuration_data[host], &data);
212 return data;
213}
214
215/********************************************************************
216* pciOverBridgeWriteConfigReg - Write to a PCI configuration register where
217* the agent is placed on another Bus. For more
218* information read P2P in the PCI spec.
219*
220* Inputs: unsigned int regOffset - The register offset as it apears in the
221* GT spec (or any other PCI device spec).
222* unsigned int pciDevNum - The device number needs to be addressed.
223* unsigned int busNum - On which bus does the Target agent connect
224* to.
225* unsigned int data - data to be written.
226*
227* Configuration Address 0xCF8:
228*
229* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
230* |congif|Reserved| Bus |Device|Function|Register|01|
231* |Enable| |Number|Number| Number | Number | | <=field Name
232*
233* The configuration Address is configure as type-I (bits[1:0] = '01') due to
234* PCI spec referring to P2P.
235*
236*********************************************************************/
237void pciOverBridgeWriteConfigReg (PCI_HOST host,
238 unsigned int regOffset,
239 unsigned int pciDevNum,
240 unsigned int busNum, unsigned int data)
241{
242 unsigned int DataForReg;
243 unsigned int functionNum;
244
245 functionNum = regOffset & 0x00000700;
246 pciDevNum = pciDevNum << 11;
247 regOffset = regOffset & 0xff;
248 busNum = busNum << 16;
249 if (pciDevNum == SELF) { /* This board */
250 DataForReg = (regOffset | pciDevNum | functionNum) | BIT0;
251 } else {
252 DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
253 BIT31 | BIT0;
254 }
255 GT_REG_WRITE (pci_configuration_address[host], DataForReg);
256 GT_REG_WRITE (pci_configuration_data[host], data);
257}
258
259
260/********************************************************************
261* pciOverBridgeReadConfigReg - Read from a PCIn configuration register where
262* the agent target locate on another PCI bus.
263* - Make sure the GT is configured as a master
264* before reading from another device on the PCI.
265* - The function takes care of Big/Little endian
266* conversion.
267* INPUTS: regOffset: The register offset as it apears in the GT spec (or PCI
268* spec). (configuration register offset.)
269* pciDevNum: The device number needs to be addressed.
270* busNum: the Bus number where the agent is place.
271* RETURNS: data , if the data == 0xffffffff check the master abort bit in the
272* cause register to make sure the data is valid
273*
274* Configuration Address 0xCF8:
275*
276* 31 30 24 23 16 15 11 10 8 7 2 0 <=bit Number
277* |congif|Reserved| Bus |Device|Function|Register|01|
278* |Enable| |Number|Number| Number | Number | | <=field Name
279*
280*********************************************************************/
281unsigned int pciOverBridgeReadConfigReg (PCI_HOST host,
282 unsigned int regOffset,
283 unsigned int pciDevNum,
284 unsigned int busNum)
285{
286 unsigned int DataForReg;
287 unsigned int data;
288 unsigned int functionNum;
289
290 functionNum = regOffset & 0x00000700;
291 pciDevNum = pciDevNum << 11;
292 regOffset = regOffset & 0xff;
293 busNum = busNum << 16;
294 if (pciDevNum == SELF) { /* This board */
295 DataForReg = (regOffset | pciDevNum | functionNum) | BIT31;
296 } else { /* agent on another bus */
297
298 DataForReg = (regOffset | pciDevNum | functionNum | busNum) |
299 BIT0 | BIT31;
300 }
301 GT_REG_WRITE (pci_configuration_address[host], DataForReg);
302 GT_REG_READ (pci_configuration_data[host], &data);
303 return data;
304}
305
306
307/********************************************************************
308* pciGetRegOffset - Gets the register offset for this region config.
309*
310* INPUT: Bus, Region - The bus and region we ask for its base address.
311* OUTPUT: N/A
312* RETURNS: PCI register base address
313*********************************************************************/
314static unsigned int pciGetRegOffset (PCI_HOST host, PCI_REGION region)
315{
316 switch (host) {
317 case PCI_HOST0:
318 switch (region) {
319 case PCI_IO:
320 return PCI_0I_O_LOW_DECODE_ADDRESS;
321 case PCI_REGION0:
322 return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
323 case PCI_REGION1:
324 return PCI_0MEMORY1_LOW_DECODE_ADDRESS;
325 case PCI_REGION2:
326 return PCI_0MEMORY2_LOW_DECODE_ADDRESS;
327 case PCI_REGION3:
328 return PCI_0MEMORY3_LOW_DECODE_ADDRESS;
329 }
330 case PCI_HOST1:
331 switch (region) {
332 case PCI_IO:
333 return PCI_1I_O_LOW_DECODE_ADDRESS;
334 case PCI_REGION0:
335 return PCI_1MEMORY0_LOW_DECODE_ADDRESS;
336 case PCI_REGION1:
337 return PCI_1MEMORY1_LOW_DECODE_ADDRESS;
338 case PCI_REGION2:
339 return PCI_1MEMORY2_LOW_DECODE_ADDRESS;
340 case PCI_REGION3:
341 return PCI_1MEMORY3_LOW_DECODE_ADDRESS;
342 }
343 }
344 return PCI_0MEMORY0_LOW_DECODE_ADDRESS;
345}
346
347static unsigned int pciGetRemapOffset (PCI_HOST host, PCI_REGION region)
348{
349 switch (host) {
350 case PCI_HOST0:
351 switch (region) {
352 case PCI_IO:
353 return PCI_0I_O_ADDRESS_REMAP;
354 case PCI_REGION0:
355 return PCI_0MEMORY0_ADDRESS_REMAP;
356 case PCI_REGION1:
357 return PCI_0MEMORY1_ADDRESS_REMAP;
358 case PCI_REGION2:
359 return PCI_0MEMORY2_ADDRESS_REMAP;
360 case PCI_REGION3:
361 return PCI_0MEMORY3_ADDRESS_REMAP;
362 }
363 case PCI_HOST1:
364 switch (region) {
365 case PCI_IO:
366 return PCI_1I_O_ADDRESS_REMAP;
367 case PCI_REGION0:
368 return PCI_1MEMORY0_ADDRESS_REMAP;
369 case PCI_REGION1:
370 return PCI_1MEMORY1_ADDRESS_REMAP;
371 case PCI_REGION2:
372 return PCI_1MEMORY2_ADDRESS_REMAP;
373 case PCI_REGION3:
374 return PCI_1MEMORY3_ADDRESS_REMAP;
375 }
376 }
377 return PCI_0MEMORY0_ADDRESS_REMAP;
378}
379
380/********************************************************************
381* pciGetBaseAddress - Gets the base address of a PCI.
382* - If the PCI size is 0 then this base address has no meaning!!!
383*
384*
385* INPUT: Bus, Region - The bus and region we ask for its base address.
386* OUTPUT: N/A
387* RETURNS: PCI base address.
388*********************************************************************/
389unsigned int pciGetBaseAddress (PCI_HOST host, PCI_REGION region)
390{
391 unsigned int regBase;
392 unsigned int regEnd;
393 unsigned int regOffset = pciGetRegOffset (host, region);
394
395 GT_REG_READ (regOffset, &regBase);
396 GT_REG_READ (regOffset + 8, &regEnd);
397
398 if (regEnd <= regBase)
399 return 0xffffffff; /* ERROR !!! */
400
401 regBase = regBase << 16;
402 return regBase;
403}
404
405bool pciMapSpace (PCI_HOST host, PCI_REGION region, unsigned int remapBase,
406 unsigned int bankBase, unsigned int bankLength)
407{
408 unsigned int low = 0xfff;
409 unsigned int high = 0x0;
410 unsigned int regOffset = pciGetRegOffset (host, region);
411 unsigned int remapOffset = pciGetRemapOffset (host, region);
412
413 if (bankLength != 0) {
414 low = (bankBase >> 16) & 0xffff;
415 high = ((bankBase + bankLength) >> 16) - 1;
416 }
417
418 GT_REG_WRITE (regOffset, low | (1 << 24)); /* no swapping */
419 GT_REG_WRITE (regOffset + 8, high);
420
421 if (bankLength != 0) { /* must do AFTER writing maps */
422 GT_REG_WRITE (remapOffset, remapBase >> 16); /* sorry, 32 bits only.
423 dont support upper 32
424 in this driver */
425 }
426 return true;
427}
428
429unsigned int pciGetSpaceBase (PCI_HOST host, PCI_REGION region)
430{
431 unsigned int low;
432 unsigned int regOffset = pciGetRegOffset (host, region);
433
434 GT_REG_READ (regOffset, &low);
435 return (low & 0xffff) << 16;
436}
437
438unsigned int pciGetSpaceSize (PCI_HOST host, PCI_REGION region)
439{
440 unsigned int low, high;
441 unsigned int regOffset = pciGetRegOffset (host, region);
442
443 GT_REG_READ (regOffset, &low);
444 GT_REG_READ (regOffset + 8, &high);
445 return ((high & 0xffff) + 1) << 16;
446}
447
448
449/* ronen - 7/Dec/03*/
450/********************************************************************
451* gtPciDisable/EnableInternalBAR - This function enable/disable PCI BARS.
452* Inputs: one of the PCI BAR
453*********************************************************************/
454void gtPciEnableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
455{
456 RESET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
457}
458
459void gtPciDisableInternalBAR (PCI_HOST host, PCI_INTERNAL_BAR pciBAR)
460{
461 SET_REG_BITS (pci_address_space_en[host], BIT0 << pciBAR);
462}
463
464/********************************************************************
465* pciMapMemoryBank - Maps PCI_host memory bank "bank" for the slave.
466*
467* Inputs: base and size of PCI SCS
468*********************************************************************/
469void pciMapMemoryBank (PCI_HOST host, MEMORY_BANK bank,
470 unsigned int pciDramBase, unsigned int pciDramSize)
471{
472 /*ronen different function for 3rd bank. */
473 unsigned int offset = (bank < 2) ? bank * 8 : 0x100 + (bank - 2) * 8;
474
475 pciDramBase = pciDramBase & 0xfffff000;
476 pciDramBase = pciDramBase | (pciReadConfigReg (host,
477 PCI_SCS_0_BASE_ADDRESS
478 + offset,
479 SELF) & 0x00000fff);
480 pciWriteConfigReg (host, PCI_SCS_0_BASE_ADDRESS + offset, SELF,
481 pciDramBase);
482 if (pciDramSize == 0)
483 pciDramSize++;
484 GT_REG_WRITE (pci_scs_bank_size[host][bank], pciDramSize - 1);
485 gtPciEnableInternalBAR (host, bank);
486}
487
488/********************************************************************
489* pciSetRegionFeatures - This function modifys one of the 8 regions with
490* feature bits given as an input.
491* - Be advised to check the spec before modifying them.
492* Inputs: PCI_PROTECT_REGION region - one of the eight regions.
493* unsigned int features - See file: pci.h there are defintion for those
494* region features.
495* unsigned int baseAddress - The region base Address.
496* unsigned int topAddress - The region top Address.
497* Returns: false if one of the parameters is erroneous true otherwise.
498*********************************************************************/
499bool pciSetRegionFeatures (PCI_HOST host, PCI_ACCESS_REGIONS region,
500 unsigned int features, unsigned int baseAddress,
501 unsigned int regionLength)
502{
503 unsigned int accessLow;
504 unsigned int accessHigh;
505 unsigned int accessTop = baseAddress + regionLength;
506
507 if (regionLength == 0) { /* close the region. */
508 pciDisableAccessRegion (host, region);
509 return true;
510 }
511 /* base Address is store is bits [11:0] */
512 accessLow = (baseAddress & 0xfff00000) >> 20;
513 /* All the features are update according to the defines in pci.h (to be on
514 the safe side we disable bits: [11:0] */
515 accessLow = accessLow | (features & 0xfffff000);
516 /* write to the Low Access Region register */
517 GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
518 accessLow);
519
520 accessHigh = (accessTop & 0xfff00000) >> 20;
521
522 /* write to the High Access Region register */
523 GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region,
524 accessHigh - 1);
525 return true;
526}
527
528/********************************************************************
529* pciDisableAccessRegion - Disable The given Region by writing MAX size
530* to its low Address and MIN size to its high Address.
531*
532* Inputs: PCI_ACCESS_REGIONS region - The region we to be Disabled.
533* Returns: N/A.
534*********************************************************************/
535void pciDisableAccessRegion (PCI_HOST host, PCI_ACCESS_REGIONS region)
536{
537 /* writing back the registers default values. */
538 GT_REG_WRITE (pci_access_control_base_0_low[host] + 0x10 * region,
539 0x01001fff);
540 GT_REG_WRITE (pci_access_control_top_0[host] + 0x10 * region, 0);
541}
542
543/********************************************************************
544* pciArbiterEnable - Enables PCI-0`s Arbitration mechanism.
545*
546* Inputs: N/A
547* Returns: true.
548*********************************************************************/
549bool pciArbiterEnable (PCI_HOST host)
550{
551 unsigned int regData;
552
553 GT_REG_READ (pci_arbiter_control[host], &regData);
554 GT_REG_WRITE (pci_arbiter_control[host], regData | BIT31);
555 return true;
556}
557
558/********************************************************************
559* pciArbiterDisable - Disable PCI-0`s Arbitration mechanism.
560*
561* Inputs: N/A
562* Returns: true
563*********************************************************************/
564bool pciArbiterDisable (PCI_HOST host)
565{
566 unsigned int regData;
567
568 GT_REG_READ (pci_arbiter_control[host], &regData);
569 GT_REG_WRITE (pci_arbiter_control[host], regData & 0x7fffffff);
570 return true;
571}
572
573/********************************************************************
574* pciSetArbiterAgentsPriority - Priority setup for the PCI agents (Hi or Low)
575*
576* Inputs: PCI_AGENT_PRIO internalAgent - priotity for internal agent.
577* PCI_AGENT_PRIO externalAgent0 - priotity for external#0 agent.
578* PCI_AGENT_PRIO externalAgent1 - priotity for external#1 agent.
579* PCI_AGENT_PRIO externalAgent2 - priotity for external#2 agent.
580* PCI_AGENT_PRIO externalAgent3 - priotity for external#3 agent.
581* PCI_AGENT_PRIO externalAgent4 - priotity for external#4 agent.
582* PCI_AGENT_PRIO externalAgent5 - priotity for external#5 agent.
583* Returns: true
584*********************************************************************/
585bool pciSetArbiterAgentsPriority (PCI_HOST host, PCI_AGENT_PRIO internalAgent,
586 PCI_AGENT_PRIO externalAgent0,
587 PCI_AGENT_PRIO externalAgent1,
588 PCI_AGENT_PRIO externalAgent2,
589 PCI_AGENT_PRIO externalAgent3,
590 PCI_AGENT_PRIO externalAgent4,
591 PCI_AGENT_PRIO externalAgent5)
592{
593 unsigned int regData;
594 unsigned int writeData;
595
596 GT_REG_READ (pci_arbiter_control[host], &regData);
597 writeData = (internalAgent << 7) + (externalAgent0 << 8) +
598 (externalAgent1 << 9) + (externalAgent2 << 10) +
599 (externalAgent3 << 11) + (externalAgent4 << 12) +
600 (externalAgent5 << 13);
601 regData = (regData & 0xffffc07f) | writeData;
602 GT_REG_WRITE (pci_arbiter_control[host], regData & regData);
603 return true;
604}
605
606/********************************************************************
607* pciParkingDisable - Park on last option disable, with this function you can
608* disable the park on last mechanism for each agent.
609* disabling this option for all agents results parking
610* on the internal master.
611*
612* Inputs: PCI_AGENT_PARK internalAgent - parking Disable for internal agent.
613* PCI_AGENT_PARK externalAgent0 - parking Disable for external#0 agent.
614* PCI_AGENT_PARK externalAgent1 - parking Disable for external#1 agent.
615* PCI_AGENT_PARK externalAgent2 - parking Disable for external#2 agent.
616* PCI_AGENT_PARK externalAgent3 - parking Disable for external#3 agent.
617* PCI_AGENT_PARK externalAgent4 - parking Disable for external#4 agent.
618* PCI_AGENT_PARK externalAgent5 - parking Disable for external#5 agent.
619* Returns: true
620*********************************************************************/
621bool pciParkingDisable (PCI_HOST host, PCI_AGENT_PARK internalAgent,
622 PCI_AGENT_PARK externalAgent0,
623 PCI_AGENT_PARK externalAgent1,
624 PCI_AGENT_PARK externalAgent2,
625 PCI_AGENT_PARK externalAgent3,
626 PCI_AGENT_PARK externalAgent4,
627 PCI_AGENT_PARK externalAgent5)
628{
629 unsigned int regData;
630 unsigned int writeData;
631
632 GT_REG_READ (pci_arbiter_control[host], &regData);
633 writeData = (internalAgent << 14) + (externalAgent0 << 15) +
634 (externalAgent1 << 16) + (externalAgent2 << 17) +
635 (externalAgent3 << 18) + (externalAgent4 << 19) +
636 (externalAgent5 << 20);
637 regData = (regData & ~(0x7f << 14)) | writeData;
638 GT_REG_WRITE (pci_arbiter_control[host], regData);
639 return true;
640}
641
642/********************************************************************
643* pciEnableBrokenAgentDetection - A master is said to be broken if it fails to
644* respond to grant assertion within a window specified in
645* the input value: 'brokenValue'.
646*
647* Inputs: unsigned char brokenValue - A value which limits the Master to hold the
648* grant without asserting frame.
649* Returns: Error for illegal broken value otherwise true.
650*********************************************************************/
651bool pciEnableBrokenAgentDetection (PCI_HOST host, unsigned char brokenValue)
652{
653 unsigned int data;
654 unsigned int regData;
655
656 if (brokenValue > 0xf)
657 return false; /* brokenValue must be 4 bit */
658 data = brokenValue << 3;
659 GT_REG_READ (pci_arbiter_control[host], &regData);
660 regData = (regData & 0xffffff87) | data;
661 GT_REG_WRITE (pci_arbiter_control[host], regData | BIT1);
662 return true;
663}
664
665/********************************************************************
666* pciDisableBrokenAgentDetection - This function disable the Broken agent
667* Detection mechanism.
668* NOTE: This operation may cause a dead lock on the
669* pci0 arbitration.
670*
671* Inputs: N/A
672* Returns: true.
673*********************************************************************/
674bool pciDisableBrokenAgentDetection (PCI_HOST host)
675{
676 unsigned int regData;
677
678 GT_REG_READ (pci_arbiter_control[host], &regData);
679 regData = regData & 0xfffffffd;
680 GT_REG_WRITE (pci_arbiter_control[host], regData);
681 return true;
682}
683
684/********************************************************************
685* pciP2PConfig - This function set the PCI_n P2P configurate.
686* For more information on the P2P read PCI spec.
687*
688* Inputs: unsigned int SecondBusLow - Secondery PCI interface Bus Range Lower
689* Boundry.
690* unsigned int SecondBusHigh - Secondry PCI interface Bus Range upper
691* Boundry.
692* unsigned int busNum - The CPI bus number to which the PCI interface
693* is connected.
694* unsigned int devNum - The PCI interface's device number.
695*
696* Returns: true.
697*********************************************************************/
698bool pciP2PConfig (PCI_HOST host, unsigned int SecondBusLow,
699 unsigned int SecondBusHigh,
700 unsigned int busNum, unsigned int devNum)
701{
702 unsigned int regData;
703
704 regData = (SecondBusLow & 0xff) | ((SecondBusHigh & 0xff) << 8) |
705 ((busNum & 0xff) << 16) | ((devNum & 0x1f) << 24);
706 GT_REG_WRITE (pci_p2p_configuration[host], regData);
707 return true;
708}
709
710/********************************************************************
711* pciSetRegionSnoopMode - This function modifys one of the 4 regions which
712* supports Cache Coherency in the PCI_n interface.
713* Inputs: region - One of the four regions.
714* snoopType - There is four optional Types:
715* 1. No Snoop.
716* 2. Snoop to WT region.
717* 3. Snoop to WB region.
718* 4. Snoop & Invalidate to WB region.
719* baseAddress - Base Address of this region.
720* regionLength - Region length.
721* Returns: false if one of the parameters is wrong otherwise return true.
722*********************************************************************/
723bool pciSetRegionSnoopMode (PCI_HOST host, PCI_SNOOP_REGION region,
724 PCI_SNOOP_TYPE snoopType,
725 unsigned int baseAddress,
726 unsigned int regionLength)
727{
728 unsigned int snoopXbaseAddress;
729 unsigned int snoopXtopAddress;
730 unsigned int data;
731 unsigned int snoopHigh = baseAddress + regionLength;
732
733 if ((region > PCI_SNOOP_REGION3) || (snoopType > PCI_SNOOP_WB))
734 return false;
735 snoopXbaseAddress =
736 pci_snoop_control_base_0_low[host] + 0x10 * region;
737 snoopXtopAddress = pci_snoop_control_top_0[host] + 0x10 * region;
738 if (regionLength == 0) { /* closing the region */
739 GT_REG_WRITE (snoopXbaseAddress, 0x0000ffff);
740 GT_REG_WRITE (snoopXtopAddress, 0);
741 return true;
742 }
743 baseAddress = baseAddress & 0xfff00000; /* Granularity of 1MByte */
744 data = (baseAddress >> 20) | snoopType << 12;
745 GT_REG_WRITE (snoopXbaseAddress, data);
746 snoopHigh = (snoopHigh & 0xfff00000) >> 20;
747 GT_REG_WRITE (snoopXtopAddress, snoopHigh - 1);
748 return true;
749}
750
751static int gt_read_config_dword (struct pci_controller *hose,
752 pci_dev_t dev, int offset, u32 * value)
753{
754 int bus = PCI_BUS (dev);
755
756 if ((bus == local_buses[0]) || (bus == local_buses[1])) {
757 *value = pciReadConfigReg ((PCI_HOST) hose->cfg_addr, offset,
758 PCI_DEV (dev));
759 } else {
760 *value = pciOverBridgeReadConfigReg ((PCI_HOST) hose->
761 cfg_addr, offset,
762 PCI_DEV (dev), bus);
763 }
764
765 return 0;
766}
767
768static int gt_write_config_dword (struct pci_controller *hose,
769 pci_dev_t dev, int offset, u32 value)
770{
771 int bus = PCI_BUS (dev);
772
773 if ((bus == local_buses[0]) || (bus == local_buses[1])) {
774 pciWriteConfigReg ((PCI_HOST) hose->cfg_addr, offset,
775 PCI_DEV (dev), value);
776 } else {
777 pciOverBridgeWriteConfigReg ((PCI_HOST) hose->cfg_addr,
778 offset, PCI_DEV (dev), bus,
779 value);
780 }
781 return 0;
782}
783
784
785static void gt_setup_ide (struct pci_controller *hose,
786 pci_dev_t dev, struct pci_config_table *entry)
787{
788 static const int ide_bar[] = { 8, 4, 8, 4, 0, 0 };
789 u32 bar_response, bar_value;
790 int bar;
791
792 for (bar = 0; bar < 6; bar++) {
793 /*ronen different function for 3rd bank. */
794 unsigned int offset =
795 (bar < 2) ? bar * 8 : 0x100 + (bar - 2) * 8;
796
797 pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
798 0x0);
799 pci_read_config_dword (dev, PCI_BASE_ADDRESS_0 + offset,
800 &bar_response);
801
802 pciauto_region_allocate (bar_response &
803 PCI_BASE_ADDRESS_SPACE_IO ? hose->
804 pci_io : hose->pci_mem, ide_bar[bar],
805 &bar_value);
806
807 pci_write_config_dword (dev, PCI_BASE_ADDRESS_0 + bar * 4,
808 bar_value);
809 }
810}
811
812
813/* TODO BJW: Change this for DB64360. This was pulled from the EV64260 */
814/* and is curently not called *. */
815#if 0
816static void gt_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
817{
818 unsigned char pin, irq;
819
820 pci_read_config_byte (dev, PCI_INTERRUPT_PIN, &pin);
821
822 if (pin == 1) { /* only allow INT A */
823 irq = pci_irq_swizzle[(PCI_HOST) hose->
824 cfg_addr][PCI_DEV (dev)];
825 if (irq)
826 pci_write_config_byte (dev, PCI_INTERRUPT_LINE, irq);
827 }
828}
829#endif
830
831struct pci_config_table gt_config_table[] = {
832 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE,
833 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, gt_setup_ide},
834
835 {}
836};
837
838struct pci_controller pci0_hose = {
839/* fixup_irq: gt_fixup_irq, */
840 config_table:gt_config_table,
841};
842
843struct pci_controller pci1_hose = {
844/* fixup_irq: gt_fixup_irq, */
845 config_table:gt_config_table,
846};
847
848void pci_init_board (void)
849{
850 unsigned int command;
851
852#ifdef DEBUG
853 gt_pci_bus_mode_display (PCI_HOST0);
854#endif
855
856 pci0_hose.first_busno = 0;
857 pci0_hose.last_busno = 0xff;
858 local_buses[0] = pci0_hose.first_busno;
859
860 /* PCI memory space */
861 pci_set_region (pci0_hose.regions + 0,
6d0f6bcf
JCPV		 862 CONFIG_SYS_PCI0_0_MEM_SPACE,
863 CONFIG_SYS_PCI0_0_MEM_SPACE,
864 CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
3a473b2a
WD		 865
866 /* PCI I/O space */
867 pci_set_region (pci0_hose.regions + 1,
6d0f6bcf
JCPV		 868 CONFIG_SYS_PCI0_IO_SPACE_PCI,
869 CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
3a473b2a
WD		 870
871 pci_set_ops (&pci0_hose,
872 pci_hose_read_config_byte_via_dword,
873 pci_hose_read_config_word_via_dword,
874 gt_read_config_dword,
875 pci_hose_write_config_byte_via_dword,
876 pci_hose_write_config_word_via_dword,
877 gt_write_config_dword);
878 pci0_hose.region_count = 2;
879
880 pci0_hose.cfg_addr = (unsigned int *) PCI_HOST0;
881
882 pci_register_hose (&pci0_hose);
883 pciArbiterEnable (PCI_HOST0);
884 pciParkingDisable (PCI_HOST0, 1, 1, 1, 1, 1, 1, 1);
885 command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
886 command |= PCI_COMMAND_MASTER;
887 pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
888 command = pciReadConfigReg (PCI_HOST0, PCI_COMMAND, SELF);
889 command |= PCI_COMMAND_MEMORY;
890 pciWriteConfigReg (PCI_HOST0, PCI_COMMAND, SELF, command);
891
892 pci0_hose.last_busno = pci_hose_scan (&pci0_hose);
893
894#ifdef DEBUG
895 gt_pci_bus_mode_display (PCI_HOST1);
896#endif
897 pci1_hose.first_busno = pci0_hose.last_busno + 1;
898 pci1_hose.last_busno = 0xff;
899 pci1_hose.current_busno = pci1_hose.first_busno;
900 local_buses[1] = pci1_hose.first_busno;
901
902 /* PCI memory space */
903 pci_set_region (pci1_hose.regions + 0,
6d0f6bcf
JCPV		 904 CONFIG_SYS_PCI1_0_MEM_SPACE,
905 CONFIG_SYS_PCI1_0_MEM_SPACE,
906 CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
3a473b2a
WD		 907
908 /* PCI I/O space */
909 pci_set_region (pci1_hose.regions + 1,
6d0f6bcf
JCPV		 910 CONFIG_SYS_PCI1_IO_SPACE_PCI,
911 CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
3a473b2a
WD		 912
913 pci_set_ops (&pci1_hose,
914 pci_hose_read_config_byte_via_dword,
915 pci_hose_read_config_word_via_dword,
916 gt_read_config_dword,
917 pci_hose_write_config_byte_via_dword,
918 pci_hose_write_config_word_via_dword,
919 gt_write_config_dword);
920
921 pci1_hose.region_count = 2;
922
923 pci1_hose.cfg_addr = (unsigned int *) PCI_HOST1;
924
925 pci_register_hose (&pci1_hose);
926
927 pciArbiterEnable (PCI_HOST1);
928 pciParkingDisable (PCI_HOST1, 1, 1, 1, 1, 1, 1, 1);
929
930 command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
931 command |= PCI_COMMAND_MASTER;
932 pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
933
934 pci1_hose.last_busno = pci_hose_scan (&pci1_hose);
935
936 command = pciReadConfigReg (PCI_HOST1, PCI_COMMAND, SELF);
937 command |= PCI_COMMAND_MEMORY;
938 pciWriteConfigReg (PCI_HOST1, PCI_COMMAND, SELF, command);
939
940}
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