| c2042f59 |
1 | /* |
| 2 | * Copyright (C) 2007 |
| 3 | * Nobuhiro Iwamatsu <iwamatsu@nigauri.org> |
| 4 | * |
| 5 | * Copyright (C) 2007 |
| 6 | * Kenati Technologies, Inc. |
| 7 | * |
| 8 | * board/MigoR/lowlevel_init.S |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or |
| 11 | * modify it under the terms of the GNU General Public License as |
| 12 | * published by the Free Software Foundation; either version 2 of |
| 13 | * the License, or (at your option) any later version. |
| 14 | * |
| 15 | * This program is distributed in the hope that it will be useful, |
| 16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 18 | * GNU General Public License for more details. |
| 19 | * |
| 20 | * You should have received a copy of the GNU General Public License |
| 21 | * along with this program; if not, write to the Free Software |
| 22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 23 | * MA 02111-1307 USA |
| 24 | */ |
| 25 | |
| 26 | #include <config.h> |
| 27 | #include <version.h> |
| 28 | |
| 29 | #include <asm/processor.h> |
| 30 | |
| 31 | /* |
| 32 | * Board specific low level init code, called _very_ early in the |
| 33 | * startup sequence. Relocation to SDRAM has not happened yet, no |
| 34 | * stack is available, bss section has not been initialised, etc. |
| 35 | * |
| 36 | * (Note: As no stack is available, no subroutines can be called...). |
| 37 | */ |
| 38 | |
| 39 | .global lowlevel_init |
| 40 | |
| 41 | .text |
| 42 | .align 2 |
| 43 | |
| 44 | lowlevel_init: |
| c2042f59 |
45 | mov.l CCR_A, r1 ! Address of Cache Control Register |
| 46 | mov.l CCR_D, r0 ! Instruction Cache Invalidate |
| 47 | mov.l r0, @r1 |
| 48 | |
| 49 | mov.l MMUCR_A, r1 ! Address of MMU Control Register |
| 50 | mov.l MMUCR_D, r0 ! TI == TLB Invalidate bit |
| 51 | mov.l r0, @r1 |
| 52 | |
| 53 | mov.l MSTPCR0_A, r1 ! Address of Power Control Register 0 |
| 54 | mov.l MSTPCR0_D, r0 ! |
| 55 | mov.l r0, @r1 |
| 56 | |
| 57 | mov.l MSTPCR2_A, r1 ! Address of Power Control Register 2 |
| 58 | mov.l MSTPCR2_D, r0 ! |
| 59 | mov.l r0, @r1 |
| 60 | |
| 61 | mov.l PFC_PULCR_A, r1 |
| 62 | mov.w PFC_PULCR_D, r0 |
| 63 | mov.w r0,@r1 |
| 64 | |
| 65 | mov.l PFC_DRVCR_A, r1 |
| 66 | mov.w PFC_DRVCR_D, r0 |
| 67 | mov.w r0, @r1 |
| 68 | |
| 69 | mov.l SBSCR_A, r1 ! |
| 70 | mov.w SBSCR_D, r0 ! |
| 71 | mov.w r0, @r1 |
| 72 | |
| 73 | mov.l PSCR_A, r1 ! |
| 74 | mov.w PSCR_D, r0 ! |
| 75 | mov.w r0, @r1 |
| 76 | |
| 77 | mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) |
| 78 | mov.w RWTCSR_D_1, r0 ! 0xA507 -> timer_STOP/WDT_CLK=max |
| 79 | mov.w r0, @r1 |
| 80 | |
| 81 | mov.l RWTCNT_A, r1 ! 0xA4520000 (Watchdog Count Register) |
| 82 | mov.w RWTCNT_D, r0 ! 0x5A00 -> Clear |
| 83 | mov.w r0, @r1 |
| 84 | |
| 85 | mov.l RWTCSR_A, r1 ! 0xA4520004 (Watchdog Control / Status Register) |
| 86 | mov.w RWTCSR_D_2, r0 ! 0xA504 -> timer_STOP/CLK=500ms |
| 87 | mov.w r0, @r1 |
| 88 | |
| 89 | mov.l DLLFRQ_A, r1 ! 20080115 |
| 90 | mov.l DLLFRQ_D, r0 ! 20080115 |
| 91 | mov.l r0, @r1 |
| 92 | |
| 93 | mov.l FRQCR_A, r1 ! 0xA4150000 Frequency control register |
| 94 | mov.l FRQCR_D, r0 ! 20080115 |
| 95 | mov.l r0, @r1 |
| 96 | |
| 97 | mov.l CCR_A, r1 ! Address of Cache Control Register |
| 98 | mov.l CCR_D_2, r0 ! ?? |
| 99 | mov.l r0, @r1 |
| 100 | |
| 101 | bsc_init: |
| c2042f59 |
102 | mov.l CMNCR_A, r1 ! CMNCR address -> R1 |
| 103 | mov.l CMNCR_D, r0 ! CMNCR data -> R0 |
| 104 | mov.l r0, @r1 ! CMNCR set |
| 105 | |
| 106 | mov.l CS0BCR_A, r1 ! CS0BCR address -> R1 |
| 107 | mov.l CS0BCR_D, r0 ! CS0BCR data -> R0 |
| 108 | mov.l r0, @r1 ! CS0BCR set |
| 109 | |
| 110 | mov.l CS4BCR_A, r1 ! CS4BCR address -> R1 |
| 111 | mov.l CS4BCR_D, r0 ! CS4BCR data -> R0 |
| 112 | mov.l r0, @r1 ! CS4BCR set |
| 113 | |
| 114 | mov.l CS5ABCR_A, r1 ! CS5ABCR address -> R1 |
| 115 | mov.l CS5ABCR_D, r0 ! CS5ABCR data -> R0 |
| 116 | mov.l r0, @r1 ! CS5ABCR set |
| 117 | |
| 118 | mov.l CS5BBCR_A, r1 ! CS5BBCR address -> R1 |
| 119 | mov.l CS5BBCR_D, r0 ! CS5BBCR data -> R0 |
| 120 | mov.l r0, @r1 ! CS5BBCR set |
| 121 | |
| 122 | mov.l CS6ABCR_A, r1 ! CS6ABCR address -> R1 |
| 123 | mov.l CS6ABCR_D, r0 ! CS6ABCR data -> R0 |
| 124 | mov.l r0, @r1 ! CS6ABCR set |
| 125 | |
| 126 | mov.l CS0WCR_A, r1 ! CS0WCR address -> R1 |
| 127 | mov.l CS0WCR_D, r0 ! CS0WCR data -> R0 |
| 128 | mov.l r0, @r1 ! CS0WCR set |
| 129 | |
| 130 | mov.l CS4WCR_A, r1 ! CS4WCR address -> R1 |
| 131 | mov.l CS4WCR_D, r0 ! CS4WCR data -> R0 |
| 132 | mov.l r0, @r1 ! CS4WCR set |
| 133 | |
| 134 | mov.l CS5AWCR_A, r1 ! CS5AWCR address -> R1 |
| 135 | mov.l CS5AWCR_D, r0 ! CS5AWCR data -> R0 |
| 136 | mov.l r0, @r1 ! CS5AWCR set |
| 137 | |
| 138 | mov.l CS5BWCR_A, r1 ! CS5BWCR address -> R1 |
| 139 | mov.l CS5BWCR_D, r0 ! CS5BWCR data -> R0 |
| 140 | mov.l r0, @r1 ! CS5BWCR set |
| 141 | |
| 142 | mov.l CS6AWCR_A, r1 ! CS6AWCR address -> R1 |
| 143 | mov.l CS6AWCR_D, r0 ! CS6AWCR data -> R0 |
| 144 | mov.l r0, @r1 ! CS6AWCR set |
| 145 | |
| 146 | ! SDRAM initialization |
| 147 | mov.l SDCR_A, r1 ! SB_SDCR address -> R1 |
| 148 | mov.l SDCR_D, r0 ! SB_SDCR data -> R0 |
| 149 | mov.l r0, @r1 ! SB_SDCR set |
| 150 | |
| 151 | mov.l SDWCR_A, r1 ! SB_SDWCR address -> R1 |
| 152 | mov.l SDWCR_D, r0 ! SB_SDWCR data -> R0 |
| 153 | mov.l r0, @r1 ! SB_SDWCR set |
| 154 | |
| 155 | mov.l SDPCR_A, r1 ! SB_SDPCR address -> R1 |
| 156 | mov.l SDPCR_D, r0 ! SB_SDPCR data -> R0 |
| 157 | mov.l r0, @r1 ! SB_SDPCR set |
| 158 | |
| 159 | mov.l RTCOR_A, r1 ! SB_RTCOR address -> R1 |
| 160 | mov.l RTCOR_D, r0 ! SB_RTCOR data -> R0 |
| 161 | mov.l r0, @r1 ! SB_RTCOR set |
| 162 | |
| 163 | mov.l RTCNT_A, r1 ! SB_RTCNT address -> R1 |
| 164 | mov.l RTCNT_D, r0 ! SB_RTCNT data -> R0 |
| 165 | mov.l r0, @r1 |
| 166 | |
| 167 | mov.l RTCSR_A, r1 ! SB_RTCSR address -> R1 |
| 168 | mov.l RTCSR_D, r0 ! SB_RTCSR data -> R0 |
| 169 | mov.l r0, @r1 ! SB_RTCSR set |
| 170 | |
| 171 | mov.l RFCR_A, r1 ! SB_RFCR address -> R1 |
| 172 | mov.l RFCR_D, r0 ! SB_RFCR data -> R0 |
| 173 | mov.l r0, @r1 |
| 174 | |
| 175 | mov.l SDMR3_A, r1 ! SDMR3 address -> R1 |
| 176 | mov #0x00, r0 ! SDMR3 data -> R0 |
| 177 | mov.b r0, @r1 ! SDMR3 set |
| 178 | |
| 179 | ! BL bit off (init = ON) (?!?) |
| 180 | |
| 181 | stc sr, r0 ! BL bit off(init=ON) |
| 182 | mov.l SR_MASK_D, r1 |
| 183 | and r1, r0 |
| 184 | ldc r0, sr |
| 185 | |
| 186 | rts |
| 187 | mov #0, r0 |
| 188 | |
| c2042f59 |
189 | .align 4 |
| 190 | |
| 191 | CCR_A: .long CCR |
| 192 | MMUCR_A: .long MMUCR |
| 193 | MSTPCR0_A: .long MSTPCR0 |
| 194 | MSTPCR2_A: .long MSTPCR2 |
| 195 | PFC_PULCR_A: .long PULCR |
| 196 | PFC_DRVCR_A: .long DRVCR |
| 197 | SBSCR_A: .long SBSCR |
| 198 | PSCR_A: .long PSCR |
| 199 | RWTCSR_A: .long RWTCSR |
| 200 | RWTCNT_A: .long RWTCNT |
| 201 | FRQCR_A: .long FRQCR |
| 202 | PLLCR_A: .long PLLCR |
| 203 | DLLFRQ_A: .long DLLFRQ |
| 204 | |
| 205 | CCR_D: .long 0x00000800 |
| 206 | CCR_D_2: .long 0x00000103 |
| 207 | MMUCR_D: .long 0x00000004 |
| 208 | MSTPCR0_D: .long 0x00001001 |
| 209 | MSTPCR2_D: .long 0xffffffff |
| 210 | PFC_PULCR_D: .long 0x6000 |
| 211 | PFC_DRVCR_D: .long 0x0464 |
| 212 | FRQCR_D: .long 0x07033639 |
| 213 | PLLCR_D: .long 0x00005000 |
| 214 | DLLFRQ_D: .long 0x000004F6 ! 20080115 |
| 215 | |
| 216 | CMNCR_A: .long CMNCR |
| 217 | CMNCR_D: .long 0x0000001B ! 20080115 |
| 218 | CS0BCR_A: .long CS0BCR ! Flash bank 1 |
| 219 | CS0BCR_D: .long 0x24920400 |
| 220 | CS4BCR_A: .long CS4BCR ! |
| 221 | CS4BCR_D: .long 0x10003400 ! 20080115 |
| 222 | CS5ABCR_A: .long CS5ABCR ! |
| 223 | CS5ABCR_D: .long 0x24920400 |
| 224 | CS5BBCR_A: .long CS5BBCR ! |
| 225 | CS5BBCR_D: .long 0x24920400 |
| 226 | CS6ABCR_A: .long CS6ABCR ! |
| 227 | CS6ABCR_D: .long 0x24920400 |
| 228 | |
| 229 | CS0WCR_A: .long CS0WCR |
| 230 | CS0WCR_D: .long 0x00000380 |
| 231 | CS4WCR_A: .long CS4WCR |
| 232 | CS4WCR_D: .long 0x00100A81 ! 20080115 |
| 233 | CS5AWCR_A: .long CS5AWCR |
| 234 | CS5AWCR_D: .long 0x00000300 |
| 235 | CS5BWCR_A: .long CS5BWCR |
| 236 | CS5BWCR_D: .long 0x00000300 |
| 237 | CS6AWCR_A: .long CS6AWCR |
| 238 | CS6AWCR_D: .long 0x00000300 |
| 239 | |
| 240 | SDCR_A: .long SBSC_SDCR |
| 241 | SDCR_D: .long 0x80160809 ! 20080115 |
| 242 | SDWCR_A: .long SBSC_SDWCR |
| 243 | SDWCR_D: .long 0x0014450C ! 20080115 |
| 244 | SDPCR_A: .long SBSC_SDPCR |
| 245 | SDPCR_D: .long 0x00000087 |
| 246 | RTCOR_A: .long SBSC_RTCOR |
| 247 | RTCNT_A: .long SBSC_RTCNT |
| 248 | RTCNT_D: .long 0xA55A0012 |
| 249 | RTCOR_D: .long 0xA55A001C ! 20080115 |
| 250 | RTCSR_A: .long SBSC_RTCSR |
| 251 | RFCR_A: .long SBSC_RFCR |
| 252 | RFCR_D: .long 0xA55A0221 |
| 253 | RTCSR_D: .long 0xA55A009a ! 20080115 |
| 254 | SDMR3_A: .long 0xFE581180 ! 20080115 |
| 255 | |
| 256 | SR_MASK_D: .long 0xEFFFFF0F |
| 257 | |
| 258 | .align 2 |
| 259 | |
| 260 | SBSCR_D: .word 0x0044 |
| 261 | PSCR_D: .word 0x0000 |
| 262 | RWTCSR_D_1: .word 0xA507 |
| 263 | RWTCSR_D_2: .word 0xA504 ! 20080115 |
| 264 | RWTCNT_D: .word 0x5A00 |
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