[thirdparty/u-boot.git] / board / RPXClassic / eccx.c

/*
 * (C) Copyright 2002
 * Stäubli Faverges - <www.staubli.com>
 * Pierre AUBERT  p.aubert@staubli.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
/* Video support for the ECCX daughter board                                 */


#include <common.h>
#include <config.h>

#ifdef CONFIG_VIDEO_SED13806
#include <sed13806.h>


/* Screen configurations: the initialization of the SD13806 depends on
   screen and on display mode. We handle only 8bpp and 16 bpp modes          */

/* ECCX board is supplied with a NEC NL6448BC20 screen                       */
#ifdef CONFIG_NEC_NL6448BC20
#define DISPLAY_WIDTH   640
#define DISPLAY_HEIGHT  480

#ifdef CONFIG_VIDEO_SED13806_8BPP
static const S1D_REGS init_regs [] =
{
    {0x0001,0x00},   /* Miscellaneous Register */
    {0x01FC,0x00},   /* Display Mode Register */
    {0x0004,0x1b},   /* General IO Pins Configuration Register 0 */
    {0x0005,0x00},   /* General IO Pins Configuration Register 1 */
    {0x0008,0xe5},   /* General IO Pins Control Register 0 */
    {0x0009,0x1f},   /* General IO Pins Control Register 1 */
    {0x0010,0x02},   /* Memory Clock Configuration Register */
    {0x0014,0x10},   /* LCD Pixel Clock Configuration Register */
    {0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
    {0x001C,0x02},   /* MediaPlug Clock Configuration Register */
    {0x001E,0x01},   /* CPU To Memory Wait State Select Register */
    {0x0021,0x04},   /* DRAM Refresh Rate Register */
    {0x002A,0x00},   /* DRAM Timings Control Register 0 */
    {0x002B,0x01},   /* DRAM Timings Control Register 1 */
    {0x0020,0x80},   /* Memory Configuration Register */
    {0x0030,0x25},   /* Panel Type Register */
    {0x0031,0x00},   /* MOD Rate Register */
    {0x0032,0x4F},   /* LCD Horizontal Display Width Register */
    {0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
    {0x0035,0x01},   /* TFT FPLINE Start Position Register */
    {0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
    {0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
    {0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
    {0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
    {0x003B,0x00},   /* TFT FPFRAME Start Position Register */
    {0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
    {0x0040,0x03},   /* LCD Display Mode Register */
    {0x0041,0x02},   /* LCD Miscellaneous Register */
    {0x0042,0x00},   /* LCD Display Start Address Register 0 */
    {0x0043,0x00},   /* LCD Display Start Address Register 1 */
    {0x0044,0x00},   /* LCD Display Start Address Register 2 */
    {0x0046,0x40},   /* LCD Memory Address Offset Register 0 */
    {0x0047,0x01},   /* LCD Memory Address Offset Register 1 */
    {0x0048,0x00},   /* LCD Pixel Panning Register */
    {0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
    {0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
    {0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
    {0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
    {0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
    {0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
    {0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
    {0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
    {0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
    {0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
    {0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
    {0x005B,0x00},   /* TV Output Control Register */
    {0x0060,0x03},   /* CRT/TV Display Mode Register */
    {0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
    {0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
    {0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
    {0x0066,0x40},   /* CRT/TV Memory Address Offset Register 0 */
    {0x0067,0x01},   /* CRT/TV Memory Address Offset Register 1 */
    {0x0068,0x00},   /* CRT/TV Pixel Panning Register */
    {0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
    {0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
    {0x0070,0x00},   /* LCD Ink/Cursor Control Register */
    {0x0071,0x00},   /* LCD Ink/Cursor Start Address Register */
    {0x0072,0x00},   /* LCD Cursor X Position Register 0 */
    {0x0073,0x00},   /* LCD Cursor X Position Register 1 */
    {0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
    {0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
    {0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
    {0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
    {0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
    {0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
    {0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
    {0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
    {0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
    {0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
    {0x0081,0x00},   /* CRT/TV Ink/Cursor Start Address Register */
    {0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
    {0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
    {0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
    {0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
    {0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
    {0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
    {0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
    {0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
    {0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
    {0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
    {0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
    {0x0100,0x00},   /* BitBlt Control Register 0 */
    {0x0101,0x00},   /* BitBlt Control Register 1 */
    {0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
    {0x0103,0x00},   /* BitBlt Operation Register */
    {0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
    {0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
    {0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
    {0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
    {0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
    {0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
    {0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
    {0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
    {0x0110,0x00},   /* BitBlt Width Register 0 */
    {0x0111,0x00},   /* BitBlt Width Register 1 */
    {0x0112,0x00},   /* BitBlt Height Register 0 */
    {0x0113,0x00},   /* BitBlt Height Register 1 */
    {0x0114,0x00},   /* BitBlt Background Color Register 0 */
    {0x0115,0x00},   /* BitBlt Background Color Register 1 */
    {0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
    {0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
    {0x01E0,0x00},   /* Look-Up Table Mode Register */
    {0x01E2,0x00},   /* Look-Up Table Address Register */
    {0x01E4,0x00},   /* Look-Up Table Data Register */
    {0x01F0,0x10},   /* Power Save Configuration Register */
    {0x01F1,0x00},   /* Power Save Status Register */
    {0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
    {0x01FC,0x01},   /* Display Mode Register */
    {0, 0}
};
#endif /* CONFIG_VIDEO_SED13806_8BPP */

#ifdef CONFIG_VIDEO_SED13806_16BPP

static const S1D_REGS init_regs [] =
{
    {0x0001,0x00},   /* Miscellaneous Register */
    {0x01FC,0x00},   /* Display Mode Register */
    {0x0004,0x1b},   /* General IO Pins Configuration Register 0 */
    {0x0005,0x00},   /* General IO Pins Configuration Register 1 */
    {0x0008,0xe5},   /* General IO Pins Control Register 0 */
    {0x0009,0x1f},   /* General IO Pins Control Register 1 */
    {0x0010,0x02},   /* Memory Clock Configuration Register */
    {0x0014,0x10},   /* LCD Pixel Clock Configuration Register */
    {0x0018,0x02},   /* CRT/TV Pixel Clock Configuration Register */
    {0x001C,0x02},   /* MediaPlug Clock Configuration Register */
    {0x001E,0x01},   /* CPU To Memory Wait State Select Register */
    {0x0021,0x04},   /* DRAM Refresh Rate Register */
    {0x002A,0x00},   /* DRAM Timings Control Register 0 */
    {0x002B,0x01},   /* DRAM Timings Control Register 1 */
    {0x0020,0x80},   /* Memory Configuration Register */
    {0x0030,0x25},   /* Panel Type Register */
    {0x0031,0x00},   /* MOD Rate Register */
    {0x0032,0x4F},   /* LCD Horizontal Display Width Register */
    {0x0034,0x13},   /* LCD Horizontal Non-Display Period Register */
    {0x0035,0x01},   /* TFT FPLINE Start Position Register */
    {0x0036,0x0B},   /* TFT FPLINE Pulse Width Register */
    {0x0038,0xDF},   /* LCD Vertical Display Height Register 0 */
    {0x0039,0x01},   /* LCD Vertical Display Height Register 1 */
    {0x003A,0x2C},   /* LCD Vertical Non-Display Period Register */
    {0x003B,0x00},   /* TFT FPFRAME Start Position Register */
    {0x003C,0x01},   /* TFT FPFRAME Pulse Width Register */
    {0x0040,0x05},   /* LCD Display Mode Register */
    {0x0041,0x02},   /* LCD Miscellaneous Register */
    {0x0042,0x00},   /* LCD Display Start Address Register 0 */
    {0x0043,0x00},   /* LCD Display Start Address Register 1 */
    {0x0044,0x00},   /* LCD Display Start Address Register 2 */
    {0x0046,0x80},   /* LCD Memory Address Offset Register 0 */
    {0x0047,0x02},   /* LCD Memory Address Offset Register 1 */
    {0x0048,0x00},   /* LCD Pixel Panning Register */
    {0x004A,0x00},   /* LCD Display FIFO High Threshold Control Register */
    {0x004B,0x00},   /* LCD Display FIFO Low Threshold Control Register */
    {0x0050,0x4F},   /* CRT/TV Horizontal Display Width Register */
    {0x0052,0x13},   /* CRT/TV Horizontal Non-Display Period Register */
    {0x0053,0x01},   /* CRT/TV HRTC Start Position Register */
    {0x0054,0x0B},   /* CRT/TV HRTC Pulse Width Register */
    {0x0056,0xDF},   /* CRT/TV Vertical Display Height Register 0 */
    {0x0057,0x01},   /* CRT/TV Vertical Display Height Register 1 */
    {0x0058,0x2B},   /* CRT/TV Vertical Non-Display Period Register */
    {0x0059,0x09},   /* CRT/TV VRTC Start Position Register */
    {0x005A,0x01},   /* CRT/TV VRTC Pulse Width Register */
    {0x005B,0x00},   /* TV Output Control Register */
    {0x0060,0x05},   /* CRT/TV Display Mode Register */
    {0x0062,0x00},   /* CRT/TV Display Start Address Register 0 */
    {0x0063,0x00},   /* CRT/TV Display Start Address Register 1 */
    {0x0064,0x00},   /* CRT/TV Display Start Address Register 2 */
    {0x0066,0x80},   /* CRT/TV Memory Address Offset Register 0 */
    {0x0067,0x02},   /* CRT/TV Memory Address Offset Register 1 */
    {0x0068,0x00},   /* CRT/TV Pixel Panning Register */
    {0x006A,0x00},   /* CRT/TV Display FIFO High Threshold Control Register */
    {0x006B,0x00},   /* CRT/TV Display FIFO Low Threshold Control Register */
    {0x0070,0x00},   /* LCD Ink/Cursor Control Register */
    {0x0071,0x00},   /* LCD Ink/Cursor Start Address Register */
    {0x0072,0x00},   /* LCD Cursor X Position Register 0 */
    {0x0073,0x00},   /* LCD Cursor X Position Register 1 */
    {0x0074,0x00},   /* LCD Cursor Y Position Register 0 */
    {0x0075,0x00},   /* LCD Cursor Y Position Register 1 */
    {0x0076,0x00},   /* LCD Ink/Cursor Blue Color 0 Register */
    {0x0077,0x00},   /* LCD Ink/Cursor Green Color 0 Register */
    {0x0078,0x00},   /* LCD Ink/Cursor Red Color 0 Register */
    {0x007A,0x1F},   /* LCD Ink/Cursor Blue Color 1 Register */
    {0x007B,0x3F},   /* LCD Ink/Cursor Green Color 1 Register */
    {0x007C,0x1F},   /* LCD Ink/Cursor Red Color 1 Register */
    {0x007E,0x00},   /* LCD Ink/Cursor FIFO Threshold Register */
    {0x0080,0x00},   /* CRT/TV Ink/Cursor Control Register */
    {0x0081,0x00},   /* CRT/TV Ink/Cursor Start Address Register */
    {0x0082,0x00},   /* CRT/TV Cursor X Position Register 0 */
    {0x0083,0x00},   /* CRT/TV Cursor X Position Register 1 */
    {0x0084,0x00},   /* CRT/TV Cursor Y Position Register 0 */
    {0x0085,0x00},   /* CRT/TV Cursor Y Position Register 1 */
    {0x0086,0x00},   /* CRT/TV Ink/Cursor Blue Color 0 Register */
    {0x0087,0x00},   /* CRT/TV Ink/Cursor Green Color 0 Register */
    {0x0088,0x00},   /* CRT/TV Ink/Cursor Red Color 0 Register */
    {0x008A,0x1F},   /* CRT/TV Ink/Cursor Blue Color 1 Register */
    {0x008B,0x3F},   /* CRT/TV Ink/Cursor Green Color 1 Register */
    {0x008C,0x1F},   /* CRT/TV Ink/Cursor Red Color 1 Register */
    {0x008E,0x00},   /* CRT/TV Ink/Cursor FIFO Threshold Register */
    {0x0100,0x00},   /* BitBlt Control Register 0 */
    {0x0101,0x00},   /* BitBlt Control Register 1 */
    {0x0102,0x00},   /* BitBlt ROP Code/Color Expansion Register */
    {0x0103,0x00},   /* BitBlt Operation Register */
    {0x0104,0x00},   /* BitBlt Source Start Address Register 0 */
    {0x0105,0x00},   /* BitBlt Source Start Address Register 1 */
    {0x0106,0x00},   /* BitBlt Source Start Address Register 2 */
    {0x0108,0x00},   /* BitBlt Destination Start Address Register 0 */
    {0x0109,0x00},   /* BitBlt Destination Start Address Register 1 */
    {0x010A,0x00},   /* BitBlt Destination Start Address Register 2 */
    {0x010C,0x00},   /* BitBlt Memory Address Offset Register 0 */
    {0x010D,0x00},   /* BitBlt Memory Address Offset Register 1 */
    {0x0110,0x00},   /* BitBlt Width Register 0 */
    {0x0111,0x00},   /* BitBlt Width Register 1 */
    {0x0112,0x00},   /* BitBlt Height Register 0 */
    {0x0113,0x00},   /* BitBlt Height Register 1 */
    {0x0114,0x00},   /* BitBlt Background Color Register 0 */
    {0x0115,0x00},   /* BitBlt Background Color Register 1 */
    {0x0118,0x00},   /* BitBlt Foreground Color Register 0 */
    {0x0119,0x00},   /* BitBlt Foreground Color Register 1 */
    {0x01E0,0x01},   /* Look-Up Table Mode Register */
    {0x01E2,0x00},   /* Look-Up Table Address Register */
    {0x01E4,0x00},   /* Look-Up Table Data Register */
    {0x01F0,0x10},   /* Power Save Configuration Register */
    {0x01F1,0x00},   /* Power Save Status Register */
    {0x01F4,0x00},   /* CPU-to-Memory Access Watchdog Timer Register */
    {0x01FC,0x01},   /* Display Mode Register */
    {0, 0}
};

#endif /* CONFIG_VIDEO_SED13806_16BPP */
#endif /* CONFIG_NEC_NL6448BC20 */


#ifdef CONFIG_CONSOLE_EXTRA_INFO

/*-----------------------------------------------------------------------------
 * video_get_info_str -- setup a board string: type, speed, etc.
 * line_number= location to place info string beside logo
 * info= buffer for info string
 *-----------------------------------------------------------------------------
 */
void video_get_info_str (int line_number, char *info)
{
    if (line_number == 1) {
	strcpy (info, " RPXClassic board");
    }
    else {
	info [0] = '\0';
    }

}
#endif

/*-----------------------------------------------------------------------------
 * board_video_init -- init de l'EPSON, config du CS
 *-----------------------------------------------------------------------------
 */
unsigned int board_video_init (void)
{
    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
    volatile memctl8xx_t *memctl = &immap->im_memctl;

    /* Program ECCX registers                                                */
    *(ECCX_CSR12) |= ECCX_860;
    *(ECCX_CSR8) |= ECCX_BE | ECCX_CS2;
    *(ECCX_CSR8) |= ECCX_ENEPSON;

    memctl->memc_or2 = SED13806_OR;
    memctl->memc_br2 = SED13806_REG_ADDR | SED13806_ACCES;

    return (SED13806_REG_ADDR);
}

/*-----------------------------------------------------------------------------
 * board_validate_screen --
 *-----------------------------------------------------------------------------
 */
void board_validate_screen (unsigned int base)
{
    /* Activate the panel bias power                                         */
    *(volatile unsigned char *)(base + REG_GPIO_CTRL) = 0x80;
}
/*-----------------------------------------------------------------------------
 * board_get_regs --
 *-----------------------------------------------------------------------------
 */
const S1D_REGS *board_get_regs (void)
{
    return (init_regs);
}
/*-----------------------------------------------------------------------------
 * board_get_width --
 *-----------------------------------------------------------------------------
 */
int board_get_width (void)
{
    return (DISPLAY_WIDTH);
}

/*-----------------------------------------------------------------------------
 * board_get_height --
 *-----------------------------------------------------------------------------
 */
int board_get_height (void)
{
    return (DISPLAY_HEIGHT);
}

#endif /* CONFIG_VIDEO_SED13806 */
Commit	Line	Data
a6c7ad2f WD	1	/*
a6c7ad2f WD	2	* (C) Copyright 2002
fa82f871	3	* Stäubli Faverges - <www.staubli.com>
a6c7ad2f WD	4	* Pierre AUBERT p.aubert@staubli.com
a6c7ad2f WD	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
a6c7ad2f WD	7	*/
	8	/* Video support for the ECCX daughter board */
	9
	10
	11	#include <common.h>
	12	#include <config.h>
	13
	14	#ifdef CONFIG_VIDEO_SED13806
	15	#include <sed13806.h>
	16
	17
a6c7ad2f WD	18	/* Screen configurations: the initialization of the SD13806 depends on
	19	screen and on display mode. We handle only 8bpp and 16 bpp modes */
	20
	21	/* ECCX board is supplied with a NEC NL6448BC20 screen */
	22	#ifdef CONFIG_NEC_NL6448BC20
	23	#define DISPLAY_WIDTH 640
	24	#define DISPLAY_HEIGHT 480
	25
	26	#ifdef CONFIG_VIDEO_SED13806_8BPP
8bde7f77	27	static const S1D_REGS init_regs [] =
a6c7ad2f	28	{
8bde7f77 WD	29	{0x0001,0x00}, /* Miscellaneous Register */
	30	{0x01FC,0x00}, /* Display Mode Register */
	31	{0x0004,0x1b}, /* General IO Pins Configuration Register 0 */
	32	{0x0005,0x00}, /* General IO Pins Configuration Register 1 */
	33	{0x0008,0xe5}, /* General IO Pins Control Register 0 */
	34	{0x0009,0x1f}, /* General IO Pins Control Register 1 */
	35	{0x0010,0x02}, /* Memory Clock Configuration Register */
	36	{0x0014,0x10}, /* LCD Pixel Clock Configuration Register */
	37	{0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
	38	{0x001C,0x02}, /* MediaPlug Clock Configuration Register */
	39	{0x001E,0x01}, /* CPU To Memory Wait State Select Register */
	40	{0x0021,0x04}, /* DRAM Refresh Rate Register */
	41	{0x002A,0x00}, /* DRAM Timings Control Register 0 */
	42	{0x002B,0x01}, /* DRAM Timings Control Register 1 */
	43	{0x0020,0x80}, /* Memory Configuration Register */
	44	{0x0030,0x25}, /* Panel Type Register */
	45	{0x0031,0x00}, /* MOD Rate Register */
	46	{0x0032,0x4F}, /* LCD Horizontal Display Width Register */
	47	{0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
	48	{0x0035,0x01}, /* TFT FPLINE Start Position Register */
	49	{0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
	50	{0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
	51	{0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
	52	{0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
	53	{0x003B,0x00}, /* TFT FPFRAME Start Position Register */
	54	{0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
	55	{0x0040,0x03}, /* LCD Display Mode Register */
	56	{0x0041,0x02}, /* LCD Miscellaneous Register */
	57	{0x0042,0x00}, /* LCD Display Start Address Register 0 */
	58	{0x0043,0x00}, /* LCD Display Start Address Register 1 */
	59	{0x0044,0x00}, /* LCD Display Start Address Register 2 */
	60	{0x0046,0x40}, /* LCD Memory Address Offset Register 0 */
	61	{0x0047,0x01}, /* LCD Memory Address Offset Register 1 */
	62	{0x0048,0x00}, /* LCD Pixel Panning Register */
	63	{0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
	64	{0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
	65	{0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
	66	{0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
	67	{0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
	68	{0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
	69	{0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
	70	{0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
	71	{0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
	72	{0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
	73	{0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
	74	{0x005B,0x00}, /* TV Output Control Register */
	75	{0x0060,0x03}, /* CRT/TV Display Mode Register */
	76	{0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
	77	{0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
	78	{0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
	79	{0x0066,0x40}, /* CRT/TV Memory Address Offset Register 0 */
	80	{0x0067,0x01}, /* CRT/TV Memory Address Offset Register 1 */
	81	{0x0068,0x00}, /* CRT/TV Pixel Panning Register */
	82	{0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
	83	{0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
	84	{0x0070,0x00}, /* LCD Ink/Cursor Control Register */
	85	{0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */
	86	{0x0072,0x00}, /* LCD Cursor X Position Register 0 */
	87	{0x0073,0x00}, /* LCD Cursor X Position Register 1 */
	88	{0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
	89	{0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
	90	{0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
	91	{0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
	92	{0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
93	{0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
94	{0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
95	{0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
96	{0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
97	{0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
98	{0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */
99	{0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
100	{0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
101	{0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
102	{0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
103	{0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
104	{0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
105	{0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
106	{0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
107	{0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
108	{0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
109	{0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
110	{0x0100,0x00}, /* BitBlt Control Register 0 */
111	{0x0101,0x00}, /* BitBlt Control Register 1 */
112	{0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
113	{0x0103,0x00}, /* BitBlt Operation Register */
114	{0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
115	{0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
116	{0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
117	{0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
118	{0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
119	{0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
120	{0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
121	{0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
122	{0x0110,0x00}, /* BitBlt Width Register 0 */
123	{0x0111,0x00}, /* BitBlt Width Register 1 */
124	{0x0112,0x00}, /* BitBlt Height Register 0 */
125	{0x0113,0x00}, /* BitBlt Height Register 1 */
126	{0x0114,0x00}, /* BitBlt Background Color Register 0 */
127	{0x0115,0x00}, /* BitBlt Background Color Register 1 */
128	{0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
129	{0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
130	{0x01E0,0x00}, /* Look-Up Table Mode Register */
131	{0x01E2,0x00}, /* Look-Up Table Address Register */
132	{0x01E4,0x00}, /* Look-Up Table Data Register */
133	{0x01F0,0x10}, /* Power Save Configuration Register */
134	{0x01F1,0x00}, /* Power Save Status Register */
135	{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
136	{0x01FC,0x01}, /* Display Mode Register */
a6c7ad2f WD	137	{0, 0}
	138	};
	139	#endif /* CONFIG_VIDEO_SED13806_8BPP */
	140
	141	#ifdef CONFIG_VIDEO_SED13806_16BPP
	142
8bde7f77	143	static const S1D_REGS init_regs [] =
a6c7ad2f	144	{
8bde7f77 WD	145	{0x0001,0x00}, /* Miscellaneous Register */
	146	{0x01FC,0x00}, /* Display Mode Register */
	147	{0x0004,0x1b}, /* General IO Pins Configuration Register 0 */
	148	{0x0005,0x00}, /* General IO Pins Configuration Register 1 */
	149	{0x0008,0xe5}, /* General IO Pins Control Register 0 */
	150	{0x0009,0x1f}, /* General IO Pins Control Register 1 */
	151	{0x0010,0x02}, /* Memory Clock Configuration Register */
	152	{0x0014,0x10}, /* LCD Pixel Clock Configuration Register */
	153	{0x0018,0x02}, /* CRT/TV Pixel Clock Configuration Register */
	154	{0x001C,0x02}, /* MediaPlug Clock Configuration Register */
	155	{0x001E,0x01}, /* CPU To Memory Wait State Select Register */
	156	{0x0021,0x04}, /* DRAM Refresh Rate Register */
	157	{0x002A,0x00}, /* DRAM Timings Control Register 0 */
	158	{0x002B,0x01}, /* DRAM Timings Control Register 1 */
	159	{0x0020,0x80}, /* Memory Configuration Register */
	160	{0x0030,0x25}, /* Panel Type Register */
	161	{0x0031,0x00}, /* MOD Rate Register */
	162	{0x0032,0x4F}, /* LCD Horizontal Display Width Register */
	163	{0x0034,0x13}, /* LCD Horizontal Non-Display Period Register */
	164	{0x0035,0x01}, /* TFT FPLINE Start Position Register */
	165	{0x0036,0x0B}, /* TFT FPLINE Pulse Width Register */
	166	{0x0038,0xDF}, /* LCD Vertical Display Height Register 0 */
	167	{0x0039,0x01}, /* LCD Vertical Display Height Register 1 */
	168	{0x003A,0x2C}, /* LCD Vertical Non-Display Period Register */
	169	{0x003B,0x00}, /* TFT FPFRAME Start Position Register */
	170	{0x003C,0x01}, /* TFT FPFRAME Pulse Width Register */
	171	{0x0040,0x05}, /* LCD Display Mode Register */
	172	{0x0041,0x02}, /* LCD Miscellaneous Register */
	173	{0x0042,0x00}, /* LCD Display Start Address Register 0 */
	174	{0x0043,0x00}, /* LCD Display Start Address Register 1 */
	175	{0x0044,0x00}, /* LCD Display Start Address Register 2 */
	176	{0x0046,0x80}, /* LCD Memory Address Offset Register 0 */
	177	{0x0047,0x02}, /* LCD Memory Address Offset Register 1 */
	178	{0x0048,0x00}, /* LCD Pixel Panning Register */
	179	{0x004A,0x00}, /* LCD Display FIFO High Threshold Control Register */
	180	{0x004B,0x00}, /* LCD Display FIFO Low Threshold Control Register */
	181	{0x0050,0x4F}, /* CRT/TV Horizontal Display Width Register */
	182	{0x0052,0x13}, /* CRT/TV Horizontal Non-Display Period Register */
	183	{0x0053,0x01}, /* CRT/TV HRTC Start Position Register */
	184	{0x0054,0x0B}, /* CRT/TV HRTC Pulse Width Register */
	185	{0x0056,0xDF}, /* CRT/TV Vertical Display Height Register 0 */
	186	{0x0057,0x01}, /* CRT/TV Vertical Display Height Register 1 */
	187	{0x0058,0x2B}, /* CRT/TV Vertical Non-Display Period Register */
	188	{0x0059,0x09}, /* CRT/TV VRTC Start Position Register */
	189	{0x005A,0x01}, /* CRT/TV VRTC Pulse Width Register */
	190	{0x005B,0x00}, /* TV Output Control Register */
	191	{0x0060,0x05}, /* CRT/TV Display Mode Register */
	192	{0x0062,0x00}, /* CRT/TV Display Start Address Register 0 */
	193	{0x0063,0x00}, /* CRT/TV Display Start Address Register 1 */
	194	{0x0064,0x00}, /* CRT/TV Display Start Address Register 2 */
	195	{0x0066,0x80}, /* CRT/TV Memory Address Offset Register 0 */
	196	{0x0067,0x02}, /* CRT/TV Memory Address Offset Register 1 */
	197	{0x0068,0x00}, /* CRT/TV Pixel Panning Register */
	198	{0x006A,0x00}, /* CRT/TV Display FIFO High Threshold Control Register */
	199	{0x006B,0x00}, /* CRT/TV Display FIFO Low Threshold Control Register */
	200	{0x0070,0x00}, /* LCD Ink/Cursor Control Register */
	201	{0x0071,0x00}, /* LCD Ink/Cursor Start Address Register */
	202	{0x0072,0x00}, /* LCD Cursor X Position Register 0 */
	203	{0x0073,0x00}, /* LCD Cursor X Position Register 1 */
	204	{0x0074,0x00}, /* LCD Cursor Y Position Register 0 */
	205	{0x0075,0x00}, /* LCD Cursor Y Position Register 1 */
	206	{0x0076,0x00}, /* LCD Ink/Cursor Blue Color 0 Register */
	207	{0x0077,0x00}, /* LCD Ink/Cursor Green Color 0 Register */
	208	{0x0078,0x00}, /* LCD Ink/Cursor Red Color 0 Register */
209	{0x007A,0x1F}, /* LCD Ink/Cursor Blue Color 1 Register */
210	{0x007B,0x3F}, /* LCD Ink/Cursor Green Color 1 Register */
211	{0x007C,0x1F}, /* LCD Ink/Cursor Red Color 1 Register */
212	{0x007E,0x00}, /* LCD Ink/Cursor FIFO Threshold Register */
213	{0x0080,0x00}, /* CRT/TV Ink/Cursor Control Register */
214	{0x0081,0x00}, /* CRT/TV Ink/Cursor Start Address Register */
215	{0x0082,0x00}, /* CRT/TV Cursor X Position Register 0 */
216	{0x0083,0x00}, /* CRT/TV Cursor X Position Register 1 */
217	{0x0084,0x00}, /* CRT/TV Cursor Y Position Register 0 */
218	{0x0085,0x00}, /* CRT/TV Cursor Y Position Register 1 */
219	{0x0086,0x00}, /* CRT/TV Ink/Cursor Blue Color 0 Register */
220	{0x0087,0x00}, /* CRT/TV Ink/Cursor Green Color 0 Register */
221	{0x0088,0x00}, /* CRT/TV Ink/Cursor Red Color 0 Register */
222	{0x008A,0x1F}, /* CRT/TV Ink/Cursor Blue Color 1 Register */
223	{0x008B,0x3F}, /* CRT/TV Ink/Cursor Green Color 1 Register */
224	{0x008C,0x1F}, /* CRT/TV Ink/Cursor Red Color 1 Register */
225	{0x008E,0x00}, /* CRT/TV Ink/Cursor FIFO Threshold Register */
226	{0x0100,0x00}, /* BitBlt Control Register 0 */
227	{0x0101,0x00}, /* BitBlt Control Register 1 */
228	{0x0102,0x00}, /* BitBlt ROP Code/Color Expansion Register */
229	{0x0103,0x00}, /* BitBlt Operation Register */
230	{0x0104,0x00}, /* BitBlt Source Start Address Register 0 */
231	{0x0105,0x00}, /* BitBlt Source Start Address Register 1 */
232	{0x0106,0x00}, /* BitBlt Source Start Address Register 2 */
233	{0x0108,0x00}, /* BitBlt Destination Start Address Register 0 */
234	{0x0109,0x00}, /* BitBlt Destination Start Address Register 1 */
235	{0x010A,0x00}, /* BitBlt Destination Start Address Register 2 */
236	{0x010C,0x00}, /* BitBlt Memory Address Offset Register 0 */
237	{0x010D,0x00}, /* BitBlt Memory Address Offset Register 1 */
238	{0x0110,0x00}, /* BitBlt Width Register 0 */
239	{0x0111,0x00}, /* BitBlt Width Register 1 */
240	{0x0112,0x00}, /* BitBlt Height Register 0 */
241	{0x0113,0x00}, /* BitBlt Height Register 1 */
242	{0x0114,0x00}, /* BitBlt Background Color Register 0 */
243	{0x0115,0x00}, /* BitBlt Background Color Register 1 */
244	{0x0118,0x00}, /* BitBlt Foreground Color Register 0 */
245	{0x0119,0x00}, /* BitBlt Foreground Color Register 1 */
246	{0x01E0,0x01}, /* Look-Up Table Mode Register */
247	{0x01E2,0x00}, /* Look-Up Table Address Register */
248	{0x01E4,0x00}, /* Look-Up Table Data Register */
249	{0x01F0,0x10}, /* Power Save Configuration Register */
250	{0x01F1,0x00}, /* Power Save Status Register */
251	{0x01F4,0x00}, /* CPU-to-Memory Access Watchdog Timer Register */
252	{0x01FC,0x01}, /* Display Mode Register */
a6c7ad2f WD	253	{0, 0}
	254	};
	255
	256	#endif /* CONFIG_VIDEO_SED13806_16BPP */
	257	#endif /* CONFIG_NEC_NL6448BC20 */
	258
	259
a6c7ad2f WD	260	#ifdef CONFIG_CONSOLE_EXTRA_INFO
	261
	262	/*-----------------------------------------------------------------------------
	263	* video_get_info_str -- setup a board string: type, speed, etc.
	264	* line_number= location to place info string beside logo
	265	* info= buffer for info string
	266	*-----------------------------------------------------------------------------
	267	*/
	268	void video_get_info_str (int line_number, char *info)
	269	{
	270	if (line_number == 1) {
8bde7f77	271	strcpy (info, " RPXClassic board");
a6c7ad2f WD	272	}
a6c7ad2f WD	273	else {
8bde7f77	274	info [0] = '\0';
a6c7ad2f WD	275	}
	276
	277	}
	278	#endif
	279
	280	/*-----------------------------------------------------------------------------
	281	* board_video_init -- init de l'EPSON, config du CS
	282	*-----------------------------------------------------------------------------
	283	*/
	284	unsigned int board_video_init (void)
	285	{
6d0f6bcf	286	volatile immap_t immap = (immap_t )CONFIG_SYS_IMMR;
a6c7ad2f WD	287	volatile memctl8xx_t *memctl = &immap->im_memctl;
	288
	289	/* Program ECCX registers */
	290	*(ECCX_CSR12) \|= ECCX_860;
	291	*(ECCX_CSR8) \|= ECCX_BE \| ECCX_CS2;
	292	*(ECCX_CSR8) \|= ECCX_ENEPSON;
8bde7f77	293
a6c7ad2f WD	294	memctl->memc_or2 = SED13806_OR;
	295	memctl->memc_br2 = SED13806_REG_ADDR \| SED13806_ACCES;
	296
	297	return (SED13806_REG_ADDR);
	298	}
	299
	300	/*-----------------------------------------------------------------------------
8bde7f77	301	* board_validate_screen --
a6c7ad2f WD	302	*-----------------------------------------------------------------------------
	303	*/
	304	void board_validate_screen (unsigned int base)
	305	{
	306	/* Activate the panel bias power */
	307	(volatile unsigned char )(base + REG_GPIO_CTRL) = 0x80;
	308	}
	309	/*-----------------------------------------------------------------------------
8bde7f77	310	* board_get_regs --
a6c7ad2f WD	311	*-----------------------------------------------------------------------------
	312	*/
	313	const S1D_REGS *board_get_regs (void)
	314	{
	315	return (init_regs);
	316	}
	317	/*-----------------------------------------------------------------------------
8bde7f77	318	* board_get_width --
a6c7ad2f WD	319	*-----------------------------------------------------------------------------
	320	*/
	321	int board_get_width (void)
	322	{
	323	return (DISPLAY_WIDTH);
	324	}
	325
	326	/*-----------------------------------------------------------------------------
8bde7f77	327	* board_get_height --
a6c7ad2f WD	328	*-----------------------------------------------------------------------------
	329	*/
	330	int board_get_height (void)
	331	{
	332	return (DISPLAY_HEIGHT);
	333	}
	334
	335	#endif /* CONFIG_VIDEO_SED13806 */