[people/ms/u-boot.git] / board / Seagate / goflexhome / goflexhome.c

/*
 * Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
 *
 * Based on dockstar.c originally written by
 * Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
 *
 * Based on sheevaplug.c originally written by
 * Prafulla Wadaskar <prafulla@marvell.com>
 * (C) Copyright 2009
 * Marvell Semiconductor <www.marvell.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#include <common.h>
#include <miiphy.h>
#include <asm/mach-types.h>
#include <asm/arch/soc.h>
#include <asm/arch/mpp.h>
#include <asm/arch/cpu.h>
#include <asm/io.h>

DECLARE_GLOBAL_DATA_PTR;

int board_early_init_f(void)
{
	/* Multi-Purpose Pins Functionality configuration */
	static const u32 kwmpp_config[] = {
		MPP0_NF_IO2,
		MPP1_NF_IO3,
		MPP2_NF_IO4,
		MPP3_NF_IO5,
		MPP4_NF_IO6,
		MPP5_NF_IO7,
		MPP6_SYSRST_OUTn,
		MPP7_GPO,
		MPP8_UART0_RTS,
		MPP9_UART0_CTS,
		MPP10_UART0_TXD,
		MPP11_UART0_RXD,
		MPP12_SD_CLK,
		MPP13_SD_CMD,
		MPP14_SD_D0,
		MPP15_SD_D1,
		MPP16_SD_D2,
		MPP17_SD_D3,
		MPP18_NF_IO0,
		MPP19_NF_IO1,
		MPP20_GPIO,
		MPP21_GPIO,
		MPP22_GPIO,
		MPP23_GPIO,
		MPP24_GPIO,
		MPP25_GPIO,
		MPP26_GPIO,
		MPP27_GPIO,
		MPP28_GPIO,
		MPP29_TSMP9,
		MPP30_GPIO,
		MPP31_GPIO,
		MPP32_GPIO,
		MPP33_GPIO,
		MPP34_GPIO,
		MPP35_GPIO,
		MPP36_GPIO,
		MPP37_GPIO,
		MPP38_GPIO,
		MPP39_GPIO,
		MPP40_GPIO,
		MPP41_GPIO,
		MPP42_GPIO,
		MPP43_GPIO,
		MPP44_GPIO,
		MPP45_GPIO,
		MPP46_GPIO,
		MPP47_GPIO,
		MPP48_GPIO,
		MPP49_GPIO,
		0
	};

	/*
	 * default gpio configuration
	 * There are maximum 64 gpios controlled through 2 sets of registers
	 * the  below configuration configures mainly initial LED status
	 */
	mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW,
			  GOFLEXHOME_OE_VAL_HIGH,
			  GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
	kirkwood_mpp_conf(kwmpp_config, NULL);
	return 0;
}

int board_init(void)
{
	/*
	 * arch number of board
	 */
	gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME;

	/* address of boot parameters */
	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;

	return 0;
}

#ifdef CONFIG_RESET_PHY_R
/* Configure and enable MV88E1116 PHY */
void reset_phy(void)
{
	u16 reg;
	u16 devadr;
	char *name = "egiga0";

	if (miiphy_set_current_dev(name))
		return;

	/* command to read PHY dev address */
	if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
		printf("Err..%s could not read PHY dev address\n",
		       __func__);
		return;
	}

	/*
	 * Enable RGMII delay on Tx and Rx for CPU port
	 * Ref: sec 4.7.2 of chip datasheet
	 */
	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
	reg |= (MV88E1116_RGMII_RXTM_CTRL | MV88E1116_RGMII_TXTM_CTRL);
	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);

	/* reset the phy */
	miiphy_reset(name, devadr);

	printf("88E1116 Initialized on %s\n", name);
}
#endif /* CONFIG_RESET_PHY_R */

#define GREEN_LED	(1 << 14)
#define ORANGE_LED	(1 << 15)
#define BOTH_LEDS	(GREEN_LED | ORANGE_LED)
#define NEITHER_LED	0

static void set_leds(u32 leds, u32 blinking)
{
	struct kwgpio_registers *r;
	u32 oe;
	u32 bl;

	r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
	oe = readl(&r->oe) | BOTH_LEDS;
	writel(oe & ~leds, &r->oe);	/* active low */
	bl = readl(&r->blink_en) & ~BOTH_LEDS;
	writel(bl | blinking, &r->blink_en);
}

void show_boot_progress(int val)
{
	switch (val) {
	case BOOTSTAGE_ID_RUN_OS:		/* booting Linux */
		set_leds(BOTH_LEDS, NEITHER_LED);
		break;
	case BOOTSTAGE_ID_NET_ETH_START:	/* Ethernet initialization */
		set_leds(GREEN_LED, GREEN_LED);
		break;
	default:
		if (val < 0)	/* error */
			set_leds(ORANGE_LED, ORANGE_LED);
		break;
	}
}
Commit	Line	Data
0ad6c34c SR	1	/*
	2	* Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
	3	*
	4	* Based on dockstar.c originally written by
	5	* Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
	6	*
	7	* Based on sheevaplug.c originally written by
	8	* Prafulla Wadaskar <prafulla@marvell.com>
	9	* (C) Copyright 2009
	10	* Marvell Semiconductor <www.marvell.com>
	11	*
1a459660	12	* SPDX-License-Identifier: GPL-2.0+
0ad6c34c SR	13	*/
	14
	15	#include <common.h>
	16	#include <miiphy.h>
c62db35d	17	#include <asm/mach-types.h>
3dc23f78	18	#include <asm/arch/soc.h>
0ad6c34c SR	19	#include <asm/arch/mpp.h>
	20	#include <asm/arch/cpu.h>
	21	#include <asm/io.h>
	22
	23	DECLARE_GLOBAL_DATA_PTR;
	24
	25	int board_early_init_f(void)
	26	{
	27	/* Multi-Purpose Pins Functionality configuration */
	28	static const u32 kwmpp_config[] = {
	29	MPP0_NF_IO2,
	30	MPP1_NF_IO3,
	31	MPP2_NF_IO4,
	32	MPP3_NF_IO5,
	33	MPP4_NF_IO6,
	34	MPP5_NF_IO7,
	35	MPP6_SYSRST_OUTn,
	36	MPP7_GPO,
	37	MPP8_UART0_RTS,
	38	MPP9_UART0_CTS,
	39	MPP10_UART0_TXD,
	40	MPP11_UART0_RXD,
	41	MPP12_SD_CLK,
	42	MPP13_SD_CMD,
	43	MPP14_SD_D0,
	44	MPP15_SD_D1,
	45	MPP16_SD_D2,
	46	MPP17_SD_D3,
	47	MPP18_NF_IO0,
	48	MPP19_NF_IO1,
	49	MPP20_GPIO,
	50	MPP21_GPIO,
	51	MPP22_GPIO,
	52	MPP23_GPIO,
	53	MPP24_GPIO,
	54	MPP25_GPIO,
	55	MPP26_GPIO,
	56	MPP27_GPIO,
	57	MPP28_GPIO,
	58	MPP29_TSMP9,
	59	MPP30_GPIO,
	60	MPP31_GPIO,
	61	MPP32_GPIO,
	62	MPP33_GPIO,
	63	MPP34_GPIO,
	64	MPP35_GPIO,
	65	MPP36_GPIO,
	66	MPP37_GPIO,
	67	MPP38_GPIO,
	68	MPP39_GPIO,
	69	MPP40_GPIO,
	70	MPP41_GPIO,
	71	MPP42_GPIO,
	72	MPP43_GPIO,
	73	MPP44_GPIO,
	74	MPP45_GPIO,
	75	MPP46_GPIO,
	76	MPP47_GPIO,
	77	MPP48_GPIO,
	78	MPP49_GPIO,
	79	0
	80	};
	81
	82	/*
83	* default gpio configuration
84	* There are maximum 64 gpios controlled through 2 sets of registers
85	* the below configuration configures mainly initial LED status
86	*/
d5c5132f SR	87	mvebu_config_gpio(GOFLEXHOME_OE_VAL_LOW,
	88	GOFLEXHOME_OE_VAL_HIGH,
	89	GOFLEXHOME_OE_LOW, GOFLEXHOME_OE_HIGH);
0ad6c34c SR	90	kirkwood_mpp_conf(kwmpp_config, NULL);
	91	return 0;
	92	}
	93
	94	int board_init(void)
	95	{
94ba26f2 TR	96	/*
	97	* arch number of board
	98	*/
	99	gd->bd->bi_arch_number = MACH_TYPE_GOFLEXHOME;
	100
0ad6c34c	101	/* address of boot parameters */
96c5f081	102	gd->bd->bi_boot_params = mvebu_sdram_bar(0) + 0x100;
0ad6c34c SR	103
	104	return 0;
	105	}
	106
	107	#ifdef CONFIG_RESET_PHY_R
	108	/* Configure and enable MV88E1116 PHY */
	109	void reset_phy(void)
	110	{
	111	u16 reg;
	112	u16 devadr;
	113	char *name = "egiga0";
	114
	115	if (miiphy_set_current_dev(name))
	116	return;
	117
	118	/* command to read PHY dev address */
	119	if (miiphy_read(name, 0xEE, 0xEE, (u16 *)&devadr)) {
	120	printf("Err..%s could not read PHY dev address\n",
	121	__func__);
	122	return;
	123	}
	124
	125	/*
	126	* Enable RGMII delay on Tx and Rx for CPU port
	127	* Ref: sec 4.7.2 of chip datasheet
	128	*/
	129	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 2);
	130	miiphy_read(name, devadr, MV88E1116_MAC_CTRL_REG, &reg);
	131	reg \|= (MV88E1116_RGMII_RXTM_CTRL \| MV88E1116_RGMII_TXTM_CTRL);
	132	miiphy_write(name, devadr, MV88E1116_MAC_CTRL_REG, reg);
	133	miiphy_write(name, devadr, MV88E1116_PGADR_REG, 0);
	134
	135	/* reset the phy */
	136	miiphy_reset(name, devadr);
	137
	138	printf("88E1116 Initialized on %s\n", name);
	139	}
	140	#endif /* CONFIG_RESET_PHY_R */
	141
	142	#define GREEN_LED (1 << 14)
	143	#define ORANGE_LED (1 << 15)
	144	#define BOTH_LEDS (GREEN_LED \| ORANGE_LED)
	145	#define NEITHER_LED 0
	146
	147	static void set_leds(u32 leds, u32 blinking)
	148	{
	149	struct kwgpio_registers *r;
	150	u32 oe;
	151	u32 bl;
	152
d5c5132f	153	r = (struct kwgpio_registers *)MVEBU_GPIO1_BASE;
0ad6c34c SR	154	oe = readl(&r->oe) \| BOTH_LEDS;
	155	writel(oe & ~leds, &r->oe); /* active low */
	156	bl = readl(&r->blink_en) & ~BOTH_LEDS;
	157	writel(bl \| blinking, &r->blink_en);
	158	}
	159
	160	void show_boot_progress(int val)
	161	{
	162	switch (val) {
	163	case BOOTSTAGE_ID_RUN_OS: /* booting Linux */
	164	set_leds(BOTH_LEDS, NEITHER_LED);
	165	break;
	166	case BOOTSTAGE_ID_NET_ETH_START: /* Ethernet initialization */
	167	set_leds(GREEN_LED, GREEN_LED);
	168	break;
	169	default:
	170	if (val < 0) /* error */
	171	set_leds(ORANGE_LED, ORANGE_LED);
	172	break;
	173	}
	174	}