[thirdparty/u-boot.git] / board / Seagate / goflexhome / kwbimage.cfg

#
# Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
#
# Based on dockstar/kwbimage.cfg originally written by
# Copyright (C) 2010  Eric C. Cooper <ecc@cmu.edu>
#
# Based on sheevaplug/kwbimage.cfg originally written by
# Prafulla Wadaskar <prafulla@marvell.com>
# (C) Copyright 2009
# Marvell Semiconductor <www.marvell.com>
#
# SPDX-License-Identifier:	GPL-2.0+
#
# Refer docs/README.kwimage for more details about how-to configure
# and create kirkwood boot image
#

# Boot Media configurations
BOOT_FROM	nand
NAND_ECC_MODE	default
NAND_PAGE_SIZE	0x0800

# SOC registers configuration using bootrom header extension
# Maximum KWBIMAGE_MAX_CONFIG configurations allowed

# Configure RGMII-0 interface pad voltage to 1.8V
DATA 0xFFD100e0 0x1b1b1b9b

#Dram initalization for SINGLE x16 CL=5 @ 400MHz
DATA 0xFFD01400 0x43000c30	# DDR Configuration register
# bit13-0:  0xc30 (3120 DDR2 clks refresh rate)
# bit23-14: zero
# bit24: 1= enable exit self refresh mode on DDR access
# bit25: 1 required
# bit29-26: zero
# bit31-30: 01

DATA 0xFFD01404 0x37543000	# DDR Controller Control Low
# bit 4:    0=addr/cmd in smame cycle
# bit 5:    0=clk is driven during self refresh, we don't care for APX
# bit 6:    0=use recommended falling edge of clk for addr/cmd
# bit14:    0=input buffer always powered up
# bit18:    1=cpu lock transaction enabled
# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
# bit30-28: 3 required
# bit31:    0=no additional STARTBURST delay

DATA 0xFFD01408 0x22125451	# DDR Timing (Low) (active cycles value +1)
# bit3-0:   TRAS lsbs
# bit7-4:   TRCD
# bit11- 8: TRP
# bit15-12: TWR
# bit19-16: TWTR
# bit20:    TRAS msb
# bit23-21: 0x0
# bit27-24: TRRD
# bit31-28: TRTP

DATA 0xFFD0140C 0x00000a33	#  DDR Timing (High)
# bit6-0:   TRFC
# bit8-7:   TR2R
# bit10-9:  TR2W
# bit12-11: TW2W
# bit31-13: zero required

DATA 0xFFD01410 0x0000000d	#  DDR Address Control
# bit1-0:   00, Cs0width=x8
# bit3-2:   11, Cs0size=1Gb
# bit5-4:   00, Cs1width=nonexistent
# bit7-6:   00, Cs1size =nonexistent
# bit9-8:   00, Cs2width=nonexistent
# bit11-10: 00, Cs2size =nonexistent
# bit13-12: 00, Cs3width=nonexistent
# bit15-14: 00, Cs3size =nonexistent
# bit16:    0,  Cs0AddrSel
# bit17:    0,  Cs1AddrSel
# bit18:    0,  Cs2AddrSel
# bit19:    0,  Cs3AddrSel
# bit31-20: 0 required

DATA 0xFFD01414 0x00000000	#  DDR Open Pages Control
# bit0:    0,  OpenPage enabled
# bit31-1: 0 required

DATA 0xFFD01418 0x00000000	#  DDR Operation
# bit3-0:   0x0, DDR cmd
# bit31-4:  0 required

DATA 0xFFD0141C 0x00000C52	#  DDR Mode
# bit2-0:   2, BurstLen=2 required
# bit3:     0, BurstType=0 required
# bit6-4:   4, CL=5
# bit7:     0, TestMode=0 normal
# bit8:     0, DLL reset=0 normal
# bit11-9:  6, auto-precharge write recovery ????????????
# bit12:    0, PD must be zero
# bit31-13: 0 required

DATA 0xFFD01420 0x00000040	#  DDR Extended Mode
# bit0:    0,  DDR DLL enabled
# bit1:    0,  DDR drive strenght normal
# bit2:    0,  DDR ODT control lsd (disabled)
# bit5-3:  000, required
# bit6:    1,  DDR ODT control msb, (disabled)
# bit9-7:  000, required
# bit10:   0,  differential DQS enabled
# bit11:   0, required
# bit12:   0, DDR output buffer enabled
# bit31-13: 0 required

DATA 0xFFD01424 0x0000F17F	#  DDR Controller Control High
# bit2-0:  111, required
# bit3  :  1  , MBUS Burst Chop disabled
# bit6-4:  111, required
# bit7  :  0
# bit8  :  1  , add writepath sample stage, must be 1 for DDR freq >= 300MHz
# bit9  :  0  , no half clock cycle addition to dataout
# bit10 :  0  , 1/4 clock cycle skew enabled for addr/ctl signals
# bit11 :  0  , 1/4 clock cycle skew disabled for write mesh
# bit15-12: 1111 required
# bit31-16: 0    required

DATA 0xFFD01428 0x00085520	# DDR2 ODT Read Timing (default values)
DATA 0xFFD0147C 0x00008552	# DDR2 ODT Write Timing (default values)

DATA 0xFFD01500 0x00000000	# CS[0]n Base address to 0x0
DATA 0xFFD01504 0x07FFFFF1	# CS[0]n Size
# bit0:    1,  Window enabled
# bit1:    0,  Write Protect disabled
# bit3-2:  00, CS0 hit selected
# bit23-4: ones, required
# bit31-24: 0x07, Size (i.e. 128MB)

DATA 0xFFD01508 0x10000000	# CS[1]n Base address to 256Mb
DATA 0xFFD0150C 0x00000000	# CS[1]n Size, window disabled

DATA 0xFFD01514 0x00000000	# CS[2]n Size, window disabled
DATA 0xFFD0151C 0x00000000	# CS[3]n Size, window disabled

DATA 0xFFD01494 0x00030000	#  DDR ODT Control (Low)
DATA 0xFFD01498 0x00000000	#  DDR ODT Control (High)
# bit1-0:  00, ODT0 controlled by ODT Control (low) register above
# bit3-2:  01, ODT1 active NEVER!
# bit31-4: zero, required

DATA 0xFFD0149C 0x0000E803	# CPU ODT Control
DATA 0xFFD01480 0x00000001	# DDR Initialization Control
#bit0=1, enable DDR init upon this register write

# End of Header extension
DATA 0x0 0x0
Commit	Line	Data
0ad6c34c SR	1	#
	2	# Copyright (C) 2013 Suriyan Ramasami <suriyan.r@gmail.com>
	3	#
	4	# Based on dockstar/kwbimage.cfg originally written by
	5	# Copyright (C) 2010 Eric C. Cooper <ecc@cmu.edu>
	6	#
	7	# Based on sheevaplug/kwbimage.cfg originally written by
	8	# Prafulla Wadaskar <prafulla@marvell.com>
	9	# (C) Copyright 2009
	10	# Marvell Semiconductor <www.marvell.com>
	11	#
1a459660	12	# SPDX-License-Identifier: GPL-2.0+
0ad6c34c SR	13	#
	14	# Refer docs/README.kwimage for more details about how-to configure
	15	# and create kirkwood boot image
	16	#
	17
	18	# Boot Media configurations
	19	BOOT_FROM nand
	20	NAND_ECC_MODE default
	21	NAND_PAGE_SIZE 0x0800
	22
	23	# SOC registers configuration using bootrom header extension
	24	# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
	25
	26	# Configure RGMII-0 interface pad voltage to 1.8V
	27	DATA 0xFFD100e0 0x1b1b1b9b
	28
	29	#Dram initalization for SINGLE x16 CL=5 @ 400MHz
	30	DATA 0xFFD01400 0x43000c30 # DDR Configuration register
	31	# bit13-0: 0xc30 (3120 DDR2 clks refresh rate)
	32	# bit23-14: zero
	33	# bit24: 1= enable exit self refresh mode on DDR access
	34	# bit25: 1 required
	35	# bit29-26: zero
	36	# bit31-30: 01
	37
	38	DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
	39	# bit 4: 0=addr/cmd in smame cycle
	40	# bit 5: 0=clk is driven during self refresh, we don't care for APX
	41	# bit 6: 0=use recommended falling edge of clk for addr/cmd
	42	# bit14: 0=input buffer always powered up
	43	# bit18: 1=cpu lock transaction enabled
	44	# bit23-20: 5=recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
	45	# bit27-24: 7= CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
	46	# bit30-28: 3 required
	47	# bit31: 0=no additional STARTBURST delay
	48
	49	DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
	50	# bit3-0: TRAS lsbs
	51	# bit7-4: TRCD
	52	# bit11- 8: TRP
	53	# bit15-12: TWR
	54	# bit19-16: TWTR
	55	# bit20: TRAS msb
	56	# bit23-21: 0x0
	57	# bit27-24: TRRD
	58	# bit31-28: TRTP
	59
	60	DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
	61	# bit6-0: TRFC
	62	# bit8-7: TR2R
	63	# bit10-9: TR2W
	64	# bit12-11: TW2W
	65	# bit31-13: zero required
	66
	67	DATA 0xFFD01410 0x0000000d # DDR Address Control
	68	# bit1-0: 00, Cs0width=x8
	69	# bit3-2: 11, Cs0size=1Gb
	70	# bit5-4: 00, Cs1width=nonexistent
	71	# bit7-6: 00, Cs1size =nonexistent
	72	# bit9-8: 00, Cs2width=nonexistent
	73	# bit11-10: 00, Cs2size =nonexistent
	74	# bit13-12: 00, Cs3width=nonexistent
	75	# bit15-14: 00, Cs3size =nonexistent
	76	# bit16: 0, Cs0AddrSel
77	# bit17: 0, Cs1AddrSel
78	# bit18: 0, Cs2AddrSel
79	# bit19: 0, Cs3AddrSel
80	# bit31-20: 0 required
81
82	DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
83	# bit0: 0, OpenPage enabled
84	# bit31-1: 0 required
85
86	DATA 0xFFD01418 0x00000000 # DDR Operation
87	# bit3-0: 0x0, DDR cmd
88	# bit31-4: 0 required
89
90	DATA 0xFFD0141C 0x00000C52 # DDR Mode
91	# bit2-0: 2, BurstLen=2 required
92	# bit3: 0, BurstType=0 required
93	# bit6-4: 4, CL=5
94	# bit7: 0, TestMode=0 normal
95	# bit8: 0, DLL reset=0 normal
96	# bit11-9: 6, auto-precharge write recovery ????????????
97	# bit12: 0, PD must be zero
98	# bit31-13: 0 required
99
100	DATA 0xFFD01420 0x00000040 # DDR Extended Mode
101	# bit0: 0, DDR DLL enabled
102	# bit1: 0, DDR drive strenght normal
103	# bit2: 0, DDR ODT control lsd (disabled)
104	# bit5-3: 000, required
105	# bit6: 1, DDR ODT control msb, (disabled)
106	# bit9-7: 000, required
107	# bit10: 0, differential DQS enabled
108	# bit11: 0, required
109	# bit12: 0, DDR output buffer enabled
110	# bit31-13: 0 required
111
112	DATA 0xFFD01424 0x0000F17F # DDR Controller Control High
113	# bit2-0: 111, required
114	# bit3 : 1 , MBUS Burst Chop disabled
115	# bit6-4: 111, required
116	# bit7 : 0
117	# bit8 : 1 , add writepath sample stage, must be 1 for DDR freq >= 300MHz
118	# bit9 : 0 , no half clock cycle addition to dataout
119	# bit10 : 0 , 1/4 clock cycle skew enabled for addr/ctl signals
120	# bit11 : 0 , 1/4 clock cycle skew disabled for write mesh
121	# bit15-12: 1111 required
122	# bit31-16: 0 required
123
124	DATA 0xFFD01428 0x00085520 # DDR2 ODT Read Timing (default values)
125	DATA 0xFFD0147C 0x00008552 # DDR2 ODT Write Timing (default values)
126
127	DATA 0xFFD01500 0x00000000 # CS[0]n Base address to 0x0
128	DATA 0xFFD01504 0x07FFFFF1 # CS[0]n Size
129	# bit0: 1, Window enabled
130	# bit1: 0, Write Protect disabled
131	# bit3-2: 00, CS0 hit selected
132	# bit23-4: ones, required
133	# bit31-24: 0x07, Size (i.e. 128MB)
134
135	DATA 0xFFD01508 0x10000000 # CS[1]n Base address to 256Mb
136	DATA 0xFFD0150C 0x00000000 # CS[1]n Size, window disabled
137
138	DATA 0xFFD01514 0x00000000 # CS[2]n Size, window disabled
139	DATA 0xFFD0151C 0x00000000 # CS[3]n Size, window disabled
140
141	DATA 0xFFD01494 0x00030000 # DDR ODT Control (Low)
142	DATA 0xFFD01498 0x00000000 # DDR ODT Control (High)
143	# bit1-0: 00, ODT0 controlled by ODT Control (low) register above
144	# bit3-2: 01, ODT1 active NEVER!
145	# bit31-4: zero, required
146
147	DATA 0xFFD0149C 0x0000E803 # CPU ODT Control
148	DATA 0xFFD01480 0x00000001 # DDR Initialization Control
149	#bit0=1, enable DDR init upon this register write
150
151	# End of Header extension
152	DATA 0x0 0x0