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9531a238 SP |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004 | |
6 | * Mark Jonas, Freescale Semiconductor, mark.jonas@motorola.com. | |
7 | * | |
8 | * (C) Copyright 2010 | |
9 | * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. | |
10 | * | |
1a459660 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
9531a238 SP |
12 | */ |
13 | ||
14 | #include <common.h> | |
15 | #include <mpc5xxx.h> | |
16 | #include <pci.h> | |
17 | #include <asm/processor.h> | |
18 | #include <asm/io.h> | |
19 | #include <libfdt.h> | |
20 | #include <netdev.h> | |
cb5639cb | 21 | #include <led-display.h> |
92d1a400 | 22 | #include <linux/err.h> |
9531a238 SP |
23 | |
24 | #include "mt46v32m16.h" | |
25 | ||
088454cd SG |
26 | DECLARE_GLOBAL_DATA_PTR; |
27 | ||
9531a238 SP |
28 | #ifndef CONFIG_SYS_RAMBOOT |
29 | static void sdram_start (int hi_addr) | |
30 | { | |
31 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; | |
32 | long control = SDRAM_CONTROL | hi_addr_bit; | |
33 | ||
34 | /* unlock mode register */ | |
35 | out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000000); | |
36 | __asm__ volatile ("sync"); | |
37 | ||
38 | /* precharge all banks */ | |
39 | out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); | |
40 | __asm__ volatile ("sync"); | |
41 | ||
42 | #if SDRAM_DDR | |
43 | /* set mode register: extended mode */ | |
44 | out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_EMODE); | |
45 | __asm__ volatile ("sync"); | |
46 | ||
47 | /* set mode register: reset DLL */ | |
48 | out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE | 0x04000000); | |
49 | __asm__ volatile ("sync"); | |
50 | #endif | |
51 | ||
52 | /* precharge all banks */ | |
53 | out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000002); | |
54 | __asm__ volatile ("sync"); | |
55 | ||
56 | /* auto refresh */ | |
57 | out_be32((void *)MPC5XXX_SDRAM_CTRL, control | 0x80000004); | |
58 | __asm__ volatile ("sync"); | |
59 | ||
60 | /* set mode register */ | |
61 | out_be32((void *)MPC5XXX_SDRAM_MODE, SDRAM_MODE); | |
62 | __asm__ volatile ("sync"); | |
63 | ||
64 | /* normal operation */ | |
65 | out_be32((void *)MPC5XXX_SDRAM_CTRL, control); | |
66 | __asm__ volatile ("sync"); | |
67 | } | |
68 | #endif | |
69 | ||
70 | /* | |
f1683aa7 | 71 | * ATTENTION: Although partially referenced dram_init does NOT make real use |
9531a238 SP |
72 | * use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE |
73 | * is something else than 0x00000000. | |
74 | */ | |
75 | ||
f1683aa7 | 76 | int dram_init(void) |
9531a238 SP |
77 | { |
78 | ulong dramsize = 0; | |
79 | uint svr, pvr; | |
80 | ||
81 | #ifndef CONFIG_SYS_RAMBOOT | |
82 | ulong test1, test2; | |
83 | ||
84 | /* setup SDRAM chip selects */ | |
85 | out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0x0000001e); /* 2GB at 0x0 */ | |
86 | out_be32((void *)MPC5XXX_SDRAM_CS1CFG, 0x80000000); /* disabled */ | |
87 | __asm__ volatile ("sync"); | |
88 | ||
89 | /* setup config registers */ | |
90 | out_be32((void *)MPC5XXX_SDRAM_CONFIG1, SDRAM_CONFIG1); | |
91 | out_be32((void *)MPC5XXX_SDRAM_CONFIG2, SDRAM_CONFIG2); | |
92 | __asm__ volatile ("sync"); | |
93 | ||
94 | #if SDRAM_DDR | |
95 | /* set tap delay */ | |
96 | out_be32((void *)MPC5XXX_CDM_PORCFG, SDRAM_TAPDELAY); | |
97 | __asm__ volatile ("sync"); | |
98 | #endif | |
99 | ||
100 | /* find RAM size using SDRAM CS0 only */ | |
101 | sdram_start(0); | |
102 | test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); | |
103 | sdram_start(1); | |
104 | test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); | |
105 | if (test1 > test2) { | |
106 | sdram_start(0); | |
107 | dramsize = test1; | |
108 | } else { | |
109 | dramsize = test2; | |
110 | } | |
111 | ||
112 | /* memory smaller than 1MB is impossible */ | |
113 | if (dramsize < (1 << 20)) { | |
114 | dramsize = 0; | |
115 | } | |
116 | ||
117 | /* set SDRAM CS0 size according to the amount of RAM found */ | |
118 | if (dramsize > 0) { | |
119 | out_be32((void *)MPC5XXX_SDRAM_CS0CFG, | |
120 | 0x13 + __builtin_ffs(dramsize >> 20) - 1); | |
121 | } else { | |
122 | out_be32((void *)MPC5XXX_SDRAM_CS0CFG, 0); /* disabled */ | |
123 | } | |
124 | ||
125 | #else /* CONFIG_SYS_RAMBOOT */ | |
126 | ||
127 | /* retrieve size of memory connected to SDRAM CS0 */ | |
128 | dramsize = in_be32((void *)MPC5XXX_SDRAM_CS0CFG) & 0xFF; | |
129 | if (dramsize >= 0x13) { | |
130 | dramsize = (1 << (dramsize - 0x13)) << 20; | |
131 | } else { | |
132 | dramsize = 0; | |
133 | } | |
134 | ||
135 | #endif /* CONFIG_SYS_RAMBOOT */ | |
136 | ||
137 | /* | |
138 | * On MPC5200B we need to set the special configuration delay in the | |
139 | * DDR controller. Please refer to Freescale's AN3221 "MPC5200B SDRAM | |
140 | * Initialization and Configuration", 3.3.1 SDelay--MBAR + 0x0190: | |
141 | * | |
142 | * "The SDelay should be written to a value of 0x00000004. It is | |
143 | * required to account for changes caused by normal wafer processing | |
144 | * parameters." | |
145 | */ | |
146 | svr = get_svr(); | |
147 | pvr = get_pvr(); | |
148 | if ((SVR_MJREV(svr) >= 2) && | |
149 | (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) { | |
150 | ||
151 | out_be32((void *)MPC5XXX_SDRAM_SDELAY, 0x04); | |
152 | __asm__ volatile ("sync"); | |
153 | } | |
154 | ||
088454cd SG |
155 | gd->ram_size = dramsize; |
156 | ||
157 | return 0; | |
9531a238 SP |
158 | } |
159 | ||
160 | int checkboard (void) | |
161 | { | |
162 | puts ("Board: A4M072\n"); | |
163 | return 0; | |
164 | } | |
165 | ||
166 | #ifdef CONFIG_PCI | |
167 | static struct pci_controller hose; | |
168 | ||
169 | extern void pci_mpc5xxx_init(struct pci_controller *); | |
170 | ||
171 | void pci_init_board(void) | |
172 | { | |
173 | pci_mpc5xxx_init(&hose); | |
174 | } | |
175 | #endif | |
176 | ||
7ffe3cd6 | 177 | #ifdef CONFIG_OF_BOARD_SETUP |
e895a4b0 | 178 | int ft_board_setup(void *blob, bd_t *bd) |
9531a238 SP |
179 | { |
180 | ft_cpu_setup(blob, bd); | |
e895a4b0 SG |
181 | |
182 | return 0; | |
9531a238 | 183 | } |
7ffe3cd6 | 184 | #endif /* CONFIG_OF_BOARD_SETUP */ |
9531a238 SP |
185 | |
186 | int board_eth_init(bd_t *bis) | |
187 | { | |
188 | int rv, num_if = 0; | |
189 | ||
190 | /* Initialize TSECs first */ | |
191 | if ((rv = cpu_eth_init(bis)) >= 0) | |
192 | num_if += rv; | |
193 | else | |
194 | printf("ERROR: failed to initialize FEC.\n"); | |
195 | ||
196 | if ((rv = pci_eth_init(bis)) >= 0) | |
197 | num_if += rv; | |
198 | else | |
199 | printf("ERROR: failed to initialize PCI Ethernet.\n"); | |
200 | ||
201 | return num_if; | |
202 | } | |
203 | /* | |
204 | * Miscellaneous late-boot configurations | |
205 | * | |
206 | * Initialize EEPROM write-protect GPIO pin. | |
207 | */ | |
208 | int misc_init_r(void) | |
209 | { | |
210 | #if defined(CONFIG_SYS_EEPROM_WREN) | |
211 | /* Enable GPIO pin */ | |
212 | setbits_be32((void *)MPC5XXX_WU_GPIO_ENABLE, CONFIG_SYS_EEPROM_WP); | |
213 | /* Set direction, output */ | |
214 | setbits_be32((void *)MPC5XXX_WU_GPIO_DIR, CONFIG_SYS_EEPROM_WP); | |
215 | /* De-assert write enable */ | |
216 | setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP); | |
217 | #endif | |
218 | return 0; | |
219 | } | |
220 | #if defined(CONFIG_SYS_EEPROM_WREN) | |
221 | /* Input: <dev_addr> I2C address of EEPROM device to enable. | |
222 | * <state> -1: deliver current state | |
223 | * 0: disable write | |
224 | * 1: enable write | |
225 | * Returns: -1: wrong device address | |
226 | * 0: dis-/en- able done | |
227 | * 0/1: current state if <state> was -1. | |
228 | */ | |
229 | int eeprom_write_enable (unsigned dev_addr, int state) | |
230 | { | |
231 | if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) { | |
232 | return -1; | |
233 | } else { | |
234 | switch (state) { | |
235 | case 1: | |
236 | /* Enable write access */ | |
237 | clrbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP); | |
238 | state = 0; | |
239 | break; | |
240 | case 0: | |
241 | /* Disable write access */ | |
242 | setbits_be32((void *)MPC5XXX_WU_GPIO_DATA_O, CONFIG_SYS_EEPROM_WP); | |
243 | state = 0; | |
244 | break; | |
245 | default: | |
246 | /* Read current status back. */ | |
247 | state = (0 == (in_be32((void *)MPC5XXX_WU_GPIO_DATA_O) & | |
248 | CONFIG_SYS_EEPROM_WP)); | |
249 | break; | |
250 | } | |
251 | } | |
252 | return state; | |
253 | } | |
254 | #endif | |
cb5639cb IY |
255 | |
256 | #ifdef CONFIG_CMD_DISPLAY | |
257 | #define DISPLAY_BUF_SIZE 2 | |
258 | static u8 display_buf[DISPLAY_BUF_SIZE]; | |
259 | static u8 display_putc_pos; | |
260 | static u8 display_out_pos; | |
261 | ||
cb5639cb IY |
262 | void display_set(int cmd) { |
263 | ||
264 | if (cmd & DISPLAY_CLEAR) { | |
265 | display_buf[0] = display_buf[1] = 0; | |
266 | } | |
267 | ||
268 | if (cmd & DISPLAY_HOME) { | |
269 | display_putc_pos = 0; | |
270 | } | |
cb5639cb IY |
271 | } |
272 | ||
273 | #define SEG_A (1<<0) | |
274 | #define SEG_B (1<<1) | |
275 | #define SEG_C (1<<2) | |
276 | #define SEG_D (1<<3) | |
277 | #define SEG_E (1<<4) | |
278 | #define SEG_F (1<<5) | |
279 | #define SEG_G (1<<6) | |
280 | #define SEG_P (1<<7) | |
281 | #define SEG__ 0 | |
282 | ||
283 | /* | |
284 | * +- A -+ | |
285 | * | | | |
286 | * F B | |
287 | * | | | |
288 | * +- G -+ | |
289 | * | | | |
290 | * E C | |
291 | * | | | |
292 | * +- D -+ P | |
293 | * | |
294 | * 0..9 index 0..9 | |
295 | * A..Z index 10..35 | |
296 | * - index 36 | |
297 | * _ index 37 | |
8f54dd4f | 298 | * . index 38 |
cb5639cb IY |
299 | */ |
300 | ||
301 | #define SYMBOL_DASH (36) | |
302 | #define SYMBOL_UNDERLINE (37) | |
8f54dd4f | 303 | #define SYMBOL_DOT (38) |
cb5639cb IY |
304 | |
305 | static u8 display_char2seg7_tbl[]= | |
306 | { | |
307 | SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* 0 */ | |
308 | SEG_B | SEG_C, /* 1 */ | |
309 | SEG_A | SEG_B | SEG_D | SEG_E | SEG_G, /* 2 */ | |
310 | SEG_A | SEG_B | SEG_C | SEG_D | SEG_G, /* 3 */ | |
311 | SEG_B | SEG_C | SEG_F | SEG_G, /* 4 */ | |
312 | SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* 5 */ | |
313 | SEG_A | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 6 */ | |
314 | SEG_A | SEG_B | SEG_C, /* 7 */ | |
315 | SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* 8 */ | |
316 | SEG_A | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* 9 */ | |
317 | SEG_A | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* A */ | |
318 | SEG_C | SEG_D | SEG_E | SEG_F | SEG_G, /* b */ | |
319 | SEG_A | SEG_D | SEG_E | SEG_F, /* C */ | |
320 | SEG_B | SEG_C | SEG_D | SEG_E | SEG_G, /* d */ | |
321 | SEG_A | SEG_D | SEG_E | SEG_F | SEG_G, /* E */ | |
322 | SEG_A | SEG_E | SEG_F | SEG_G, /* F */ | |
8f54dd4f | 323 | 0, /* g - not displayed */ |
cb5639cb | 324 | SEG_B | SEG_C | SEG_E | SEG_F | SEG_G, /* H */ |
8f54dd4f IY |
325 | SEG_B | SEG_C, /* I */ |
326 | 0, /* J - not displayed */ | |
327 | 0, /* K - not displayed */ | |
cb5639cb | 328 | SEG_D | SEG_E | SEG_F, /* L */ |
8f54dd4f IY |
329 | 0, /* m - not displayed */ |
330 | 0, /* n - not displayed */ | |
331 | SEG_A | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* O */ | |
cb5639cb | 332 | SEG_A | SEG_B | SEG_E | SEG_F | SEG_G, /* P */ |
8f54dd4f IY |
333 | 0, /* q - not displayed */ |
334 | 0, /* r - not displayed */ | |
cb5639cb IY |
335 | SEG_A | SEG_C | SEG_D | SEG_F | SEG_G, /* S */ |
336 | SEG_D | SEG_E | SEG_F | SEG_G, /* t */ | |
337 | SEG_B | SEG_C | SEG_D | SEG_E | SEG_F, /* U */ | |
8f54dd4f IY |
338 | 0, /* V - not displayed */ |
339 | 0, /* w - not displayed */ | |
340 | 0, /* X - not displayed */ | |
cb5639cb | 341 | SEG_B | SEG_C | SEG_D | SEG_F | SEG_G, /* Y */ |
8f54dd4f | 342 | 0, /* Z - not displayed */ |
cb5639cb | 343 | SEG_G, /* - */ |
8f54dd4f IY |
344 | SEG_D, /* _ */ |
345 | SEG_P /* . */ | |
cb5639cb IY |
346 | }; |
347 | ||
348 | /* Convert char to the LED segments representation */ | |
349 | static u8 display_char2seg7(char c) | |
350 | { | |
351 | u8 val = 0; | |
352 | ||
353 | if (c >= '0' && c <= '9') | |
354 | c -= '0'; | |
355 | else if (c >= 'a' && c <= 'z') | |
356 | c -= 'a' - 10; | |
357 | else if (c >= 'A' && c <= 'Z') | |
358 | c -= 'A' - 10; | |
359 | else if (c == '-') | |
360 | c = SYMBOL_DASH; | |
8f54dd4f | 361 | else if (c == '_') |
cb5639cb | 362 | c = SYMBOL_UNDERLINE; |
8f54dd4f IY |
363 | else if (c == '.') |
364 | c = SYMBOL_DOT; | |
cb5639cb IY |
365 | else |
366 | c = ' '; /* display unsupported symbols as space */ | |
367 | ||
368 | if (c != ' ') | |
369 | val = display_char2seg7_tbl[(int)c]; | |
370 | ||
cb5639cb IY |
371 | return val; |
372 | } | |
373 | ||
8f54dd4f | 374 | int display_putc(char c) |
cb5639cb IY |
375 | { |
376 | if (display_putc_pos >= DISPLAY_BUF_SIZE) | |
377 | return -1; | |
378 | ||
379 | display_buf[display_putc_pos++] = display_char2seg7(c); | |
380 | /* one-symbol message should be steady */ | |
381 | if (display_putc_pos == 1) | |
382 | display_buf[display_putc_pos] = display_char2seg7(c); | |
383 | ||
384 | return c; | |
385 | } | |
386 | ||
cb5639cb | 387 | /* |
92d1a400 IY |
388 | * Flush current symbol to the LED display hardware |
389 | */ | |
390 | static inline void display_flush(void) | |
391 | { | |
392 | u32 val = display_buf[display_out_pos]; | |
393 | ||
394 | val |= (val << 8) | (val << 16) | (val << 24); | |
395 | out_be32((void *)CONFIG_SYS_DISP_CHR_RAM, val); | |
396 | } | |
397 | ||
398 | /* | |
399 | * Output contents of the software display buffer to the LED display every 0.5s | |
cb5639cb IY |
400 | */ |
401 | void board_show_activity(ulong timestamp) | |
402 | { | |
403 | static ulong last; | |
404 | static u8 once; | |
cb5639cb IY |
405 | |
406 | if (!once || (timestamp - last >= (CONFIG_SYS_HZ / 2))) { | |
92d1a400 | 407 | display_flush(); |
cb5639cb IY |
408 | display_out_pos ^= 1; |
409 | last = timestamp; | |
410 | once = 1; | |
411 | } | |
412 | } | |
413 | ||
414 | /* | |
415 | * Empty fake function | |
416 | */ | |
417 | void show_activity(int arg) | |
418 | { | |
419 | } | |
420 | #endif | |
92d1a400 IY |
421 | #if defined (CONFIG_SHOW_BOOT_PROGRESS) |
422 | static int a4m072_status2code(int status, char *buf) | |
423 | { | |
424 | char c = 0; | |
425 | ||
426 | if (((status > 0) && (status <= 8)) || | |
427 | ((status >= 100) && (status <= 108)) || | |
428 | ((status < 0) && (status >= -9)) || | |
429 | (status == -100) || (status == -101) || | |
430 | ((status <= -103) && (status >= -113))) { | |
431 | c = '5'; | |
432 | } else if (((status >= 9) && (status <= 14)) || | |
433 | ((status >= 120) && (status <= 123)) || | |
434 | ((status >= 125) && (status <= 129)) || | |
435 | ((status >= -13) && (status <= -10)) || | |
436 | (status == -120) || (status == -122) || | |
437 | ((status <= -124) && (status >= -127)) || | |
438 | (status == -129)) { | |
439 | c = '8'; | |
440 | } else if (status == 15) { | |
441 | c = '9'; | |
442 | } else if ((status <= -30) && (status >= -32)) { | |
443 | c = 'A'; | |
444 | } else if (((status <= -35) && (status >= -40)) || | |
445 | ((status <= -42) && (status >= -51)) || | |
446 | ((status <= -53) && (status >= -58)) || | |
447 | (status == -64) || | |
448 | ((status <= -80) && (status >= -83)) || | |
449 | (status == -130) || (status == -140) || | |
450 | (status == -150)) { | |
451 | c = 'B'; | |
452 | } | |
453 | ||
454 | if (c == 0) | |
455 | return -EINVAL; | |
456 | ||
457 | buf[0] = (status < 0) ? '-' : c; | |
458 | buf[1] = c; | |
459 | ||
460 | return 0; | |
461 | } | |
462 | ||
463 | void show_boot_progress(int status) | |
464 | { | |
465 | char buf[2]; | |
466 | ||
467 | if (a4m072_status2code(status, buf) < 0) | |
468 | return; | |
469 | ||
8f54dd4f IY |
470 | display_putc(buf[0]); |
471 | display_putc(buf[1]); | |
92d1a400 IY |
472 | display_set(DISPLAY_HOME); |
473 | display_out_pos = 0; /* reset output position */ | |
474 | ||
475 | /* we want to flush status 15 now */ | |
578ac1e9 | 476 | if (status == BOOTSTAGE_ID_RUN_OS) |
92d1a400 IY |
477 | display_flush(); |
478 | } | |
479 | #endif |