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aebf00fc MS |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Michael Schwingen, michael@schwingen.org | |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
7 | * | |
8 | * (C) Copyright 2002 | |
9 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
10 | * | |
11 | * (C) Copyright 2002 | |
12 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
13 | * Marius Groeger <mgroeger@sysgo.de> | |
14 | * | |
1a459660 | 15 | * SPDX-License-Identifier: GPL-2.0+ |
aebf00fc MS |
16 | */ |
17 | ||
18 | #include <common.h> | |
19 | #include <command.h> | |
20 | #include <malloc.h> | |
21 | #include <asm/arch/ixp425.h> | |
22 | #include <asm/io.h> | |
23 | ||
24 | #include <miiphy.h> | |
25 | ||
26 | #include "actux2_hw.h" | |
27 | ||
28 | DECLARE_GLOBAL_DATA_PTR; | |
29 | ||
af050485 MS |
30 | int board_early_init_f(void) |
31 | { | |
32 | /* CS1: IPAC-X */ | |
33 | writel(0x94d10013, IXP425_EXP_CS1); | |
34 | /* CS5: Debug port */ | |
35 | writel(0x9d520003, IXP425_EXP_CS5); | |
36 | /* CS6: HW release register */ | |
37 | writel(0x81860001, IXP425_EXP_CS6); | |
38 | /* CS7: LEDs */ | |
39 | writel(0x80900003, IXP425_EXP_CS7); | |
40 | ||
41 | return 0; | |
42 | } | |
43 | ||
44 | int board_init(void) | |
aebf00fc | 45 | { |
aebf00fc MS |
46 | /* adress of boot parameters */ |
47 | gd->bd->bi_boot_params = 0x00000100; | |
48 | ||
af050485 MS |
49 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); |
50 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST); | |
51 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR); | |
52 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD); | |
aebf00fc | 53 | |
af050485 MS |
54 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); |
55 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST); | |
aebf00fc | 56 | |
af050485 MS |
57 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR); |
58 | GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD); | |
aebf00fc | 59 | |
af050485 MS |
60 | /* Setup GPIOs for Interrupt inputs */ |
61 | GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT); | |
62 | GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT); | |
aebf00fc | 63 | |
af050485 MS |
64 | /* Setup GPIOs for 33MHz clock output */ |
65 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); | |
66 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); | |
67 | writel(0x011001FF, IXP425_GPIO_GPCLKR); | |
aebf00fc | 68 | |
af050485 MS |
69 | udelay(533); |
70 | GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); | |
71 | GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST); | |
aebf00fc | 72 | |
af050485 MS |
73 | ACTUX2_LED1(1); |
74 | ACTUX2_LED2(0); | |
75 | ACTUX2_LED3(0); | |
76 | ACTUX2_LED4(0); | |
aebf00fc MS |
77 | |
78 | return 0; | |
79 | } | |
80 | ||
81 | /* | |
82 | * Check Board Identity | |
83 | */ | |
af050485 | 84 | int checkboard(void) |
aebf00fc | 85 | { |
f0c0b3a9 WD |
86 | char buf[64]; |
87 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
aebf00fc | 88 | |
af050485 MS |
89 | puts("Board: AcTux-2 rev."); |
90 | putc(ACTUX2_BOARDREL + 'A' - 1); | |
c9bcf75f | 91 | |
f0c0b3a9 WD |
92 | if (i > 0) { |
93 | puts(", serial# "); | |
94 | puts(buf); | |
c9bcf75f | 95 | } |
af050485 | 96 | putc('\n'); |
aebf00fc | 97 | |
af050485 | 98 | return 0; |
aebf00fc MS |
99 | } |
100 | ||
af050485 | 101 | int dram_init(void) |
aebf00fc | 102 | { |
af050485 MS |
103 | gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); |
104 | return 0; | |
aebf00fc MS |
105 | } |
106 | ||
107 | /************************************************************************* | |
108 | * get_board_rev() - setup to pass kernel board revision information | |
109 | * 0 = reserved | |
110 | * 1 = Rev. A | |
111 | * 2 = Rev. B | |
112 | *************************************************************************/ | |
af050485 | 113 | u32 get_board_rev(void) |
aebf00fc MS |
114 | { |
115 | return ACTUX2_BOARDREL; | |
116 | } | |
117 | ||
af050485 | 118 | void reset_phy(void) |
aebf00fc | 119 | { |
aebf00fc | 120 | /* init IcPlus IP175C ethernet switch to native IP175C mode */ |
af050485 | 121 | miiphy_write("NPE0", 29, 31, 0x175C); |
aebf00fc | 122 | } |