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bc24345e MS |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Michael Schwingen, michael@schwingen.org | |
4 | * | |
5 | * (C) Copyright 2006 | |
6 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
7 | * | |
8 | * (C) Copyright 2002 | |
9 | * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net | |
10 | * | |
11 | * (C) Copyright 2002 | |
12 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
13 | * Marius Groeger <mgroeger@sysgo.de> | |
14 | * | |
1a459660 | 15 | * SPDX-License-Identifier: GPL-2.0+ |
bc24345e MS |
16 | */ |
17 | ||
18 | #include <common.h> | |
19 | #include <command.h> | |
20 | #include <malloc.h> | |
21 | #include <asm/arch/ixp425.h> | |
22 | #include <asm/io.h> | |
bc24345e | 23 | #include <miiphy.h> |
bc24345e MS |
24 | #include "actux3_hw.h" |
25 | ||
26 | DECLARE_GLOBAL_DATA_PTR; | |
27 | ||
8b5ab4c1 MS |
28 | int board_early_init_f(void) |
29 | { | |
30 | /* CS1: IPAC-X */ | |
31 | writel(0x94d10013, IXP425_EXP_CS1); | |
32 | /* CS5: Debug port */ | |
33 | writel(0x9d520003, IXP425_EXP_CS5); | |
34 | /* CS6: Release/Option register */ | |
35 | writel(0x81860001, IXP425_EXP_CS6); | |
36 | /* CS7: LEDs */ | |
37 | writel(0x80900003, IXP425_EXP_CS7); | |
38 | ||
39 | return 0; | |
40 | } | |
41 | ||
42 | int board_init(void) | |
bc24345e | 43 | { |
bc24345e MS |
44 | /* adress of boot parameters */ |
45 | gd->bd->bi_boot_params = 0x00000100; | |
46 | ||
8b5ab4c1 MS |
47 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_IORST); |
48 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_ETHRST); | |
49 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DSR); | |
50 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DCD); | |
51 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED5_GN); | |
52 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_RT); | |
53 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_LED6_GN); | |
bc24345e | 54 | |
8b5ab4c1 MS |
55 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_IORST); |
56 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_ETHRST); | |
bc24345e | 57 | |
8b5ab4c1 MS |
58 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DSR); |
59 | GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_DCD); | |
bc24345e | 60 | |
8b5ab4c1 MS |
61 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED5_GN); |
62 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_RT); | |
63 | GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_LED6_GN); | |
bc24345e MS |
64 | |
65 | /* | |
66 | * Setup GPIO's for Interrupt inputs | |
67 | */ | |
8b5ab4c1 MS |
68 | GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DBGINT); |
69 | GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_ETHINT); | |
bc24345e MS |
70 | |
71 | /* | |
72 | * Setup GPIO's for 33MHz clock output | |
73 | */ | |
8b5ab4c1 MS |
74 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK); |
75 | GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK); | |
76 | writel(0x011001FF, IXP425_GPIO_GPCLKR); | |
77 | ||
78 | /* we need a minimum PCI reset pulse width after enabling the clock */ | |
79 | udelay(533); | |
80 | GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_IORST); | |
81 | GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_ETHRST); | |
82 | ||
83 | ACTUX3_LED1_RT(1); | |
84 | ACTUX3_LED1_GN(0); | |
85 | ACTUX3_LED2_RT(0); | |
86 | ACTUX3_LED2_GN(0); | |
87 | ACTUX3_LED3_RT(0); | |
88 | ACTUX3_LED3_GN(0); | |
89 | ACTUX3_LED4_GN(0); | |
90 | ACTUX3_LED5_RT(0); | |
bc24345e MS |
91 | |
92 | return 0; | |
93 | } | |
94 | ||
95 | /* | |
96 | * Check Board Identity | |
97 | */ | |
8b5ab4c1 | 98 | int checkboard(void) |
bc24345e | 99 | { |
f0c0b3a9 WD |
100 | char buf[64]; |
101 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
bc24345e | 102 | |
8b5ab4c1 MS |
103 | puts("Board: AcTux-3 rev."); |
104 | putc(ACTUX3_BOARDREL + 'A' - 1); | |
bc24345e | 105 | |
f0c0b3a9 | 106 | if (i > 0) { |
bc24345e | 107 | puts (", serial# "); |
f0c0b3a9 | 108 | puts (buf); |
bc24345e | 109 | } |
8b5ab4c1 | 110 | putc('\n'); |
bc24345e | 111 | |
8b5ab4c1 | 112 | return 0; |
bc24345e MS |
113 | } |
114 | ||
115 | /************************************************************************* | |
116 | * get_board_rev() - setup to pass kernel board revision information | |
117 | * 0 = reserved | |
118 | * 1 = Rev. A | |
119 | * 2 = Rev. B | |
120 | *************************************************************************/ | |
8b5ab4c1 | 121 | u32 get_board_rev(void) |
bc24345e MS |
122 | { |
123 | return ACTUX3_BOARDREL; | |
124 | } | |
125 | ||
8b5ab4c1 | 126 | int dram_init(void) |
bc24345e | 127 | { |
8b5ab4c1 MS |
128 | gd->ram_size = get_ram_size(CONFIG_SYS_SDRAM_BASE, 128<<20); |
129 | return 0; | |
bc24345e MS |
130 | } |
131 | ||
8b5ab4c1 | 132 | void reset_phy(void) |
bc24345e MS |
133 | { |
134 | int i; | |
135 | ||
136 | /* initialize the PHY */ | |
8b5ab4c1 | 137 | miiphy_reset("NPE0", CONFIG_PHY_ADDR); |
bc24345e MS |
138 | |
139 | /* all LED outputs = Link/Act */ | |
8b5ab4c1 | 140 | miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA); |
bc24345e MS |
141 | |
142 | /* | |
143 | * The Marvell 88E6060 switch comes up with all ports disabled. | |
144 | * set all ethernet switch ports to forwarding state | |
145 | */ | |
146 | for (i = 1; i <= 5; i++) | |
8b5ab4c1 | 147 | miiphy_write("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03); |
bc24345e MS |
148 | |
149 | } |