[thirdparty/u-boot.git] / board / advantech / imx8qm_dmsse20_a1 / spl.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Copyright 2017-2018 NXP
 * Copyright 2019-2023 Kococonnector GmbH
 */
#include <common.h>
#include <dm.h>
#include <spl.h>
#include <init.h>

#include <asm/io.h>
#include <asm/gpio.h>
#include <asm/arch/clock.h>
#include <firmware/imx/sci/sci.h>
#include <asm/arch/imx8-pins.h>
#include <asm/arch/iomux.h>
#include <fsl_esdhc_imx.h>

DECLARE_GLOBAL_DATA_PTR;

#define ESDHC_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))

#define ESDHC_CLK_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))

#define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | \
		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
		(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))

#define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
		(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | \
		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))

#define FSPI_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))

#define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | \
		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))

#define I2C_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
		(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | \
		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))

#define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
		(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
		(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
		(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
#ifdef CONFIG_FSL_ESDHC_IMX

#define USDHC1_CD_GPIO	IMX_GPIO_NR(5, 22)
#define USDHC2_CD_GPIO	IMX_GPIO_NR(4, 12)

static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
	{USDHC1_BASE_ADDR, 0, 8},
	{USDHC3_BASE_ADDR, 0, 4},
};

static iomux_cfg_t emmc0[] = {
	SC_P_EMMC0_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
	SC_P_EMMC0_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_EMMC0_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_EMMC0_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_EMMC0_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_EMMC0_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_EMMC0_DATA4 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_EMMC0_DATA5 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_EMMC0_DATA6 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_EMMC0_DATA7 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_EMMC0_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_EMMC0_STROBE | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
};

static iomux_cfg_t usdhc2_sd[] = {
	SC_P_USDHC2_CLK | MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
	SC_P_USDHC2_CMD | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_USDHC2_DATA0 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_USDHC2_DATA1 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_USDHC2_DATA2 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_USDHC2_DATA3 | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_USDHC2_RESET_B | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_USDHC2_WP   | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	SC_P_USDHC2_CD_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(ESDHC_PAD_CTRL),
};

void init_clk_usdhc(u32 index);

int board_mmc_init(struct bd_info *bis)
{
	int i, ret;

	/*
	 * According to the board_mmc_init() the following map is done:
	 * (U-Boot device node)    (Physical Port)
	 * mmc0                    USDHC1
	 * mmc1                    USDHC2
	 * mmc2                    USDHC3
	 */
	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
		switch (i) {
		case 0:
			ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
			if (ret != SC_ERR_NONE)
				return ret;

			imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
			init_clk_usdhc(0);
			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
			break;
		case 1:
			ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
			if (ret != SC_ERR_NONE)
				return ret;
			ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
			if (ret != SC_ERR_NONE)
				return ret;

			imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
			init_clk_usdhc(2);
			usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
			gpio_request(USDHC2_CD_GPIO, "sd2_cd");
			gpio_direction_input(USDHC2_CD_GPIO);
			break;
		default:
			printf("Warning: you configured more USDHC controllers"
				"(%d) than supported by the board\n", i + 1);
			return 0;
		}
		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
		if (ret) {
			printf("Warning: failed to initialize mmc dev %d\n", i);
			return ret;
		}
	}

	return 0;
}

int board_mmc_getcd(struct mmc *mmc)
{
	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
	int ret = 0;

	switch (cfg->esdhc_base) {
	case USDHC1_BASE_ADDR:
		ret = 1;
		break;
	case USDHC2_BASE_ADDR:
		ret = !gpio_get_value(USDHC1_CD_GPIO);
		break;
	case USDHC3_BASE_ADDR:
		ret = !gpio_get_value(USDHC2_CD_GPIO);
		break;
	}

	return ret;
}

#endif /* CONFIG_FSL_ESDHC_IMX */

void spl_board_init(void)
{
#if defined(CONFIG_SPL_SPI_SUPPORT)
	if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
		if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
			puts("Warning: failed to initialize FSPI0\n");
		}
	}
#endif

	puts("Normal Boot\n");
}

void spl_board_prepare_for_boot(void)
{
#if defined(CONFIG_SPL_SPI_SUPPORT)
	if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
		if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
			puts("Warning: failed to turn off FSPI0\n");
		}
	}
#endif
}

#ifdef CONFIG_SPL_LOAD_FIT
int board_fit_config_name_match(const char *name)
{
	/* Just empty function now - can't decide what to choose */
	debug("%s: %s\n", __func__, name);

	return 0;
}
#endif

void board_init_f(ulong dummy)
{
	/* Clear global data */
	memset((void *)gd, 0, sizeof(gd_t));

	arch_cpu_init();

	board_early_init_f();

	timer_init();

	preloader_console_init();

	/* Clear the BSS. */
	memset(__bss_start, 0, __bss_end - __bss_start);

	board_init_r(NULL, 0);
}
Commit	Line	Data
3bc6257e OG	1	// SPDX-License-Identifier: GPL-2.0-or-later
	2	/*
	3	* Copyright 2017-2018 NXP
	4	* Copyright 2019-2023 Kococonnector GmbH
	5	*/
	6	#include <common.h>
	7	#include <dm.h>
	8	#include <spl.h>
	9	#include <init.h>
	10
	11	#include <asm/io.h>
	12	#include <asm/gpio.h>
	13	#include <asm/arch/clock.h>
99ac6c76	14	#include <firmware/imx/sci/sci.h>
3bc6257e OG	15	#include <asm/arch/imx8-pins.h>
	16	#include <asm/arch/iomux.h>
	17	#include <fsl_esdhc_imx.h>
	18
	19	DECLARE_GLOBAL_DATA_PTR;
	20
	21	#define ESDHC_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) \| \
	22	(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \| \
	23	(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) \| \
	24	(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
	25
	26	#define ESDHC_CLK_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) \| \
	27	(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \| \
	28	(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) \| \
	29	(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
	30
	31	#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) \| \
	32	(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \| \
	33	(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) \| \
	34	(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
	35
	36	#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) \| \
	37	(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \| \
	38	(SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) \| \
	39	(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
	40
	41	#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) \| \
	42	(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \| \
	43	(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) \| \
	44	(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
	45
	46	#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) \| \
	47	(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \| \
	48	(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) \| \
	49	(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
	50
	51	#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) \| \
	52	(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \| \
	53	(SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) \| \
	54	(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
	55
	56	#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) \| \
	57	(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \| \
	58	(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) \| \
	59	(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
	60	#ifdef CONFIG_FSL_ESDHC_IMX
	61
	62	#define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22)
	63	#define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
	64
	65	static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = {
	66	{USDHC1_BASE_ADDR, 0, 8},
	67	{USDHC3_BASE_ADDR, 0, 4},
	68	};
	69
	70	static iomux_cfg_t emmc0[] = {
	71	SC_P_EMMC0_CLK \| MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
	72	SC_P_EMMC0_CMD \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	73	SC_P_EMMC0_DATA0 \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	74	SC_P_EMMC0_DATA1 \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	75	SC_P_EMMC0_DATA2 \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	76	SC_P_EMMC0_DATA3 \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	77	SC_P_EMMC0_DATA4 \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
	78	SC_P_EMMC0_DATA5 \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
79	SC_P_EMMC0_DATA6 \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
80	SC_P_EMMC0_DATA7 \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
81	SC_P_EMMC0_RESET_B \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
82	SC_P_EMMC0_STROBE \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
83	};
84
85	static iomux_cfg_t usdhc2_sd[] = {
86	SC_P_USDHC2_CLK \| MUX_PAD_CTRL(ESDHC_CLK_PAD_CTRL),
87	SC_P_USDHC2_CMD \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
88	SC_P_USDHC2_DATA0 \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
89	SC_P_USDHC2_DATA1 \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
90	SC_P_USDHC2_DATA2 \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
91	SC_P_USDHC2_DATA3 \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
92	SC_P_USDHC2_RESET_B \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
93	SC_P_USDHC2_WP \| MUX_MODE_ALT(3) \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
94	SC_P_USDHC2_CD_B \| MUX_MODE_ALT(3) \| MUX_PAD_CTRL(ESDHC_PAD_CTRL),
95	};
96
97	void init_clk_usdhc(u32 index);
98
99	int board_mmc_init(struct bd_info *bis)
100	{
101	int i, ret;
102
103	/*
104	* According to the board_mmc_init() the following map is done:
105	* (U-Boot device node) (Physical Port)
106	* mmc0 USDHC1
107	* mmc1 USDHC2
108	* mmc2 USDHC3
109	*/
110	for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) {
111	switch (i) {
112	case 0:
113	ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON);
114	if (ret != SC_ERR_NONE)
115	return ret;
116
117	imx8_iomux_setup_multiple_pads(emmc0, ARRAY_SIZE(emmc0));
118	init_clk_usdhc(0);
119	usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
120	break;
121	case 1:
122	ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_2, SC_PM_PW_MODE_ON);
123	if (ret != SC_ERR_NONE)
124	return ret;
125	ret = sc_pm_set_resource_power_mode(-1, SC_R_GPIO_4, SC_PM_PW_MODE_ON);
126	if (ret != SC_ERR_NONE)
127	return ret;
128
129	imx8_iomux_setup_multiple_pads(usdhc2_sd, ARRAY_SIZE(usdhc2_sd));
130	init_clk_usdhc(2);
131	usdhc_cfg[i].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
132	gpio_request(USDHC2_CD_GPIO, "sd2_cd");
133	gpio_direction_input(USDHC2_CD_GPIO);
134	break;
135	default:
136	printf("Warning: you configured more USDHC controllers"
137	"(%d) than supported by the board\n", i + 1);
138	return 0;
139	}
140	ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
141	if (ret) {
142	printf("Warning: failed to initialize mmc dev %d\n", i);
143	return ret;
144	}
145	}
146
147	return 0;
148	}
149
150	int board_mmc_getcd(struct mmc *mmc)
151	{
152	struct fsl_esdhc_cfg cfg = (struct fsl_esdhc_cfg )mmc->priv;
153	int ret = 0;
154
155	switch (cfg->esdhc_base) {
156	case USDHC1_BASE_ADDR:
157	ret = 1;
158	break;
159	case USDHC2_BASE_ADDR:
160	ret = !gpio_get_value(USDHC1_CD_GPIO);
161	break;
162	case USDHC3_BASE_ADDR:
163	ret = !gpio_get_value(USDHC2_CD_GPIO);
164	break;
165	}
166
167	return ret;
168	}
169
170	#endif /* CONFIG_FSL_ESDHC_IMX */
171
172	void spl_board_init(void)
173	{
174	#if defined(CONFIG_SPL_SPI_SUPPORT)
175	if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
176	if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_ON)) {
177	puts("Warning: failed to initialize FSPI0\n");
178	}
179	}
180	#endif
181
182	puts("Normal Boot\n");
183	}
184
185	void spl_board_prepare_for_boot(void)
186	{
187	#if defined(CONFIG_SPL_SPI_SUPPORT)
188	if (sc_rm_is_resource_owned(-1, SC_R_FSPI_0)) {
189	if (sc_pm_set_resource_power_mode(-1, SC_R_FSPI_0, SC_PM_PW_MODE_OFF)) {
190	puts("Warning: failed to turn off FSPI0\n");
191	}
192	}
193	#endif
194	}
195
196	#ifdef CONFIG_SPL_LOAD_FIT
197	int board_fit_config_name_match(const char *name)
198	{
199	/* Just empty function now - can't decide what to choose */
200	debug("%s: %s\n", __func__, name);
201
202	return 0;
203	}
204	#endif
205
206	void board_init_f(ulong dummy)
207	{
208	/* Clear global data */
209	memset((void *)gd, 0, sizeof(gd_t));
210
211	arch_cpu_init();
212
213	board_early_init_f();
214
215	timer_init();
216
217	preloader_console_init();
218
219	/* Clear the BSS. */
220	memset(__bss_start, 0, __bss_end - __bss_start);
221
222	board_init_r(NULL, 0);
223	}