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Commit | Line | Data |
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16c0cc1c SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
16c0cc1c SR |
6 | */ |
7 | ||
8 | #include <common.h> | |
9 | #include <asm/processor.h> | |
b36df561 | 10 | #include <asm/ppc405.h> |
16c0cc1c SR |
11 | |
12 | /* test-only: move into cpu directory!!! */ | |
13 | ||
14 | #if defined(PLLMR0_200_133_66) | |
15 | void board_pll_init_f(void) | |
16 | { | |
17 | /* | |
18 | * set PLL clocks based on input sysclk is 33M | |
19 | * | |
20 | * ---------------------------------- | |
21 | * | CLK | FREQ (MHz) | DIV RATIO | | |
22 | * ---------------------------------- | |
23 | * | CPU | 200.0 | 4 (0x02)| | |
24 | * | PLB | 133.3 | 6 (0x06)| | |
25 | * | OPB | 66.6 | 12 (0x0C)| | |
26 | * | EBC | 66.6 | 12 (0x0C)| | |
27 | * | SPI | 66.6 | 12 (0x0C)| | |
28 | * | UART0 | 10.0 | 40 (0x28)| | |
29 | * | UART1 | 10.0 | 40 (0x28)| | |
30 | * | DAC | 2.0 | 200 (0xC8)| | |
31 | * | ADC | 2.0 | 200 (0xC8)| | |
32 | * | PWM | 100.0 | 4 (0x04)| | |
33 | * | EMAC | 25.0 | 16 (0x10)| | |
34 | * ----------------------------------- | |
35 | */ | |
36 | ||
37 | /* Initialize PLL */ | |
d1c3b275 SR |
38 | mtcpr(CPR0_PLLC, 0x0000033c); |
39 | mtcpr(CPR0_PLLD, 0x0c010200); | |
afabb498 SR |
40 | mtcpr(CPR0_PRIMAD, 0x04060c0c); |
41 | mtcpr(CPR0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ | |
42 | mtcpr(CPR0_CLKUPD, 0x40000000); | |
16c0cc1c SR |
43 | } |
44 | ||
45 | #elif defined(PLLMR0_266_160_80) | |
46 | ||
47 | void board_pll_init_f(void) | |
48 | { | |
49 | /* | |
50 | * set PLL clocks based on input sysclk is 33M | |
51 | * | |
52 | * ---------------------------------- | |
53 | * | CLK | FREQ (MHz) | DIV RATIO | | |
54 | * ---------------------------------- | |
55 | * | CPU | 266.64 | 3 | | |
56 | * | PLB | 159.98 | 5 (0x05)| | |
57 | * | OPB | 79.99 | 10 (0x0A)| | |
58 | * | EBC | 79.99 | 10 (0x0A)| | |
59 | * | SPI | 79.99 | 10 (0x0A)| | |
60 | * | UART0 | 28.57 | 7 (0x07)| | |
61 | * | UART1 | 28.57 | 7 (0x07)| | |
62 | * | DAC | 28.57 | 7 (0xA7)| | |
3cb86f3e | 63 | * | ADC | 4 | 50 (0x32)| |
16c0cc1c SR |
64 | * | PWM | 28.57 | 7 (0x07)| |
65 | * | EMAC | 4 | 50 (0x32)| | |
66 | * ----------------------------------- | |
67 | */ | |
68 | ||
69 | /* Initialize PLL */ | |
d1c3b275 SR |
70 | mtcpr(CPR0_PLLC, 0x20000238); |
71 | mtcpr(CPR0_PLLD, 0x03010400); | |
afabb498 SR |
72 | mtcpr(CPR0_PRIMAD, 0x03050a0a); |
73 | mtcpr(CPR0_PERC0, 0x00000000); | |
74 | mtcpr(CPR0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ | |
75 | mtcpr(CPR0_PERD1, 0x07323200); | |
d1c3b275 | 76 | mtcpr(CPR0_CLKUP, 0x40000000); |
16c0cc1c SR |
77 | } |
78 | ||
79 | #elif defined(PLLMR0_333_166_83) | |
80 | ||
81 | void board_pll_init_f(void) | |
82 | { | |
83 | /* | |
84 | * set PLL clocks based on input sysclk is 33M | |
85 | * | |
86 | * ---------------------------------- | |
87 | * | CLK | FREQ (MHz) | DIV RATIO | | |
88 | * ---------------------------------- | |
89 | * | CPU | 333.33 | 2 | | |
90 | * | PLB | 166.66 | 4 (0x04)| | |
91 | * | OPB | 83.33 | 8 (0x08)| | |
92 | * | EBC | 83.33 | 8 (0x08)| | |
93 | * | SPI | 83.33 | 8 (0x08)| | |
94 | * | UART0 | 16.66 | 5 (0x05)| | |
95 | * | UART1 | 16.66 | 5 (0x05)| | |
96 | * | DAC | ???? | 166 (0xA6)| | |
97 | * | ADC | ???? | 166 (0xA6)| | |
98 | * | PWM | 41.66 | 3 (0x03)| | |
99 | * | EMAC | ???? | 3 (0x03)| | |
100 | * ----------------------------------- | |
101 | */ | |
102 | ||
103 | /* Initialize PLL */ | |
d1c3b275 SR |
104 | mtcpr(CPR0_PLLC, 0x0000033C); |
105 | mtcpr(CPR0_PLLD, 0x0a010000); | |
afabb498 SR |
106 | mtcpr(CPR0_PRIMAD, 0x02040808); |
107 | mtcpr(CPR0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ | |
108 | mtcpr(CPR0_PERD1, 0xA6A60300); | |
d1c3b275 | 109 | mtcpr(CPR0_CLKUP, 0x40000000); |
16c0cc1c SR |
110 | } |
111 | ||
112 | #elif defined(PLLMR0_100_100_12) | |
113 | ||
114 | void board_pll_init_f(void) | |
115 | { | |
116 | /* | |
117 | * set PLL clocks based on input sysclk is 33M | |
118 | * | |
119 | * ---------------------- | |
120 | * | CLK | FREQ (MHz) | | |
121 | * ---------------------- | |
122 | * | CPU | 100.00 | | |
123 | * | PLB | 100.00 | | |
124 | * | OPB | 12.00 | | |
125 | * | EBC | 49.00 | | |
126 | * ---------------------- | |
127 | */ | |
128 | ||
129 | /* Initialize PLL */ | |
d1c3b275 SR |
130 | mtcpr(CPR0_PLLC, 0x000003BC); |
131 | mtcpr(CPR0_PLLD, 0x06060600); | |
afabb498 SR |
132 | mtcpr(CPR0_PRIMAD, 0x02020004); |
133 | mtcpr(CPR0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ | |
134 | mtcpr(CPR0_PERD1, 0xC8C81600); | |
d1c3b275 | 135 | mtcpr(CPR0_CLKUP, 0x40000000); |
16c0cc1c | 136 | } |
3cb86f3e | 137 | #endif /* CPU_<speed>_405EZ */ |
16c0cc1c SR |
138 | |
139 | #if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) | |
140 | /* | |
141 | * Get timebase clock frequency | |
142 | */ | |
3cb86f3e | 143 | unsigned long get_tbclk(void) |
16c0cc1c SR |
144 | { |
145 | unsigned long cpr_plld; | |
146 | unsigned long cpr_primad; | |
147 | unsigned long primad_cpudv; | |
148 | unsigned long pllFbkDiv; | |
149 | unsigned long freqProcessor; | |
150 | ||
151 | /* | |
152 | * Read PLL Mode registers | |
153 | */ | |
d1c3b275 | 154 | mfcpr(CPR0_PLLD, cpr_plld); |
16c0cc1c SR |
155 | |
156 | /* | |
157 | * Read CPR_PRIMAD register | |
158 | */ | |
afabb498 | 159 | mfcpr(CPR0_PRIMAD, cpr_primad); |
16c0cc1c SR |
160 | |
161 | /* | |
162 | * Determine CPU clock frequency | |
163 | */ | |
164 | primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); | |
165 | if (primad_cpudv == 0) | |
166 | primad_cpudv = 16; | |
167 | ||
168 | /* | |
169 | * Determine FBK_DIV. | |
170 | */ | |
3cb86f3e SR |
171 | pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); |
172 | if (pllFbkDiv == 0) | |
173 | pllFbkDiv = 256; | |
16c0cc1c SR |
174 | |
175 | freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv; | |
176 | ||
177 | return (freqProcessor); | |
178 | } | |
3cb86f3e | 179 | #endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ |