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16c0cc1c SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <asm/processor.h> | |
26 | #include <ppc405.h> | |
27 | ||
28 | /* test-only: move into cpu directory!!! */ | |
29 | ||
30 | #if defined(PLLMR0_200_133_66) | |
31 | void board_pll_init_f(void) | |
32 | { | |
33 | /* | |
34 | * set PLL clocks based on input sysclk is 33M | |
35 | * | |
36 | * ---------------------------------- | |
37 | * | CLK | FREQ (MHz) | DIV RATIO | | |
38 | * ---------------------------------- | |
39 | * | CPU | 200.0 | 4 (0x02)| | |
40 | * | PLB | 133.3 | 6 (0x06)| | |
41 | * | OPB | 66.6 | 12 (0x0C)| | |
42 | * | EBC | 66.6 | 12 (0x0C)| | |
43 | * | SPI | 66.6 | 12 (0x0C)| | |
44 | * | UART0 | 10.0 | 40 (0x28)| | |
45 | * | UART1 | 10.0 | 40 (0x28)| | |
46 | * | DAC | 2.0 | 200 (0xC8)| | |
47 | * | ADC | 2.0 | 200 (0xC8)| | |
48 | * | PWM | 100.0 | 4 (0x04)| | |
49 | * | EMAC | 25.0 | 16 (0x10)| | |
50 | * ----------------------------------- | |
51 | */ | |
52 | ||
53 | /* Initialize PLL */ | |
d1c3b275 SR |
54 | mtcpr(CPR0_PLLC, 0x0000033c); |
55 | mtcpr(CPR0_PLLD, 0x0c010200); | |
56 | mtcpr(CPC0_PRIMAD, 0x04060c0c); | |
57 | mtcpr(CPC0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ | |
58 | mtcpr(CPR0_CLKUP, 0x40000000); | |
16c0cc1c SR |
59 | } |
60 | ||
61 | #elif defined(PLLMR0_266_160_80) | |
62 | ||
63 | void board_pll_init_f(void) | |
64 | { | |
65 | /* | |
66 | * set PLL clocks based on input sysclk is 33M | |
67 | * | |
68 | * ---------------------------------- | |
69 | * | CLK | FREQ (MHz) | DIV RATIO | | |
70 | * ---------------------------------- | |
71 | * | CPU | 266.64 | 3 | | |
72 | * | PLB | 159.98 | 5 (0x05)| | |
73 | * | OPB | 79.99 | 10 (0x0A)| | |
74 | * | EBC | 79.99 | 10 (0x0A)| | |
75 | * | SPI | 79.99 | 10 (0x0A)| | |
76 | * | UART0 | 28.57 | 7 (0x07)| | |
77 | * | UART1 | 28.57 | 7 (0x07)| | |
78 | * | DAC | 28.57 | 7 (0xA7)| | |
3cb86f3e | 79 | * | ADC | 4 | 50 (0x32)| |
16c0cc1c SR |
80 | * | PWM | 28.57 | 7 (0x07)| |
81 | * | EMAC | 4 | 50 (0x32)| | |
82 | * ----------------------------------- | |
83 | */ | |
84 | ||
85 | /* Initialize PLL */ | |
d1c3b275 SR |
86 | mtcpr(CPR0_PLLC, 0x20000238); |
87 | mtcpr(CPR0_PLLD, 0x03010400); | |
88 | mtcpr(CPC0_PRIMAD, 0x03050a0a); | |
89 | mtcpr(CPC0_PERC0, 0x00000000); | |
90 | mtcpr(CPC0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ | |
91 | mtcpr(CPC0_PERD1, 0x07323200); | |
92 | mtcpr(CPR0_CLKUP, 0x40000000); | |
16c0cc1c SR |
93 | } |
94 | ||
95 | #elif defined(PLLMR0_333_166_83) | |
96 | ||
97 | void board_pll_init_f(void) | |
98 | { | |
99 | /* | |
100 | * set PLL clocks based on input sysclk is 33M | |
101 | * | |
102 | * ---------------------------------- | |
103 | * | CLK | FREQ (MHz) | DIV RATIO | | |
104 | * ---------------------------------- | |
105 | * | CPU | 333.33 | 2 | | |
106 | * | PLB | 166.66 | 4 (0x04)| | |
107 | * | OPB | 83.33 | 8 (0x08)| | |
108 | * | EBC | 83.33 | 8 (0x08)| | |
109 | * | SPI | 83.33 | 8 (0x08)| | |
110 | * | UART0 | 16.66 | 5 (0x05)| | |
111 | * | UART1 | 16.66 | 5 (0x05)| | |
112 | * | DAC | ???? | 166 (0xA6)| | |
113 | * | ADC | ???? | 166 (0xA6)| | |
114 | * | PWM | 41.66 | 3 (0x03)| | |
115 | * | EMAC | ???? | 3 (0x03)| | |
116 | * ----------------------------------- | |
117 | */ | |
118 | ||
119 | /* Initialize PLL */ | |
d1c3b275 SR |
120 | mtcpr(CPR0_PLLC, 0x0000033C); |
121 | mtcpr(CPR0_PLLD, 0x0a010000); | |
122 | mtcpr(CPC0_PRIMAD, 0x02040808); | |
123 | mtcpr(CPC0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ | |
124 | mtcpr(CPC0_PERD1, 0xA6A60300); | |
125 | mtcpr(CPR0_CLKUP, 0x40000000); | |
16c0cc1c SR |
126 | } |
127 | ||
128 | #elif defined(PLLMR0_100_100_12) | |
129 | ||
130 | void board_pll_init_f(void) | |
131 | { | |
132 | /* | |
133 | * set PLL clocks based on input sysclk is 33M | |
134 | * | |
135 | * ---------------------- | |
136 | * | CLK | FREQ (MHz) | | |
137 | * ---------------------- | |
138 | * | CPU | 100.00 | | |
139 | * | PLB | 100.00 | | |
140 | * | OPB | 12.00 | | |
141 | * | EBC | 49.00 | | |
142 | * ---------------------- | |
143 | */ | |
144 | ||
145 | /* Initialize PLL */ | |
d1c3b275 SR |
146 | mtcpr(CPR0_PLLC, 0x000003BC); |
147 | mtcpr(CPR0_PLLD, 0x06060600); | |
148 | mtcpr(CPC0_PRIMAD, 0x02020004); | |
149 | mtcpr(CPC0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ | |
150 | mtcpr(CPC0_PERD1, 0xC8C81600); | |
151 | mtcpr(CPR0_CLKUP, 0x40000000); | |
16c0cc1c | 152 | } |
3cb86f3e | 153 | #endif /* CPU_<speed>_405EZ */ |
16c0cc1c SR |
154 | |
155 | #if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) | |
156 | /* | |
157 | * Get timebase clock frequency | |
158 | */ | |
3cb86f3e | 159 | unsigned long get_tbclk(void) |
16c0cc1c SR |
160 | { |
161 | unsigned long cpr_plld; | |
162 | unsigned long cpr_primad; | |
163 | unsigned long primad_cpudv; | |
164 | unsigned long pllFbkDiv; | |
165 | unsigned long freqProcessor; | |
166 | ||
167 | /* | |
168 | * Read PLL Mode registers | |
169 | */ | |
d1c3b275 | 170 | mfcpr(CPR0_PLLD, cpr_plld); |
16c0cc1c SR |
171 | |
172 | /* | |
173 | * Read CPR_PRIMAD register | |
174 | */ | |
d1c3b275 | 175 | mfcpr(CPC0_PRIMAD, cpr_primad); |
16c0cc1c SR |
176 | |
177 | /* | |
178 | * Determine CPU clock frequency | |
179 | */ | |
180 | primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); | |
181 | if (primad_cpudv == 0) | |
182 | primad_cpudv = 16; | |
183 | ||
184 | /* | |
185 | * Determine FBK_DIV. | |
186 | */ | |
3cb86f3e SR |
187 | pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); |
188 | if (pllFbkDiv == 0) | |
189 | pllFbkDiv = 256; | |
16c0cc1c SR |
190 | |
191 | freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv; | |
192 | ||
193 | return (freqProcessor); | |
194 | } | |
3cb86f3e | 195 | #endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ |