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8e1a3fe5 SR |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <ppc_asm.tmpl> | |
25 | #include <config.h> | |
26 | #include <asm-ppc/mmu.h> | |
27 | ||
28 | /************************************************************************** | |
29 | * TLB TABLE | |
30 | * | |
31 | * This table is used by the cpu boot code to setup the initial tlb | |
32 | * entries. Rather than make broad assumptions in the cpu source tree, | |
33 | * this table lets each board set things up however they like. | |
34 | * | |
35 | * Pointer to the table is returned in r1 | |
36 | * | |
37 | *************************************************************************/ | |
38 | .section .bootpg,"ax" | |
39 | .globl tlbtab | |
40 | ||
41 | tlbtab: | |
42 | tlbtab_start | |
43 | ||
44 | /* | |
45 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to | |
46 | * use the speed up boot process. It is patched after relocation to | |
47 | * enable SA_I | |
48 | */ | |
71665ebf | 49 | #ifndef CONFIG_NAND_SPL |
6d0f6bcf | 50 | tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */ |
71665ebf | 51 | #else |
6d0f6bcf JCPV |
52 | tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G) |
53 | tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I) | |
499e7831 | 54 | tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I) |
71665ebf | 55 | #endif |
8e1a3fe5 SR |
56 | |
57 | /* | |
58 | * TLB entries for SDRAM are not needed on this platform. | |
59 | * They are dynamically generated in the SPD DDR(2) detection | |
60 | * routine. | |
61 | */ | |
62 | ||
6d0f6bcf | 63 | #ifdef CONFIG_SYS_INIT_RAM_DCACHE |
8e1a3fe5 | 64 | /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */ |
6d0f6bcf | 65 | tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G) |
8e1a3fe5 SR |
66 | #endif |
67 | ||
6d0f6bcf JCPV |
68 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I) |
69 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I) | |
70 | tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I) | |
8e1a3fe5 | 71 | |
6d0f6bcf JCPV |
72 | tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I) |
73 | tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I) | |
74 | tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I) | |
75 | tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I) | |
8e1a3fe5 SR |
76 | |
77 | /* PCIe UTL register */ | |
6d0f6bcf | 78 | tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I) |
8e1a3fe5 SR |
79 | |
80 | /* TLB-entry for NAND */ | |
6d0f6bcf | 81 | tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I) |
8e1a3fe5 SR |
82 | |
83 | /* TLB-entry for CPLD */ | |
6d0f6bcf | 84 | tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I) |
8e1a3fe5 SR |
85 | |
86 | /* TLB-entry for OCM */ | |
6d0f6bcf | 87 | tlbentry(CONFIG_SYS_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I) |
8e1a3fe5 SR |
88 | |
89 | /* TLB-entry for Local Configuration registers => peripherals */ | |
6d0f6bcf | 90 | tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I) |
8e1a3fe5 | 91 | |
41712b4e | 92 | /* AHB: Internal USB Peripherals (USB, SATA) */ |
6d0f6bcf | 93 | tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I) |
41712b4e | 94 | |
8e1a3fe5 SR |
95 | tlbtab_end |
96 | ||
97 | #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) | |
98 | /* | |
99 | * For NAND booting the first TLB has to be reconfigured to full size | |
100 | * and with caching disabled after running from RAM! | |
101 | */ | |
6d0f6bcf JCPV |
102 | #define TLB00 TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M) |
103 | #define TLB01 TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1) | |
8e1a3fe5 SR |
104 | #define TLB02 TLB2(AC_R|AC_W|AC_X|SA_G|SA_I) |
105 | ||
106 | .globl reconfig_tlb0 | |
107 | reconfig_tlb0: | |
108 | sync | |
109 | isync | |
110 | addi r4,r0,0x0000 /* TLB entry #0 */ | |
111 | lis r5,TLB00@h | |
112 | ori r5,r5,TLB00@l | |
113 | tlbwe r5,r4,0x0000 /* Save it out */ | |
114 | lis r5,TLB01@h | |
115 | ori r5,r5,TLB01@l | |
116 | tlbwe r5,r4,0x0001 /* Save it out */ | |
117 | lis r5,TLB02@h | |
118 | ori r5,r5,TLB02@l | |
119 | tlbwe r5,r4,0x0002 /* Save it out */ | |
120 | sync | |
121 | isync | |
122 | blr | |
123 | #endif |