[people/ms/u-boot.git] / board / amcc / ebony / ebony.c

/*
 *  Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <common.h>
#include <asm/processor.h>
#include <spd_sdram.h>

#define BOOT_SMALL_FLASH	32	/* 00100000 */
#define FLASH_ONBD_N		2	/* 00000010 */
#define FLASH_SRAM_SEL		1	/* 00000001 */

long int fixed_sdram(void);

int board_early_init_f(void)
{
	uint reg;
	unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
	unsigned char status;

	/*--------------------------------------------------------------------
	 * Setup the external bus controller/chip selects
	 *-------------------------------------------------------------------*/
	mtdcr(ebccfga, xbcfg);
	reg = mfdcr(ebccfgd);
	mtdcr(ebccfgd, reg | 0x04000000);	/* Set ATC */

	mtebc(pb1ap, 0x02815480);	/* NVRAM/RTC */
	mtebc(pb1cr, 0x48018000);	/* BA=0x480 1MB R/W 8-bit */
	mtebc(pb7ap, 0x01015280);	/* FPGA registers */
	mtebc(pb7cr, 0x48318000);	/* BA=0x483 1MB R/W 8-bit */

	/* read FPGA_REG0  and set the bus controller */
	status = *fpga_base;
	if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
		mtebc(pb0ap, 0x9b015480);	/* FLASH/SRAM */
		mtebc(pb0cr, 0xfff18000);	/* BAS=0xfff 1MB R/W 8-bit */
		mtebc(pb2ap, 0x9b015480);	/* 4MB FLASH */
		mtebc(pb2cr, 0xff858000);	/* BAS=0xff8 4MB R/W 8-bit */
	} else {
		mtebc(pb0ap, 0x9b015480);	/* 4MB FLASH */
		mtebc(pb0cr, 0xffc58000);	/* BAS=0xffc 4MB R/W 8-bit */

		/* set CS2 if FLASH_ONBD_N == 0 */
		if (!(status & FLASH_ONBD_N)) {
			mtebc(pb2ap, 0x9b015480);	/* FLASH/SRAM */
			mtebc(pb2cr, 0xff818000);	/* BAS=0xff8 4MB R/W 8-bit */
		}
	}

	/*--------------------------------------------------------------------
	 * Setup the interrupt controller polarities, triggers, etc.
	 *-------------------------------------------------------------------*/
	mtdcr(uic0sr, 0xffffffff);	/* clear all */
	mtdcr(uic0er, 0x00000000);	/* disable all */
	mtdcr(uic0cr, 0x00000009);	/* SMI & UIC1 crit are critical */
	mtdcr(uic0pr, 0xfffffe13);	/* per ref-board manual */
	mtdcr(uic0tr, 0x01c00008);	/* per ref-board manual */
	mtdcr(uic0vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(uic0sr, 0xffffffff);	/* clear all */

	mtdcr(uic1sr, 0xffffffff);	/* clear all */
	mtdcr(uic1er, 0x00000000);	/* disable all */
	mtdcr(uic1cr, 0x00000000);	/* all non-critical */
	mtdcr(uic1pr, 0xffffe0ff);	/* per ref-board manual */
	mtdcr(uic1tr, 0x00ffc000);	/* per ref-board manual */
	mtdcr(uic1vr, 0x00000001);	/* int31 highest, base=0x000 */
	mtdcr(uic1sr, 0xffffffff);	/* clear all */

	return 0;
}

int checkboard(void)
{
	char *s = getenv("serial#");

	printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	return (0);
}

long int initdram(int board_type)
{
	long dram_size = 0;

#if defined(CONFIG_SPD_EEPROM)
	dram_size = spd_sdram(0);
#else
	dram_size = fixed_sdram();
#endif
	return dram_size;
}

#if defined(CFG_DRAM_TEST)
int testdram(void)
{
	uint *pstart = (uint *) 0x00000000;
	uint *pend = (uint *) 0x08000000;
	uint *p;

	for (p = pstart; p < pend; p++)
		*p = 0xaaaaaaaa;

	for (p = pstart; p < pend; p++) {
		if (*p != 0xaaaaaaaa) {
			printf("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}

	for (p = pstart; p < pend; p++)
		*p = 0x55555555;

	for (p = pstart; p < pend; p++) {
		if (*p != 0x55555555) {
			printf("SDRAM test fails at: %08x\n", (uint) p);
			return 1;
		}
	}
	return 0;
}
#endif

#if !defined(CONFIG_SPD_EEPROM)
/*************************************************************************
 *  fixed sdram init -- doesn't use serial presence detect.
 *
 *  Assumes:    128 MB, non-ECC, non-registered
 *              PLB @ 133 MHz
 *
 ************************************************************************/
long int fixed_sdram(void)
{
	uint reg;

	/*--------------------------------------------------------------------
	 * Setup some default
	 *------------------------------------------------------------------*/
	mtsdram(mem_uabba, 0x00000000);	/* ubba=0 (default)             */
	mtsdram(mem_slio, 0x00000000);	/* rdre=0 wrre=0 rarw=0         */
	mtsdram(mem_devopt, 0x00000000);	/* dll=0 ds=0 (normal)          */
	mtsdram(mem_wddctr, 0x00000000);	/* wrcp=0 dcd=0                 */
	mtsdram(mem_clktr, 0x40000000);	/* clkp=1 (90 deg wr) dcdt=0    */

	/*--------------------------------------------------------------------
	 * Setup for board-specific specific mem
	 *------------------------------------------------------------------*/
	/*
	 * Following for CAS Latency = 2.5 @ 133 MHz PLB
	 */
	mtsdram(mem_b0cr, 0x000a4001);	/* SDBA=0x000 128MB, Mode 3, enabled */
	mtsdram(mem_tr0, 0x410a4012);	/* WR=2  WD=1 CL=2.5 PA=3 CP=4 LD=2 */
	/* RA=10 RD=3                       */
	mtsdram(mem_tr1, 0x8080082f);	/* SS=T2 SL=STAGE 3 CD=1 CT=0x02f   */
	mtsdram(mem_rtr, 0x08200000);	/* Rate 15.625 ns @ 133 MHz PLB     */
	mtsdram(mem_cfg1, 0x00000000);	/* Self-refresh exit, disable PM    */
	udelay(400);		/* Delay 200 usecs (min)            */

	/*--------------------------------------------------------------------
	 * Enable the controller, then wait for DCEN to complete
	 *------------------------------------------------------------------*/
	mtsdram(mem_cfg0, 0x86000000);	/* DCEN=1, PMUD=1, 64-bit           */
	for (;;) {
		mfsdram(mem_mcsts, reg);
		if (reg & 0x80000000)
			break;
	}

	return (128 * 1024 * 1024);	/* 128 MB                           */
}
#endif				/* !defined(CONFIG_SPD_EEPROM) */

/*************************************************************************
 *  pci_pre_init
 *
 *  This routine is called just prior to registering the hose and gives
 *  the board the opportunity to check things. Returning a value of zero
 *  indicates that things are bad & PCI initialization should be aborted.
 *
 *	Different boards may wish to customize the pci controller structure
 *	(add regions, override default access routines, etc) or perform
 *	certain pre-initialization actions.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
int pci_pre_init(struct pci_controller *hose)
{
	unsigned long strap;

	/*--------------------------------------------------------------------------+
     *	The ebony board is always configured as the host & requires the
     *	PCI arbiter to be enabled.
	 *--------------------------------------------------------------------------*/
	strap = mfdcr(cpc0_strp1);
	if ((strap & 0x00100000) == 0) {
		printf("PCI: CPC0_STRP1[PAE] not set.\n");
		return 0;
	}

	return 1;
}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */

/*************************************************************************
 *  pci_target_init
 *
 *	The bootstrap configuration provides default settings for the pci
 *	inbound map (PIM). But the bootstrap config choices are limited and
 *	may not be sufficient for a given board.
 *
 ************************************************************************/
#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
void pci_target_init(struct pci_controller *hose)
{
	DECLARE_GLOBAL_DATA_PTR;

	/*--------------------------------------------------------------------------+
	 * Disable everything
	 *--------------------------------------------------------------------------*/
	out32r(PCIX0_PIM0SA, 0);	/* disable */
	out32r(PCIX0_PIM1SA, 0);	/* disable */
	out32r(PCIX0_PIM2SA, 0);	/* disable */
	out32r(PCIX0_EROMBA, 0);	/* disable expansion rom */

	/*--------------------------------------------------------------------------+
	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
     * options to not support sizes such as 128/256 MB.
	 *--------------------------------------------------------------------------*/
	out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
	out32r(PCIX0_PIM0LAH, 0);
	out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);

	out32r(PCIX0_BAR0, 0);

	/*--------------------------------------------------------------------------+
	 * Program the board's subsystem id/vendor id
	 *--------------------------------------------------------------------------*/
	out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
	out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);

	out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
}
#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */

/*************************************************************************
 *  is_pci_host
 *
 *	This routine is called to determine if a pci scan should be
 *	performed. With various hardware environments (especially cPCI and
 *	PPMC) it's insufficient to depend on the state of the arbiter enable
 *	bit in the strap register, or generic host/adapter assumptions.
 *
 *	Rather than hard-code a bad assumption in the general 440 code, the
 *	440 pci code requires the board to decide at runtime.
 *
 *	Return 0 for adapter mode, non-zero for host (monarch) mode.
 *
 *
 ************************************************************************/
#if defined(CONFIG_PCI)
int is_pci_host(struct pci_controller *hose)
{
	/* The ebony board is always configured as host. */
	return (1);
}
#endif				/* defined(CONFIG_PCI) */
Commit	Line	Data
c609719b WD	1	/*
	2	* Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com>
	3	*
	4	* See file CREDITS for list of people who contributed to this
	5	* project.
	6	*
	7	* This program is free software; you can redistribute it and/or
	8	* modify it under the terms of the GNU General Public License as
	9	* published by the Free Software Foundation; either version 2 of
	10	* the License, or (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	20	* MA 02111-1307 USA
	21	*/
	22
c609719b	23	#include <common.h>
c609719b	24	#include <asm/processor.h>
db2f721f	25	#include <spd_sdram.h>
c609719b WD	26
	27	#define BOOT_SMALL_FLASH 32 /* 00100000 */
	28	#define FLASH_ONBD_N 2 /* 00000010 */
	29	#define FLASH_SRAM_SEL 1 /* 00000001 */
	30
8a316c9b	31	long int fixed_sdram(void);
c609719b	32
8a316c9b	33	int board_early_init_f(void)
c609719b WD	34	{
c609719b WD	35	uint reg;
8a316c9b	36	unsigned char fpga_base = (unsigned char )CFG_FPGA_BASE;
c609719b WD	37	unsigned char status;
c609719b WD	38
c609719b WD	39	/*--------------------------------------------------------------------
	40	* Setup the external bus controller/chip selects
	41	-------------------------------------------------------------------/
8a316c9b SR	42	mtdcr(ebccfga, xbcfg);
	43	reg = mfdcr(ebccfgd);
	44	mtdcr(ebccfgd, reg \| 0x04000000); /* Set ATC */
c609719b	45
8a316c9b SR	46	mtebc(pb1ap, 0x02815480); /* NVRAM/RTC */
	47	mtebc(pb1cr, 0x48018000); /* BA=0x480 1MB R/W 8-bit */
	48	mtebc(pb7ap, 0x01015280); /* FPGA registers */
	49	mtebc(pb7cr, 0x48318000); /* BA=0x483 1MB R/W 8-bit */
c609719b WD	50
	51	/* read FPGA_REG0 and set the bus controller */
	52	status = *fpga_base;
	53	if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) {
8a316c9b SR	54	mtebc(pb0ap, 0x9b015480); /* FLASH/SRAM */
	55	mtebc(pb0cr, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */
	56	mtebc(pb2ap, 0x9b015480); /* 4MB FLASH */
	57	mtebc(pb2cr, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */
c609719b	58	} else {
8a316c9b SR	59	mtebc(pb0ap, 0x9b015480); /* 4MB FLASH */
8a316c9b SR	60	mtebc(pb0cr, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */
c609719b WD	61
	62	/* set CS2 if FLASH_ONBD_N == 0 */
	63	if (!(status & FLASH_ONBD_N)) {
8a316c9b SR	64	mtebc(pb2ap, 0x9b015480); /* FLASH/SRAM */
8a316c9b SR	65	mtebc(pb2cr, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */
c609719b WD	66	}
	67	}
	68
	69	/*--------------------------------------------------------------------
	70	* Setup the interrupt controller polarities, triggers, etc.
	71	-------------------------------------------------------------------/
8a316c9b SR	72	mtdcr(uic0sr, 0xffffffff); /* clear all */
	73	mtdcr(uic0er, 0x00000000); /* disable all */
	74	mtdcr(uic0cr, 0x00000009); /* SMI & UIC1 crit are critical */
	75	mtdcr(uic0pr, 0xfffffe13); /* per ref-board manual */
	76	mtdcr(uic0tr, 0x01c00008); /* per ref-board manual */
	77	mtdcr(uic0vr, 0x00000001); /* int31 highest, base=0x000 */
	78	mtdcr(uic0sr, 0xffffffff); /* clear all */
	79
	80	mtdcr(uic1sr, 0xffffffff); /* clear all */
	81	mtdcr(uic1er, 0x00000000); /* disable all */
	82	mtdcr(uic1cr, 0x00000000); /* all non-critical */
	83	mtdcr(uic1pr, 0xffffe0ff); /* per ref-board manual */
	84	mtdcr(uic1tr, 0x00ffc000); /* per ref-board manual */
	85	mtdcr(uic1vr, 0x00000001); /* int31 highest, base=0x000 */
	86	mtdcr(uic1sr, 0xffffffff); /* clear all */
c609719b WD	87
	88	return 0;
	89	}
	90
8a316c9b	91	int checkboard(void)
c609719b	92	{
77ddac94	93	char *s = getenv("serial#");
c609719b	94
8a316c9b SR	95	printf("Board: Ebony - AMCC PPC440GP Evaluation Board");
	96	if (s != NULL) {
	97	puts(", serial# ");
	98	puts(s);
	99	}
	100	putc('\n');
	101
c609719b WD	102	return (0);
	103	}
	104
8a316c9b	105	long int initdram(int board_type)
c609719b WD	106	{
c609719b WD	107	long dram_size = 0;
c609719b WD	108
c609719b WD	109	#if defined(CONFIG_SPD_EEPROM)
8a316c9b	110	dram_size = spd_sdram(0);
c609719b	111	#else
8a316c9b	112	dram_size = fixed_sdram();
c609719b WD	113	#endif
	114	return dram_size;
	115	}
	116
c609719b	117	#if defined(CFG_DRAM_TEST)
8a316c9b	118	int testdram(void)
c609719b WD	119	{
	120	uint pstart = (uint ) 0x00000000;
	121	uint pend = (uint ) 0x08000000;
	122	uint *p;
	123
	124	for (p = pstart; p < pend; p++)
	125	*p = 0xaaaaaaaa;
	126
	127	for (p = pstart; p < pend; p++) {
	128	if (*p != 0xaaaaaaaa) {
8a316c9b	129	printf("SDRAM test fails at: %08x\n", (uint) p);
c609719b WD	130	return 1;
	131	}
	132	}
	133
	134	for (p = pstart; p < pend; p++)
	135	*p = 0x55555555;
	136
	137	for (p = pstart; p < pend; p++) {
	138	if (*p != 0x55555555) {
8a316c9b	139	printf("SDRAM test fails at: %08x\n", (uint) p);
c609719b WD	140	return 1;
	141	}
	142	}
	143	return 0;
	144	}
	145	#endif
	146
	147	#if !defined(CONFIG_SPD_EEPROM)
	148	/*************************************************************************
	149	* fixed sdram init -- doesn't use serial presence detect.
	150	*
	151	* Assumes: 128 MB, non-ECC, non-registered
	152	* PLB @ 133 MHz
	153	*
	154	************************************************************************/
8a316c9b	155	long int fixed_sdram(void)
c609719b WD	156	{
	157	uint reg;
	158
	159	/*--------------------------------------------------------------------
	160	* Setup some default
	161	------------------------------------------------------------------/
8a316c9b SR	162	mtsdram(mem_uabba, 0x00000000); /* ubba=0 (default) */
	163	mtsdram(mem_slio, 0x00000000); /* rdre=0 wrre=0 rarw=0 */
	164	mtsdram(mem_devopt, 0x00000000); /* dll=0 ds=0 (normal) */
	165	mtsdram(mem_wddctr, 0x00000000); /* wrcp=0 dcd=0 */
	166	mtsdram(mem_clktr, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */
c609719b WD	167
	168	/*--------------------------------------------------------------------
	169	* Setup for board-specific specific mem
	170	------------------------------------------------------------------/
	171	/*
	172	* Following for CAS Latency = 2.5 @ 133 MHz PLB
	173	*/
8a316c9b SR	174	mtsdram(mem_b0cr, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */
8a316c9b SR	175	mtsdram(mem_tr0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */
c609719b	176	/* RA=10 RD=3 */
8a316c9b SR	177	mtsdram(mem_tr1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */
	178	mtsdram(mem_rtr, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */
	179	mtsdram(mem_cfg1, 0x00000000); /* Self-refresh exit, disable PM */
	180	udelay(400); /* Delay 200 usecs (min) */
c609719b WD	181
	182	/*--------------------------------------------------------------------
	183	* Enable the controller, then wait for DCEN to complete
	184	------------------------------------------------------------------/
8a316c9b	185	mtsdram(mem_cfg0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */
c609719b	186	for (;;) {
8a316c9b	187	mfsdram(mem_mcsts, reg);
c609719b WD	188	if (reg & 0x80000000)
	189	break;
	190	}
	191
	192	return (128 * 1024 * 1024); /* 128 MB */
	193	}
8a316c9b	194	#endif /* !defined(CONFIG_SPD_EEPROM) */
c609719b WD	195
	196	/*************************************************************************
	197	* pci_pre_init
	198	*
	199	* This routine is called just prior to registering the hose and gives
	200	* the board the opportunity to check things. Returning a value of zero
	201	* indicates that things are bad & PCI initialization should be aborted.
	202	*
	203	* Different boards may wish to customize the pci controller structure
	204	* (add regions, override default access routines, etc) or perform
	205	* certain pre-initialization actions.
	206	*
	207	************************************************************************/
	208	#if defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT)
8a316c9b	209	int pci_pre_init(struct pci_controller *hose)
c609719b	210	{
8a316c9b	211	unsigned long strap;
c609719b WD	212
	213	/*--------------------------------------------------------------------------+
	214	* The ebony board is always configured as the host & requires the
	215	* PCI arbiter to be enabled.
	216	--------------------------------------------------------------------------/
8a316c9b SR	217	strap = mfdcr(cpc0_strp1);
	218	if ((strap & 0x00100000) == 0) {
	219	printf("PCI: CPC0_STRP1[PAE] not set.\n");
	220	return 0;
	221	}
c609719b	222
8a316c9b	223	return 1;
c609719b	224	}
8a316c9b	225	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_PRE_INIT) */
c609719b WD	226
	227	/*************************************************************************
	228	* pci_target_init
	229	*
	230	* The bootstrap configuration provides default settings for the pci
	231	* inbound map (PIM). But the bootstrap config choices are limited and
	232	* may not be sufficient for a given board.
	233	*
	234	************************************************************************/
	235	#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
8a316c9b	236	void pci_target_init(struct pci_controller *hose)
c609719b WD	237	{
	238	DECLARE_GLOBAL_DATA_PTR;
	239
	240	/*--------------------------------------------------------------------------+
	241	* Disable everything
	242	--------------------------------------------------------------------------/
8a316c9b SR	243	out32r(PCIX0_PIM0SA, 0); /* disable */
	244	out32r(PCIX0_PIM1SA, 0); /* disable */
	245	out32r(PCIX0_PIM2SA, 0); /* disable */
	246	out32r(PCIX0_EROMBA, 0); /* disable expansion rom */
c609719b WD	247
	248	/*--------------------------------------------------------------------------+
	249	* Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
	250	* options to not support sizes such as 128/256 MB.
	251	--------------------------------------------------------------------------/
8a316c9b SR	252	out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
	253	out32r(PCIX0_PIM0LAH, 0);
	254	out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) \| 1);
c609719b	255
8a316c9b	256	out32r(PCIX0_BAR0, 0);
c609719b WD	257
	258	/*--------------------------------------------------------------------------+
	259	* Program the board's subsystem id/vendor id
	260	--------------------------------------------------------------------------/
8a316c9b SR	261	out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
8a316c9b SR	262	out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
c609719b	263
8a316c9b	264	out16r(PCIX0_CMD, in16r(PCIX0_CMD) \| PCI_COMMAND_MEMORY);
c609719b	265	}
8a316c9b	266	#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
c609719b WD	267
	268	/*************************************************************************
	269	* is_pci_host
	270	*
	271	* This routine is called to determine if a pci scan should be
	272	* performed. With various hardware environments (especially cPCI and
	273	* PPMC) it's insufficient to depend on the state of the arbiter enable
	274	* bit in the strap register, or generic host/adapter assumptions.
	275	*
	276	* Rather than hard-code a bad assumption in the general 440 code, the
	277	* 440 pci code requires the board to decide at runtime.
	278	*
	279	* Return 0 for adapter mode, non-zero for host (monarch) mode.
	280	*
	281	*
	282	************************************************************************/
	283	#if defined(CONFIG_PCI)
	284	int is_pci_host(struct pci_controller *hose)
	285	{
8a316c9b SR	286	/* The ebony board is always configured as host. */
8a316c9b SR	287	return (1);
c609719b	288	}
8a316c9b	289	#endif /* defined(CONFIG_PCI) */