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c609719b WD |
1 | /* |
2 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> | |
3 | * | |
4 | * See file CREDITS for list of people who contributed to this | |
5 | * project. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
c609719b | 23 | #include <common.h> |
c609719b | 24 | #include <asm/processor.h> |
db2f721f | 25 | #include <spd_sdram.h> |
c609719b WD |
26 | |
27 | #define BOOT_SMALL_FLASH 32 /* 00100000 */ | |
28 | #define FLASH_ONBD_N 2 /* 00000010 */ | |
29 | #define FLASH_SRAM_SEL 1 /* 00000001 */ | |
30 | ||
d87080b7 WD |
31 | DECLARE_GLOBAL_DATA_PTR; |
32 | ||
8a316c9b | 33 | long int fixed_sdram(void); |
c609719b | 34 | |
8a316c9b | 35 | int board_early_init_f(void) |
c609719b WD |
36 | { |
37 | uint reg; | |
6d0f6bcf | 38 | unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE; |
c609719b WD |
39 | unsigned char status; |
40 | ||
c609719b WD |
41 | /*-------------------------------------------------------------------- |
42 | * Setup the external bus controller/chip selects | |
43 | *-------------------------------------------------------------------*/ | |
d1c3b275 SR |
44 | mtdcr(EBC0_CFGADDR, EBC0_CFG); |
45 | reg = mfdcr(EBC0_CFGDATA); | |
46 | mtdcr(EBC0_CFGDATA, reg | 0x04000000); /* Set ATC */ | |
c609719b | 47 | |
d1c3b275 SR |
48 | mtebc(PB1AP, 0x02815480); /* NVRAM/RTC */ |
49 | mtebc(PB1CR, 0x48018000); /* BA=0x480 1MB R/W 8-bit */ | |
50 | mtebc(PB7AP, 0x01015280); /* FPGA registers */ | |
51 | mtebc(PB7CR, 0x48318000); /* BA=0x483 1MB R/W 8-bit */ | |
c609719b WD |
52 | |
53 | /* read FPGA_REG0 and set the bus controller */ | |
54 | status = *fpga_base; | |
55 | if ((status & BOOT_SMALL_FLASH) && !(status & FLASH_ONBD_N)) { | |
d1c3b275 SR |
56 | mtebc(PB0AP, 0x9b015480); /* FLASH/SRAM */ |
57 | mtebc(PB0CR, 0xfff18000); /* BAS=0xfff 1MB R/W 8-bit */ | |
58 | mtebc(PB2AP, 0x9b015480); /* 4MB FLASH */ | |
59 | mtebc(PB2CR, 0xff858000); /* BAS=0xff8 4MB R/W 8-bit */ | |
c609719b | 60 | } else { |
d1c3b275 SR |
61 | mtebc(PB0AP, 0x9b015480); /* 4MB FLASH */ |
62 | mtebc(PB0CR, 0xffc58000); /* BAS=0xffc 4MB R/W 8-bit */ | |
c609719b WD |
63 | |
64 | /* set CS2 if FLASH_ONBD_N == 0 */ | |
65 | if (!(status & FLASH_ONBD_N)) { | |
d1c3b275 SR |
66 | mtebc(PB2AP, 0x9b015480); /* FLASH/SRAM */ |
67 | mtebc(PB2CR, 0xff818000); /* BAS=0xff8 4MB R/W 8-bit */ | |
c609719b WD |
68 | } |
69 | } | |
70 | ||
71 | /*-------------------------------------------------------------------- | |
72 | * Setup the interrupt controller polarities, triggers, etc. | |
73 | *-------------------------------------------------------------------*/ | |
952e7760 SR |
74 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ |
75 | mtdcr(UIC0ER, 0x00000000); /* disable all */ | |
76 | mtdcr(UIC0CR, 0x00000009); /* SMI & UIC1 crit are critical */ | |
77 | mtdcr(UIC0PR, 0xfffffe13); /* per ref-board manual */ | |
78 | mtdcr(UIC0TR, 0x01c00008); /* per ref-board manual */ | |
79 | mtdcr(UIC0VR, 0x00000001); /* int31 highest, base=0x000 */ | |
80 | mtdcr(UIC0SR, 0xffffffff); /* clear all */ | |
81 | ||
82 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ | |
83 | mtdcr(UIC1ER, 0x00000000); /* disable all */ | |
84 | mtdcr(UIC1CR, 0x00000000); /* all non-critical */ | |
85 | mtdcr(UIC1PR, 0xffffe0ff); /* per ref-board manual */ | |
86 | mtdcr(UIC1TR, 0x00ffc000); /* per ref-board manual */ | |
87 | mtdcr(UIC1VR, 0x00000001); /* int31 highest, base=0x000 */ | |
88 | mtdcr(UIC1SR, 0xffffffff); /* clear all */ | |
c609719b WD |
89 | |
90 | return 0; | |
91 | } | |
92 | ||
8a316c9b | 93 | int checkboard(void) |
c609719b | 94 | { |
f0c0b3a9 WD |
95 | char buf[64]; |
96 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
c609719b | 97 | |
8a316c9b | 98 | printf("Board: Ebony - AMCC PPC440GP Evaluation Board"); |
f0c0b3a9 | 99 | if (i > 0) { |
8a316c9b | 100 | puts(", serial# "); |
f0c0b3a9 | 101 | puts(buf); |
8a316c9b SR |
102 | } |
103 | putc('\n'); | |
104 | ||
c609719b WD |
105 | return (0); |
106 | } | |
107 | ||
9973e3c6 | 108 | phys_size_t initdram(int board_type) |
c609719b WD |
109 | { |
110 | long dram_size = 0; | |
c609719b WD |
111 | |
112 | #if defined(CONFIG_SPD_EEPROM) | |
d87080b7 | 113 | dram_size = spd_sdram(); |
c609719b | 114 | #else |
8a316c9b | 115 | dram_size = fixed_sdram(); |
c609719b WD |
116 | #endif |
117 | return dram_size; | |
118 | } | |
119 | ||
c609719b WD |
120 | #if !defined(CONFIG_SPD_EEPROM) |
121 | /************************************************************************* | |
122 | * fixed sdram init -- doesn't use serial presence detect. | |
123 | * | |
124 | * Assumes: 128 MB, non-ECC, non-registered | |
125 | * PLB @ 133 MHz | |
126 | * | |
127 | ************************************************************************/ | |
8a316c9b | 128 | long int fixed_sdram(void) |
c609719b WD |
129 | { |
130 | uint reg; | |
131 | ||
132 | /*-------------------------------------------------------------------- | |
133 | * Setup some default | |
134 | *------------------------------------------------------------------*/ | |
95b602ba SR |
135 | mtsdram(SDRAM0_UABBA, 0x00000000); /* ubba=0 (default) */ |
136 | mtsdram(SDRAM0_SLIO, 0x00000000); /* rdre=0 wrre=0 rarw=0 */ | |
137 | mtsdram(SDRAM0_DEVOPT, 0x00000000); /* dll=0 ds=0 (normal) */ | |
138 | mtsdram(SDRAM0_WDDCTR, 0x00000000); /* wrcp=0 dcd=0 */ | |
139 | mtsdram(SDRAM0_CLKTR, 0x40000000); /* clkp=1 (90 deg wr) dcdt=0 */ | |
c609719b WD |
140 | |
141 | /*-------------------------------------------------------------------- | |
142 | * Setup for board-specific specific mem | |
143 | *------------------------------------------------------------------*/ | |
144 | /* | |
145 | * Following for CAS Latency = 2.5 @ 133 MHz PLB | |
146 | */ | |
95b602ba SR |
147 | mtsdram(SDRAM0_B0CR, 0x000a4001); /* SDBA=0x000 128MB, Mode 3, enabled */ |
148 | mtsdram(SDRAM0_TR0, 0x410a4012); /* WR=2 WD=1 CL=2.5 PA=3 CP=4 LD=2 */ | |
c609719b | 149 | /* RA=10 RD=3 */ |
95b602ba SR |
150 | mtsdram(SDRAM0_TR1, 0x8080082f); /* SS=T2 SL=STAGE 3 CD=1 CT=0x02f */ |
151 | mtsdram(SDRAM0_RTR, 0x08200000); /* Rate 15.625 ns @ 133 MHz PLB */ | |
152 | mtsdram(SDRAM0_CFG1, 0x00000000); /* Self-refresh exit, disable PM */ | |
8a316c9b | 153 | udelay(400); /* Delay 200 usecs (min) */ |
c609719b WD |
154 | |
155 | /*-------------------------------------------------------------------- | |
156 | * Enable the controller, then wait for DCEN to complete | |
157 | *------------------------------------------------------------------*/ | |
95b602ba | 158 | mtsdram(SDRAM0_CFG0, 0x86000000); /* DCEN=1, PMUD=1, 64-bit */ |
c609719b | 159 | for (;;) { |
95b602ba | 160 | mfsdram(SDRAM0_MCSTS, reg); |
c609719b WD |
161 | if (reg & 0x80000000) |
162 | break; | |
163 | } | |
164 | ||
165 | return (128 * 1024 * 1024); /* 128 MB */ | |
166 | } | |
8a316c9b | 167 | #endif /* !defined(CONFIG_SPD_EEPROM) */ |