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4745acaa SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
4745acaa SR |
8 | */ |
9 | ||
10 | #include <ppc_asm.tmpl> | |
11 | #include <config.h> | |
61f2b38a | 12 | #include <asm/mmu.h> |
550650dd | 13 | #include <asm/ppc4xx.h> |
4745acaa SR |
14 | |
15 | /************************************************************************** | |
16 | * TLB TABLE | |
17 | * | |
18 | * This table is used by the cpu boot code to setup the initial tlb | |
19 | * entries. Rather than make broad assumptions in the cpu source tree, | |
20 | * this table lets each board set things up however they like. | |
21 | * | |
22 | * Pointer to the table is returned in r1 | |
23 | * | |
24 | *************************************************************************/ | |
25 | ||
26 | .section .bootpg,"ax" | |
27 | ||
28 | /************************************************************************** | |
29 | * TLB table for revA | |
30 | *************************************************************************/ | |
31 | .globl tlbtabA | |
32 | tlbtabA: | |
33 | tlbtab_start | |
2721a68a SR |
34 | |
35 | /* | |
36 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
37 | * speed up boot process. It is patched after relocation to enable SA_I | |
38 | */ | |
cf6eb6da | 39 | tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) |
4745acaa SR |
40 | |
41 | /* | |
42 | * TLB entries for SDRAM are not needed on this platform. | |
43 | * They are dynamically generated in the SPD DDR(2) detection | |
44 | * routine. | |
45 | */ | |
46 | ||
cf6eb6da SR |
47 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) |
48 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) | |
6d0f6bcf | 49 | |
cf6eb6da SR |
50 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) |
51 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) | |
52 | tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) | |
53 | tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG) | |
6d0f6bcf | 54 | |
cf6eb6da SR |
55 | tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG) |
56 | tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG) | |
57 | tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG) | |
58 | tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG) | |
59 | tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG) | |
60 | tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG) | |
4745acaa SR |
61 | tlbtab_end |
62 | ||
63 | /************************************************************************** | |
64 | * TLB table for revB | |
65 | * | |
66 | * Notice: revB of the 440SPe chip is very strict about PLB real addresses | |
67 | * and ranges to be mapped for config space: it seems to only work with | |
68 | * d_nnnn_nnnn range (hangs the core upon config transaction attempts when | |
69 | * set otherwise) while revA uses c_nnnn_nnnn. | |
70 | *************************************************************************/ | |
71 | .globl tlbtabB | |
72 | tlbtabB: | |
73 | tlbtab_start | |
2721a68a SR |
74 | |
75 | /* | |
76 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
77 | * speed up boot process. It is patched after relocation to enable SA_I | |
78 | */ | |
cf6eb6da | 79 | tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) |
4745acaa SR |
80 | |
81 | /* | |
82 | * TLB entries for SDRAM are not needed on this platform. | |
83 | * They are dynamically generated in the SPD DDR(2) detection | |
84 | * routine. | |
85 | */ | |
86 | ||
cf6eb6da | 87 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) |
4745acaa | 88 | |
cf6eb6da | 89 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) |
4745acaa | 90 | |
cf6eb6da | 91 | tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_RW | SA_IG) |
4745acaa | 92 | |
cf6eb6da SR |
93 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) |
94 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) | |
95 | tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) | |
4745acaa | 96 | |
cf6eb6da SR |
97 | tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG) |
98 | tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG) | |
99 | tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG) | |
100 | tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG) | |
101 | tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG) | |
102 | tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG) | |
4745acaa | 103 | tlbtab_end |