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4745acaa SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * Copyright (C) 2002 Scott McNutt <smcnutt@artesyncp.com> | |
6 | * | |
7 | * See file CREDITS for list of people who contributed to this | |
8 | * project. | |
9 | * | |
10 | * This program is free software; you can redistribute it and/or | |
11 | * modify it under the terms of the GNU General Public License as | |
12 | * published by the Free Software Foundation; either version 2 of | |
13 | * the License, or (at your option) any later version. | |
14 | * | |
15 | * This program is distributed in the hope that it will be useful, | |
16 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
17 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
18 | * GNU General Public License for more details. | |
19 | * | |
20 | * You should have received a copy of the GNU General Public License | |
21 | * along with this program; if not, write to the Free Software | |
22 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
23 | * MA 02111-1307 USA | |
24 | */ | |
25 | ||
26 | #include <ppc_asm.tmpl> | |
27 | #include <config.h> | |
61f2b38a | 28 | #include <asm/mmu.h> |
550650dd | 29 | #include <asm/ppc4xx.h> |
4745acaa SR |
30 | |
31 | /************************************************************************** | |
32 | * TLB TABLE | |
33 | * | |
34 | * This table is used by the cpu boot code to setup the initial tlb | |
35 | * entries. Rather than make broad assumptions in the cpu source tree, | |
36 | * this table lets each board set things up however they like. | |
37 | * | |
38 | * Pointer to the table is returned in r1 | |
39 | * | |
40 | *************************************************************************/ | |
41 | ||
42 | .section .bootpg,"ax" | |
43 | ||
44 | /************************************************************************** | |
45 | * TLB table for revA | |
46 | *************************************************************************/ | |
47 | .globl tlbtabA | |
48 | tlbtabA: | |
49 | tlbtab_start | |
2721a68a SR |
50 | |
51 | /* | |
52 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
53 | * speed up boot process. It is patched after relocation to enable SA_I | |
54 | */ | |
cf6eb6da | 55 | tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) |
4745acaa SR |
56 | |
57 | /* | |
58 | * TLB entries for SDRAM are not needed on this platform. | |
59 | * They are dynamically generated in the SPD DDR(2) detection | |
60 | * routine. | |
61 | */ | |
62 | ||
cf6eb6da SR |
63 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) |
64 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) | |
6d0f6bcf | 65 | |
cf6eb6da SR |
66 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) |
67 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) | |
68 | tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) | |
69 | tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_RW | SA_IG) | |
6d0f6bcf | 70 | |
cf6eb6da SR |
71 | tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_RW | SA_IG) |
72 | tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_RW | SA_IG) | |
73 | tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_RW | SA_IG) | |
74 | tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_RW | SA_IG) | |
75 | tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_RW | SA_IG) | |
76 | tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_RW | SA_IG) | |
4745acaa SR |
77 | tlbtab_end |
78 | ||
79 | /************************************************************************** | |
80 | * TLB table for revB | |
81 | * | |
82 | * Notice: revB of the 440SPe chip is very strict about PLB real addresses | |
83 | * and ranges to be mapped for config space: it seems to only work with | |
84 | * d_nnnn_nnnn range (hangs the core upon config transaction attempts when | |
85 | * set otherwise) while revA uses c_nnnn_nnnn. | |
86 | *************************************************************************/ | |
87 | .globl tlbtabB | |
88 | tlbtabB: | |
89 | tlbtab_start | |
2721a68a SR |
90 | |
91 | /* | |
92 | * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the | |
93 | * speed up boot process. It is patched after relocation to enable SA_I | |
94 | */ | |
cf6eb6da | 95 | tlbentry(0xff000000, SZ_16M, 0xff000000, 4, AC_RWX | SA_G) |
4745acaa SR |
96 | |
97 | /* | |
98 | * TLB entries for SDRAM are not needed on this platform. | |
99 | * They are dynamically generated in the SPD DDR(2) detection | |
100 | * routine. | |
101 | */ | |
102 | ||
cf6eb6da | 103 | tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_RWX | SA_I) |
4745acaa | 104 | |
cf6eb6da | 105 | tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_RW | SA_IG) |
4745acaa | 106 | |
cf6eb6da | 107 | tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_RW | SA_IG) |
4745acaa | 108 | |
cf6eb6da SR |
109 | tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_RW | SA_IG) |
110 | tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_RW | SA_IG) | |
111 | tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_RW | SA_IG) | |
4745acaa | 112 | |
cf6eb6da SR |
113 | tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_RW | SA_IG) |
114 | tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_RW | SA_IG) | |
115 | tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_RW | SA_IG) | |
116 | tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_RW | SA_IG) | |
117 | tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_RW | SA_IG) | |
118 | tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_RW | SA_IG) | |
4745acaa | 119 | tlbtab_end |