projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 4745acaa SR |
1 | /* |
| 2 | * (C) Copyright 2007 | |
| 3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
| 4 | * | |
| 5 | * See file CREDITS for list of people who contributed to this | |
| 6 | * project. | |
| 7 | * | |
| 8 | * This program is free software; you can redistribute it and/or | |
| 9 | * modify it under the terms of the GNU General Public License as | |
| 10 | * published by the Free Software Foundation; either version 2 of | |
| 11 | * the License, or (at your option) any later version. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | * You should have received a copy of the GNU General Public License | |
| 19 | * along with this program; if not, write to the Free Software | |
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
| 21 | * MA 02111-1307 USA | |
| 22 | * | |
| 23 | */ | |
| 24 | ||
| 25 | #include <common.h> | |
| 26 | #include <ppc4xx.h> | |
| 27 | #include <asm/processor.h> | |
| 28 | #include <i2c.h> | |
| 29 | #include <asm-ppc/io.h> | |
| 0d974d52 | 30 | #include <asm-ppc/gpio.h> |
| 4745acaa | 31 | |
| 4745acaa SR |
32 | #include "../cpu/ppc4xx/440spe_pcie.h" |
| 33 | ||
| 34 | #undef PCIE_ENDPOINT | |
| 35 | /* #define PCIE_ENDPOINT 1 */ | |
| 36 | ||
| 1218abf1 WD |
37 | DECLARE_GLOBAL_DATA_PTR; |
| 38 | ||
| 4745acaa SR |
39 | int ppc440spe_init_pcie_rootport(int port); |
| 40 | void ppc440spe_setup_pcie(struct pci_controller *hose, int port); | |
| 41 | ||
| 42 | int board_early_init_f (void) | |
| 43 | { | |
| 44 | unsigned long mfr; | |
| 4745acaa SR |
45 | |
| 46 | /*----------------------------------------------------------------------+ | |
| 47 | * Interrupt controller setup for the Katmai 440SPe Evaluation board. | |
| 48 | *-----------------------------------------------------------------------+ | |
| 49 | *-----------------------------------------------------------------------+ | |
| 50 | * Interrupt | Source | Pol. | Sensi.| Crit. | | |
| 51 | *-----------+-----------------------------------+-------+-------+-------+ | |
| 52 | * IRQ 00 | UART0 | High | Level | Non | | |
| 53 | * IRQ 01 | UART1 | High | Level | Non | | |
| 54 | * IRQ 02 | IIC0 | High | Level | Non | | |
| 55 | * IRQ 03 | IIC1 | High | Level | Non | | |
| 56 | * IRQ 04 | PCI0X0 MSG IN | High | Level | Non | | |
| 57 | * IRQ 05 | PCI0X0 CMD Write | High | Level | Non | | |
| 58 | * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non | | |
| 59 | * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non | | |
| 60 | * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non | | |
| 61 | * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non | | |
| 62 | * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non | | |
| 63 | * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit | | |
| 64 | * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non | | |
| 65 | * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non | | |
| 66 | * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non | | |
| 67 | * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non | | |
| 68 | * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non | | |
| 69 | * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit | | |
| 70 | * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non | | |
| 71 | * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non | | |
| 72 | * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non | | |
| 73 | * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non | | |
| 74 | * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non | | |
| 75 | * IRQ 23 | I2O Inbound Doorbell | High | Level | Non | | |
| 76 | * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non | | |
| 77 | * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non | | |
| 78 | * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non | | |
| 79 | * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non | | |
| 80 | * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non | | |
| 81 | * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non | | |
| 82 | * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non | | |
| 83 | * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. | | |
| 84 | *------------------------------------------------------------------------ | |
| 85 | * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non | | |
| 86 | * IRQ 33 | MAL Serr | High | Level | Non | | |
| 87 | * IRQ 34 | MAL Txde | High | Level | Non | | |
| 88 | * IRQ 35 | MAL Rxde | High | Level | Non | | |
| 89 | * IRQ 36 | DMC CE or DMC UE | High | Level | Non | | |
| 90 | * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non | | |
| 91 | * IRQ 38 | MAL TX EOB | High | Level | Non | | |
| 92 | * IRQ 39 | MAL RX EOB | High | Level | Non | | |
| 93 | * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non | | |
| 94 | * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non | | |
| 95 | * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non | | |
| 96 | * IRQ 43 | L2 Cache | Risin | Edge | Non | | |
| 97 | * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non | | |
| 98 | * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non | | |
| 99 | * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non | | |
| 100 | * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | | |
| 101 | * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | | |
| 102 | * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non | | |
| 103 | * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non | | |
| 104 | * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non | | |
| 105 | * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | | |
| 106 | * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non | | |
| 107 | * IRQ 54 | DMA Error | High | Level | Non | | |
| 108 | * IRQ 55 | DMA I2O Error | High | Level | Non | | |
| 109 | * IRQ 56 | Serial ROM | High | Level | Non | | |
| 110 | * IRQ 57 | PCIX0 Error | High | Edge | Non | | |
| 111 | * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non | | |
| 112 | * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non | | |
| 113 | * IRQ 60 | EMAC0 Interrupt | High | Level | Non | | |
| 114 | * IRQ 61 | EMAC0 Wake-up | High | Level | Non | | |
| 115 | * IRQ 62 | Reserved | High | Level | Non | | |
| 116 | * IRQ 63 | XOR | High | Level | Non | | |
| 117 | *----------------------------------------------------------------------- | |
| 118 | * IRQ 64 | PE0 AL | High | Level | Non | | |
| 119 | * IRQ 65 | PE0 VPD Access | Risin | Edge | Non | | |
| 120 | * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | | |
| 121 | * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | | |
| 122 | * IRQ 68 | PE0 TCR | High | Level | Non | | |
| 123 | * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | | |
| 124 | * IRQ 70 | PE0 DCR Error | High | Level | Non | | |
| 125 | * IRQ 71 | Reserved | N/A | N/A | Non | | |
| 126 | * IRQ 72 | PE1 AL | High | Level | Non | | |
| 127 | * IRQ 73 | PE1 VPD Access | Risin | Edge | Non | | |
| 128 | * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | | |
| 129 | * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | | |
| 130 | * IRQ 76 | PE1 TCR | High | Level | Non | | |
| 131 | * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | | |
| 132 | * IRQ 78 | PE1 DCR Error | High | Level | Non | | |
| 133 | * IRQ 79 | Reserved | N/A | N/A | Non | | |
| 134 | * IRQ 80 | PE2 AL | High | Level | Non | | |
| 135 | * IRQ 81 | PE2 VPD Access | Risin | Edge | Non | | |
| 136 | * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | | |
| 137 | * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | | |
| 138 | * IRQ 84 | PE2 TCR | High | Level | Non | | |
| 139 | * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | | |
| 140 | * IRQ 86 | PE2 DCR Error | High | Level | Non | | |
| 141 | * IRQ 87 | Reserved | N/A | N/A | Non | | |
| 142 | * IRQ 88 | External IRQ(5) | Progr | Progr | Non | | |
| 143 | * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | | |
| 144 | * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | | |
| 145 | * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | | |
| 146 | * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | | |
| 147 | * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | | |
| 148 | * IRQ 94 | Reserved | N/A | N/A | Non | | |
| 149 | * IRQ 95 | Reserved | N/A | N/A | Non | | |
| 150 | *----------------------------------------------------------------------- | |
| 151 | * IRQ 96 | PE0 INTA | High | Level | Non | | |
| 152 | * IRQ 97 | PE0 INTB | High | Level | Non | | |
| 153 | * IRQ 98 | PE0 INTC | High | Level | Non | | |
| 154 | * IRQ 99 | PE0 INTD | High | Level | Non | | |
| 155 | * IRQ 100 | PE1 INTA | High | Level | Non | | |
| 156 | * IRQ 101 | PE1 INTB | High | Level | Non | | |
| 157 | * IRQ 102 | PE1 INTC | High | Level | Non | | |
| 158 | * IRQ 103 | PE1 INTD | High | Level | Non | | |
| 159 | * IRQ 104 | PE2 INTA | High | Level | Non | | |
| 160 | * IRQ 105 | PE2 INTB | High | Level | Non | | |
| 161 | * IRQ 106 | PE2 INTC | High | Level | Non | | |
| 162 | * IRQ 107 | PE2 INTD | Risin | Edge | Non | | |
| 163 | * IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non | | |
| 164 | * IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non | | |
| 165 | * IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non | | |
| 166 | * IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non | | |
| 167 | * IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non | | |
| 168 | * IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non | | |
| 169 | * IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non | | |
| 170 | * IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non | | |
| 171 | * IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non | | |
| 172 | * IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non | | |
| 173 | * IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non | | |
| 174 | * IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non | | |
| 175 | * IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non | | |
| 176 | * IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non | | |
| 177 | * IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non | | |
| 178 | * IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non | | |
| 179 | * IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non | | |
| 180 | * IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non | | |
| 181 | * IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non | | |
| 182 | * IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non | | |
| 183 | *-----------+-----------------------------------+-------+-------+-------+ */ | |
| 184 | /*-------------------------------------------------------------------------+ | |
| 185 | * Put UICs in PowerPC440SPemode. | |
| 186 | * Initialise UIC registers. Clear all interrupts. Disable all interrupts. | |
| 187 | * Set critical interrupt values. Set interrupt polarities. Set interrupt | |
| 188 | * trigger levels. Make bit 0 High priority. Clear all interrupts again. | |
| 189 | *------------------------------------------------------------------------*/ | |
| 190 | mtdcr (uic3sr, 0xffffffff); /* Clear all interrupts */ | |
| 191 | mtdcr (uic3er, 0x00000000); /* disable all interrupts */ | |
| 192 | mtdcr (uic3cr, 0x00000000); /* Set Critical / Non Critical interrupts: */ | |
| 193 | mtdcr (uic3pr, 0xffffffff); /* Set Interrupt Polarities*/ | |
| 194 | mtdcr (uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */ | |
| 195 | mtdcr (uic3vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ | |
| 196 | mtdcr (uic3sr, 0x00000000); /* clear all interrupts*/ | |
| 197 | mtdcr (uic3sr, 0xffffffff); /* clear all interrupts*/ | |
| 198 | ||
| 199 | ||
| 200 | mtdcr (uic2sr, 0xffffffff); /* Clear all interrupts */ | |
| 201 | mtdcr (uic2er, 0x00000000); /* disable all interrupts*/ | |
| 202 | mtdcr (uic2cr, 0x00000000); /* Set Critical / Non Critical interrupts*/ | |
| 203 | mtdcr (uic2pr, 0xebebebff); /* Set Interrupt Polarities*/ | |
| 204 | mtdcr (uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */ | |
| 205 | mtdcr (uic2vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ | |
| 206 | mtdcr (uic2sr, 0x00000000); /* clear all interrupts */ | |
| 207 | mtdcr (uic2sr, 0xffffffff); /* clear all interrupts */ | |
| 208 | ||
| 209 | mtdcr (uic1sr, 0xffffffff); /* Clear all interrupts*/ | |
| 210 | mtdcr (uic1er, 0x00000000); /* disable all interrupts*/ | |
| 211 | mtdcr (uic1cr, 0x00000000); /* Set Critical / Non Critical interrupts*/ | |
| 212 | mtdcr (uic1pr, 0xffffffff); /* Set Interrupt Polarities */ | |
| 213 | mtdcr (uic1tr, 0x001f8040); /* Set Interrupt Trigger Levels*/ | |
| 214 | mtdcr (uic1vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ | |
| 215 | mtdcr (uic1sr, 0x00000000); /* clear all interrupts*/ | |
| 216 | mtdcr (uic1sr, 0xffffffff); /* clear all interrupts*/ | |
| 217 | ||
| 218 | mtdcr (uic0sr, 0xffffffff); /* Clear all interrupts */ | |
| 219 | mtdcr (uic0er, 0x00000000); /* disable all interrupts excepted cascade to be checked */ | |
| 220 | mtdcr (uic0cr, 0x00104001); /* Set Critical / Non Critical interrupts*/ | |
| 221 | mtdcr (uic0pr, 0xffffffff); /* Set Interrupt Polarities*/ | |
| 222 | mtdcr (uic0tr, 0x010f0004); /* Set Interrupt Trigger Levels */ | |
| 223 | mtdcr (uic0vr, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ | |
| 224 | mtdcr (uic0sr, 0x00000000); /* clear all interrupts*/ | |
| 225 | mtdcr (uic0sr, 0xffffffff); /* clear all interrupts*/ | |
| 226 | ||
| 227 | /* SDR0_MFR should be part of Ethernet init */ | |
| 228 | mfsdr (sdr_mfr, mfr); | |
| 229 | mfr &= ~SDR0_MFR_ECS_MASK; | |
| 230 | /* mtsdr(sdr_mfr, mfr); */ | |
| 231 | ||
| ba58e4c9 | 232 | mtsdr(SDR0_PFC0, CFG_PFC0); |
| 4745acaa | 233 | |
| ba58e4c9 SR |
234 | out32(GPIO0_OR, CFG_GPIO_OR); |
| 235 | out32(GPIO0_ODR, CFG_GPIO_ODR); | |
| 236 | out32(GPIO0_TCR, CFG_GPIO_TCR); | |
| 4745acaa SR |
237 | |
| 238 | return 0; | |
| 239 | } | |
| 240 | ||
| 241 | int checkboard (void) | |
| 242 | { | |
| 243 | char *s = getenv("serial#"); | |
| 244 | ||
| 245 | printf("Board: Katmai - AMCC 440SPe Evaluation Board"); | |
| 246 | if (s != NULL) { | |
| 247 | puts(", serial# "); | |
| 248 | puts(s); | |
| 249 | } | |
| 250 | putc('\n'); | |
| 251 | ||
| 252 | return 0; | |
| 253 | } | |
| 254 | ||
| 255 | #if defined(CFG_DRAM_TEST) | |
| 256 | int testdram (void) | |
| 257 | { | |
| 258 | uint *pstart = (uint *) 0x00000000; | |
| 259 | uint *pend = (uint *) 0x08000000; | |
| 260 | uint *p; | |
| 261 | ||
| 262 | for (p = pstart; p < pend; p++) | |
| 263 | *p = 0xaaaaaaaa; | |
| 264 | ||
| 265 | for (p = pstart; p < pend; p++) { | |
| 266 | if (*p != 0xaaaaaaaa) { | |
| 267 | printf ("SDRAM test fails at: %08x\n", (uint) p); | |
| 268 | return 1; | |
| 269 | } | |
| 270 | } | |
| 271 | ||
| 272 | for (p = pstart; p < pend; p++) | |
| 273 | *p = 0x55555555; | |
| 274 | ||
| 275 | for (p = pstart; p < pend; p++) { | |
| 276 | if (*p != 0x55555555) { | |
| 277 | printf ("SDRAM test fails at: %08x\n", (uint) p); | |
| 278 | return 1; | |
| 279 | } | |
| 280 | } | |
| 281 | return 0; | |
| 282 | } | |
| 283 | #endif | |
| 284 | ||
| 285 | /************************************************************************* | |
| 286 | * pci_pre_init | |
| 287 | * | |
| 288 | * This routine is called just prior to registering the hose and gives | |
| 289 | * the board the opportunity to check things. Returning a value of zero | |
| 290 | * indicates that things are bad & PCI initialization should be aborted. | |
| 291 | * | |
| 292 | * Different boards may wish to customize the pci controller structure | |
| 293 | * (add regions, override default access routines, etc) or perform | |
| 294 | * certain pre-initialization actions. | |
| 295 | * | |
| 296 | ************************************************************************/ | |
| 466fff1a | 297 | #if defined(CONFIG_PCI) |
| 4745acaa SR |
298 | int pci_pre_init(struct pci_controller * hose ) |
| 299 | { | |
| 300 | unsigned long strap; | |
| 301 | ||
| 302 | /*-------------------------------------------------------------------+ | |
| 303 | * The katmai board is always configured as the host & requires the | |
| 304 | * PCI arbiter to be enabled. | |
| 305 | *-------------------------------------------------------------------*/ | |
| 306 | mfsdr(sdr_sdstp1, strap); | |
| 307 | if( (strap & SDR0_SDSTP1_PAE_MASK) == 0 ) { | |
| 308 | printf("PCI: SDR0_STRP1[%08lX] - PCI Arbiter disabled.\n",strap); | |
| 309 | return 0; | |
| 310 | } | |
| 311 | ||
| 312 | return 1; | |
| 313 | } | |
| 466fff1a | 314 | #endif /* defined(CONFIG_PCI) */ |
| 4745acaa SR |
315 | |
| 316 | /************************************************************************* | |
| 317 | * pci_target_init | |
| 318 | * | |
| 319 | * The bootstrap configuration provides default settings for the pci | |
| 320 | * inbound map (PIM). But the bootstrap config choices are limited and | |
| 321 | * may not be sufficient for a given board. | |
| 322 | * | |
| 323 | ************************************************************************/ | |
| 324 | #if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) | |
| 325 | void pci_target_init(struct pci_controller * hose ) | |
| 326 | { | |
| 4745acaa SR |
327 | /*-------------------------------------------------------------------+ |
| 328 | * Disable everything | |
| 329 | *-------------------------------------------------------------------*/ | |
| 330 | out32r( PCIX0_PIM0SA, 0 ); /* disable */ | |
| 331 | out32r( PCIX0_PIM1SA, 0 ); /* disable */ | |
| 332 | out32r( PCIX0_PIM2SA, 0 ); /* disable */ | |
| 333 | out32r( PCIX0_EROMBA, 0 ); /* disable expansion rom */ | |
| 334 | ||
| 335 | /*-------------------------------------------------------------------+ | |
| 336 | * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 | |
| 337 | * strapping options to not support sizes such as 128/256 MB. | |
| 338 | *-------------------------------------------------------------------*/ | |
| 339 | out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE ); | |
| 340 | out32r( PCIX0_PIM0LAH, 0 ); | |
| 341 | out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 ); | |
| 342 | out32r( PCIX0_BAR0, 0 ); | |
| 343 | ||
| 344 | /*-------------------------------------------------------------------+ | |
| 345 | * Program the board's subsystem id/vendor id | |
| 346 | *-------------------------------------------------------------------*/ | |
| 347 | out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID ); | |
| 348 | out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID ); | |
| 349 | ||
| 350 | out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY ); | |
| 351 | } | |
| 352 | #endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */ | |
| 353 | ||
| 354 | #if defined(CONFIG_PCI) | |
| 355 | /************************************************************************* | |
| 356 | * is_pci_host | |
| 357 | * | |
| 358 | * This routine is called to determine if a pci scan should be | |
| 359 | * performed. With various hardware environments (especially cPCI and | |
| 360 | * PPMC) it's insufficient to depend on the state of the arbiter enable | |
| 361 | * bit in the strap register, or generic host/adapter assumptions. | |
| 362 | * | |
| 363 | * Rather than hard-code a bad assumption in the general 440 code, the | |
| 364 | * 440 pci code requires the board to decide at runtime. | |
| 365 | * | |
| 366 | * Return 0 for adapter mode, non-zero for host (monarch) mode. | |
| 367 | * | |
| 368 | * | |
| 369 | ************************************************************************/ | |
| 370 | int is_pci_host(struct pci_controller *hose) | |
| 371 | { | |
| 372 | /* The katmai board is always configured as host. */ | |
| 373 | return 1; | |
| 374 | } | |
| 375 | ||
| ba58e4c9 SR |
376 | int katmai_pcie_card_present(int port) |
| 377 | { | |
| 378 | u32 val; | |
| 379 | ||
| 380 | val = in32(GPIO0_IR); | |
| 381 | switch (port) { | |
| 382 | case 0: | |
| 383 | return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT0)); | |
| 384 | case 1: | |
| 385 | return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT1)); | |
| 386 | case 2: | |
| 387 | return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT2)); | |
| 388 | default: | |
| 389 | return 0; | |
| 390 | } | |
| 391 | } | |
| 392 | ||
| 4745acaa SR |
393 | static struct pci_controller pcie_hose[3] = {{0},{0},{0}}; |
| 394 | ||
| 7f191393 | 395 | void pcie_setup_hoses(int busno) |
| 4745acaa SR |
396 | { |
| 397 | struct pci_controller *hose; | |
| 398 | int i, bus; | |
| 6efc1fc0 GB |
399 | char *env; |
| 400 | unsigned int delay; | |
| 4745acaa SR |
401 | |
| 402 | /* | |
| 403 | * assume we're called after the PCIX hose is initialized, which takes | |
| 404 | * bus ID 0 and therefore start numbering PCIe's from 1. | |
| 405 | */ | |
| 7f191393 | 406 | bus = busno; |
| 4745acaa | 407 | for (i = 0; i <= 2; i++) { |
| ba58e4c9 SR |
408 | /* Check for katmai card presence */ |
| 409 | if (!katmai_pcie_card_present(i)) | |
| 410 | continue; | |
| 411 | ||
| 4745acaa SR |
412 | #ifdef PCIE_ENDPOINT |
| 413 | if (ppc440spe_init_pcie_endport(i)) { | |
| 414 | #else | |
| 415 | if (ppc440spe_init_pcie_rootport(i)) { | |
| 416 | #endif | |
| 417 | printf("PCIE%d: initialization failed\n", i); | |
| 418 | continue; | |
| 419 | } | |
| 420 | ||
| 421 | hose = &pcie_hose[i]; | |
| 422 | hose->first_busno = bus; | |
| 7f191393 GB |
423 | hose->last_busno = bus; |
| 424 | hose->current_busno = bus; | |
| 4745acaa SR |
425 | |
| 426 | /* setup mem resource */ | |
| 427 | pci_set_region(hose->regions + 0, | |
| 428 | CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, | |
| 429 | CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE, | |
| 430 | CFG_PCIE_MEMSIZE, | |
| 431 | PCI_REGION_MEM | |
| 432 | ); | |
| 433 | hose->region_count = 1; | |
| 434 | pci_register_hose(hose); | |
| 435 | ||
| 436 | #ifdef PCIE_ENDPOINT | |
| 437 | ppc440spe_setup_pcie_endpoint(hose, i); | |
| 438 | /* | |
| 439 | * Reson for no scanning is endpoint can not generate | |
| 440 | * upstream configuration accesses. | |
| 441 | */ | |
| 442 | #else | |
| 443 | ppc440spe_setup_pcie_rootpoint(hose, i); | |
| 6efc1fc0 GB |
444 | |
| 445 | env = getenv ("pciscandelay"); | |
| 446 | if (env != NULL) { | |
| 447 | delay = simple_strtoul (env, NULL, 10); | |
| 448 | if (delay > 5) | |
| 449 | printf ("Warning, expect noticable delay before PCIe" | |
| 450 | "scan due to 'pciscandelay' value!\n"); | |
| 451 | mdelay (delay * 1000); | |
| 452 | } | |
| 453 | ||
| 4745acaa SR |
454 | /* |
| 455 | * Config access can only go down stream | |
| 456 | */ | |
| 457 | hose->last_busno = pci_hose_scan(hose); | |
| 7f191393 | 458 | bus = hose->last_busno + 1; |
| 4745acaa SR |
459 | #endif |
| 460 | } | |
| 461 | } | |
| 462 | #endif /* defined(CONFIG_PCI) */ | |
| 463 | ||
| 464 | int misc_init_f (void) | |
| 465 | { | |
| 466 | uint reg; | |
| 467 | #if defined(CONFIG_STRESS) | |
| 468 | uint i ; | |
| 469 | uint disp; | |
| 470 | #endif | |
| 471 | ||
| 472 | /* minimal init for PCIe */ | |
| 473 | #if 0 /* test-only: test endpoint at some time, for now rootpoint only */ | |
| 474 | /* pci express 0 Endpoint Mode */ | |
| 475 | mfsdr(SDR0_PE0DLPSET, reg); | |
| 476 | reg &= (~0x00400000); | |
| 477 | mtsdr(SDR0_PE0DLPSET, reg); | |
| 478 | #else | |
| 479 | /* pci express 0 Rootpoint Mode */ | |
| 480 | mfsdr(SDR0_PE0DLPSET, reg); | |
| 481 | reg |= 0x00400000; | |
| 482 | mtsdr(SDR0_PE0DLPSET, reg); | |
| 483 | #endif | |
| 484 | /* pci express 1 Rootpoint Mode */ | |
| 485 | mfsdr(SDR0_PE1DLPSET, reg); | |
| 486 | reg |= 0x00400000; | |
| 487 | mtsdr(SDR0_PE1DLPSET, reg); | |
| 488 | /* pci express 2 Rootpoint Mode */ | |
| 489 | mfsdr(SDR0_PE2DLPSET, reg); | |
| 490 | reg |= 0x00400000; | |
| 491 | mtsdr(SDR0_PE2DLPSET, reg); | |
| 492 | ||
| 493 | #if defined(CONFIG_STRESS) | |
| 494 | /* | |
| 495 | * All this setting done by linux only needed by stress an charac. test | |
| 496 | * procedure | |
| 497 | * PCIe 1 Rootpoint PCIe2 Endpoint | |
| 498 | * PCIe 0 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level | |
| 499 | */ | |
| 500 | for (i=0,disp=0; i<8; i++,disp+=3) { | |
| 501 | mfsdr(SDR0_PE0HSSSET1L0+disp, reg); | |
| 502 | reg |= 0x33000000; | |
| 503 | mtsdr(SDR0_PE0HSSSET1L0+disp, reg); | |
| 504 | } | |
| 505 | ||
| 506 | /*PCIe 1 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */ | |
| 507 | for (i=0,disp=0; i<4; i++,disp+=3) { | |
| 508 | mfsdr(SDR0_PE1HSSSET1L0+disp, reg); | |
| 509 | reg |= 0x33000000; | |
| 510 | mtsdr(SDR0_PE1HSSSET1L0+disp, reg); | |
| 511 | } | |
| 512 | ||
| 513 | /*PCIE 2 FIR Pre-emphasis Filter Coefficients & Transmit Driver Power Level */ | |
| 514 | for (i=0,disp=0; i<4; i++,disp+=3) { | |
| 515 | mfsdr(SDR0_PE2HSSSET1L0+disp, reg); | |
| 516 | reg |= 0x33000000; | |
| 517 | mtsdr(SDR0_PE2HSSSET1L0+disp, reg); | |
| 518 | } | |
| 519 | ||
| 520 | reg = 0x21242222; | |
| 521 | mtsdr(SDR0_PE2UTLSET1, reg); | |
| 522 | reg = 0x11000000; | |
| 523 | mtsdr(SDR0_PE2UTLSET2, reg); | |
| 524 | /* pci express 1 Endpoint Mode */ | |
| 525 | reg = 0x00004000; | |
| 526 | mtsdr(SDR0_PE2DLPSET, reg); | |
| 527 | ||
| 528 | mtsdr(SDR0_UART1, 0x2080005a); /* patch for TG */ | |
| 529 | #endif | |
| 530 | ||
| 531 | return 0; | |
| 532 | } | |
| 533 | ||
| 534 | #ifdef CONFIG_POST | |
| 535 | /* | |
| 536 | * Returns 1 if keys pressed to start the power-on long-running tests | |
| 537 | * Called from board_init_f(). | |
| 538 | */ | |
| 539 | int post_hotkeys_pressed(void) | |
| 540 | { | |
| 541 | return (ctrlc()); | |
| 542 | } | |
| 543 | #endif |