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4745acaa | 1 | /* |
1095493a | 2 | * (C) Copyright 2007-2009 |
4745acaa SR |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | * | |
23 | */ | |
24 | ||
25 | #include <common.h> | |
26 | #include <ppc4xx.h> | |
4745acaa | 27 | #include <i2c.h> |
bf8324e4 SR |
28 | #include <libfdt.h> |
29 | #include <fdt_support.h> | |
10efa024 | 30 | #include <netdev.h> |
c7c6da23 SR |
31 | #include <asm/processor.h> |
32 | #include <asm/io.h> | |
33 | #include <asm/gpio.h> | |
34 | #include <asm/4xx_pcie.h> | |
06dfaeef | 35 | #include <asm/errno.h> |
4745acaa | 36 | |
1218abf1 WD |
37 | DECLARE_GLOBAL_DATA_PTR; |
38 | ||
4745acaa SR |
39 | int board_early_init_f (void) |
40 | { | |
41 | unsigned long mfr; | |
4745acaa SR |
42 | |
43 | /*----------------------------------------------------------------------+ | |
44 | * Interrupt controller setup for the Katmai 440SPe Evaluation board. | |
45 | *-----------------------------------------------------------------------+ | |
46 | *-----------------------------------------------------------------------+ | |
47 | * Interrupt | Source | Pol. | Sensi.| Crit. | | |
48 | *-----------+-----------------------------------+-------+-------+-------+ | |
49 | * IRQ 00 | UART0 | High | Level | Non | | |
50 | * IRQ 01 | UART1 | High | Level | Non | | |
51 | * IRQ 02 | IIC0 | High | Level | Non | | |
52 | * IRQ 03 | IIC1 | High | Level | Non | | |
53 | * IRQ 04 | PCI0X0 MSG IN | High | Level | Non | | |
54 | * IRQ 05 | PCI0X0 CMD Write | High | Level | Non | | |
55 | * IRQ 06 | PCI0X0 Power Mgt | High | Level | Non | | |
56 | * IRQ 07 | PCI0X0 VPD Access | Rising| Edge | Non | | |
57 | * IRQ 08 | PCI0X0 MSI level 0 | High | Lvl/ed| Non | | |
58 | * IRQ 09 | External IRQ 15 - (PCI-Express) | pgm H | Pgm | Non | | |
59 | * IRQ 10 | UIC2 Non-critical Int. | NA | NA | Non | | |
60 | * IRQ 11 | UIC2 Critical Interrupt | NA | NA | Crit | | |
61 | * IRQ 12 | PCI Express MSI Level 0 | Rising| Edge | Non | | |
62 | * IRQ 13 | PCI Express MSI Level 1 | Rising| Edge | Non | | |
63 | * IRQ 14 | PCI Express MSI Level 2 | Rising| Edge | Non | | |
64 | * IRQ 15 | PCI Express MSI Level 3 | Rising| Edge | Non | | |
65 | * IRQ 16 | UIC3 Non-critical Int. | NA | NA | Non | | |
66 | * IRQ 17 | UIC3 Critical Interrupt | NA | NA | Crit | | |
67 | * IRQ 18 | External IRQ 14 - (PCI-Express) | Pgm | Pgm | Non | | |
68 | * IRQ 19 | DMA Channel 0 FIFO Full | High | Level | Non | | |
69 | * IRQ 20 | DMA Channel 0 Stat FIFO | High | Level | Non | | |
70 | * IRQ 21 | DMA Channel 1 FIFO Full | High | Level | Non | | |
71 | * IRQ 22 | DMA Channel 1 Stat FIFO | High | Level | Non | | |
72 | * IRQ 23 | I2O Inbound Doorbell | High | Level | Non | | |
73 | * IRQ 24 | Inbound Post List FIFO Not Empt | High | Level | Non | | |
74 | * IRQ 25 | I2O Region 0 LL PLB Write | High | Level | Non | | |
75 | * IRQ 26 | I2O Region 1 LL PLB Write | High | Level | Non | | |
76 | * IRQ 27 | I2O Region 0 HB PLB Write | High | Level | Non | | |
77 | * IRQ 28 | I2O Region 1 HB PLB Write | High | Level | Non | | |
78 | * IRQ 29 | GPT Down Count Timer | Rising| Edge | Non | | |
79 | * IRQ 30 | UIC1 Non-critical Int. | NA | NA | Non | | |
80 | * IRQ 31 | UIC1 Critical Interrupt | NA | NA | Crit. | | |
81 | *------------------------------------------------------------------------ | |
82 | * IRQ 32 | Ext. IRQ 13 - (PCI-Express) |pgm (H)|pgm/Lvl| Non | | |
83 | * IRQ 33 | MAL Serr | High | Level | Non | | |
84 | * IRQ 34 | MAL Txde | High | Level | Non | | |
85 | * IRQ 35 | MAL Rxde | High | Level | Non | | |
86 | * IRQ 36 | DMC CE or DMC UE | High | Level | Non | | |
87 | * IRQ 37 | EBC or UART2 | High |Lvl Edg| Non | | |
88 | * IRQ 38 | MAL TX EOB | High | Level | Non | | |
89 | * IRQ 39 | MAL RX EOB | High | Level | Non | | |
90 | * IRQ 40 | PCIX0 MSI Level 1 | High |Lvl Edg| Non | | |
91 | * IRQ 41 | PCIX0 MSI level 2 | High |Lvl Edg| Non | | |
92 | * IRQ 42 | PCIX0 MSI level 3 | High |Lvl Edg| Non | | |
93 | * IRQ 43 | L2 Cache | Risin | Edge | Non | | |
94 | * IRQ 44 | GPT Compare Timer 0 | Risin | Edge | Non | | |
95 | * IRQ 45 | GPT Compare Timer 1 | Risin | Edge | Non | | |
96 | * IRQ 46 | GPT Compare Timer 2 | Risin | Edge | Non | | |
97 | * IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | | |
98 | * IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | | |
99 | * IRQ 49 | Ext. IRQ 12 - PCI-X |pgm/Fal|pgm/Lvl| Non | | |
100 | * IRQ 50 | Ext. IRQ 11 - |pgm (H)|pgm/Lvl| Non | | |
101 | * IRQ 51 | Ext. IRQ 10 - |pgm (H)|pgm/Lvl| Non | | |
102 | * IRQ 52 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | | |
103 | * IRQ 53 | Ext. IRQ 8 |pgm (H)|pgm/Lvl| Non | | |
104 | * IRQ 54 | DMA Error | High | Level | Non | | |
105 | * IRQ 55 | DMA I2O Error | High | Level | Non | | |
106 | * IRQ 56 | Serial ROM | High | Level | Non | | |
107 | * IRQ 57 | PCIX0 Error | High | Edge | Non | | |
108 | * IRQ 58 | Ext. IRQ 7- |pgm (H)|pgm/Lvl| Non | | |
109 | * IRQ 59 | Ext. IRQ 6- |pgm (H)|pgm/Lvl| Non | | |
110 | * IRQ 60 | EMAC0 Interrupt | High | Level | Non | | |
111 | * IRQ 61 | EMAC0 Wake-up | High | Level | Non | | |
112 | * IRQ 62 | Reserved | High | Level | Non | | |
113 | * IRQ 63 | XOR | High | Level | Non | | |
114 | *----------------------------------------------------------------------- | |
115 | * IRQ 64 | PE0 AL | High | Level | Non | | |
116 | * IRQ 65 | PE0 VPD Access | Risin | Edge | Non | | |
117 | * IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | | |
118 | * IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | | |
119 | * IRQ 68 | PE0 TCR | High | Level | Non | | |
120 | * IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | | |
121 | * IRQ 70 | PE0 DCR Error | High | Level | Non | | |
122 | * IRQ 71 | Reserved | N/A | N/A | Non | | |
123 | * IRQ 72 | PE1 AL | High | Level | Non | | |
124 | * IRQ 73 | PE1 VPD Access | Risin | Edge | Non | | |
125 | * IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | | |
126 | * IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | | |
127 | * IRQ 76 | PE1 TCR | High | Level | Non | | |
128 | * IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | | |
129 | * IRQ 78 | PE1 DCR Error | High | Level | Non | | |
130 | * IRQ 79 | Reserved | N/A | N/A | Non | | |
131 | * IRQ 80 | PE2 AL | High | Level | Non | | |
132 | * IRQ 81 | PE2 VPD Access | Risin | Edge | Non | | |
133 | * IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | | |
134 | * IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | | |
135 | * IRQ 84 | PE2 TCR | High | Level | Non | | |
136 | * IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | | |
137 | * IRQ 86 | PE2 DCR Error | High | Level | Non | | |
138 | * IRQ 87 | Reserved | N/A | N/A | Non | | |
139 | * IRQ 88 | External IRQ(5) | Progr | Progr | Non | | |
140 | * IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | | |
141 | * IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | | |
142 | * IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | | |
143 | * IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | | |
144 | * IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | | |
145 | * IRQ 94 | Reserved | N/A | N/A | Non | | |
146 | * IRQ 95 | Reserved | N/A | N/A | Non | | |
147 | *----------------------------------------------------------------------- | |
148 | * IRQ 96 | PE0 INTA | High | Level | Non | | |
149 | * IRQ 97 | PE0 INTB | High | Level | Non | | |
150 | * IRQ 98 | PE0 INTC | High | Level | Non | | |
151 | * IRQ 99 | PE0 INTD | High | Level | Non | | |
152 | * IRQ 100 | PE1 INTA | High | Level | Non | | |
153 | * IRQ 101 | PE1 INTB | High | Level | Non | | |
154 | * IRQ 102 | PE1 INTC | High | Level | Non | | |
155 | * IRQ 103 | PE1 INTD | High | Level | Non | | |
156 | * IRQ 104 | PE2 INTA | High | Level | Non | | |
157 | * IRQ 105 | PE2 INTB | High | Level | Non | | |
158 | * IRQ 106 | PE2 INTC | High | Level | Non | | |
159 | * IRQ 107 | PE2 INTD | Risin | Edge | Non | | |
160 | * IRQ 108 | PCI Express MSI Level 4 | Risin | Edge | Non | | |
161 | * IRQ 109 | PCI Express MSI Level 5 | Risin | Edge | Non | | |
162 | * IRQ 110 | PCI Express MSI Level 6 | Risin | Edge | Non | | |
163 | * IRQ 111 | PCI Express MSI Level 7 | Risin | Edge | Non | | |
164 | * IRQ 116 | PCI Express MSI Level 12 | Risin | Edge | Non | | |
165 | * IRQ 112 | PCI Express MSI Level 8 | Risin | Edge | Non | | |
166 | * IRQ 113 | PCI Express MSI Level 9 | Risin | Edge | Non | | |
167 | * IRQ 114 | PCI Express MSI Level 10 | Risin | Edge | Non | | |
168 | * IRQ 115 | PCI Express MSI Level 11 | Risin | Edge | Non | | |
169 | * IRQ 117 | PCI Express MSI Level 13 | Risin | Edge | Non | | |
170 | * IRQ 118 | PCI Express MSI Level 14 | Risin | Edge | Non | | |
171 | * IRQ 119 | PCI Express MSI Level 15 | Risin | Edge | Non | | |
172 | * IRQ 120 | PCI Express MSI Level 16 | Risin | Edge | Non | | |
173 | * IRQ 121 | PCI Express MSI Level 17 | Risin | Edge | Non | | |
174 | * IRQ 122 | PCI Express MSI Level 18 | Risin | Edge | Non | | |
175 | * IRQ 123 | PCI Express MSI Level 19 | Risin | Edge | Non | | |
176 | * IRQ 124 | PCI Express MSI Level 20 | Risin | Edge | Non | | |
177 | * IRQ 125 | PCI Express MSI Level 21 | Risin | Edge | Non | | |
178 | * IRQ 126 | PCI Express MSI Level 22 | Risin | Edge | Non | | |
179 | * IRQ 127 | PCI Express MSI Level 23 | Risin | Edge | Non | | |
180 | *-----------+-----------------------------------+-------+-------+-------+ */ | |
181 | /*-------------------------------------------------------------------------+ | |
182 | * Put UICs in PowerPC440SPemode. | |
183 | * Initialise UIC registers. Clear all interrupts. Disable all interrupts. | |
184 | * Set critical interrupt values. Set interrupt polarities. Set interrupt | |
185 | * trigger levels. Make bit 0 High priority. Clear all interrupts again. | |
186 | *------------------------------------------------------------------------*/ | |
952e7760 SR |
187 | mtdcr (UIC3SR, 0xffffffff); /* Clear all interrupts */ |
188 | mtdcr (UIC3ER, 0x00000000); /* disable all interrupts */ | |
189 | mtdcr (UIC3CR, 0x00000000); /* Set Critical / Non Critical interrupts: */ | |
190 | mtdcr (UIC3PR, 0xffffffff); /* Set Interrupt Polarities*/ | |
191 | mtdcr (UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ | |
192 | mtdcr (UIC3VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ | |
193 | mtdcr (UIC3SR, 0x00000000); /* clear all interrupts*/ | |
194 | mtdcr (UIC3SR, 0xffffffff); /* clear all interrupts*/ | |
195 | ||
196 | ||
197 | mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ | |
198 | mtdcr (UIC2ER, 0x00000000); /* disable all interrupts*/ | |
199 | mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts*/ | |
200 | mtdcr (UIC2PR, 0xebebebff); /* Set Interrupt Polarities*/ | |
201 | mtdcr (UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ | |
202 | mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ | |
203 | mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ | |
204 | mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ | |
205 | ||
206 | mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts*/ | |
207 | mtdcr (UIC1ER, 0x00000000); /* disable all interrupts*/ | |
208 | mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts*/ | |
209 | mtdcr (UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ | |
210 | mtdcr (UIC1TR, 0x001f8040); /* Set Interrupt Trigger Levels*/ | |
211 | mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ | |
212 | mtdcr (UIC1SR, 0x00000000); /* clear all interrupts*/ | |
213 | mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts*/ | |
214 | ||
215 | mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ | |
216 | mtdcr (UIC0ER, 0x00000000); /* disable all interrupts excepted cascade to be checked */ | |
217 | mtdcr (UIC0CR, 0x00104001); /* Set Critical / Non Critical interrupts*/ | |
218 | mtdcr (UIC0PR, 0xffffffff); /* Set Interrupt Polarities*/ | |
219 | mtdcr (UIC0TR, 0x010f0004); /* Set Interrupt Trigger Levels */ | |
220 | mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ | |
221 | mtdcr (UIC0SR, 0x00000000); /* clear all interrupts*/ | |
222 | mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts*/ | |
4745acaa | 223 | |
d1c3b275 | 224 | mfsdr(SDR0_MFR, mfr); |
a27044b1 | 225 | mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ |
d1c3b275 | 226 | mtsdr(SDR0_MFR, mfr); |
4745acaa | 227 | |
6d0f6bcf | 228 | mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0); |
4745acaa | 229 | |
6d0f6bcf JCPV |
230 | out32(GPIO0_OR, CONFIG_SYS_GPIO_OR); |
231 | out32(GPIO0_ODR, CONFIG_SYS_GPIO_ODR); | |
232 | out32(GPIO0_TCR, CONFIG_SYS_GPIO_TCR); | |
4745acaa SR |
233 | |
234 | return 0; | |
235 | } | |
236 | ||
237 | int checkboard (void) | |
238 | { | |
239 | char *s = getenv("serial#"); | |
240 | ||
241 | printf("Board: Katmai - AMCC 440SPe Evaluation Board"); | |
242 | if (s != NULL) { | |
243 | puts(", serial# "); | |
244 | puts(s); | |
245 | } | |
246 | putc('\n'); | |
247 | ||
248 | return 0; | |
249 | } | |
250 | ||
845c6c95 | 251 | /* |
a47a12be | 252 | * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with |
845c6c95 SR |
253 | * board specific values. |
254 | */ | |
255 | u32 ddr_wrdtr(u32 default_val) { | |
256 | return (SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_180_DEG_ADV | 0x823); | |
257 | } | |
258 | ||
259 | u32 ddr_clktr(u32 default_val) { | |
260 | return (SDRAM_CLKTR_CLKP_90_DEG_ADV); | |
261 | } | |
262 | ||
4745acaa | 263 | #if defined(CONFIG_PCI) |
b0b86746 | 264 | int board_pcie_card_present(int port) |
ba58e4c9 SR |
265 | { |
266 | u32 val; | |
267 | ||
268 | val = in32(GPIO0_IR); | |
269 | switch (port) { | |
270 | case 0: | |
6d0f6bcf | 271 | return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0)); |
ba58e4c9 | 272 | case 1: |
6d0f6bcf | 273 | return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1)); |
ba58e4c9 | 274 | case 2: |
6d0f6bcf | 275 | return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2)); |
ba58e4c9 SR |
276 | default: |
277 | return 0; | |
278 | } | |
279 | } | |
4745acaa SR |
280 | #endif /* defined(CONFIG_PCI) */ |
281 | ||
10efa024 BW |
282 | int board_eth_init(bd_t *bis) |
283 | { | |
cef0efaf | 284 | cpu_eth_init(bis); |
10efa024 BW |
285 | return pci_eth_init(bis); |
286 | } |