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566806ca SR |
1 | /* |
2 | * (C) Copyright 2007 | |
3 | * Stefan Roese, DENX Software Engineering, sr@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
b36df561 SR |
25 | #include <asm/ppc4xx.h> |
26 | #include <asm/ppc405.h> | |
566806ca | 27 | #include <libfdt.h> |
8697e6a1 | 28 | #include <fdt_support.h> |
566806ca | 29 | #include <asm/processor.h> |
353f2688 | 30 | #include <asm/io.h> |
06dfaeef | 31 | #include <asm/errno.h> |
566806ca SR |
32 | |
33 | #if defined(CONFIG_PCI) | |
34 | #include <pci.h> | |
35 | #include <asm/4xx_pcie.h> | |
36 | #endif | |
37 | ||
38 | DECLARE_GLOBAL_DATA_PTR; | |
39 | ||
6d0f6bcf | 40 | extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
566806ca | 41 | |
9998b136 SR |
42 | static int board_cpld_version(void) |
43 | { | |
44 | u32 cpld; | |
45 | ||
46 | cpld = in_be32((void *)CONFIG_SYS_FPGA_FIFO_BASE); | |
47 | if ((cpld & CONFIG_SYS_FPGA_MAGIC_MASK) != CONFIG_SYS_FPGA_MAGIC) { | |
48 | /* | |
49 | * Magic not found -> "old" CPLD revision which needs | |
50 | * the "old" EBC configuration | |
51 | */ | |
52 | mtebc(PB2AP, EBC_BXAP_BME_ENABLED | EBC_BXAP_FWT_ENCODE(5) | | |
53 | EBC_BXAP_BWT_ENCODE(0) | EBC_BXAP_BCE_DISABLE | | |
54 | EBC_BXAP_BCT_2TRANS | EBC_BXAP_CSN_ENCODE(0) | | |
55 | EBC_BXAP_OEN_ENCODE(0) | EBC_BXAP_WBN_ENCODE(3) | | |
56 | EBC_BXAP_WBF_ENCODE(0) | EBC_BXAP_TH_ENCODE(4) | | |
57 | EBC_BXAP_RE_DISABLED | EBC_BXAP_SOR_DELAYED | | |
58 | EBC_BXAP_BEM_WRITEONLY | EBC_BXAP_PEN_DISABLED); | |
59 | ||
60 | /* | |
61 | * Return 0 for "old" CPLD version | |
62 | */ | |
63 | return 0; | |
64 | } | |
65 | ||
66 | /* | |
67 | * Magic found -> "new" CPLD revision which needs no new | |
68 | * EBC configuration | |
69 | */ | |
70 | return (cpld & CONFIG_SYS_FPGA_VER_MASK) >> 8; | |
71 | } | |
72 | ||
566806ca SR |
73 | /* |
74 | * Board early initialization function | |
75 | */ | |
76 | int board_early_init_f (void) | |
77 | { | |
78 | u32 val; | |
79 | ||
80 | /*--------------------------------------------------------------------+ | |
81 | | Interrupt controller setup for the AMCC 405EX(r) PINE evaluation board. | |
82 | +--------------------------------------------------------------------+ | |
83 | +---------------------------------------------------------------------+ | |
84 | |Interrupt| Source | Pol. | Sensi.| Crit. | | |
85 | +---------+-----------------------------------+-------+-------+-------+ | |
86 | | IRQ 00 | UART0 | High | Level | Non | | |
87 | | IRQ 01 | UART1 | High | Level | Non | | |
88 | | IRQ 02 | IIC0 | High | Level | Non | | |
89 | | IRQ 03 | TBD | High | Level | Non | | |
90 | | IRQ 04 | TBD | High | Level | Non | | |
91 | | IRQ 05 | EBM | High | Level | Non | | |
92 | | IRQ 06 | BGI | High | Level | Non | | |
93 | | IRQ 07 | IIC1 | Rising| Edge | Non | | |
94 | | IRQ 08 | SPI | High | Lvl/ed| Non | | |
95 | | IRQ 09 | External IRQ 0 - (PCI-Express) | pgm H | Pgm | Non | | |
96 | | IRQ 10 | MAL TX EOB | High | Level | Non | | |
97 | | IRQ 11 | MAL RX EOB | High | Level | Non | | |
98 | | IRQ 12 | DMA Channel 0 FIFO Full | High | Level | Non | | |
99 | | IRQ 13 | DMA Channel 0 Stat FIFO | High | Level | Non | | |
100 | | IRQ 14 | DMA Channel 1 FIFO Full | High | Level | Non | | |
101 | | IRQ 15 | DMA Channel 1 Stat FIFO | High | Level | Non | | |
102 | | IRQ 16 | PCIE0 AL | high | Level | Non | | |
103 | | IRQ 17 | PCIE0 VPD access | rising| Edge | Non | | |
104 | | IRQ 18 | PCIE0 hot reset request | rising| Edge | Non | | |
105 | | IRQ 19 | PCIE0 hot reset request | faling| Edge | Non | | |
106 | | IRQ 20 | PCIE0 TCR | High | Level | Non | | |
107 | | IRQ 21 | PCIE0 MSI level0 | High | Level | Non | | |
108 | | IRQ 22 | PCIE0 MSI level1 | High | Level | Non | | |
109 | | IRQ 23 | Security EIP-94 | High | Level | Non | | |
110 | | IRQ 24 | EMAC0 interrupt | High | Level | Non | | |
111 | | IRQ 25 | EMAC1 interrupt | High | Level | Non | | |
112 | | IRQ 26 | PCIE0 MSI level2 | High | Level | Non | | |
113 | | IRQ 27 | External IRQ 4 | pgm H | Pgm | Non | | |
114 | | IRQ 28 | UIC2 Non-critical Int. | High | Level | Non | | |
115 | | IRQ 29 | UIC2 Critical Interrupt | High | Level | Crit. | | |
116 | | IRQ 30 | UIC1 Non-critical Int. | High | Level | Non | | |
117 | | IRQ 31 | UIC1 Critical Interrupt | High | Level | Crit. | | |
118 | |---------------------------------------------------------------------- | |
119 | | IRQ 32 | MAL Serr | High | Level | Non | | |
120 | | IRQ 33 | MAL Txde | High | Level | Non | | |
121 | | IRQ 34 | MAL Rxde | High | Level | Non | | |
122 | | IRQ 35 | PCIE0 bus master VC0 |falling| Edge | Non | | |
123 | | IRQ 36 | PCIE0 DCR Error | High | Level | Non | | |
124 | | IRQ 37 | EBC | High |Lvl Edg| Non | | |
125 | | IRQ 38 | NDFC | High | Level | Non | | |
126 | | IRQ 39 | GPT Compare Timer 8 | Risin | Edge | Non | | |
127 | | IRQ 40 | GPT Compare Timer 9 | Risin | Edge | Non | | |
128 | | IRQ 41 | PCIE1 AL | high | Level | Non | | |
129 | | IRQ 42 | PCIE1 VPD access | rising| edge | Non | | |
130 | | IRQ 43 | PCIE1 hot reset request | rising| Edge | Non | | |
131 | | IRQ 44 | PCIE1 hot reset request | faling| Edge | Non | | |
132 | | IRQ 45 | PCIE1 TCR | High | Level | Non | | |
133 | | IRQ 46 | PCIE1 bus master VC0 |falling| Edge | Non | | |
134 | | IRQ 47 | GPT Compare Timer 3 | Risin | Edge | Non | | |
135 | | IRQ 48 | GPT Compare Timer 4 | Risin | Edge | Non | | |
136 | | IRQ 49 | Ext. IRQ 7 |pgm/Fal|pgm/Lvl| Non | | |
137 | | IRQ 50 | Ext. IRQ 8 - |pgm (H)|pgm/Lvl| Non | | |
138 | | IRQ 51 | Ext. IRQ 9 |pgm (H)|pgm/Lvl| Non | | |
139 | | IRQ 52 | GPT Compare Timer 5 | high | Edge | Non | | |
140 | | IRQ 53 | GPT Compare Timer 6 | high | Edge | Non | | |
141 | | IRQ 54 | GPT Compare Timer 7 | high | Edge | Non | | |
142 | | IRQ 55 | Serial ROM | High | Level | Non | | |
143 | | IRQ 56 | GPT Decrement Pulse | High | Level | Non | | |
144 | | IRQ 57 | Ext. IRQ 2 |pgm/Fal|pgm/Lvl| Non | | |
145 | | IRQ 58 | Ext. IRQ 5 |pgm/Fal|pgm/Lvl| Non | | |
146 | | IRQ 59 | Ext. IRQ 6 |pgm/Fal|pgm/Lvl| Non | | |
147 | | IRQ 60 | EMAC0 Wake-up | High | Level | Non | | |
148 | | IRQ 61 | Ext. IRQ 1 |pgm/Fal|pgm/Lvl| Non | | |
149 | | IRQ 62 | EMAC1 Wake-up | High | Level | Non | | |
150 | |---------------------------------------------------------------------- | |
151 | | IRQ 64 | PE0 AL | High | Level | Non | | |
152 | | IRQ 65 | PE0 VPD Access | Risin | Edge | Non | | |
153 | | IRQ 66 | PE0 Hot Reset Request | Risin | Edge | Non | | |
154 | | IRQ 67 | PE0 Hot Reset Request | Falli | Edge | Non | | |
155 | | IRQ 68 | PE0 TCR | High | Level | Non | | |
156 | | IRQ 69 | PE0 BusMaster VCO | Falli | Edge | Non | | |
157 | | IRQ 70 | PE0 DCR Error | High | Level | Non | | |
158 | | IRQ 71 | Reserved | N/A | N/A | Non | | |
159 | | IRQ 72 | PE1 AL | High | Level | Non | | |
160 | | IRQ 73 | PE1 VPD Access | Risin | Edge | Non | | |
161 | | IRQ 74 | PE1 Hot Reset Request | Risin | Edge | Non | | |
162 | | IRQ 75 | PE1 Hot Reset Request | Falli | Edge | Non | | |
163 | | IRQ 76 | PE1 TCR | High | Level | Non | | |
164 | | IRQ 77 | PE1 BusMaster VCO | Falli | Edge | Non | | |
165 | | IRQ 78 | PE1 DCR Error | High | Level | Non | | |
166 | | IRQ 79 | Reserved | N/A | N/A | Non | | |
167 | | IRQ 80 | PE2 AL | High | Level | Non | | |
168 | | IRQ 81 | PE2 VPD Access | Risin | Edge | Non | | |
169 | | IRQ 82 | PE2 Hot Reset Request | Risin | Edge | Non | | |
170 | | IRQ 83 | PE2 Hot Reset Request | Falli | Edge | Non | | |
171 | | IRQ 84 | PE2 TCR | High | Level | Non | | |
172 | | IRQ 85 | PE2 BusMaster VCO | Falli | Edge | Non | | |
173 | | IRQ 86 | PE2 DCR Error | High | Level | Non | | |
174 | | IRQ 87 | Reserved | N/A | N/A | Non | | |
175 | | IRQ 88 | External IRQ(5) | Progr | Progr | Non | | |
176 | | IRQ 89 | External IRQ 4 - Ethernet | Progr | Progr | Non | | |
177 | | IRQ 90 | External IRQ 3 - PCI-X | Progr | Progr | Non | | |
178 | | IRQ 91 | External IRQ 2 - PCI-X | Progr | Progr | Non | | |
179 | | IRQ 92 | External IRQ 1 - PCI-X | Progr | Progr | Non | | |
180 | | IRQ 93 | External IRQ 0 - PCI-X | Progr | Progr | Non | | |
181 | | IRQ 94 | Reserved | N/A | N/A | Non | | |
182 | | IRQ 95 | Reserved | N/A | N/A | Non | | |
183 | |--------------------------------------------------------------------- | |
184 | +---------+-----------------------------------+-------+-------+------*/ | |
185 | /*--------------------------------------------------------------------+ | |
186 | | Initialise UIC registers. Clear all interrupts. Disable all | |
187 | | interrupts. | |
188 | | Set critical interrupt values. Set interrupt polarities. Set | |
189 | | interrupt trigger levels. Make bit 0 High priority. Clear all | |
190 | | interrupts again. | |
191 | +-------------------------------------------------------------------*/ | |
192 | ||
952e7760 SR |
193 | mtdcr (UIC2SR, 0xffffffff); /* Clear all interrupts */ |
194 | mtdcr (UIC2ER, 0x00000000); /* disable all interrupts */ | |
195 | mtdcr (UIC2CR, 0x00000000); /* Set Critical / Non Critical interrupts */ | |
196 | mtdcr (UIC2PR, 0xf7ffffff); /* Set Interrupt Polarities */ | |
197 | mtdcr (UIC2TR, 0x01e1fff8); /* Set Interrupt Trigger Levels */ | |
198 | mtdcr (UIC2VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ | |
199 | mtdcr (UIC2SR, 0x00000000); /* clear all interrupts */ | |
200 | mtdcr (UIC2SR, 0xffffffff); /* clear all interrupts */ | |
566806ca | 201 | |
952e7760 SR |
202 | mtdcr (UIC1SR, 0xffffffff); /* Clear all interrupts */ |
203 | mtdcr (UIC1ER, 0x00000000); /* disable all interrupts */ | |
204 | mtdcr (UIC1CR, 0x00000000); /* Set Critical / Non Critical interrupts */ | |
205 | mtdcr (UIC1PR, 0xfffac785); /* Set Interrupt Polarities */ | |
206 | mtdcr (UIC1TR, 0x001d0040); /* Set Interrupt Trigger Levels */ | |
207 | mtdcr (UIC1VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ | |
208 | mtdcr (UIC1SR, 0x00000000); /* clear all interrupts */ | |
209 | mtdcr (UIC1SR, 0xffffffff); /* clear all interrupts */ | |
566806ca | 210 | |
952e7760 SR |
211 | mtdcr (UIC0SR, 0xffffffff); /* Clear all interrupts */ |
212 | mtdcr (UIC0ER, 0x0000000a); /* Disable all interrupts */ | |
566806ca | 213 | /* Except cascade UIC0 and UIC1 */ |
952e7760 SR |
214 | mtdcr (UIC0CR, 0x00000000); /* Set Critical / Non Critical interrupts */ |
215 | mtdcr (UIC0PR, 0xffbfefef); /* Set Interrupt Polarities */ | |
216 | mtdcr (UIC0TR, 0x00007000); /* Set Interrupt Trigger Levels */ | |
217 | mtdcr (UIC0VR, 0x00000001); /* Set Vect base=0,INT31 Highest priority */ | |
218 | mtdcr (UIC0SR, 0x00000000); /* clear all interrupts */ | |
219 | mtdcr (UIC0SR, 0xffffffff); /* clear all interrupts */ | |
566806ca SR |
220 | |
221 | /* | |
222 | * Note: Some cores are still in reset when the chip starts, so | |
223 | * take them out of reset | |
224 | */ | |
225 | mtsdr(SDR0_SRST, 0); | |
226 | ||
566806ca SR |
227 | /* Configure 405EX for NAND usage */ |
228 | val = SDR0_CUST0_MUX_NDFC_SEL | | |
229 | SDR0_CUST0_NDFC_ENABLE | | |
230 | SDR0_CUST0_NDFC_BW_8_BIT | | |
231 | SDR0_CUST0_NRB_BUSY | | |
6d0f6bcf | 232 | (0x80000000 >> (28 + CONFIG_SYS_NAND_CS)); |
566806ca | 233 | mtsdr(SDR0_CUST0, val); |
7cfc12a7 SR |
234 | |
235 | /* | |
236 | * Configure PFC (Pin Function Control) registers | |
237 | * -> Enable USB | |
238 | */ | |
239 | val = SDR0_PFC1_USBEN | SDR0_PFC1_USBBIGEN | SDR0_PFC1_GPT_FREQ; | |
240 | mtsdr(SDR0_PFC1, val); | |
566806ca | 241 | |
9998b136 SR |
242 | /* |
243 | * The CPLD version detection has to be the first access to | |
244 | * the CPLD, so we need to make this access this early and | |
245 | * save the CPLD version for later. | |
246 | */ | |
247 | gd->board_type = board_cpld_version(); | |
248 | ||
a0dd99d5 SR |
249 | /* |
250 | * Configure FPGA register with PCIe reset | |
251 | */ | |
6d0f6bcf | 252 | out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4); /* assert PCIe reset */ |
a0dd99d5 | 253 | mdelay(50); |
6d0f6bcf | 254 | out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7); /* deassert PCIe reset */ |
a0dd99d5 | 255 | |
566806ca SR |
256 | return 0; |
257 | } | |
258 | ||
259 | int misc_init_r(void) | |
260 | { | |
5a1aceb0 | 261 | #ifdef CONFIG_ENV_IS_IN_FLASH |
566806ca SR |
262 | /* Monitor protection ON by default */ |
263 | flash_protect(FLAG_PROTECT_SET, | |
6d0f6bcf | 264 | -CONFIG_SYS_MONITOR_LEN, |
566806ca SR |
265 | 0xffffffff, |
266 | &flash_info[0]); | |
267 | #endif | |
268 | ||
269 | return 0; | |
270 | } | |
271 | ||
70fab190 | 272 | static int is_405exr(void) |
353f2688 SR |
273 | { |
274 | u32 pvr = get_pvr(); | |
275 | ||
70fab190 SR |
276 | if (pvr & 0x00000004) |
277 | return 0; /* bit 2 set -> 405EX */ | |
278 | ||
279 | return 1; /* bit 2 cleared -> 405EXr */ | |
280 | } | |
281 | ||
282 | int board_emac_count(void) | |
283 | { | |
353f2688 SR |
284 | /* |
285 | * 405EXr only has one EMAC interface, 405EX has two | |
286 | */ | |
70fab190 | 287 | if (is_405exr()) |
353f2688 SR |
288 | return 1; |
289 | else | |
290 | return 2; | |
291 | } | |
292 | ||
b0b86746 SR |
293 | /* |
294 | * Override the weak default implementation and return the | |
295 | * last PCIe slot number (max number - 1). | |
296 | */ | |
297 | int board_pcie_last(void) | |
353f2688 | 298 | { |
353f2688 SR |
299 | /* |
300 | * 405EXr only has one EMAC interface, 405EX has two | |
301 | */ | |
70fab190 | 302 | if (is_405exr()) |
b0b86746 | 303 | return 1 - 1; |
353f2688 | 304 | else |
b0b86746 | 305 | return 2 - 1; |
353f2688 SR |
306 | } |
307 | ||
566806ca SR |
308 | int checkboard (void) |
309 | { | |
f0c0b3a9 WD |
310 | char buf[64]; |
311 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
566806ca | 312 | |
70fab190 | 313 | if (is_405exr()) |
353f2688 SR |
314 | printf("Board: Haleakala - AMCC PPC405EXr Evaluation Board"); |
315 | else | |
316 | printf("Board: Kilauea - AMCC PPC405EX Evaluation Board"); | |
566806ca | 317 | |
f0c0b3a9 | 318 | if (i > 0) { |
566806ca | 319 | puts(", serial# "); |
f0c0b3a9 | 320 | puts(buf); |
566806ca | 321 | } |
9998b136 | 322 | printf(" (CPLD rev. %ld)\n", gd->board_type); |
566806ca SR |
323 | |
324 | return (0); | |
325 | } |