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6e7fb6ea SR |
1 | /* |
2 | * (C) Copyright 2005 | |
3 | * John Otken, jotken@softadvances.com | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #include <common.h> | |
25 | #include <command.h> | |
b36df561 | 26 | #include <asm/ppc4xx.h> |
6e7fb6ea | 27 | #include <asm/processor.h> |
b14ca4b6 | 28 | #include <asm/ppc4xx-isram.h> |
6e7fb6ea SR |
29 | #include <spd_sdram.h> |
30 | #include "epld.h" | |
31 | ||
d87080b7 | 32 | DECLARE_GLOBAL_DATA_PTR; |
6e7fb6ea | 33 | |
6d0f6bcf | 34 | extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ |
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35 | |
36 | ||
37 | /************************************************************************* | |
38 | * int board_early_init_f() | |
39 | * | |
40 | ************************************************************************/ | |
41 | int board_early_init_f(void) | |
42 | { | |
a27044b1 SR |
43 | u32 mfr; |
44 | ||
d1c3b275 SR |
45 | mtebc( PB0AP, 0x03800000 ); /* set chip selects */ |
46 | mtebc( PB0CR, 0xffc58000 ); /* ebc0_b0cr, 4MB at 0xffc00000 CS0 */ | |
47 | mtebc( PB1AP, 0x03800000 ); | |
48 | mtebc( PB1CR, 0xff018000 ); /* ebc0_b1cr, 1MB at 0xff000000 CS1 */ | |
49 | mtebc( PB2AP, 0x03800000 ); | |
50 | mtebc( PB2CR, 0xff838000 ); /* ebc0_b2cr, 2MB at 0xff800000 CS2 */ | |
6e7fb6ea | 51 | |
952e7760 SR |
52 | mtdcr( UIC1SR, 0xffffffff ); /* Clear all interrupts */ |
53 | mtdcr( UIC1ER, 0x00000000 ); /* disable all interrupts */ | |
54 | mtdcr( UIC1CR, 0x00000000 ); /* Set Critical / Non Critical interrupts */ | |
55 | mtdcr( UIC1PR, 0x7fff83ff ); /* Set Interrupt Polarities */ | |
56 | mtdcr( UIC1TR, 0x001f8000 ); /* Set Interrupt Trigger Levels */ | |
57 | mtdcr( UIC1VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ | |
58 | mtdcr( UIC1SR, 0x00000000 ); /* clear all interrupts */ | |
59 | mtdcr( UIC1SR, 0xffffffff ); | |
6e7fb6ea | 60 | |
952e7760 SR |
61 | mtdcr( UIC0SR, 0xffffffff ); /* Clear all interrupts */ |
62 | mtdcr( UIC0ER, 0x00000000 ); /* disable all interrupts excepted cascade */ | |
63 | mtdcr( UIC0CR, 0x00000001 ); /* Set Critical / Non Critical interrupts */ | |
64 | mtdcr( UIC0PR, 0xffffffff ); /* Set Interrupt Polarities */ | |
65 | mtdcr( UIC0TR, 0x01000004 ); /* Set Interrupt Trigger Levels */ | |
66 | mtdcr( UIC0VR, 0x00000001 ); /* Set Vect base=0,INT31 Highest priority */ | |
67 | mtdcr( UIC0SR, 0x00000000 ); /* clear all interrupts */ | |
68 | mtdcr( UIC0SR, 0xffffffff ); | |
6e7fb6ea | 69 | |
d1c3b275 | 70 | mfsdr(SDR0_MFR, mfr); |
a27044b1 | 71 | mfr |= SDR0_MFR_FIXD; /* Workaround for PCI/DMA */ |
d1c3b275 | 72 | mtsdr(SDR0_MFR, mfr); |
a27044b1 | 73 | |
6e7fb6ea SR |
74 | return 0; |
75 | } | |
76 | ||
77 | ||
78 | /************************************************************************* | |
79 | * int misc_init_r() | |
80 | * | |
81 | ************************************************************************/ | |
82 | int misc_init_r(void) | |
83 | { | |
6d0f6bcf | 84 | volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE; |
2db64784 GB |
85 | |
86 | /* set modes of operation */ | |
87 | x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 | | |
88 | EPLD2_ETH_MODE_1000 | EPLD2_ETH_DUPLEX_MODE; | |
89 | /* clear ETHERNET_AUTO_NEGO bit to turn on autonegotiation */ | |
90 | x->ethuart &= ~EPLD2_ETH_AUTO_NEGO; | |
738815c0 | 91 | |
2db64784 GB |
92 | /* put Ethernet+PHY in reset */ |
93 | x->ethuart &= ~EPLD2_RESET_ETH_N; | |
94 | udelay(10000); | |
95 | /* take Ethernet+PHY out of reset */ | |
96 | x->ethuart |= EPLD2_RESET_ETH_N; | |
6e7fb6ea SR |
97 | |
98 | return 0; | |
99 | } | |
100 | ||
101 | ||
102 | /************************************************************************* | |
103 | * int checkboard() | |
104 | * | |
105 | ************************************************************************/ | |
106 | int checkboard(void) | |
107 | { | |
f0c0b3a9 WD |
108 | char buf[64]; |
109 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
6e7fb6ea SR |
110 | |
111 | printf("Board: Luan - AMCC PPC440SP Evaluation Board"); | |
112 | ||
f0c0b3a9 | 113 | if (i > 0) { |
6e7fb6ea | 114 | puts(", serial# "); |
f0c0b3a9 | 115 | puts(buf); |
6e7fb6ea SR |
116 | } |
117 | putc('\n'); | |
118 | ||
119 | return 0; | |
120 | } | |
121 | ||
2a49fc17 | 122 | /* |
a47a12be | 123 | * Override the default functions in arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c with |
2a49fc17 SR |
124 | * board specific values. |
125 | */ | |
126 | u32 ddr_clktr(u32 default_val) { | |
127 | return (SDRAM_CLKTR_CLKP_180_DEG_ADV); | |
128 | } | |
6e7fb6ea | 129 | |
6e7fb6ea SR |
130 | /************************************************************************* |
131 | * hw_watchdog_reset | |
132 | * | |
133 | * This routine is called to reset (keep alive) the watchdog timer | |
134 | * | |
135 | ************************************************************************/ | |
136 | #if defined(CONFIG_HW_WATCHDOG) | |
137 | void hw_watchdog_reset(void) | |
138 | { | |
139 | } | |
140 | #endif | |
141 | ||
142 | ||
143 | /************************************************************************* | |
144 | * int on_off() | |
145 | * | |
146 | ************************************************************************/ | |
147 | static int on_off( const char *s ) | |
148 | { | |
149 | if (strcmp(s, "on") == 0) { | |
150 | return 1; | |
151 | } else if (strcmp(s, "off") == 0) { | |
152 | return 0; | |
153 | } | |
154 | return -1; | |
155 | } | |
156 | ||
157 | ||
158 | /************************************************************************* | |
159 | * void l2cache_disable() | |
160 | * | |
161 | ************************************************************************/ | |
162 | static void l2cache_disable(void) | |
163 | { | |
b14ca4b6 | 164 | mtdcr( L2_CACHE_CFG, 0 ); |
6e7fb6ea SR |
165 | } |
166 | ||
167 | ||
168 | /************************************************************************* | |
169 | * void l2cache_enable() | |
170 | * | |
171 | ************************************************************************/ | |
172 | static void l2cache_enable(void) /* see p258 7.4.1 Enabling L2 Cache */ | |
173 | { | |
b14ca4b6 | 174 | mtdcr( L2_CACHE_CFG, 0x80000000 ); /* enable L2_MODE L2_CFG[L2M] */ |
6e7fb6ea | 175 | |
b14ca4b6 | 176 | mtdcr( L2_CACHE_ADDR, 0 ); /* set L2_ADDR with all zeros */ |
6e7fb6ea | 177 | |
b14ca4b6 | 178 | mtdcr( L2_CACHE_CMD, 0x80000000 ); /* issue HCLEAR command via L2_CMD */ |
6e7fb6ea | 179 | |
b14ca4b6 | 180 | while (!(mfdcr( L2_CACHE_STAT ) & 0x80000000 )) ;; /* poll L2_SR for completion */ |
6e7fb6ea | 181 | |
b14ca4b6 | 182 | mtdcr( L2_CACHE_CMD, 0x10000000 ); /* clear cache errors L2_CMD[CCP] */ |
6e7fb6ea | 183 | |
b14ca4b6 | 184 | mtdcr( L2_CACHE_CMD, 0x08000000 ); /* clear tag errors L2_CMD[CTE] */ |
6e7fb6ea | 185 | |
b14ca4b6 DM |
186 | mtdcr( L2_CACHE_SNP0, 0 ); /* snoop registers */ |
187 | mtdcr( L2_CACHE_SNP1, 0 ); | |
6e7fb6ea SR |
188 | |
189 | __asm__ volatile ("sync"); /* msync */ | |
190 | ||
b14ca4b6 | 191 | mtdcr( L2_CACHE_CFG, 0xe0000000 ); /* inst and data use L2 */ |
6e7fb6ea SR |
192 | |
193 | __asm__ volatile ("sync"); | |
194 | } | |
195 | ||
196 | ||
197 | /************************************************************************* | |
198 | * int l2cache_status() | |
199 | * | |
200 | ************************************************************************/ | |
201 | static int l2cache_status(void) | |
202 | { | |
b14ca4b6 | 203 | return (mfdcr( L2_CACHE_CFG ) & 0x60000000) != 0; |
6e7fb6ea SR |
204 | } |
205 | ||
206 | ||
207 | /************************************************************************* | |
208 | * int do_l2cache() | |
209 | * | |
210 | ************************************************************************/ | |
54841ab5 | 211 | int do_l2cache( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[] ) |
6e7fb6ea SR |
212 | { |
213 | switch (argc) { | |
214 | case 2: /* on / off */ | |
215 | switch (on_off(argv[1])) { | |
216 | case 0: l2cache_disable(); | |
217 | break; | |
218 | case 1: l2cache_enable(); | |
219 | break; | |
220 | } | |
221 | /* FALL TROUGH */ | |
222 | case 1: /* get status */ | |
223 | printf ("L2 Cache is %s\n", | |
224 | l2cache_status() ? "ON" : "OFF"); | |
225 | return 0; | |
226 | default: | |
47e26b1b | 227 | return cmd_usage(cmdtp); |
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228 | } |
229 | ||
230 | return 0; | |
231 | } | |
232 | ||
233 | ||
234 | U_BOOT_CMD( | |
235 | l2cache, 2, 1, do_l2cache, | |
2fb2604d | 236 | "enable or disable L2 cache", |
6e7fb6ea | 237 | "[on, off]\n" |
a89c33db WD |
238 | " - enable or disable L2 cache" |
239 | ); |