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Commit | Line | Data |
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0ce5c867 FK |
1 | /* |
2 | * This is the main board level file for the Redwood AMCC board. | |
3 | * | |
4 | * (C) Copyright 2008 | |
5 | * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
0ce5c867 FK |
8 | */ |
9 | ||
10 | #include <common.h> | |
11 | #include "redwood.h" | |
b36df561 | 12 | #include <asm/ppc4xx.h> |
0ce5c867 FK |
13 | #include <asm/processor.h> |
14 | #include <i2c.h> | |
61f2b38a | 15 | #include <asm/io.h> |
0ce5c867 FK |
16 | |
17 | int compare_to_true(char *str); | |
18 | char *remove_l_w_space(char *in_str); | |
19 | char *remove_t_w_space(char *in_str); | |
20 | int get_console_port(void); | |
21 | ||
22 | static void early_init_EBC(void); | |
23 | static int bootdevice_selected(void); | |
24 | static void early_reinit_EBC(int); | |
25 | static void early_init_UIC(void); | |
26 | ||
1d055473 SR |
27 | /* |
28 | * Define Boot devices | |
29 | */ | |
0ce5c867 FK |
30 | #define BOOT_FROM_8BIT_SRAM 0x00 |
31 | #define BOOT_FROM_16BIT_SRAM 0x01 | |
32 | #define BOOT_FROM_32BIT_SRAM 0x02 | |
33 | #define BOOT_FROM_8BIT_NAND 0x03 | |
34 | #define BOOT_FROM_16BIT_NOR 0x04 | |
35 | #define BOOT_DEVICE_UNKNOWN 0xff | |
36 | ||
1d055473 SR |
37 | /* |
38 | * EBC Devices Characteristics | |
39 | * Peripheral Bank Access Parameters - EBC_BxAP | |
40 | * Peripheral Bank Configuration Register - EBC_BxCR | |
41 | */ | |
0ce5c867 FK |
42 | |
43 | /* | |
44 | * 8 bit width SRAM | |
45 | * BU Value | |
46 | * BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 | |
47 | * B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000 | |
48 | * B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000 | |
49 | */ | |
1d055473 SR |
50 | #define EBC_BXAP_8BIT_SRAM \ |
51 | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \ | |
52 | EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \ | |
53 | EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \ | |
54 | EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \ | |
55 | EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \ | |
56 | EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \ | |
57 | EBC_BXAP_PEN_DISABLED | |
0ce5c867 FK |
58 | |
59 | #define EBC_BXAP_16BIT_SRAM EBC_BXAP_8BIT_SRAM | |
60 | #define EBC_BXAP_32BIT_SRAM EBC_BXAP_8BIT_SRAM | |
61 | ||
62 | /* | |
63 | * NAND flash | |
64 | * BU Value | |
65 | * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 | |
66 | * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000 | |
67 | * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000 | |
68 | */ | |
1d055473 SR |
69 | #define EBC_BXAP_NAND \ |
70 | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \ | |
71 | EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \ | |
72 | EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \ | |
73 | EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \ | |
74 | EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \ | |
75 | EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \ | |
76 | EBC_BXAP_PEN_DISABLED | |
0ce5c867 FK |
77 | |
78 | /* | |
79 | * NOR flash | |
80 | * BU Value | |
81 | * BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000 | |
82 | * B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000 | |
83 | * B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000 | |
84 | */ | |
1d055473 SR |
85 | #define EBC_BXAP_NOR \ |
86 | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(7) | \ | |
87 | EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \ | |
88 | EBC_BXAP_CSN_ENCODE(0) | EBC_BXAP_OEN_ENCODE(0) | \ | |
89 | EBC_BXAP_WBN_ENCODE(0) | EBC_BXAP_WBF_ENCODE(0) | \ | |
90 | EBC_BXAP_TH_ENCODE(0) | EBC_BXAP_RE_DISABLED | \ | |
91 | EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_WRITEONLY | \ | |
92 | EBC_BXAP_PEN_DISABLED | |
0ce5c867 FK |
93 | |
94 | /* | |
95 | * FPGA | |
96 | * BU value : | |
97 | * B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000 | |
98 | * B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000 | |
99 | */ | |
1d055473 SR |
100 | #define EBC_BXAP_FPGA \ |
101 | EBC_BXAP_BME_DISABLED | EBC_BXAP_TWT_ENCODE(11) | \ | |
102 | EBC_BXAP_BCE_DISABLE | EBC_BXAP_BCT_2TRANS | \ | |
103 | EBC_BXAP_CSN_ENCODE(10) | EBC_BXAP_OEN_ENCODE(1) | \ | |
104 | EBC_BXAP_WBN_ENCODE(1) | EBC_BXAP_WBF_ENCODE(1) | \ | |
105 | EBC_BXAP_TH_ENCODE(1) | EBC_BXAP_RE_DISABLED | \ | |
106 | EBC_BXAP_SOR_DELAYED | EBC_BXAP_BEM_RW | \ | |
107 | EBC_BXAP_PEN_DISABLED | |
108 | ||
109 | #define EBC_BXCR_8BIT_SRAM_CS0 \ | |
110 | EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_1MB | \ | |
111 | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT | |
112 | ||
113 | #define EBC_BXCR_32BIT_SRAM_CS0 \ | |
114 | EBC_BXCR_BAS_ENCODE(0xFFC00000) | EBC_BXCR_BS_1MB | \ | |
115 | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT | |
116 | ||
117 | #define EBC_BXCR_NAND_CS0 \ | |
118 | EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \ | |
119 | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT | |
120 | ||
121 | #define EBC_BXCR_16BIT_SRAM_CS0 \ | |
122 | EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_2MB | \ | |
123 | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT | |
124 | ||
125 | #define EBC_BXCR_NOR_CS0 \ | |
126 | EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB | \ | |
127 | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT | |
128 | ||
129 | #define EBC_BXCR_NOR_CS1 \ | |
130 | EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \ | |
131 | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT | |
132 | ||
133 | #define EBC_BXCR_NAND_CS1 \ | |
134 | EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB | \ | |
135 | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT | |
136 | ||
137 | #define EBC_BXCR_NAND_CS2 \ | |
138 | EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_128MB | \ | |
139 | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT | |
140 | ||
141 | #define EBC_BXCR_SRAM_CS2 \ | |
142 | EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_4MB | \ | |
143 | EBC_BXCR_BU_RW | EBC_BXCR_BW_32BIT | |
144 | ||
145 | #define EBC_BXCR_LARGE_FLASH_CS2 \ | |
146 | EBC_BXCR_BAS_ENCODE(0xE7000000) | EBC_BXCR_BS_16MB | \ | |
147 | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT | |
148 | ||
149 | #define EBC_BXCR_FPGA_CS3 \ | |
150 | EBC_BXCR_BAS_ENCODE(0xE2000000) | EBC_BXCR_BS_1MB | \ | |
151 | EBC_BXCR_BU_RW | EBC_BXCR_BW_16BIT | |
0ce5c867 FK |
152 | |
153 | /***************************************************************************** | |
154 | * UBOOT initiated board specific function calls | |
155 | ****************************************************************************/ | |
156 | ||
157 | int board_early_init_f(void) | |
158 | { | |
159 | int computed_boot_device = BOOT_DEVICE_UNKNOWN; | |
160 | ||
161 | /* | |
162 | * Initialise EBC | |
163 | */ | |
164 | early_init_EBC(); | |
165 | ||
166 | /* | |
167 | * Determine which boot device was selected | |
168 | */ | |
169 | computed_boot_device = bootdevice_selected(); | |
170 | ||
171 | /* | |
172 | * Reinit EBC based on selected boot device | |
173 | */ | |
174 | early_reinit_EBC(computed_boot_device); | |
175 | ||
176 | /* | |
177 | * Setup for UIC on 460SX redwood board | |
178 | */ | |
179 | early_init_UIC(); | |
180 | ||
181 | return 0; | |
182 | } | |
183 | ||
184 | int checkboard(void) | |
185 | { | |
f0c0b3a9 WD |
186 | char buf[64]; |
187 | int i = getenv_f("serial#", buf, sizeof(buf)); | |
0ce5c867 FK |
188 | |
189 | printf("Board: Redwood - AMCC 460SX Reference Board"); | |
f0c0b3a9 | 190 | if (i > 0) { |
0ce5c867 | 191 | puts(", serial# "); |
f0c0b3a9 | 192 | puts(buf); |
0ce5c867 FK |
193 | } |
194 | putc('\n'); | |
195 | ||
196 | return 0; | |
197 | } | |
198 | ||
199 | static void early_init_EBC(void) | |
200 | { | |
1d055473 SR |
201 | /* |
202 | * Initialize EBC CONFIG - | |
203 | * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC | |
204 | * default value : | |
205 | * 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000 | |
206 | */ | |
d1c3b275 | 207 | mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK | |
0ce5c867 FK |
208 | EBC_CFG_PTD_ENABLE | |
209 | EBC_CFG_RTC_16PERCLK | | |
210 | EBC_CFG_ATC_PREVIOUS | | |
211 | EBC_CFG_DTC_PREVIOUS | | |
212 | EBC_CFG_CTC_PREVIOUS | | |
213 | EBC_CFG_OEO_PREVIOUS | | |
214 | EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16); | |
215 | ||
1d055473 SR |
216 | /* |
217 | * PART 1 : Initialize EBC Bank 3 | |
218 | * ============================== | |
219 | * Bank1 is always associated to the EPLD. | |
220 | * It has to be initialized prior to other banks settings computation | |
221 | * since some board registers values may be needed to determine the | |
222 | * boot type | |
223 | */ | |
d1c3b275 SR |
224 | mtebc(PB1AP, EBC_BXAP_FPGA); |
225 | mtebc(PB1CR, EBC_BXCR_FPGA_CS3); | |
0ce5c867 FK |
226 | |
227 | } | |
228 | ||
229 | static int bootdevice_selected(void) | |
230 | { | |
231 | unsigned long sdr0_pinstp; | |
232 | unsigned long bootstrap_settings; | |
233 | int computed_boot_device = BOOT_DEVICE_UNKNOWN; | |
234 | ||
1d055473 SR |
235 | /* |
236 | * Determine which boot device was selected | |
237 | * ================================================= | |
238 | * | |
239 | * Read Pin Strap Register in PPC460SX | |
240 | * Result can either be : | |
241 | * - Boot strap = boot from EBC 8bits => Small Flash | |
242 | * - Boot strap = boot from PCI | |
243 | * - Boot strap = IIC | |
244 | * In case of boot from IIC, read Serial Device Strap Register1 | |
245 | * | |
246 | * Result can either be : | |
247 | * - Boot from EBC - EBC Bus Width = 8bits => Small Flash | |
248 | * - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM | |
249 | * - Boot from PCI | |
250 | */ | |
251 | ||
0ce5c867 FK |
252 | /* Read Pin Strap Register in PPC460SX */ |
253 | mfsdr(SDR0_PINSTP, sdr0_pinstp); | |
254 | bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK; | |
255 | ||
256 | switch (bootstrap_settings) { | |
257 | case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0: | |
258 | /* | |
259 | * Boot from SRAM, 8bit width | |
260 | */ | |
261 | computed_boot_device = BOOT_FROM_8BIT_SRAM; | |
262 | break; | |
263 | case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1: | |
264 | /* | |
265 | * Boot from SRAM, 32bit width | |
266 | */ | |
267 | computed_boot_device = BOOT_FROM_32BIT_SRAM; | |
268 | break; | |
269 | case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2: | |
270 | /* | |
271 | * Boot from NAND, 8bit width | |
272 | */ | |
273 | computed_boot_device = BOOT_FROM_8BIT_NAND; | |
274 | break; | |
275 | case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4: | |
276 | /* | |
277 | * Boot from SRAM, 16bit width | |
278 | * Boot setting in IIC EEPROM 0x50 | |
279 | */ | |
280 | computed_boot_device = BOOT_FROM_16BIT_SRAM; | |
281 | break; | |
282 | case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5: | |
283 | /* | |
284 | * Boot from NOR, 16bit width | |
285 | * Boot setting in IIC EEPROM 0x54 | |
286 | */ | |
287 | computed_boot_device = BOOT_FROM_16BIT_NOR; | |
288 | break; | |
289 | default: | |
290 | /* should not be */ | |
291 | computed_boot_device = BOOT_DEVICE_UNKNOWN; | |
292 | break; | |
293 | } | |
294 | ||
295 | return computed_boot_device; | |
296 | } | |
297 | ||
298 | static void early_reinit_EBC(int computed_boot_device) | |
299 | { | |
1d055473 SR |
300 | /* |
301 | * Compute EBC settings depending on selected boot device | |
302 | * ====================================================== | |
303 | * | |
304 | * Resulting EBC init will be among following configurations : | |
305 | * | |
306 | * - Boot from EBC 8bits => boot from Small Flash selected | |
307 | * EBC-CS0 = Small Flash | |
308 | * EBC-CS2 = Large Flash and SRAM | |
309 | * | |
310 | * - Boot from EBC 16bits => boot from Large Flash or SRAM | |
311 | * EBC-CS0 = Large Flash or SRAM | |
312 | * EBC-CS2 = Small Flash | |
313 | * | |
314 | * - Boot from PCI | |
315 | * EBC-CS0 = not initialized to avoid address contention | |
316 | * EBC-CS2 = same as boot from Small Flash selected | |
317 | */ | |
318 | ||
0ce5c867 FK |
319 | unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0; |
320 | unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0; | |
321 | unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0; | |
322 | ||
323 | switch (computed_boot_device) { | |
324 | /*-------------------------------------------------------------------*/ | |
325 | case BOOT_FROM_8BIT_SRAM: | |
326 | /*-------------------------------------------------------------------*/ | |
327 | ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM; | |
328 | ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0; | |
329 | ebc0_cs1_bxap_value = EBC_BXAP_NOR; | |
330 | ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; | |
331 | ebc0_cs2_bxap_value = EBC_BXAP_NAND; | |
332 | ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2; | |
333 | break; | |
334 | ||
335 | /*-------------------------------------------------------------------*/ | |
336 | case BOOT_FROM_16BIT_SRAM: | |
337 | /*-------------------------------------------------------------------*/ | |
338 | ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM; | |
339 | ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0; | |
340 | ebc0_cs1_bxap_value = EBC_BXAP_NOR; | |
341 | ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; | |
342 | ebc0_cs2_bxap_value = EBC_BXAP_NAND; | |
343 | ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2; | |
344 | break; | |
345 | ||
346 | /*-------------------------------------------------------------------*/ | |
347 | case BOOT_FROM_32BIT_SRAM: | |
348 | /*-------------------------------------------------------------------*/ | |
349 | ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM; | |
350 | ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0; | |
351 | ebc0_cs1_bxap_value = EBC_BXAP_NOR; | |
352 | ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; | |
353 | ebc0_cs2_bxap_value = EBC_BXAP_NAND; | |
354 | ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2; | |
355 | break; | |
356 | ||
357 | /*-------------------------------------------------------------------*/ | |
358 | case BOOT_FROM_16BIT_NOR: | |
359 | /*-------------------------------------------------------------------*/ | |
360 | ebc0_cs0_bxap_value = EBC_BXAP_NOR; | |
361 | ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0; | |
362 | ebc0_cs1_bxap_value = EBC_BXAP_NAND; | |
363 | ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1; | |
364 | ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM; | |
365 | ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2; | |
366 | break; | |
367 | ||
368 | /*-------------------------------------------------------------------*/ | |
369 | case BOOT_FROM_8BIT_NAND: | |
370 | /*-------------------------------------------------------------------*/ | |
371 | ebc0_cs0_bxap_value = EBC_BXAP_NAND; | |
372 | ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0; | |
373 | ebc0_cs1_bxap_value = EBC_BXAP_NOR; | |
374 | ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1; | |
375 | ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM; | |
376 | ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2; | |
377 | break; | |
378 | ||
379 | /*-------------------------------------------------------------------*/ | |
380 | default: | |
381 | /*-------------------------------------------------------------------*/ | |
382 | /* BOOT_DEVICE_UNKNOWN */ | |
383 | break; | |
384 | } | |
385 | ||
d1c3b275 SR |
386 | mtebc(PB0AP, ebc0_cs0_bxap_value); |
387 | mtebc(PB0CR, ebc0_cs0_bxcr_value); | |
388 | mtebc(PB1AP, ebc0_cs1_bxap_value); | |
389 | mtebc(PB1CR, ebc0_cs1_bxcr_value); | |
390 | mtebc(PB2AP, ebc0_cs2_bxap_value); | |
391 | mtebc(PB2CR, ebc0_cs2_bxcr_value); | |
0ce5c867 FK |
392 | } |
393 | ||
394 | static void early_init_UIC(void) | |
395 | { | |
1d055473 SR |
396 | /* |
397 | * Initialise UIC registers. Clear all interrupts. Disable all | |
398 | * interrupts. | |
399 | * Set critical interrupt values. Set interrupt polarities. Set | |
400 | * interrupt trigger levels. Make bit 0 High priority. Clear all | |
401 | * interrupts again. | |
402 | */ | |
952e7760 SR |
403 | mtdcr(UIC3SR, 0xffffffff); /* Clear all interrupts */ |
404 | mtdcr(UIC3ER, 0x00000000); /* disable all interrupts */ | |
405 | mtdcr(UIC3CR, 0x00000000); /* Set Critical / Non Critical | |
0ce5c867 | 406 | * interrupts */ |
952e7760 SR |
407 | mtdcr(UIC3PR, 0xffffffff); /* Set Interrupt Polarities */ |
408 | mtdcr(UIC3TR, 0x001fffff); /* Set Interrupt Trigger Levels */ | |
409 | mtdcr(UIC3VR, 0x00000000); /* int31 highest, base=0x000 */ | |
410 | mtdcr(UIC3SR, 0xffffffff); /* clear all interrupts */ | |
411 | ||
412 | mtdcr(UIC2SR, 0xffffffff); /* Clear all interrupts */ | |
413 | mtdcr(UIC2ER, 0x00000000); /* disable all interrupts */ | |
414 | mtdcr(UIC2CR, 0x00000000); /* Set Critical / Non Critical | |
0ce5c867 | 415 | * interrupts */ |
952e7760 SR |
416 | mtdcr(UIC2PR, 0xebebebff); /* Set Interrupt Polarities */ |
417 | mtdcr(UIC2TR, 0x74747400); /* Set Interrupt Trigger Levels */ | |
418 | mtdcr(UIC2VR, 0x00000000); /* int31 highest, base=0x000 */ | |
419 | mtdcr(UIC2SR, 0xffffffff); /* clear all interrupts */ | |
420 | ||
421 | mtdcr(UIC1SR, 0xffffffff); /* Clear all interrupts */ | |
422 | mtdcr(UIC1ER, 0x00000000); /* disable all interrupts */ | |
423 | mtdcr(UIC1CR, 0x00000000); /* Set Critical / Non Critical | |
0ce5c867 | 424 | * interrupts */ |
952e7760 SR |
425 | mtdcr(UIC1PR, 0xffffffff); /* Set Interrupt Polarities */ |
426 | mtdcr(UIC1TR, 0x001fc0ff); /* Set Interrupt Trigger Levels */ | |
427 | mtdcr(UIC1VR, 0x00000000); /* int31 highest, base=0x000 */ | |
428 | mtdcr(UIC1SR, 0xffffffff); /* clear all interrupts */ | |
0ce5c867 | 429 | |
952e7760 SR |
430 | mtdcr(UIC0SR, 0xffffffff); /* Clear all interrupts */ |
431 | mtdcr(UIC0ER, 0x00000000); /* disable all interrupts excepted | |
0ce5c867 | 432 | * cascade to be checked */ |
952e7760 | 433 | mtdcr(UIC0CR, 0x00104001); /* Set Critical / Non Critical |
0ce5c867 | 434 | * interrupts */ |
952e7760 SR |
435 | mtdcr(UIC0PR, 0xffffffff); /* Set Interrupt Polarities */ |
436 | mtdcr(UIC0TR, 0x000f003c); /* Set Interrupt Trigger Levels */ | |
437 | mtdcr(UIC0VR, 0x00000000); /* int31 highest, base=0x000 */ | |
438 | mtdcr(UIC0SR, 0xffffffff); /* clear all interrupts */ | |
0ce5c867 FK |
439 | |
440 | } |