[people/ms/u-boot.git] / board / amcc / redwood / redwood.c

/*
 * This is the main board level file for the Redwood AMCC board.
 *
 * (C) Copyright 2008
 * Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 *
 */

#include <common.h>
#include "redwood.h"
#include <ppc4xx.h>
#include <asm/processor.h>
#include <i2c.h>
#include <asm-ppc/io.h>

int compare_to_true(char *str);
char *remove_l_w_space(char *in_str);
char *remove_t_w_space(char *in_str);
int get_console_port(void);

static void early_init_EBC(void);
static int bootdevice_selected(void);
static void early_reinit_EBC(int);
static void early_init_UIC(void);

/*
 * Define Boot devices
 */
#define BOOT_FROM_8BIT_SRAM			0x00
#define BOOT_FROM_16BIT_SRAM			0x01
#define BOOT_FROM_32BIT_SRAM			0x02
#define BOOT_FROM_8BIT_NAND			0x03
#define BOOT_FROM_16BIT_NOR			0x04
#define BOOT_DEVICE_UNKNOWN			0xff

/*
 * EBC Devices Characteristics
 *   Peripheral Bank Access Parameters       -   EBC_BxAP
 *   Peripheral Bank Configuration Register  -   EBC_BxCR
 */

/*
 * 8 bit width SRAM
 * BU Value
 * BxAP : 0x03800000  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
 * B0CR : 0xff098000  - BAS = ff0 - 100 11 00 0000000000000
 * B2CR : 0xe7098000  - BAS = e70 - 100 11 00 0000000000000
 */
#define EBC_BXAP_8BIT_SRAM					\
	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(7)  |	\
	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
	EBC_BXAP_CSN_ENCODE(0)  | EBC_BXAP_OEN_ENCODE(0)  |	\
	EBC_BXAP_WBN_ENCODE(0)  | EBC_BXAP_WBF_ENCODE(0)  |	\
	EBC_BXAP_TH_ENCODE(0)   | EBC_BXAP_RE_DISABLED    |	\
	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_WRITEONLY  |	\
	EBC_BXAP_PEN_DISABLED

#define EBC_BXAP_16BIT_SRAM	EBC_BXAP_8BIT_SRAM
#define EBC_BXAP_32BIT_SRAM	EBC_BXAP_8BIT_SRAM

/*
 * NAND flash
 * BU Value
 * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
 * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
 * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
*/
#define EBC_BXAP_NAND						\
	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(7)  |	\
	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
	EBC_BXAP_CSN_ENCODE(0)  | EBC_BXAP_OEN_ENCODE(0)  |	\
	EBC_BXAP_WBN_ENCODE(0)  | EBC_BXAP_WBF_ENCODE(0)  |	\
	EBC_BXAP_TH_ENCODE(0)   | EBC_BXAP_RE_DISABLED    |	\
	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_WRITEONLY  |	\
	EBC_BXAP_PEN_DISABLED

/*
 * NOR flash
 * BU Value
 * BxAP : 0x048ff240  - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
 * B0CR : 0xff09a000  - BAS = ff0 - 100 11 01 0000000000000
 * B2CR : 0xe709a000  - BAS = e70 - 100 11 01 0000000000000
*/
#define EBC_BXAP_NOR						\
	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(7)  |	\
	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
	EBC_BXAP_CSN_ENCODE(0)  | EBC_BXAP_OEN_ENCODE(0)  |	\
	EBC_BXAP_WBN_ENCODE(0)  | EBC_BXAP_WBF_ENCODE(0)  |	\
	EBC_BXAP_TH_ENCODE(0)   | EBC_BXAP_RE_DISABLED    |	\
	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_WRITEONLY  |	\
	EBC_BXAP_PEN_DISABLED

/*
 * FPGA
 * BU value :
 * B1AP = 0x05895240  - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
 * B1CR = 0xe201a000  - BAS = e20 - 000 11 01 00000000000000
 */
#define EBC_BXAP_FPGA						\
	EBC_BXAP_BME_DISABLED   | EBC_BXAP_TWT_ENCODE(11) |	\
	EBC_BXAP_BCE_DISABLE    | EBC_BXAP_BCT_2TRANS     |	\
	EBC_BXAP_CSN_ENCODE(10) | EBC_BXAP_OEN_ENCODE(1)  |	\
	EBC_BXAP_WBN_ENCODE(1)  | EBC_BXAP_WBF_ENCODE(1)  |	\
	EBC_BXAP_TH_ENCODE(1)   | EBC_BXAP_RE_DISABLED    |	\
	EBC_BXAP_SOR_DELAYED    | EBC_BXAP_BEM_RW         |	\
	EBC_BXAP_PEN_DISABLED

#define EBC_BXCR_8BIT_SRAM_CS0						\
	EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_1MB           |	\
	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT

#define EBC_BXCR_32BIT_SRAM_CS0						\
	EBC_BXCR_BAS_ENCODE(0xFFC00000) | EBC_BXCR_BS_1MB           |	\
	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_32BIT

#define EBC_BXCR_NAND_CS0						\
	EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB          |	\
	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT

#define EBC_BXCR_16BIT_SRAM_CS0						\
	EBC_BXCR_BAS_ENCODE(0xFFE00000) | EBC_BXCR_BS_2MB           |	\
	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT

#define EBC_BXCR_NOR_CS0						\
	EBC_BXCR_BAS_ENCODE(0xFF000000) | EBC_BXCR_BS_16MB          |	\
	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT

#define EBC_BXCR_NOR_CS1						\
	EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB         |	\
	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT

#define EBC_BXCR_NAND_CS1						\
	EBC_BXCR_BAS_ENCODE(0xE0000000) | EBC_BXCR_BS_128MB         |	\
	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT

#define EBC_BXCR_NAND_CS2						\
	EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_128MB         |	\
	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_8BIT

#define EBC_BXCR_SRAM_CS2						\
	EBC_BXCR_BAS_ENCODE(0xC0000000) | EBC_BXCR_BS_4MB           |	\
	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_32BIT

#define EBC_BXCR_LARGE_FLASH_CS2					\
	EBC_BXCR_BAS_ENCODE(0xE7000000) | EBC_BXCR_BS_16MB          |	\
	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT

#define EBC_BXCR_FPGA_CS3						\
	EBC_BXCR_BAS_ENCODE(0xE2000000) | EBC_BXCR_BS_1MB           |	\
	EBC_BXCR_BU_RW                  | EBC_BXCR_BW_16BIT

/*****************************************************************************
 * UBOOT initiated board specific function calls
 ****************************************************************************/

int board_early_init_f(void)
{
	int computed_boot_device = BOOT_DEVICE_UNKNOWN;

	/*
	 * Initialise EBC
	 */
	early_init_EBC();

	/*
	 * Determine which boot device was selected
	 */
	computed_boot_device = bootdevice_selected();

	/*
	 * Reinit EBC based on selected boot device
	 */
	early_reinit_EBC(computed_boot_device);

	/*
	 * Setup for UIC on 460SX redwood board
	 */
	early_init_UIC();

	return 0;
}

int checkboard(void)
{
	char *s = getenv("serial#");

	printf("Board: Redwood - AMCC 460SX Reference Board");
	if (s != NULL) {
		puts(", serial# ");
		puts(s);
	}
	putc('\n');

	return 0;
}

static void early_init_EBC(void)
{
	/*
	 * Initialize EBC CONFIG -
	 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
	 * default value :
	 *      0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
	 */
	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK |
	      EBC_CFG_PTD_ENABLE |
	      EBC_CFG_RTC_16PERCLK |
	      EBC_CFG_ATC_PREVIOUS |
	      EBC_CFG_DTC_PREVIOUS |
	      EBC_CFG_CTC_PREVIOUS |
	      EBC_CFG_OEO_PREVIOUS |
	      EBC_CFG_EMC_DEFAULT | EBC_CFG_PME_DISABLE | EBC_CFG_PR_16);

	/*
	 * PART 1 : Initialize EBC Bank 3
	 * ==============================
	 * Bank1 is always associated to the EPLD.
	 * It has to be initialized prior to other banks settings computation
	 * since some board registers values may be needed to determine the
	 * boot type
	 */
	mtebc(PB1AP, EBC_BXAP_FPGA);
	mtebc(PB1CR, EBC_BXCR_FPGA_CS3);

}

static int bootdevice_selected(void)
{
	unsigned long sdr0_pinstp;
	unsigned long bootstrap_settings;
	int computed_boot_device = BOOT_DEVICE_UNKNOWN;

	/*
	 *  Determine which boot device was selected
	 *  =================================================
	 *
	 *  Read Pin Strap Register in PPC460SX
	 *  Result can either be :
	 *   - Boot strap = boot from EBC 8bits     => Small Flash
	 *   - Boot strap = boot from PCI
	 *   - Boot strap = IIC
	 *  In case of boot from IIC, read Serial Device Strap Register1
	 *
	 *  Result can either be :
	 *   - Boot from EBC  - EBC Bus Width = 8bits    => Small Flash
	 *   - Boot from EBC  - EBC Bus Width = 16bits   => Large Flash or SRAM
	 *   - Boot from PCI
	 */

	/* Read Pin Strap Register in PPC460SX */
	mfsdr(SDR0_PINSTP, sdr0_pinstp);
	bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK;

	switch (bootstrap_settings) {
	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
		/*
		 * Boot from SRAM, 8bit width
		 */
		computed_boot_device = BOOT_FROM_8BIT_SRAM;
		break;
	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
		/*
		 * Boot from SRAM, 32bit width
		 */
		computed_boot_device = BOOT_FROM_32BIT_SRAM;
		break;
	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
		/*
		 * Boot from NAND, 8bit width
		 */
		computed_boot_device = BOOT_FROM_8BIT_NAND;
		break;
	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
		/*
		 * Boot from SRAM, 16bit width
		 * Boot setting in IIC EEPROM 0x50
		 */
		computed_boot_device = BOOT_FROM_16BIT_SRAM;
		break;
	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5:
		/*
		 * Boot from NOR, 16bit width
		 * Boot setting in IIC EEPROM 0x54
		 */
		computed_boot_device = BOOT_FROM_16BIT_NOR;
		break;
	default:
		/* should not be */
		computed_boot_device = BOOT_DEVICE_UNKNOWN;
		break;
	}

	return computed_boot_device;
}

static void early_reinit_EBC(int computed_boot_device)
{
	/*
	 *  Compute EBC settings depending on selected boot device
	 *  ======================================================
	 *
	 * Resulting EBC init will be among following configurations :
	 *
	 *  - Boot from EBC 8bits => boot from Small Flash selected
	 *            EBC-CS0     = Small Flash
	 *            EBC-CS2     = Large Flash and SRAM
	 *
	 *  - Boot from EBC 16bits => boot from Large Flash or SRAM
	 *            EBC-CS0     = Large Flash or SRAM
	 *            EBC-CS2     = Small Flash
	 *
	 *  - Boot from PCI
	 *            EBC-CS0     = not initialized to avoid address contention
	 *            EBC-CS2     = same as boot from Small Flash selected
	 */

	unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
	unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0;
	unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;

	switch (computed_boot_device) {
		/*-------------------------------------------------------------------*/
	case BOOT_FROM_8BIT_SRAM:
		/*-------------------------------------------------------------------*/
		ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM;
		ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0;
		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
		ebc0_cs2_bxap_value = EBC_BXAP_NAND;
		ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
		break;

		/*-------------------------------------------------------------------*/
	case BOOT_FROM_16BIT_SRAM:
		/*-------------------------------------------------------------------*/
		ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM;
		ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0;
		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
		ebc0_cs2_bxap_value = EBC_BXAP_NAND;
		ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
		break;

		/*-------------------------------------------------------------------*/
	case BOOT_FROM_32BIT_SRAM:
		/*-------------------------------------------------------------------*/
		ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM;
		ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0;
		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
		ebc0_cs2_bxap_value = EBC_BXAP_NAND;
		ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
		break;

		/*-------------------------------------------------------------------*/
	case BOOT_FROM_16BIT_NOR:
		/*-------------------------------------------------------------------*/
		ebc0_cs0_bxap_value = EBC_BXAP_NOR;
		ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0;
		ebc0_cs1_bxap_value = EBC_BXAP_NAND;
		ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1;
		ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
		ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
		break;

		/*-------------------------------------------------------------------*/
	case BOOT_FROM_8BIT_NAND:
		/*-------------------------------------------------------------------*/
		ebc0_cs0_bxap_value = EBC_BXAP_NAND;
		ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0;
		ebc0_cs1_bxap_value = EBC_BXAP_NOR;
		ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
		ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
		ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
		break;

		/*-------------------------------------------------------------------*/
	default:
		/*-------------------------------------------------------------------*/
		/* BOOT_DEVICE_UNKNOWN */
		break;
	}

	mtebc(PB0AP, ebc0_cs0_bxap_value);
	mtebc(PB0CR, ebc0_cs0_bxcr_value);
	mtebc(PB1AP, ebc0_cs1_bxap_value);
	mtebc(PB1CR, ebc0_cs1_bxcr_value);
	mtebc(PB2AP, ebc0_cs2_bxap_value);
	mtebc(PB2CR, ebc0_cs2_bxcr_value);
}

static void early_init_UIC(void)
{
	/*
	 * Initialise UIC registers.  Clear all interrupts.  Disable all
	 * interrupts.
	 * Set critical interrupt values.  Set interrupt polarities.  Set
	 * interrupt trigger levels.  Make bit 0 High  priority.  Clear all
	 * interrupts again.
	 */
	mtdcr(uic3sr, 0xffffffff);	/* Clear all interrupts */
	mtdcr(uic3er, 0x00000000);	/* disable all interrupts */
	mtdcr(uic3cr, 0x00000000);	/* Set Critical / Non Critical
					 * interrupts */
	mtdcr(uic3pr, 0xffffffff);	/* Set Interrupt Polarities */
	mtdcr(uic3tr, 0x001fffff);	/* Set Interrupt Trigger Levels */
	mtdcr(uic3vr, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(uic3sr, 0xffffffff);	/* clear all  interrupts */

	mtdcr(uic2sr, 0xffffffff);	/* Clear all interrupts */
	mtdcr(uic2er, 0x00000000);	/* disable all interrupts */
	mtdcr(uic2cr, 0x00000000);	/* Set Critical / Non Critical
					 * interrupts */
	mtdcr(uic2pr, 0xebebebff);	/* Set Interrupt Polarities */
	mtdcr(uic2tr, 0x74747400);	/* Set Interrupt Trigger Levels */
	mtdcr(uic2vr, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(uic2sr, 0xffffffff);	/* clear all interrupts */

	mtdcr(uic1sr, 0xffffffff);	/* Clear all interrupts */
	mtdcr(uic1er, 0x00000000);	/* disable all interrupts */
	mtdcr(uic1cr, 0x00000000);	/* Set Critical / Non Critical
					 * interrupts */
	mtdcr(uic1pr, 0xffffffff);	/* Set Interrupt Polarities */
	mtdcr(uic1tr, 0x001fc0ff);	/* Set Interrupt Trigger Levels */
	mtdcr(uic1vr, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(uic1sr, 0xffffffff);	/* clear all interrupts */

	mtdcr(uic0sr, 0xffffffff);	/* Clear all interrupts */
	mtdcr(uic0er, 0x00000000);	/* disable all interrupts excepted
					 * cascade to be checked */
	mtdcr(uic0cr, 0x00104001);	/* Set Critical / Non Critical
					 * interrupts */
	mtdcr(uic0pr, 0xffffffff);	/* Set Interrupt Polarities */
	mtdcr(uic0tr, 0x000f003c);	/* Set Interrupt Trigger Levels */
	mtdcr(uic0vr, 0x00000000);	/* int31 highest, base=0x000 */
	mtdcr(uic0sr, 0xffffffff);	/* clear all interrupts */

}
Commit	Line	Data
0ce5c867 FK	1	/*
	2	* This is the main board level file for the Redwood AMCC board.
	3	*
	4	* (C) Copyright 2008
	5	* Feng Kan, Applied Micro Circuits Corp., fkan@amcc.com
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*
	25	*/
	26
	27	#include <common.h>
	28	#include "redwood.h"
	29	#include <ppc4xx.h>
	30	#include <asm/processor.h>
	31	#include <i2c.h>
	32	#include <asm-ppc/io.h>
	33
	34	int compare_to_true(char *str);
	35	char remove_l_w_space(char in_str);
	36	char remove_t_w_space(char in_str);
	37	int get_console_port(void);
	38
	39	static void early_init_EBC(void);
	40	static int bootdevice_selected(void);
	41	static void early_reinit_EBC(int);
	42	static void early_init_UIC(void);
	43
1d055473 SR	44	/*
	45	* Define Boot devices
	46	*/
0ce5c867 FK	47	#define BOOT_FROM_8BIT_SRAM 0x00
	48	#define BOOT_FROM_16BIT_SRAM 0x01
	49	#define BOOT_FROM_32BIT_SRAM 0x02
	50	#define BOOT_FROM_8BIT_NAND 0x03
	51	#define BOOT_FROM_16BIT_NOR 0x04
	52	#define BOOT_DEVICE_UNKNOWN 0xff
	53
1d055473 SR	54	/*
	55	* EBC Devices Characteristics
	56	* Peripheral Bank Access Parameters - EBC_BxAP
	57	* Peripheral Bank Configuration Register - EBC_BxCR
	58	*/
0ce5c867 FK	59
	60	/*
	61	* 8 bit width SRAM
	62	* BU Value
	63	* BxAP : 0x03800000 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
	64	* B0CR : 0xff098000 - BAS = ff0 - 100 11 00 0000000000000
	65	* B2CR : 0xe7098000 - BAS = e70 - 100 11 00 0000000000000
	66	*/
1d055473 SR	67	#define EBC_BXAP_8BIT_SRAM \
	68	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(7) \| \
	69	EBC_BXAP_BCE_DISABLE \| EBC_BXAP_BCT_2TRANS \| \
	70	EBC_BXAP_CSN_ENCODE(0) \| EBC_BXAP_OEN_ENCODE(0) \| \
	71	EBC_BXAP_WBN_ENCODE(0) \| EBC_BXAP_WBF_ENCODE(0) \| \
	72	EBC_BXAP_TH_ENCODE(0) \| EBC_BXAP_RE_DISABLED \| \
	73	EBC_BXAP_SOR_DELAYED \| EBC_BXAP_BEM_WRITEONLY \| \
	74	EBC_BXAP_PEN_DISABLED
0ce5c867 FK	75
	76	#define EBC_BXAP_16BIT_SRAM EBC_BXAP_8BIT_SRAM
	77	#define EBC_BXAP_32BIT_SRAM EBC_BXAP_8BIT_SRAM
	78
	79	/*
	80	* NAND flash
	81	* BU Value
	82	* BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
	83	* B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
	84	* B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
	85	*/
1d055473 SR	86	#define EBC_BXAP_NAND \
	87	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(7) \| \
	88	EBC_BXAP_BCE_DISABLE \| EBC_BXAP_BCT_2TRANS \| \
	89	EBC_BXAP_CSN_ENCODE(0) \| EBC_BXAP_OEN_ENCODE(0) \| \
	90	EBC_BXAP_WBN_ENCODE(0) \| EBC_BXAP_WBF_ENCODE(0) \| \
	91	EBC_BXAP_TH_ENCODE(0) \| EBC_BXAP_RE_DISABLED \| \
	92	EBC_BXAP_SOR_DELAYED \| EBC_BXAP_BEM_WRITEONLY \| \
	93	EBC_BXAP_PEN_DISABLED
0ce5c867 FK	94
	95	/*
	96	* NOR flash
	97	* BU Value
	98	* BxAP : 0x048ff240 - 0 00000111 0 00 00 00 00 00 000 0 0 0 0 00000
	99	* B0CR : 0xff09a000 - BAS = ff0 - 100 11 01 0000000000000
	100	* B2CR : 0xe709a000 - BAS = e70 - 100 11 01 0000000000000
	101	*/
1d055473 SR	102	#define EBC_BXAP_NOR \
	103	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(7) \| \
	104	EBC_BXAP_BCE_DISABLE \| EBC_BXAP_BCT_2TRANS \| \
	105	EBC_BXAP_CSN_ENCODE(0) \| EBC_BXAP_OEN_ENCODE(0) \| \
	106	EBC_BXAP_WBN_ENCODE(0) \| EBC_BXAP_WBF_ENCODE(0) \| \
	107	EBC_BXAP_TH_ENCODE(0) \| EBC_BXAP_RE_DISABLED \| \
	108	EBC_BXAP_SOR_DELAYED \| EBC_BXAP_BEM_WRITEONLY \| \
	109	EBC_BXAP_PEN_DISABLED
0ce5c867 FK	110
	111	/*
	112	* FPGA
	113	* BU value :
	114	* B1AP = 0x05895240 - 0 00001011 0 00 10 01 01 01 001 0 0 1 0 00000
	115	* B1CR = 0xe201a000 - BAS = e20 - 000 11 01 00000000000000
	116	*/
1d055473 SR	117	#define EBC_BXAP_FPGA \
	118	EBC_BXAP_BME_DISABLED \| EBC_BXAP_TWT_ENCODE(11) \| \
	119	EBC_BXAP_BCE_DISABLE \| EBC_BXAP_BCT_2TRANS \| \
	120	EBC_BXAP_CSN_ENCODE(10) \| EBC_BXAP_OEN_ENCODE(1) \| \
	121	EBC_BXAP_WBN_ENCODE(1) \| EBC_BXAP_WBF_ENCODE(1) \| \
	122	EBC_BXAP_TH_ENCODE(1) \| EBC_BXAP_RE_DISABLED \| \
	123	EBC_BXAP_SOR_DELAYED \| EBC_BXAP_BEM_RW \| \
	124	EBC_BXAP_PEN_DISABLED
	125
	126	#define EBC_BXCR_8BIT_SRAM_CS0 \
	127	EBC_BXCR_BAS_ENCODE(0xFFE00000) \| EBC_BXCR_BS_1MB \| \
	128	EBC_BXCR_BU_RW \| EBC_BXCR_BW_8BIT
	129
	130	#define EBC_BXCR_32BIT_SRAM_CS0 \
	131	EBC_BXCR_BAS_ENCODE(0xFFC00000) \| EBC_BXCR_BS_1MB \| \
	132	EBC_BXCR_BU_RW \| EBC_BXCR_BW_32BIT
	133
	134	#define EBC_BXCR_NAND_CS0 \
	135	EBC_BXCR_BAS_ENCODE(0xFF000000) \| EBC_BXCR_BS_16MB \| \
	136	EBC_BXCR_BU_RW \| EBC_BXCR_BW_8BIT
	137
	138	#define EBC_BXCR_16BIT_SRAM_CS0 \
	139	EBC_BXCR_BAS_ENCODE(0xFFE00000) \| EBC_BXCR_BS_2MB \| \
	140	EBC_BXCR_BU_RW \| EBC_BXCR_BW_16BIT
	141
	142	#define EBC_BXCR_NOR_CS0 \
	143	EBC_BXCR_BAS_ENCODE(0xFF000000) \| EBC_BXCR_BS_16MB \| \
	144	EBC_BXCR_BU_RW \| EBC_BXCR_BW_16BIT
	145
	146	#define EBC_BXCR_NOR_CS1 \
	147	EBC_BXCR_BAS_ENCODE(0xE0000000) \| EBC_BXCR_BS_128MB \| \
	148	EBC_BXCR_BU_RW \| EBC_BXCR_BW_16BIT
	149
	150	#define EBC_BXCR_NAND_CS1 \
	151	EBC_BXCR_BAS_ENCODE(0xE0000000) \| EBC_BXCR_BS_128MB \| \
	152	EBC_BXCR_BU_RW \| EBC_BXCR_BW_8BIT
	153
	154	#define EBC_BXCR_NAND_CS2 \
	155	EBC_BXCR_BAS_ENCODE(0xC0000000) \| EBC_BXCR_BS_128MB \| \
	156	EBC_BXCR_BU_RW \| EBC_BXCR_BW_8BIT
	157
	158	#define EBC_BXCR_SRAM_CS2 \
	159	EBC_BXCR_BAS_ENCODE(0xC0000000) \| EBC_BXCR_BS_4MB \| \
	160	EBC_BXCR_BU_RW \| EBC_BXCR_BW_32BIT
	161
	162	#define EBC_BXCR_LARGE_FLASH_CS2 \
	163	EBC_BXCR_BAS_ENCODE(0xE7000000) \| EBC_BXCR_BS_16MB \| \
	164	EBC_BXCR_BU_RW \| EBC_BXCR_BW_16BIT
	165
	166	#define EBC_BXCR_FPGA_CS3 \
	167	EBC_BXCR_BAS_ENCODE(0xE2000000) \| EBC_BXCR_BS_1MB \| \
	168	EBC_BXCR_BU_RW \| EBC_BXCR_BW_16BIT
0ce5c867 FK	169
	170	/*****************************************************************************
	171	* UBOOT initiated board specific function calls
	172	****************************************************************************/
	173
	174	int board_early_init_f(void)
	175	{
	176	int computed_boot_device = BOOT_DEVICE_UNKNOWN;
	177
	178	/*
	179	* Initialise EBC
	180	*/
	181	early_init_EBC();
	182
	183	/*
	184	* Determine which boot device was selected
	185	*/
	186	computed_boot_device = bootdevice_selected();
	187
	188	/*
	189	* Reinit EBC based on selected boot device
	190	*/
	191	early_reinit_EBC(computed_boot_device);
	192
	193	/*
	194	* Setup for UIC on 460SX redwood board
	195	*/
	196	early_init_UIC();
	197
	198	return 0;
	199	}
	200
	201	int checkboard(void)
	202	{
	203	char *s = getenv("serial#");
	204
	205	printf("Board: Redwood - AMCC 460SX Reference Board");
	206	if (s != NULL) {
	207	puts(", serial# ");
	208	puts(s);
	209	}
	210	putc('\n');
	211
	212	return 0;
	213	}
	214
	215	static void early_init_EBC(void)
	216	{
1d055473 SR	217	/*
	218	* Initialize EBC CONFIG -
	219	* Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
	220	* default value :
	221	* 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
	222	*/
d1c3b275	223	mtebc(EBC0_CFG, EBC_CFG_LE_UNLOCK \|
0ce5c867 FK	224	EBC_CFG_PTD_ENABLE \|
	225	EBC_CFG_RTC_16PERCLK \|
	226	EBC_CFG_ATC_PREVIOUS \|
	227	EBC_CFG_DTC_PREVIOUS \|
	228	EBC_CFG_CTC_PREVIOUS \|
	229	EBC_CFG_OEO_PREVIOUS \|
	230	EBC_CFG_EMC_DEFAULT \| EBC_CFG_PME_DISABLE \| EBC_CFG_PR_16);
	231
1d055473 SR	232	/*
	233	* PART 1 : Initialize EBC Bank 3
	234	* ==============================
	235	* Bank1 is always associated to the EPLD.
	236	* It has to be initialized prior to other banks settings computation
	237	* since some board registers values may be needed to determine the
	238	* boot type
	239	*/
d1c3b275 SR	240	mtebc(PB1AP, EBC_BXAP_FPGA);
d1c3b275 SR	241	mtebc(PB1CR, EBC_BXCR_FPGA_CS3);
0ce5c867 FK	242
	243	}
	244
	245	static int bootdevice_selected(void)
	246	{
	247	unsigned long sdr0_pinstp;
	248	unsigned long bootstrap_settings;
	249	int computed_boot_device = BOOT_DEVICE_UNKNOWN;
	250
1d055473 SR	251	/*
	252	* Determine which boot device was selected
	253	* =================================================
	254	*
	255	* Read Pin Strap Register in PPC460SX
	256	* Result can either be :
	257	* - Boot strap = boot from EBC 8bits => Small Flash
	258	* - Boot strap = boot from PCI
	259	* - Boot strap = IIC
	260	* In case of boot from IIC, read Serial Device Strap Register1
	261	*
	262	* Result can either be :
	263	* - Boot from EBC - EBC Bus Width = 8bits => Small Flash
	264	* - Boot from EBC - EBC Bus Width = 16bits => Large Flash or SRAM
	265	* - Boot from PCI
	266	*/
	267
0ce5c867 FK	268	/* Read Pin Strap Register in PPC460SX */
	269	mfsdr(SDR0_PINSTP, sdr0_pinstp);
	270	bootstrap_settings = sdr0_pinstp & SDR0_PSTRP0_BOOTSTRAP_MASK;
	271
	272	switch (bootstrap_settings) {
	273	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS0:
	274	/*
	275	* Boot from SRAM, 8bit width
	276	*/
	277	computed_boot_device = BOOT_FROM_8BIT_SRAM;
	278	break;
	279	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS1:
	280	/*
	281	* Boot from SRAM, 32bit width
	282	*/
	283	computed_boot_device = BOOT_FROM_32BIT_SRAM;
	284	break;
	285	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS2:
	286	/*
	287	* Boot from NAND, 8bit width
	288	*/
	289	computed_boot_device = BOOT_FROM_8BIT_NAND;
	290	break;
	291	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS4:
	292	/*
	293	* Boot from SRAM, 16bit width
	294	* Boot setting in IIC EEPROM 0x50
	295	*/
	296	computed_boot_device = BOOT_FROM_16BIT_SRAM;
	297	break;
	298	case SDR0_PSTRP0_BOOTSTRAP_SETTINGS5:
	299	/*
	300	* Boot from NOR, 16bit width
	301	* Boot setting in IIC EEPROM 0x54
	302	*/
	303	computed_boot_device = BOOT_FROM_16BIT_NOR;
	304	break;
	305	default:
	306	/* should not be */
	307	computed_boot_device = BOOT_DEVICE_UNKNOWN;
	308	break;
	309	}
	310
	311	return computed_boot_device;
	312	}
	313
	314	static void early_reinit_EBC(int computed_boot_device)
	315	{
1d055473 SR	316	/*
	317	* Compute EBC settings depending on selected boot device
	318	* ======================================================
	319	*
	320	* Resulting EBC init will be among following configurations :
	321	*
	322	* - Boot from EBC 8bits => boot from Small Flash selected
	323	* EBC-CS0 = Small Flash
	324	* EBC-CS2 = Large Flash and SRAM
	325	*
	326	* - Boot from EBC 16bits => boot from Large Flash or SRAM
	327	* EBC-CS0 = Large Flash or SRAM
	328	* EBC-CS2 = Small Flash
	329	*
	330	* - Boot from PCI
	331	* EBC-CS0 = not initialized to avoid address contention
	332	* EBC-CS2 = same as boot from Small Flash selected
	333	*/
	334
0ce5c867 FK	335	unsigned long ebc0_cs0_bxap_value = 0, ebc0_cs0_bxcr_value = 0;
	336	unsigned long ebc0_cs1_bxap_value = 0, ebc0_cs1_bxcr_value = 0;
	337	unsigned long ebc0_cs2_bxap_value = 0, ebc0_cs2_bxcr_value = 0;
	338
	339	switch (computed_boot_device) {
	340	/-------------------------------------------------------------------/
	341	case BOOT_FROM_8BIT_SRAM:
	342	/-------------------------------------------------------------------/
	343	ebc0_cs0_bxap_value = EBC_BXAP_8BIT_SRAM;
	344	ebc0_cs0_bxcr_value = EBC_BXCR_8BIT_SRAM_CS0;
	345	ebc0_cs1_bxap_value = EBC_BXAP_NOR;
	346	ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
	347	ebc0_cs2_bxap_value = EBC_BXAP_NAND;
	348	ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
	349	break;
	350
	351	/-------------------------------------------------------------------/
	352	case BOOT_FROM_16BIT_SRAM:
	353	/-------------------------------------------------------------------/
	354	ebc0_cs0_bxap_value = EBC_BXAP_16BIT_SRAM;
	355	ebc0_cs0_bxcr_value = EBC_BXCR_16BIT_SRAM_CS0;
	356	ebc0_cs1_bxap_value = EBC_BXAP_NOR;
	357	ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
	358	ebc0_cs2_bxap_value = EBC_BXAP_NAND;
	359	ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
	360	break;
	361
	362	/-------------------------------------------------------------------/
	363	case BOOT_FROM_32BIT_SRAM:
	364	/-------------------------------------------------------------------/
	365	ebc0_cs0_bxap_value = EBC_BXAP_32BIT_SRAM;
	366	ebc0_cs0_bxcr_value = EBC_BXCR_32BIT_SRAM_CS0;
	367	ebc0_cs1_bxap_value = EBC_BXAP_NOR;
	368	ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
	369	ebc0_cs2_bxap_value = EBC_BXAP_NAND;
	370	ebc0_cs2_bxcr_value = EBC_BXCR_NAND_CS2;
	371	break;
	372
	373	/-------------------------------------------------------------------/
	374	case BOOT_FROM_16BIT_NOR:
	375	/-------------------------------------------------------------------/
	376	ebc0_cs0_bxap_value = EBC_BXAP_NOR;
	377	ebc0_cs0_bxcr_value = EBC_BXCR_NOR_CS0;
	378	ebc0_cs1_bxap_value = EBC_BXAP_NAND;
	379	ebc0_cs1_bxcr_value = EBC_BXCR_NAND_CS1;
	380	ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
	381	ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
	382	break;
	383
	384	/-------------------------------------------------------------------/
	385	case BOOT_FROM_8BIT_NAND:
	386	/-------------------------------------------------------------------/
	387	ebc0_cs0_bxap_value = EBC_BXAP_NAND;
	388	ebc0_cs0_bxcr_value = EBC_BXCR_NAND_CS0;
	389	ebc0_cs1_bxap_value = EBC_BXAP_NOR;
	390	ebc0_cs1_bxcr_value = EBC_BXCR_NOR_CS1;
	391	ebc0_cs2_bxap_value = EBC_BXAP_32BIT_SRAM;
	392	ebc0_cs2_bxcr_value = EBC_BXCR_SRAM_CS2;
	393	break;
	394
	395	/-------------------------------------------------------------------/
	396	default:
	397	/-------------------------------------------------------------------/
	398	/* BOOT_DEVICE_UNKNOWN */
399	break;
400	}
401
d1c3b275 SR	402	mtebc(PB0AP, ebc0_cs0_bxap_value);
	403	mtebc(PB0CR, ebc0_cs0_bxcr_value);
	404	mtebc(PB1AP, ebc0_cs1_bxap_value);
	405	mtebc(PB1CR, ebc0_cs1_bxcr_value);
	406	mtebc(PB2AP, ebc0_cs2_bxap_value);
	407	mtebc(PB2CR, ebc0_cs2_bxcr_value);
0ce5c867 FK	408	}
	409
	410	static void early_init_UIC(void)
	411	{
1d055473 SR	412	/*
	413	* Initialise UIC registers. Clear all interrupts. Disable all
	414	* interrupts.
	415	* Set critical interrupt values. Set interrupt polarities. Set
	416	* interrupt trigger levels. Make bit 0 High priority. Clear all
	417	* interrupts again.
	418	*/
0ce5c867 FK	419	mtdcr(uic3sr, 0xffffffff); /* Clear all interrupts */
	420	mtdcr(uic3er, 0x00000000); /* disable all interrupts */
	421	mtdcr(uic3cr, 0x00000000); /* Set Critical / Non Critical
	422	* interrupts */
	423	mtdcr(uic3pr, 0xffffffff); /* Set Interrupt Polarities */
	424	mtdcr(uic3tr, 0x001fffff); /* Set Interrupt Trigger Levels */
	425	mtdcr(uic3vr, 0x00000000); /* int31 highest, base=0x000 */
	426	mtdcr(uic3sr, 0xffffffff); /* clear all interrupts */
	427
	428	mtdcr(uic2sr, 0xffffffff); /* Clear all interrupts */
	429	mtdcr(uic2er, 0x00000000); /* disable all interrupts */
	430	mtdcr(uic2cr, 0x00000000); /* Set Critical / Non Critical
	431	* interrupts */
	432	mtdcr(uic2pr, 0xebebebff); /* Set Interrupt Polarities */
	433	mtdcr(uic2tr, 0x74747400); /* Set Interrupt Trigger Levels */
	434	mtdcr(uic2vr, 0x00000000); /* int31 highest, base=0x000 */
	435	mtdcr(uic2sr, 0xffffffff); /* clear all interrupts */
	436
	437	mtdcr(uic1sr, 0xffffffff); /* Clear all interrupts */
	438	mtdcr(uic1er, 0x00000000); /* disable all interrupts */
	439	mtdcr(uic1cr, 0x00000000); /* Set Critical / Non Critical
	440	* interrupts */
	441	mtdcr(uic1pr, 0xffffffff); /* Set Interrupt Polarities */
	442	mtdcr(uic1tr, 0x001fc0ff); /* Set Interrupt Trigger Levels */
	443	mtdcr(uic1vr, 0x00000000); /* int31 highest, base=0x000 */
	444	mtdcr(uic1sr, 0xffffffff); /* clear all interrupts */
	445
	446	mtdcr(uic0sr, 0xffffffff); /* Clear all interrupts */
	447	mtdcr(uic0er, 0x00000000); /* disable all interrupts excepted
	448	* cascade to be checked */
	449	mtdcr(uic0cr, 0x00104001); /* Set Critical / Non Critical
	450	* interrupts */
	451	mtdcr(uic0pr, 0xffffffff); /* Set Interrupt Polarities */
	452	mtdcr(uic0tr, 0x000f003c); /* Set Interrupt Trigger Levels */
	453	mtdcr(uic0vr, 0x00000000); /* int31 highest, base=0x000 */
	454	mtdcr(uic0sr, 0xffffffff); /* clear all interrupts */
	455
	456	}